Floating structure at packaged ball grid array for crosstalk cancellation

Abstract

A semiconductor device, a package, and a structure are described. The semiconductor structure may include a plurality of BGA pads, wherein a plurality of BGA balls are attached to a first surface of the plurality of BGA pads. The semiconductor structure may also include a dielectric layer deposited on a second surface of the plurality of BGA pads. The second surface may be opposite the first surface. The semiconductor structure may also include at least one floating structure deposited on the dielectric layer. The at least one floating structure and at least two BGA pads of the plurality of BGA pads may form at least two capacitors connected within the interposer.

Description

Background Technology

[0001] This disclosure relates to systems and apparatuses implemented by semiconductor devices. More specifically, in some embodiments, this disclosure relates to ball grid array (BGA) packages having embedded floating structures for crosstalk cancellation.

[0002] As memory system data rates increase to relatively high speeds, such as exceeding 10 gigabits per second (Gb / s), and with a target of 17.6 Gb / s for Generation 6 Double Data Rate (DDR6) memory, signal crosstalk can negatively impact the performance of single-ended channels between the CPU, RCD / DB, and DRAM in a memory system. Signal crosstalk is a signal integrity problem caused by unwanted electromagnetic coupling between conductive paths, such as traces or vias on a printed circuit board (PCB) or package, where these paths are not physically in contact with each other. At relatively high data rates, equalization techniques struggle to open the data eye diagram of a memory system due to crosstalk noise. Therefore, in high data rate memory systems, such as those implementing DDR6 memory channel designs, reducing signal crosstalk between signals is desirable. Summary of the Invention

[0003] In one embodiment, a semiconductor package is generally described. The semiconductor package may include a semiconductor device, a plurality of ball grid array (BGA) balls, and an interposer. The semiconductor device may be mounted on the interposer. The interposer may include a plurality of BGA pads, wherein the plurality of BGA balls are attached to a first surface of the plurality of BGA pads. The interposer may further include a dielectric layer deposited on a second surface of the plurality of BGA pads. The second surface may be opposite to the first surface. The interposer may further include at least one floating structure deposited on the dielectric layer. The at least one floating structure and at least two of the plurality of BGA pads may form at least two capacitors connected within the interposer.

[0004] In one embodiment, a memory module is generally described. The memory module may include a memory device, a plurality of ball grid array (BGA) balls, and an interposer. The interposer may include a plurality of BGA pads, wherein the plurality of BGA pads are attached to a first surface of the plurality of BGA pads. The interposer may also include a dielectric layer deposited on a second surface of the plurality of BGA pads. The second surface may be opposite to the first surface. The interposer may also include at least one floating structure deposited on the dielectric layer. The at least one floating structure and at least two of the plurality of BGA pads may form at least two capacitors connected within the interposer.

[0005] In one embodiment, a semiconductor structure is generally described. The semiconductor structure may include a plurality of BGA balls attached to a plurality of BGA pads on a first surface. The semiconductor structure may also include a dielectric layer deposited on a second surface of the plurality of BGA pads. The second surface may be opposite to the first surface. The semiconductor structure may further include at least one floating structure deposited on the dielectric layer. The at least one floating structure and at least two of the plurality of BGA pads may form at least two capacitors interconnected with each other.

[0006] The above description of the invention is illustrative only and is not intended to be limiting in any way. Other aspects, embodiments, and features, besides the illustrative aspects, embodiments, and features described above, will become apparent from the accompanying drawings and the following detailed description. In the drawings, the same reference numerals denote the same or functionally similar elements. Attached Figure Description

[0007] Figure 1 This is a diagram of an example memory system according to an embodiment of the present disclosure.

[0008] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of an example memory module for a memory system.

[0009] Figure 3 This is a cross-sectional view of a semiconductor device including a floating structure at a packaged ball grid array for crosstalk cancellation in one embodiment.

[0010] Figure 4 This is a three-dimensional diagram of a multilayer semiconductor device including a floating structure at a packaged ball grid array for crosstalk cancellation in one embodiment.

[0011] Figure 5 This is a three-dimensional diagram of a semiconductor device including a floating structure at a packaged ball grid array for crosstalk cancellation in one embodiment.

[0012] Figure 6 This is a three-dimensional diagram of another semiconductor device, including a floating structure at a packaged ball grid array for crosstalk cancellation, in one embodiment.

[0013] Figure 7 This is a three-dimensional diagram of another semiconductor device, including a floating structure at a packaged ball grid array for crosstalk cancellation, in one embodiment.

[0014] Figure 8 This is a two-dimensional diagram of the arrangement of multiple floating structures at the encapsulated ball grid array for crosstalk cancellation in one embodiment. Specific Implementation

[0015] Power management in DDR random access memory (RAM) modules typically relies on the use of a power management integrated circuit (PMIC) to handle the conversion of large-volume power inputs to one or more power outputs, the voltage of which corresponds to the requirements of different components of the DDR memory module, and in some embodiments, to the requirements of different components of a fifth-generation DDR (DDR5) memory module. In one example, the disclosed embodiments may include unbuffered dual in-line memory modules (UDIMMs). For example, for laptops, the disclosed embodiments may include small dual in-line memory modules (SODIMMs), such as DDR5 SODIMMs. In another example, the disclosed embodiments may include registered dual in-line memory modules (RDIMMs). The disclosed embodiments may alternatively include any type of memory module.

[0016] Figure 1 This is a diagram of an example memory system 10 according to an embodiment of the present disclosure. The memory system 10 may include memory modules 201, 202, ..., 20 N (Also collectively or individually referred to herein as memory module 20, one or more), connector 70, and memory controller 80. In one example embodiment, memory module 20 may include a dual in-line memory module (DIMM). In some embodiments, memory module 20 may be implemented as a generation 5 double data rate (DDR5) SDRAM module. Although described and illustrated herein as components of a particular type, arrangement, and number, in other embodiments, memory module 20 may include any other type, arrangement, or number of components.

[0017] Example memory module 20 may include circuit system blocks 301, 302, 303, 304, 305, ..., 30 P-4 30 P-3 30 P-2 30 P-1 and 30 P Circuit system blocks 401, 402, ..., 40 M-1 and 40 M The registered clock driver (RCD) 50, PMIC 60, connector 70, and any other blocks, circuits, pins, connectors, traces, or other components commonly found in memory modules. In some embodiments, circuit system blocks 301, 302, 303, 304, 305, ..., 30 P-4 30 P-3 30 P-2 30 P-1 and 30 PThese can be configured as data buffers, and are collectively or individually referred to herein as data buffer(s) 30. In some embodiments, circuit system blocks 401, 402, ..., 40 M-1 and 40 M It can be configured as a memory device, and is collectively or individually referred to herein as memory device 40(one or more). Although described herein as data buffer 30 and memory device 40, circuit system blocks 30 and 40 may also, or alternatively, be used by memory module 20 for any other purpose.

[0018] In some embodiments, the data buffer 30 and memory device 40 may include a synchronous dynamic random access memory (SDRAM) device, chip, or module. In some embodiments, the data buffer 30 and memory device 40 may also, or alternatively, include any other type of memory device, such as SRAM, DRAM, MROM, PROM, EPROM, and EEPROM. The data buffer 30, memory device 40, or both may be physically located on one or both sides (e.g., the front and back) of the memory module 20.

[0019] PMIC 60 can be configured to perform power management on memory module 20. For example, PMIC 60 can be configured to boost or buck, perform DC-DC conversion, or perform other similar power management operations. In some embodiments, PMIC 60 may include a low-dropout regulator (LDO), a DC-DC converter such as a buck or boost converter, a pulse frequency modulator (PFM), a pulse width modulator (PWM), a power field-effect transistor (FET), a real-time clock (RTC), or any other circuitry common in PMICs.

[0020] Connector 70 may include, for example, pins, traces, or other connections configured to connect memory module 20 to other components of the computing system, such as memory controller 80, motherboard, or other components. In some embodiments, connector 70 may include, for example, a 288-pin configuration or any other pin configuration. In some embodiments, memory module 20 may include connector 70. In other embodiments, the motherboard of the computing device, memory controller 80, or any other component may include connector 70. In another embodiment, one or more of connectors 70 may be part of memory module 20, and one or more of connectors 70 may be part of the motherboard of the computing device, memory controller 80, or other components. Memory module 20 may be connected to the motherboard of the computing device, memory controller 80, or other components, for example, via connector 70, to transfer data between components of the computing device and memory module 20. For example, in embodiments implementing UDIMM, connector 70 may include a 64-bit bus, a 72-bit bus, or a bus including any other bit width.

[0021] Figure 1 The memory module 20 shown is connected to the memory controller 80 of the computing device via connector 70. In one example embodiment, the memory controller 80 may be implemented as a component of the computer motherboard or motherboard of the computing device, for example, on the northbridge of the motherboard. In another example, the memory controller 80 may be implemented as a component of the microprocessor of the computing device. In yet another example, the memory controller 80 may be implemented as a component of the central processing unit (CPU) of the computing device. In other embodiments, the memory controller 80 may be implemented as part of any other component of the computing device.

[0022] In some embodiments, memory module 20 may be implemented as a DDR5 SDRAM memory module. For example, memory module 20 may include memory module densities of 128 gigabytes (GB), 512GB, 1 terabyte (TB), or higher per module. Memory module 20 may operate at frequencies from about 1.2 gigahertz (GHz) to about 3.2 GHz and have a data rate range of about 3.2 GT / s to 4.6 GT / s, and in some cases, a data rate of up to 8 GT / s or higher. In some embodiments, memory module 20 may alternatively include smaller or larger densities, operate at lower or higher frequencies, and operate at lower or higher data rates.

[0023] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of an example memory module for a memory system. Memory module 20 can represent memory modules 201-20. NThe memory module 20 is shown communicating with the memory controller 80. The memory controller 80 is shown as part of circuitry 90, such as a motherboard, mainboard, or other component of a computing device that communicates with the memory module 20.

[0024] The memory module 20 may include one or more circuit groups 221, 222, 223, 224, 225, ..., 22 Q-4 ,twenty two Q-3 ,twenty two Q-2 ,twenty two Q-1 and 22 Q This is also referred to herein, collectively or individually, as data path 22 of memory module 20. In the example shown, memory module 20 may include five data paths 22, such as data paths 221, 222, 223, 224, and 225, located on one side of RCD 50, and data path 22, located on the other side of RCD 50. Q-4 ,twenty two Q-3 ,twenty two Q-2 ,twenty two Q-1 and 22 Q Five data paths 22. In other embodiments, the memory module 20 may include other arrangements having more or fewer data paths 22 on each side of the RCD 50. Each data path 22 may include corresponding memory channels 421, 422, 423, 424, 425, ..., 426. R-4 42 R-3 42 R-2 42 R-1 and 42 R Memory channels 42 are also collectively or individually referred to herein as memory channels (one or more). Each memory channel 42 may include one or more of the memory devices 40. For example, memory channel 421 may include memory devices 401 to 40. S , and memory channel 42 R It may include a memory device 40 T To memory device 40 M .

[0025] The memory controller 80 can be configured to generate various signals, including a clock signal (CLK), an address signal (ADDR), a control signal (CTRL), and a command signal (CMD). One or more of the CLK, ADDR, CTRL, and CMD signals can be provided to the RCD 50, for example, via one or more buses 23. Signals from the memory controller 80 can also be transmitted from the memory controller 80 to the PMIC 60 via bus 24, which is also referred to herein as the host interface bus 24. In some embodiments, the host interface bus 24 is bidirectional and configured to communicate commands or other data between the PMIC 60 and the memory controller 80 or other components of the memory module 20. The host interface bus 24 can implement I / O... 2 C protocol, I 3 C protocol or any other protocol.

[0026] Data bus 72 may be connected between memory controller 80 and data path 22, such as having data buffer 30, and may include connector 70 between memory controller 80 and data path 22, such as traces, pins, and other connections. Memory controller 80 may generate or receive data signals such as DQa-DQn and data strobe signals such as DQSa-DQSn, which may be presented to or received from data bus 72. A portion of signals DQa-DQn and signals DQSa-DQSn may be presented to or received from the corresponding data path 22. In the example shown, each of signals DQa-DQn may have a corresponding signal DQSa-DQSn. In some embodiments, one DQS signal may strobe multiple DQ signals; for example, in some embodiments, one DQS signal may strobe four DQ signals.

[0027] RCD 50 can be configured to communicate with memory controller 80, data buffer 30, memory channel 42, and PMIC 60. RCD 50 can be configured to decode instructions such as control words received from memory controller 80. For example, RCD 50 can be configured to receive and decode register command words (RCWs). In another example, RCD 50 can be configured to receive and decode buffer control words (BCWs). RCD 50 can be configured to train data buffer 30, memory device 40, and one or more command and address lines between RCD 50 and memory controller 80. For example, RCWs can flow from memory controller 80 to RCD 50 and be used to configure RCD 50.

[0028] In some embodiments, RCD 50 can implement a command / address register, such as a 32-bit 1:2 command / address register. RCD 50 can support high-speed buses, such as a unidirectional buffered communication (BCOM) bus between RCD 50 and data buffer 30. In some embodiments, RCD 50 can implement automatic impedance calibration, command / address parity checking, control register RCW readback, and inter-integrated circuit (I) communication, such as 1MHz I / O. 2 C) bus and 12.5MHz integrated circuit (I) 3 C) One or more of the serial buses of the bus. The inputs to the RCD 50 can be pseudo-differential using one or more of the external and internal voltages. The clock output, command / address output, control output, and data buffer control output of the RCD 50 can be grouped and enabled, and driven independently with different strengths.

[0029] RCD 50 can be configured to receive CLK, ADDR, and CMD signals, or other signals such as RCW and BCW, from memory controller 80, and utilize various digital logic components to generate corresponding output signals based on the CLK, ADDR, and CMD signals. For example, RCD 50 can be configured to generate corresponding signals, such as CLK', ADDR', and CMD' signals, based on the received CLK, ADDR, and CMD signals. The CLK', ADDR', and CMD' signals can be presented to memory channel 42. For example, the CLK' signal can be transmitted from RCD 50 to memory channel 42 on common bus 25, while the ADDR' and CMD' signals can be transmitted from RCD 50 to memory channel 42 on common bus 26. RCD 50 can also be configured to generate one or more data buffer control (DBC) signals, which are transmitted, for example, to data buffer 30 on common bus 27, also referred to herein as data buffer control bus 27.

[0030] Data buffer 30 can be configured to receive commands and data from data buffer control bus 27, generate data, receive data from data bus 72, or transfer data to data bus 72. Each data path 22 also includes a bus 28 between its data buffer 30 and memory channel 42, configured to carry data between the data buffer 30 and memory channel 42. For example, as Figure 2As shown, data path 221 includes a bus 28 between data buffer 301 and memory channel 421. Data buffer 30 is configured to buffer data on buses 72 and 28 for write operations such as data transfer from memory controller 80 to the corresponding memory channel 42 and read operations such as data transfer from the corresponding memory channel 42 to memory controller 80.

[0031] In some example embodiments, data buffer 30 exchanges data with memory device 40 via bus 28 in small units such as 4-bit nibbles. In other embodiments, larger or smaller data transfer sizes may be used instead. In some cases, memory devices 40 may be arranged in multiple sets, such as two sets. For example, in a two-set / two-memory-device embodiment, such as memory devices 401 and 402, each set may contain a single memory device 40 (e.g., 401 or 402), each memory device 40 being connected to a corresponding data buffer 30 via an upper nibble and a lower nibble. In a two-set / four-memory-device embodiment, each set may contain two memory devices 40. The first set may be connected to a corresponding data buffer 30 via an upper nibble, while the second set may be connected to a corresponding data buffer 30 via a lower nibble. In a two-set / eight-memory-device embodiment, each set may contain four memory devices 40. The four memory devices 40 of the first set may be connected to a corresponding data buffer 30 via upper nibbles, while the four memory devices of the second set may be connected to a corresponding data buffer 30 via lower nibbles. Alternatively, other numbers of sets, other numbers of memory devices for each set, and other data unit sizes can be used.

[0032] The memory module 20 may also include an interface 29 configured to enable communication between the RCD 50 and the PMIC 60. For example, interface 29 may be used as part of a register clock driver / power management integrated circuit interface such as an RCD-PMIC interface. Interface 29 is configured to support one or more signals or connections, which may be bidirectional or unidirectional.

[0033] A ball grid array (BGA) is a type of surface-mount package used to mount integrated circuits. The leads are in the form of solder balls, arranged in a grid pattern on the lower surface of the package. For example, memory device 40, data buffer 30, and RCD 50 can be packaged in a ball grid array (BGA) package. Memory module 20 may include a PCB, and the BGA package containing memory device 40, data buffer 30, and RCD 50 can be soldered to the PCB of memory module 20 using the BGA solder balls. The BGA solder balls can be melted during assembly, thereby establishing electrical connections with other components mounted on the PCB. Unwanted electromagnetic coupling generated between the conductive paths of the connectors when data and signals are exchanged between memory module 20 and controller 80 can lead to signal crosstalk. This unwanted electromagnetic coupling may occur because the conductive paths are not in physical contact with each other. For BGA packages, since the solder balls connecting the BGA package to the PCB can be conductive and can be part of the signal path between the BGA package and the PCB, signal crosstalk can occur in these signal paths including the BGA solder balls.

[0034] As digital systems like DDR and serializer / deserializers increase in speed, meeting eye diagram margins at low bit error rates (BER) becomes more challenging. Signal crosstalk can be one of the factors that negatively impact system eye diagram margins, such as in systems using single-ended parallel DDR buses. In some respects, signal crosstalk can be difficult to eliminate through equalization or decision feedback equalization (DFE). One contributing factor to signal crosstalk throughout the system can be signal crosstalk originating within the package, such as single-ended signals in DDR memory systems, because signal traces and vias can be relatively close to each other, and signals can share the same negative supply voltage (VSS) BGA ball. Some conventional methods for reducing inter-signal crosstalk in high-data-rate memory systems, such as those implementing DDR6 memory channel designs, include using tapped transmission lines to increase capacitive coupling to eliminate inductive coupling, or using multilayer capacitor electrode structures interconnected through vias in the interposer layers.

[0035] As will be described in more detail below, the systems described herein may include BGA packages with a floating structure that can improve package signal crosstalk and system eye diagram margin. In one embodiment, for such... Figure 1The memory system of System 10 shown herein, including components such as memory controller 80, RCD 50, data buffer 30, memory device 40, etc., can be housed in a BGA package, and the floating structure described herein can be positioned within the BGA region of these packages for signal crosstalk reduction or elimination. The floating structure described herein can be selectively embedded in a single intermediate layer of the BGA region, such as a ground plane layer, without affecting existing signal routing. The design and implementation of the floating structure's location is relatively simple because the floating structure can be laterally positioned on a single layer, thus eliminating the need to occupy vias in the intermediate layer to connect to other layers. Adding a floating structure near BGA pads can provide effective signal crosstalk elimination because the BGA pads are also included in the signal path between the BGA package and the PCB. Furthermore, the floating structure described herein can provide signal crosstalk elimination between multiple signal paths even if the signal paths are not adjacent to each other. Moreover, because the floating structure is floating (e.g., not connected to any voltage or reference point in the system), the floating structure does not act as a signal stud and does not introduce resonance at high frequencies. Furthermore, the shape, size, and number of floating structures can be arbitrary and can be adjusted to meet the requirements of signal crosstalk cancellation at different locations and in different quantities.

[0036] Figure 3 This is a cross-sectional view of a semiconductor device including a floating structure at a packaged ball grid array for crosstalk cancellation in one embodiment. Figure 3 The description can be found here. Figure 1 and Figure 2 The components shown. Figure 3 An example BGA package 300 is shown. The BGA package 300 may include at least a device 302, an interposer 310, and a plurality of BGA balls 324-1, 324-2, 324-3, 324-4, 324-5, and 324-6 (collectively referred to as BGA balls 324). A plurality of logic components 304 (“logic 304”) may also be present in the BGA package. The device 302 may include one or more electronic components, including active and passive components and / or memory components. For example, the device 302 may be an RCD 50, a data buffer 30, a memory device 40, or other devices that may be packaged in the BGA package. The logic 304 may include logic circuitry configured to route and distribute signals transmitted from the PCB 301 to the device 302 or from the device 302 to the PCB 301 when the BGA package 300 is connected to the PCB 301.

[0037] Interposer 310 may be a multilayer structure comprising multiple layers of conductive and insulating materials for forming a network of electrical, power, and ground connections for routing signals between device 302 and PCB 301 when BGA package 300 is attached to PCB 301. The layers of interposer 310 may be formed of various materials, such as silicon or various organic materials such as epoxy resin. Conductive traces, such as trace 308, may be formed (e.g., printed) on the top surface (e.g., z-direction) of interposer 310. At least one bonding wire 306 or other bonding techniques, such as flip-chip mounting using solder bumps, may also connect device 302 to trace 308 on the top surface of interposer 310. Multiple vias, such as via 312, may be formed in multiple intermediate layers of interposer 310 (e.g., layers between the top and bottom layers of interposer 310) to provide vertical routing and connections between different layers of interposer 310.

[0038] Multiple BGA pads 322-1, 322-2, 322-3, 322-4, 322-5, and 322-6 (collectively referred to as BGA pads 322) may be formed on the bottom surface of the interposer 310 (e.g., the surface in the -z direction). The BGA pads 322 may be printed on the bottom surface of the interposer 310 by etching. The BGA pads 322 may be formed of a conductive material, such as copper. On the one hand, after printing the BGA pads 322, a solder mask layer having openings for BGA balls may be applied, exposing the BGA pads 322 on the bottom surface of the interposer 310. Multiple BGA balls 324-1, 324-2, 324-3, 324-4, 324-5, and 324-6 (collectively referred to as BGA balls 324) can be formed on the bottom surface (-z direction) of the BGA pad 322 (or the bottom surface of the exposed BGA pad 322 of the interposer layer 310). The solder paste used to form the BGA balls 324 can be various solder alloys formed of conductive materials, such as tin-silver-copper (SAC) alloys, tin-lead (Sn-Pb) alloys, or lead-free alloys. A solder mask layer prevents the solder paste used to solder the BGA balls 324 from spreading to unwanted areas. The BGA package 300 can be mounted on the PCB 301. During mounting, the BGA balls 324 can melt, thereby establishing an electrical connection between the device 302 and the PCB 301.

[0039] Bond lines 306 or other bonding techniques such as solder bumps, traces 308 on the top surface of the interposer 310, and vias 312 in the intermediate layers of the interposer 310, BGA pads 322, and BGA balls 324 can provide a signal path network between the device 302 and the PCB 301. When signals are exchanged using this signal path network, signal crosstalk may occur between adjacent and / or multiple signal paths in the network. In the various embodiments described herein, at least one floating structure may be formed in region 314 of the interposer 310 to reduce and / or eliminate signal crosstalk. Region 314 may be an intermediate layer in the interposer 310 located above the BGA pads 322 (e.g., in the z-direction). In one embodiment, region 314 may be a ground layer in the interposer 310. The floating structure in region 314 may be formed of a conductive material and may form a parallel capacitor with the BGA pads 322, thereby increasing capacitive coupling to reduce inductive coupling between signal paths including the BGA pads 322 and the BGA balls 324.

[0040] Figure 4 This is a three-dimensional diagram of a semiconductor device including a floating structure at a packaged ball grid array for crosstalk cancellation in one embodiment. Figure 4 The description can be found here. Figures 1 to 3 The components shown. In Figure 4 In one embodiment shown, the interposer 310 may include multiple layers 402-1, 402-2, and 402-3 (collectively referred to as layer 402). Layer 402-3 may be the bottom layer (-z direction) of the interposer 310 forming the BGA pads 322. BGA balls 324 may be soldered to the bottom surface of layer 402-3, which is also the bottom surface of the interposer 310. Layer 402-2 may be an intermediate layer above layer 402-3 (z direction). Layer 402-2 may be a ground layer and may include multiple ground gaps 404-2, 404-3, 404-4, and 404-5 (collectively referred to as ground gap 404) above the BGA pads 322. In one embodiment, layer 402-2 may be... Figure 3 The area shown is 314. Each signal BGA pad 322 on layer 402-3 can have a corresponding ground gap 404 above it in layer 402-2. The ground gap 404 can be a blank portion of layer 402-2, which is intentionally cut off or formed without any conductive material. Layer 402-1 can be above layer 402-2. Each layer in layer 402 can include signal traces and such... Figure 3 The via 312 in the intermediate layer 310 is used to connect signal traces on different layers 402 within the intermediate layer 310. Although Figure 4 The diagram shows three layers, but the intermediary layer 310 may include more than three layers.

[0041] In one embodiment, at least one floating structure 410 may be formed in a portion of layer 402-2, such as portion 404. In one embodiment, portion 404 may be a void in layer 402-2. In one embodiment, portion 404 may be a portion of layer 402-2 formed of a conductive material. In one embodiment, layer 402-2 may be a ground layer, and portion 404 may be a ground void. The floating structure 410 may include a plate portion 412, a plate portion 414, and a trace 416. Plate portions 412 and 414 may be metal plates, such as copper plates, and may have any shape and size. The trace 416 may be a copper trace. Plate portions 412 and 414 may be located within the ground void 404 of layer 402-2. In one embodiment, to fabricate an interposer layer 310 having at least one floating structure 410, a dielectric layer 408 formed of an insulating material, such as various dielectrics, may be deposited on layer 402-3 to cover the BGA pads 322. If the BGA ball 324 is connected to a first surface (e.g., bottom) of the BGA pad 322, a dielectric layer 408 can be deposited on a second surface (e.g., top) of the BGA pad 322 opposite to the first surface. After depositing the dielectric 408 on layer 402-3, a layer 402-2 including a portion 404 can be deposited on the dielectric layer 408. After depositing layer 402-2, at least one floating structure 410 can be deposited into the portion 404 of layer 402-2.

[0042] A capacitor, such as a parallel-plate capacitor, can be formed between the floating structure 410 with dielectric 408 and BGA pads 322. The formation of the capacitor can enhance capacitive coupling and reduce inductive coupling between the two signal paths. Figure 4 In the example shown, the board portion 412 of the floating structure 410 is placed in the ground gap 404-2, while the board portion 414 of the floating structure 410 is placed in the ground gap 404-3. Therefore, the BGA pad 322-2 and the board portion 412 in the ground gap 404-2 form a first capacitor, and the BGA pad 322-3 and the board portion 414 in the ground gap 404-3 form a second capacitor. The traces 416 connecting the board portions 412 and 414 of the floating structure 410 can also connect the formed first and second capacitors, thereby enhancing capacitive coupling.

[0043] It is important to note that the design and arrangement of the location of (one or more) floating structures 410 is flexible. The number of floating structures and their location within layer 402-2 can depend on which signal paths require reduced crosstalk and the desired amount of crosstalk reduction. On one hand, floating structures 410 may be components not electrically connected to a specific voltage or reference point within the BGA package 300. Therefore, the floating structures 410 disclosed herein can be used to enhance capacitive coupling in specific signal paths without interfering with signal routing within the BGA package 300.

[0044] Figure 5 This is a three-dimensional diagram of a semiconductor device including a floating structure at a packaged ball grid array for crosstalk cancellation in one embodiment. Figure 5 The description can be found here. Figures 1 to 4 The components shown. In Figure 5 In the embodiment shown, Figure 4 The floating structure 410 shown can be used to reduce signal crosstalk between two signal paths. For example... Figure 5 As shown, the first floating structure 502 can connect a first signal path including BGA pads 322-2 and BGA balls 324-2, and a second signal path including BGA pads 322-3 and BGA balls 324-3. The second floating structure 504 can connect the second signal path and a third signal path including BGA pads 322-4 and BGA balls 324-4. The third floating structure 506 can connect the third signal path and a fourth signal path including BGA pads 322-5 and BGA balls 324-5. Floating structures 502, 504, and 506 can be... Figure 4 A replica of the floating structure 410 shown.

[0045] Floating structures 502, 504, and 506 may not be stacked (e.g., disconnected from each other or not in contact). The shape and dimensions of the board portions 412 and 414 of floating structures 502, 504, and 506 can be designed to avoid stacking on the same BGA pad. For example, the dimensions and shape of board 414 of floating structure 502 on BGA pad 422-3 can be designed to leave sufficient space in the ground gap 404-3 for mounting board portion 412 of floating structure 504. Because floating structures 502, 504, and 506 are not stacked, Figure 5 The embodiments described herein can reduce and / or eliminate signal crosstalk between pairs of adjacent signal paths. For example, since the floating structures 502 and 504 are not stacked, there is no capacitive coupling between the signal paths including BGA pads 322-2 and 322-4. Furthermore, in Figure 5In the example shown, BGA balls 324-1 and 324-6 can be VSS BGA balls, such as BGA balls that form a path connecting device 302 to a VSS source. The floating structure described herein may not be positioned above these VSS BGA balls to prevent the floating structure from being connected to any reference point.

[0046] Figure 6 This is a three-dimensional diagram of another semiconductor device, including a floating structure at a packaged ball grid array for crosstalk cancellation, in one embodiment. Figure 6 The description can be found here. Figures 1 to 5 The components shown. In Figure 6 In the embodiment shown, Figure 4 The floating structure 410 shown may include additional board space and traces to reduce signal crosstalk between more than two signal paths. For example... Figure 6 As shown, the floating structure 602 can be a variant of the floating structure 410 with additional board portions and traces, connecting four signal paths from BGA pad 322-2 to BGA pad 322-5. The floating structure 602 can include four board portions, each of which can be positioned above the corresponding BGA pad among BGA pads 322-2 to 322-5. Furthermore, each of the four board portions of the floating structure 602 can form an independent capacitor with its corresponding BGA pad. Figure 6 In the illustrated embodiment, the four board portions of the floating structure 602 can be connected using three traces between the board portions. Therefore, four capacitors can be connected to reduce signal crosstalk across the four signal paths from BGA pad 322-2 to BGA pad 322-5.

[0047] Figure 7 This is a three-dimensional diagram of another semiconductor device, including a floating structure at a packaged ball grid array for crosstalk cancellation, in one embodiment. Figure 7 The description can be found here. Figures 1 to 6 The components shown. In Figure 7 In the embodiment shown, Figure 4 The floating structure 410 shown can have different sizes and / or shapes to reduce signal crosstalk between two or more signal paths in a two-dimensional plane. Figure 5 and Figure 6 In the illustrated embodiment, the floating structure can reduce signal crosstalk across signal paths, such as along a single lateral dimension along the x-axis. Figure 7 In the illustrated embodiment, the floating structure can reduce signal crosstalk between signal paths arranged on a transverse two-dimensional plane such as the xy plane.

[0048] like Figure 7 As shown, the first floating structure 702 can be connected with... Figure 6 Similar to floating structure 602, it can be connected across four signal paths to reduce signal crosstalk between the four signal paths. Although the shape and / or size are the same, the board portion of floating structure 702 can be in a different orientation compared to the board portion of floating structure 602. Differences in size, shape, and orientation provide ample space to add floating structures to reduce signal crosstalk between signal paths in different orthogonal lateral directions, such as different BGA pads along the x-axis and y-axis. Floating structure sets 704, 706, and 708 can be respectively connected to… Figure 5 The floating structures 502, 504, and 506 shown are similar. Floating structure 704 can connect a first signal path including BGA pad 322-2 and BGA ball 324-2, and a second signal path including BGA pad 322-3 and BGA ball 324-3. Floating structure 706 can connect the second signal path and a third signal path including BGA pad 322-4 and BGA ball 324-4. Floating structure 708 can connect the third signal path and a fourth signal path including BGA pad 322-5 and BGA ball 324-5.

[0049] and Figure 5 Compared to floating structures 502, 504, and 506, floating structures 704, 706, and 708 can have different shapes and smaller dimensions to provide space for additional floating structures. For example, BGA pad 322-3 can correspond to three different floating structures 702, 704, and 706. Floating structures 704, 706, and 708 can include additional traces for connecting to other signal paths in the -y direction. For example, floating structure 704 can include an additional trace 705 extending in the -y direction for connecting to another board portion of floating structure 704, which can correspond to a BGA pad positioned near BGA pad 322-2 in the -y direction.

[0050] Figure 8 This is a two-dimensional diagram of the arrangement of multiple floating structures at the encapsulated ball grid array for crosstalk cancellation in one embodiment. Figure 8 The description can be found here. Figures 1 to 7 The components shown. Figure 8 The layout of layer 402-3 of interposer 310 in the xy plane is shown, which includes BGA pads 322. Figure 8 The layout shown may include BGA pads 322 arranged in rows and columns. In one embodiment, various tests and / or simulations may be performed to determine the amount of signal crosstalk between different signal paths in the BGA package 300, such as unwanted coupling. The results of these tests and / or simulations may define the number, location, shape, size, orientation, or other properties of floating structures to be added above the BGA pads to reduce signal crosstalk.

[0051] exist Figure 8 In the example shown, test or simulation results may indicate relatively high levels of signal crosstalk in the BGA pads of columns 1 through 3. Therefore, various floating structures can be added above these BGA pads to reduce signal crosstalk. For example, floating structure 802 can be added to reduce or eliminate signal crosstalk between the BGA pads in row 1 from columns 1 to 3. Floating structure 802 can be a floating structure used to eliminate signal crosstalk between two or more signal paths in a lateral direction (e.g., the x-axis). Another floating structure 804 can be added to reduce or eliminate signal crosstalk between the BGA pads in rows 2 and 3 from columns 1 to 3. Floating structure 804 can be a floating structure used to eliminate signal crosstalk between two or more signal paths in two orthogonal lateral directions (e.g., the x-axis and y-axis). Another floating structure 806 can be added to reduce or eliminate signal crosstalk between two BGA pads in row 3 from columns 1 to 2. Floating structure 806 can be a floating structure used to eliminate signal crosstalk between two adjacent signal paths in a lateral direction (e.g., the x-axis). Another floating structure 808 can be added to reduce or eliminate signal crosstalk between two BGA pads from column 1 to column 2 in row 4. Floating structure 808 can be a floating structure used to eliminate signal crosstalk between two adjacent signal paths in a lateral direction (e.g., the x-axis). Both floating structures 806 and 808 can facilitate the elimination of signal crosstalk between two adjacent signal paths in a lateral direction that differ in size, shape, and orientation.

[0052] The floating structure described herein can reduce and / or eliminate signal crosstalk between two or more signal paths in a BGA package. The floating structure can be arranged on a single layer within an interposer, which is relatively less complex compared to the traditional method of adding electrodes across multiple layers. Furthermore, the arrangement on a single layer does not interfere with existing via networks across multiple layers of interposers. Moreover, the floating structure can be flexible in terms of shape, size, and location, allowing different parts of the BGA package to have different amounts of signal crosstalk reduction. Furthermore, for systems or modules comprising multiple BGA packages, such as… Figure 1 The memory system shown or Figure 2 The memory module 20 shown can have different floating structures arranged in different BGA packages according to the possible amount of signal crosstalk. For example, different numbers of floating structures can be added to the BGA package that houses the memory device 40 and the BGA package that houses the RCD 50 in the memory module 20.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “an,” and “the” used herein also include the plural forms unless the context clearly indicates otherwise. It should also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0054] All means or steps and functional elements in the following claims, including their corresponding structures, materials, actions, and equivalents, if any, are intended to include any structure, material, or action for performing a function in combination with other claimed elements of the specific claim. The disclosed embodiments of the invention are presented for purposes of illustration and description, but are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles and practical application of the invention and to enable others skilled in the art to understand the various embodiments of the invention with various modifications suitable for the intended particular purpose.

Claims

1. A semiconductor package, comprising: Semiconductor devices; Multiple ball grid array (BGA) balls; as well as Intermediary layer The semiconductor device is mounted on the interposer layer; and The intermediary layer includes: Multiple BGA pads, wherein the multiple BGA balls are attached to a first surface of the multiple BGA pads; A dielectric layer, said dielectric layer being deposited on a second surface of the plurality of BGA pads, the second surface being opposite to the first surface; and At least one floating structure is deposited on the dielectric layer, wherein the at least one floating structure and at least two of the plurality of BGA pads form at least two capacitors connected within the interposer layer.

2. The semiconductor device according to claim 1, wherein: The semiconductor device is mounted on the top layer of the interposer layer; The plurality of BGA pads are formed on the bottom layer of the interposer layer; and The at least one floating structure is formed in the intermediate layer between the topmost and bottommost layers of the intermediate layer.

3. The semiconductor device according to claim 2, wherein: The intermediate layer is the ground layer of the intermediate layer; and The at least one floating structure is formed in at least one grounding gap in the grounding layer.

4. The semiconductor device according to claim 1, wherein: The floating structure in the at least one floating structure includes a first plate portion, a second plate portion, and wiring connecting the first plate portion and the second plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; and The first BGA pad and the second BGA pad are adjacent to each other.

5. The semiconductor device according to claim 1, wherein: The at least one floating structure includes at least a first plate portion, a second plate portion, a third plate portion, a first trace connecting the first plate portion and the second plate portion, and a second trace connecting the second plate portion and the third plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; The third board portion and the third BGA pad among the plurality of BGA pads form a third capacitor; The first BGA pad and the second BGA pad are adjacent to each other in the lateral direction; and The second BGA pad and the third BGA pad are adjacent to each other in the lateral direction.

6. The semiconductor device according to claim 1, wherein: The at least one floating structure includes at least a first plate portion, a second plate portion, a third plate portion, a first trace connecting the first plate portion and the second plate portion, and a second trace connecting the second plate portion and the third plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; The third board portion forms a third capacitor with the third BGA pad among the plurality of BGA pads; and The first BGA pad and the second BGA pad are adjacent to each other in the first lateral direction; and The second BGA pad and the third BGA pad are adjacent to each other in a second lateral direction orthogonal to the first lateral direction.

7. The semiconductor device according to claim 1, wherein, The at least one floating structure does not overlap with each other.

8. A memory module, comprising: Memory devices; Multiple ball grid array (BGA) balls; as well as Intermediary layer The memory device is mounted on the interposer layer; and The intermediary layer includes: Multiple BGA pads, wherein the multiple BGA balls are attached to a first surface of the multiple BGA pads; A dielectric layer, said dielectric layer being deposited on a second surface of the plurality of BGA pads, the second surface being opposite to the first surface; and At least one floating structure is deposited on the dielectric layer, wherein the at least one floating structure and at least two of the plurality of BGA pads form at least two capacitors connected within the interposer layer.

9. The memory module according to claim 8, wherein: The semiconductor device is mounted on the top layer of the interposer layer; The plurality of BGA pads are formed on the bottom layer of the interposer layer; and The at least one floating structure is formed in the intermediate layer between the topmost and bottommost layers of the intermediate layer.

10. The memory module according to claim 9, wherein: The intermediate layer is the ground layer of the intermediate layer; and The at least one floating structure is formed in at least one grounding gap in the grounding layer.

11. The memory module according to claim 8, wherein: The floating structure in the at least one floating structure includes a first plate portion, a second plate portion, and wiring connecting the first plate portion and the second plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; and The first BGA pad and the second BGA pad are adjacent to each other.

12. The memory module according to claim 8, wherein: The at least one floating structure includes at least a first plate portion, a second plate portion, a third plate portion, a first trace connecting the first plate portion and the second plate portion, and a second trace connecting the second plate portion and the third plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; The third board portion and the third BGA pad among the plurality of BGA pads form a third capacitor; The first BGA pad and the second BGA pad are adjacent to each other in the lateral direction; and The second BGA pad and the third BGA pad are adjacent to each other in the lateral direction.

13. The memory module according to claim 8, wherein: The at least one floating structure includes at least a first plate portion, a second plate portion, a third plate portion, a first trace connecting the first plate portion and the second plate portion, and a second trace connecting the second plate portion and the third plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; The third board portion forms a third capacitor with the third BGA pad among the plurality of BGA pads; and The first BGA pad and the second BGA pad are adjacent to each other in the first lateral direction; and The second BGA pad and the third BGA pad are adjacent to each other in a second lateral direction orthogonal to the first lateral direction.

14. The memory module according to claim 8, wherein, The at least one floating structure does not overlap with each other.

15. A semiconductor structure comprising: Multiple BGA balls are attached to multiple BGA pads on a first surface of multiple BGA pads; A dielectric layer is deposited on a second surface of the plurality of BGA pads, the second surface being opposite to the first surface; as well as At least one floating structure is deposited on the dielectric layer, wherein the at least one floating structure and at least two of the plurality of BGA pads form at least two capacitors connected to each other.

16. The semiconductor structure according to claim 15, further comprising: Top floor; The bottom layer, wherein the plurality of BGA pads are formed on the bottom layer; and An intermediate layer, located between the top layer and the bottom layer, wherein the at least one floating structure is formed in the intermediate layer.

17. The semiconductor structure according to claim 16, wherein: The intermediate layer is a grounding layer; and The at least one floating structure is formed in at least one grounding gap in the grounding layer.

18. The semiconductor structure according to claim 15, wherein: The floating structure in the at least one floating structure includes a first plate portion, a second plate portion, and wiring connecting the first plate portion and the second plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; and The first BGA pad and the second BGA pad are adjacent to each other.

19. The semiconductor structure according to claim 15, wherein: The at least one floating structure includes at least a first plate portion, a second plate portion, a third plate portion, a first trace connecting the first plate portion and the second plate portion, and a second trace connecting the second plate portion and the third plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; The third board portion and the third BGA pad among the plurality of BGA pads form a third capacitor; The first BGA pad and the second BGA pad are adjacent to each other in the lateral direction; and The second BGA pad and the third BGA pad are adjacent to each other in the lateral direction.

20. The semiconductor structure according to claim 15, wherein: The at least one floating structure includes at least a first plate portion, a second plate portion, a third plate portion, a first trace connecting the first plate portion and the second plate portion, and a second trace connecting the second plate portion and the third plate portion; The first board portion forms a first capacitor with the first BGA pad among the plurality of BGA pads; The second board portion forms a second capacitor with the second BGA pad among the plurality of BGA pads; The third board portion forms a third capacitor with the third BGA pad among the plurality of BGA pads; and The first BGA pad and the second BGA pad are adjacent to each other in the first lateral direction; and The second BGA pad and the third BGA pad are adjacent to each other in a second lateral direction orthogonal to the first lateral direction.

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