AIO double-platform collaborative load balancing method and system

Abstract

The invention relates to an AIO double-platform collaborative load balancing method and system. The method comprises the following steps of S1, load quantitative modeling; s2, real-time load acquisition; wherein the value of the sum of N of the 2D detection platform and the 3D detection platform is periodically acquired, so that the load value L2D of the 2D detection platform and the load value L3D of the 3D detection platform are updated in real time; s3, performing LLF scheduling decision based on the real-time load condition; s4, carrying out abnormal adaptation; when it is detected that the platform is abnormal, the load state of the platform is automatically adjusted to avoid continuing to dispatch wafer to the platform, and therefore it is ensured that the system continuously operates to avoid stagnation. According to the method, the problems of scheduling strategy stiffness, load definition fuzziness, response lag and the like in the prior art are effectively solved, the problems of wafer queue backlog and resource idleness are avoided, and the overall utilization rate and the continuous operation capability of the system are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor automated optical inspection technology, specifically to an AIO dual-platform collaborative load balancing method and system. Background Technology

[0002] In semiconductor manufacturing, automated optical inspection (AOI) dual-platform systems are widely used for wafer defect detection. The 2D planar inspection platform is responsible for surface defect identification, while the 3D high-precision inspection platform is used for precision measurements such as height differences. However, existing scheduling mechanisms have significant flaws, severely limiting system operating efficiency.

[0003] Specifically, most devices employ a fixed-sequence transfer strategy, meaning that after a wafer completes inspection on the 2D inspection platform, it is directly transferred to the 3D platform regardless of its current load status. Similarly, when the 3D platform is idle, it can only passively wait for the 2D platform to output wafers. This rigid scheduling logic leads to wafer queue backlog during busy periods on the 3D platform due to continuous output from the 2D platform, while resources remain idle when the 3D platform is idle, resulting in low overall equipment utilization. Furthermore, traditional methods rely solely on platform idleness as a binary state criterion, failing to quantitatively analyze the load. For example, key indicators such as the length of the currently waiting wafer queue and the remaining processing time of wafers being inspected are not included, making scheduling decisions imprecise.

[0004] Meanwhile, the system lacks real-time load sensing capabilities. When the detection time changes abruptly due to process node changes, wafer type differences, or equipment malfunctions, it cannot dynamically adjust the handling strategy, resulting in drastic fluctuations in the detection cycle and affecting production continuity and system stability.

[0005] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0006] In view of the above-mentioned deficiencies of the prior art, the first aspect of the present invention provides an AIO dual-platform collaborative load balancing method, wherein the dual platforms include a 2D detection platform and a 3D detection platform, comprising the following steps: Step S1: Load quantification modeling; where the platform load value L is defined as a comprehensive index, and its formula is configured as follows: ; Where N is the length of the wafer queue currently waiting to be detected on the platform, in units of wafers; The remaining processing time of the currently monitored wafer is in seconds; α and β are adjustable weight coefficients that reflect the impact of wafer queue backlog and current task time, respectively. Step S2: Real-time load acquisition; wherein, the values of N for the 2D detection platform and the 3D detection platform are periodically acquired to update the load value L2D of the 2D detection platform and the load value L3D of the 3D detection platform in real time; Step S3: Make LLF (Least Load First) scheduling decisions based on the real-time load situation; wherein, when any detection platform completes wafer detection, the collaborative control unit compares the load of the other platform according to the real-time load status at the completion moment, and determines whether to perform cross-platform handling of the wafer or temporarily store it at the cache location according to the least load first principle; When there is already a wafer to be processed at the cache location, trigger the intelligent handling module to preferentially transport the cached wafer to the platform with a lower load based on the current real-time load status; Step S4: Abnormal adaptation; wherein, when an abnormality occurs in the detection platform, automatically adjust its load status to avoid continuing to schedule wafers to this platform, so as to ensure the continuous operation of the system and avoid stagnation. In the AIO dual-platform collaborative load balancing method as described above, optionally, in step S3, when the 2D detection platform completes wafer detection, the collaborative control unit obtains the real-time loads L2D and L3D of the two platforms at that moment and makes a comparison:

[0007] When L3D < L2D - Δ, transport the wafer from the 2D detection platform to the 3D detection platform, and at the same time update L3D = L3D + 1; When L3D ≥ L2D - Δ, control the wafer to be temporarily stored at the cache location at the exit of the 2D detection platform, and re-compare the real-time loads of the two platforms at a preset period to decide whether to perform handling; wherein, Δ is an adjustable load threshold; When the 3D detection platform completes wafer detection, the collaborative control unit updates the real-time load status, and preferentially schedules the next wafer to the 3D detection platform when L2D < L3D.

[0008] In the AIO dual-platform collaborative load balancing method as described above, optionally, in step S4, when a failure occurs in the 2D detection platform or the 3D detection platform or a sensor alarm appears, the collaborative control unit sets the real-time load value of this platform to infinity, and temporarily schedules the subsequent wafers to be processed to another normally operating platform to avoid system stagnation and ensure the continuous operation of the equipment.

[0009] ​In the AIO dual-platform collaborative load balancing method described above, optionally, the adjustable weight coefficients α, β and load threshold Δ are dynamically adjusted according to the different detection time characteristics of the type, size or process node of the wafer to be detected; Specifically, when 3D detection takes a relatively long time, the weight of the remaining detection time in the load calculation is increased by increasing β; when the 2D detection platform is more prone to queuing, the weight of the queue length in the load calculation is increased by increasing α; when the wafer detection process causes significant differences in the load between the two platforms, the sensitivity of cross-platform transfer is increased by reducing the load threshold Δ, so as to adapt to different wafer detection scenarios and maintain the load balance between the two platforms.

[0010] In the AIO dual-platform collaborative load balancing method described above, optionally, the default value of the adjustable load threshold Δ is set to 5%, α=0.6, and β=0.4.

[0011] In the AIO dual-platform collaborative load balancing method described above, optionally, the adjustable weight coefficients α and β range from 0.2 to 0.8, and α+β=1, and the load threshold Δ ranges from 2% to 15%.

[0012] In the AIO dual-platform collaborative load balancing method described above, optionally, in step S2, the N and N values ​​of the 2D detection platform and the 3D detection platform are adjusted. The sampling period for periodically collecting values ​​is configured to be 100ms.

[0013] To achieve the above objectives, a second aspect of the present invention provides an AIO dual-platform collaborative load balancing system, wherein the AIO dual-platform collaborative load balancing method as described in any of the embodiments of the first aspect above is used, comprising: dual platforms, an intelligent handling module, and a collaborative control unit. The dual platforms include: The 2D inspection platform is equipped with a 2D stage and an optical imaging module for performing surface defect inspection on wafers. The 3D inspection platform is equipped with a 3D stage using air-bearing positioning and a white light interferometry inspection module, used to perform height difference detection of the wafer; The intelligent handling module includes a robotic arm with a repeatability of ±3 μm and an anti-static vacuum adsorption assembly, configured to handle wafers between the 2D inspection platform and the 3D inspection platform; The collaborative control unit includes an industrial PC and a PLC, and is equipped with a load sensing module, an LLF scheduling module and an execution drive module. The load sensing module is used to collect the queue lengths of the 2D and 3D detection platforms and the remaining processing time of the wafers being detected, so as to generate real-time load L2D and L3D for both platforms. The LLF scheduling module is used to determine whether the wafer should be moved across platforms or temporarily stored in a cache location based on the real-time load status when wafer detection is completed on either detection platform, and to trigger the intelligent transfer module to prioritize the transfer of the wafer to the platform with a lower load when there are wafers to be processed in the cache location. The execution drive module is used to execute the corresponding wafer transfer operation after the scheduling strategy is determined, or to adjust the load status of the corresponding platform when an anomaly occurs on the detection platform, so as to maintain the continuous operation of the system.

[0014] To achieve the above objectives, a third aspect of the present invention provides a terminal device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when running the program, implements the AIO dual-platform collaborative load balancing method as described in any one of the first aspects above.

[0015] To achieve the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium storing computer-executable instructions or a computer program that, when executed by a processor, implements the AIO dual-platform collaborative load balancing method as described in any one of the first aspects above.

[0016] The present invention provides an AIO dual-platform collaborative load balancing method and system that achieves accurate quantification and dynamic balancing of dual-platform load. It has the advantages of real-time quantification of dual-platform load and intelligent scheduling through dynamic load balancing. It effectively solves the problems of rigid scheduling strategies, ambiguous load definitions and response lag in the prior art, avoids the problems of wafer queue backlog and resource idleness, and improves the overall system utilization and continuous operation capability.

[0017] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating an embodiment of an AIO dual-platform collaborative load balancing method provided by the present invention; Figure 2 Is adopted Figure 1 A schematic diagram illustrating the specific process of an embodiment of the AIO dual-platform collaborative load balancing method for detecting 12-inch wafers. Detailed Implementation

[0019] To make the technical means, inventive features, objectives, and effects of the invention readily understandable, the invention is further illustrated below with reference to specific figures. However, the invention is not limited to the embodiments described below.

[0020] It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0021] Terms such as “comprising” and “including” indicate that, in addition to the components that are directly and explicitly stated in the specification and claims, the technical solution of the present invention does not exclude the presence of other components that are not directly or explicitly stated.

[0022] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0023] In dual-platform systems for automated optical inspection of semiconductors, existing scheduling schemes fail to dynamically adapt to the real-time load differences between the 2D planar inspection platform and the 3D high-precision inspection platform, leading to reduced overall equipment utilization and fluctuations in inspection cycles. Specifically, traditional scheduling logic employs a fixed-sequence transport mechanism, where wafers are directly transferred to the 3D platform after 2D inspection without considering the current load status of the 3D platform; conversely, when the 3D platform is idle, it passively waits for output from the 2D platform. Furthermore, the platform status is judged solely by whether it is idle, without quantifying the load, such as considering waiting queue length and remaining processing time. In addition, the lack of a real-time load awareness mechanism prevents scheduling decisions from responding to sudden load changes, resulting in an imbalance in task allocation between the two platforms.

[0024] For example, in the actual operation of a semiconductor production line, when the 3D inspection platform's remaining processing time is extended due to handling complex defect analysis tasks, the 2D platform continues to output wafers that have already been inspected, causing wafer accumulation in the buffer area. Conversely, when the 3D platform completes its task ahead of schedule and is idle, it still has to wait for the 2D platform to complete its current inspection, resulting in idle platform resources. In this scenario, the ambiguous load definition makes it impossible for the scheduling unit to accurately identify the actual processing pressure of the 3D platform, and the response lag further exacerbates the wafer's dwell time in the system, manifesting as reduced effective equipment working time and interruptions in the inspection process.

[0025] If the above issues are not resolved, the dual-platform system will remain in an unbalanced operating state for a long time, with equipment utilization consistently at a low level and uncontrollable fluctuations in the testing cycle, thereby affecting the stability and throughput of the semiconductor manufacturing process. Especially when the testing platform malfunctions, a rigid scheduling strategy may lead to task backlog and overall system shutdown, making it impossible to maintain continuous production requirements.

[0026] To address this, the present invention provides an AIO dual-platform collaborative load balancing method, wherein the dual platforms include a 2D detection platform and a 3D detection platform, such as... Figure 1 As shown, it may include the following steps: Step S1: Load quantization modeling.

[0027] In step S1, the platform load value L is defined as a comprehensive index, and its formula is configured as follows: .

[0028] Where N is the length of the wafer queue currently waiting to be detected on the platform, in units of wafers. This represents the remaining processing time for the currently monitored wafer, in seconds. α and β are flexible, adjustable weighting coefficients that reflect the impact of wafer queue backlog and current task latency, respectively.

[0029] In an optional embodiment, the adjustable weighting coefficients α, β, and load threshold Δ are dynamically adjusted according to the different detection time characteristics of the type, size, or process node of the wafer to be detected.

[0030] Specifically, when 3D detection takes a relatively long time, the weight of the remaining detection time in the load calculation is increased by increasing β. When the 2D detection platform is more prone to queuing, the weight of the queue length in the load calculation is increased by increasing α. When the wafer detection process leads to significant differences in load between the two platforms, the sensitivity of cross-platform transfer is increased by decreasing the load threshold Δ to adapt to different wafer detection scenarios and maintain load balance between the two platforms.

[0031] Specifically, the time required for 2D and 3D inspection varies significantly depending on the wafer type, size, and process node, as shown in Table 1 below: Table 1 Therefore, if 3D inspection takes a relatively long time, the remaining inspection time should have a greater impact on the load, and β should be increased. If 2D inspection is easier to queue, the queue length should have a greater impact on the load, and α should be increased. If a certain type of wafer causes a naturally large difference in platform load, requiring a more stringent balance, Δ should be decreased. If wafer processing is very stable and frequent platform switching is not required, Δ should be increased.

[0032] Specifically, α, β, and the load threshold Δ can be adjusted according to the wafer type (e.g., 8-inch / 12-inch wafer) and the inspection requirements (e.g., high-precision 3D inspection, which takes longer). For example, when inspecting a 12-inch wafer (where 3D inspection takes longer), β can be increased to enhance the impact of the remaining inspection time on the load, enabling the system to adapt to different semiconductor inspection scenarios, which is superior to the fixed parameter design of existing systems.

[0033] Through the above scheme, this application can dynamically adjust the scheduling parameters according to the characteristics of the wafer, so that the load calculation model can be accurately adapted to different detection scenarios, effectively prevent overload accumulation on the 3D platform and task blocking on the 2D platform, respond to load fluctuations on both platforms in a timely manner, thereby maintaining a stable load balance and improving the overall operating efficiency of the system.

[0034] In this embodiment, the default value of the adjustable load threshold Δ is set to 5%, α=0.6, and β=0.4.

[0035] Specifically, the solution in this embodiment automatically loads preset default parameter values ​​during system initialization, ensuring that the load quantization model has a reasonable baseline at startup. When any detection platform completes wafer detection, the collaborative control unit compares L2D and L3D based on a threshold of Δ=5%. If L3D < L2D - 5%, cross-platform transfer is triggered; otherwise, it is temporarily stored in the cache. Simultaneously, the weight allocation of α=0.6 and β=0.4 ensures a scientific ratio between queue length and remaining processing time in load calculation. Especially in typical scenarios where 2D detection platforms are prone to queuing and 3D detection is time-consuming, this effectively avoids transfer decision deviations caused by improper initial parameter configuration, thereby maintaining dynamic load balance between the two platforms.

[0036] In other optional embodiments, the adjustable weighting coefficients α and β range from 0.2 to 0.8, and α+β=1, while the load threshold Δ ranges from 2% to 15%.

[0037] Specifically, the adjustable weighting coefficient α is a weighting coefficient reflecting the impact of wafer queue backlog in load quantization modeling. It can be implemented using continuous real values ​​between 0.2 and 0.8, such as dynamically setting intermediate values ​​like 0.3 or 0.7 through the software configuration interface. The purpose is to avoid α being too low, causing the queue length impact to be excessively weakened and unable to respond promptly to wafer backlog dynamics, or α being too high, causing the queue backlog to be excessively amplified and ignoring the trend of remaining processing time changes. The adjustable weighting coefficient β is a weighting coefficient reflecting the impact of the remaining processing time of the current task in load quantization modeling. It can also be implemented using continuous real values ​​between 0.2 and 0.8, and its sum with α is always equal to 1. Its purpose is to ensure that the calculated load value L has normalization characteristics, preventing quantization distortion caused by the coefficient deviating from 1, thereby supporting the accuracy of cross-platform load comparison. The load threshold Δ is a critical value used in LLF scheduling decisions to determine whether the load difference between the two platforms triggers cross-platform migration. It can be implemented as a percentage value between 2% and 15%, such as 5% or 12% through the parameter configuration module. The purpose is to avoid Δ being too low, which would cause frequent cross-platform migration operations due to small load fluctuations, thus increasing system overhead, or Δ being too high, which would cause the inability to respond to significant load differences in a timely manner, resulting in platform idleness or increased congestion.

[0038] In summary, this embodiment's solution limits α and β to the range of 0.2 to 0.8 and forces their sum to 1, ensuring that the load value L can evenly reflect the actual workload of the platform and avoid computational imbalance caused by extreme values. Simultaneously, by constraining Δ to the range of 2% to 15%, the sensitivity of scheduling decisions is effectively controlled, preventing frequent data transfers or sluggish responses due to inappropriate thresholds. This parameter range setting, combined with the load quantization model and scheduling decision mechanism, ensures the stability of load calculation and the real-time performance of scheduling response during dual-platform collaborative operation, thereby maintaining overall system load balance.

[0039] Step S2: Real-time load acquisition.

[0040] In step S2, N and 3D detection platforms are... The values ​​are periodically collected to update the load values ​​L2D of the 2D inspection platform and L3D of the 3D inspection platform in real time.

[0041] In an optional embodiment, N and 3D inspection platforms are... The periodic collection period for the value is configured to be 100ms. Here, the collection period refers to the time interval at which the system periodically obtains platform load data. It can be implemented by using a hardware timer trigger or a software polling mechanism. Specifically, this period setting aims to balance the real-time performance of load perception with system resource overhead by precisely controlling the data collection frequency, avoiding the introduction of additional computing burden due to excessively frequent collection or data lag due to excessively long collection intervals.

[0042] As a preferred embodiment, the solution of this application is implemented as follows: A timed interrupt service routine is configured in the industrial PC of the collaborative control unit. When the routine is triggered every 100ms, the current queue length N and remaining processing time of the 2D and 3D detection platforms are read through the PLC interface. The collected results are transmitted to the load sensing module for real-time load value L2D and L3D update calculations. During this process, the industrial PC's timer function is set to a precise 100ms interval to ensure that the data acquisition operation is synchronized with the wafer detection process. At the same time, the PLC is responsible for coordinating the acquisition timing of sensor signals to avoid system response delays caused by data reading conflicts.

[0043] Step S3: Make LLF scheduling decisions based on real-time load conditions.

[0044] In step S3, when any detection platform completes wafer detection, the collaborative control unit compares the load of the other platform with the real-time load status at the time of completion, and determines whether the wafer should be moved across platforms or temporarily stored in the cache location according to the principle of minimum load priority.

[0045] When there is already a wafer to be processed in the cache location, the intelligent transfer module is triggered based on the current real-time load status to prioritize the delivery of the cache wafer to the platform with a lower load.

[0046] In an optional embodiment, when the 2D detection platform completes wafer detection, the collaborative control unit obtains and compares the real-time load L2D and L3D of the two platforms at that moment: When L3D < L2D - Δ, the wafer is transferred from the 2D inspection platform to the 3D inspection platform, and L3D is updated to L3D + 1.

[0047] When L3D ≥ L2D - Δ, control the wafer to be temporarily stored at the buffer position at the exit of the 2D detection platform, and re-compare the real-time loads of the two platforms at a preset period to determine whether to perform handling. The preset period refers to the time interval for re-evaluating the load status of the two platforms, which can be configured as a fixed time period or adjusted dynamically according to the system load. Specifically, it can be implemented through a PLC timer, aiming to ensure that the system can respond to load changes in a timely manner.

[0048] Among them, Δ is an adjustable load threshold, which can be understood as the load difference critical value for triggering cross-platform handling decisions. It can be set as a percentage or an absolute value of the load value. Specifically, it can be configured through a human-machine interface, aiming to adjust the sensitivity of handling decisions according to the actual detection scenario.

[0049] When the 3D detection platform completes wafer detection, the collaborative control unit updates the real-time load status, and preferentially schedules the next wafer to the 3D detection platform when L2D < L3D.

[0050] In practical applications, the real-time loads L2D and L3D refer to the quantitative indicators reflecting the workload of the detection platform, which can be implemented by using the weighted sum of the comprehensive queue length and the remaining processing time. Specifically, it can be obtained through real-time calculation by an industrial PC, aiming to accurately represent the current working state of the platform. The buffer position refers to the temporary storage area located at the exit of the detection platform, which can be implemented by using a mechanical tray or a vacuum adsorption platform, and is used to temporarily store wafers when the loads of the two platforms are close. Its purpose is to provide a buffer space for load balancing.

[0051] Specifically, the solution of this application compares the real-time load values of the two platforms in real time when the 2D detection platform completes wafer detection, sets the decision boundary based on the adjustable load threshold Δ, and triggers cross-platform handling when the load of the 3D platform is significantly lower than that of the 2D platform, avoiding frequent handling caused by minor load fluctuations; when the load difference is insufficient, the wafer is temporarily stored at the buffer position and re-evaluated periodically, providing a buffer space for dynamic adjustment of the system. At the same time, when the 3D platform is idle, tasks are preferentially scheduled to this platform, forming a two-way load balancing mechanism, thus effectively solving the system efficiency problem caused by improper sensitivity of handling decisions.

[0052] Through the above solution, this application effectively avoids the problems of over-sensitivity or insensitivity of cross-platform handling decisions, reduces unnecessary handling operations and platform idle waiting time, and improves the overall operation efficiency and load balancing of the two-platform system.

[0053] Step S4: Abnormal adaptation.

[0054] In step S4, when an anomaly occurs on the detection platform, its load status is automatically adjusted to prevent further scheduling of wafers to that platform, thereby ensuring continuous system operation and preventing shutdowns. Real-time monitoring of the platform's operating status through fault detection can be achieved using hardware sensor signal acquisition modules or software status diagnostic algorithms, with the aim of promptly capturing abnormal equipment signals.

[0055] In an optional embodiment, when the 2D or 3D inspection platform malfunctions or a sensor alarm occurs, the collaborative control unit sets the real-time load value of the platform to infinity and temporarily schedules the subsequent wafers to be processed to another normally operating platform to avoid system shutdown and ensure continuous operation of the equipment.

[0056] Among them, the infinite load value refers to a special numerical identifier that represents the unavailable state in the load quantization model. It can be implemented by a preset maximum value threshold or logical flag bit. The purpose is to make the faulty platform automatically put into the highest load state in the minimum load priority comparison.

[0057] This embodiment triggers load status adjustment through fault detection. When the 2D or 3D detection platform malfunctions, the collaborative control unit immediately sets the real-time load value of that platform to infinity. This operation ensures that the faulty platform is at its highest load in the LLF scheduling decision within the load quantization model, thus automatically excluding it in the cross-platform handling judgment in step S3. Simultaneously, the collaborative control unit temporarily schedules subsequent wafers to another normally operating platform. This scheduling is dynamically executed based on the current real-time load status of both platforms, ensuring that the wafer transfer path is switched to available detection resources in real time, preventing wafers from accumulating at the fault point. This step, together with the load quantization modeling, real-time load acquisition, and LLF scheduling decision in steps S1-S3, forms a closed-loop control. When a platform malfunction occurs, the load perception module updates the load status of the faulty platform in real time, the LLF scheduling module reassesses the platform availability based on the updated load value, and the execution drive module drives the intelligent handling module to complete the temporary wafer scheduling operation, thereby maintaining the system's continuous operation capability under abnormal conditions.

[0058] As a specific implementation method, when the sensors of the 3D inspection platform issue an alarm signal, the load sensing module of the collaborative control unit receives the abnormal signal, the LLF scheduling module sets L3D to a logical infinity value, and the execution drive module then controls the intelligent handling module to redirect the wafer originally planned to be delivered to the 3D inspection platform to the buffer position of the 2D inspection platform. After the 2D inspection platform completes the inspection of the current wafer, it prioritizes scheduling the wafer to enter the 2D inspection platform for inspection, while continuously monitoring the recovery status of the 3D inspection platform.

[0059] With the above solution, when the detection platform malfunctions or the sensor alarms, this application can reliably remove the faulty platform from the scheduling decision and dynamically transfer the wafer task to the normal operating platform. This effectively avoids the incorrect allocation of wafers to abnormal platforms, eliminates the risk of system stagnation, and ensures the continuous detection capability of AOI equipment under abnormal operating conditions.

[0060] Through the above mechanisms, this method systematically solves the problems of rigid scheduling strategies, ambiguous load definitions, and response lag. Load quantification modeling enables scheduling decisions to be based on precise comprehensive indicators rather than fuzzy state judgments, eliminating the biases caused by queue backlogs or unquantified task time in traditional solutions. Real-time load acquisition ensures that the scheduling strategy is always based on the latest platform status, effectively addressing response delays caused by fluctuations in detection time. LLF scheduling decisions dynamically allocate wafers based on the minimum load priority principle, avoiding inefficient scenarios such as wafer accumulation during busy 3D platforms or waiting during idle periods. Simultaneously, the priority delivery mechanism for cached wafers enhances load balancing capabilities. Anomaly adaptation automatically adjusts load status to avoid faulty platforms, maintaining continuous system operation. As a result, overall equipment utilization is improved, detection cycle fluctuations are effectively suppressed, and the efficiency of dual-platform collaboration is significantly improved.

[0061] Actual testing shows that the proposed solution, through dynamic load balancing, can significantly reduce the load difference between the two platforms (from the traditional 30%-40% to ≤10%), while increasing the throughput of AOI equipment by 10%-20% and enhancing the operational stability of the equipment, thus meeting the core requirements of "high efficiency, stability, and accuracy" for wafer inspection in semiconductor manufacturing.

[0062] To achieve the above objectives, this application further proposes an AIO dual-platform collaborative load balancing system, which uses the AIO dual-platform collaborative load balancing method as described in any of the foregoing embodiments, specifically including dual platforms, an intelligent handling module, and a collaborative control unit.

[0063] The dual-platform system includes a 2D inspection platform and a 3D inspection platform. The 2D inspection platform is equipped with a 2D stage and an optical imaging module for inspecting surface defects on the wafer. The 3D inspection platform is equipped with an air-bearing positioning 3D stage and a white light interferometry module for inspecting height differences on the wafer.

[0064] The intelligent handling module includes a robotic arm with a repeatability of ±3 μm and an anti-static vacuum adsorption assembly, configured to handle wafers between 2D and 3D inspection platforms.

[0065] The collaborative control unit includes an industrial PC and a PLC, and is equipped with a load sensing module, an LLF scheduling module, and an execution drive module.

[0066] The load perception module collects the queue lengths and remaining processing time of the wafers being inspected on both the 2D and 3D inspection platforms to generate real-time load L2D and L3D for both platforms. The LLF scheduling module determines whether a wafer should be moved across platforms or temporarily stored in a cache location based on the real-time load status when wafer inspection is completed on either platform. If a wafer is available for processing in the cache, the intelligent transfer module is triggered to prioritize its transfer to a platform with a lower load. The execution driver module executes the corresponding wafer transfer operation after the scheduling strategy is determined, or adjusts the load status of the corresponding platform when an anomaly occurs on the inspection platform to maintain continuous system operation.

[0067] Taking the above-mentioned AIO dual-platform collaborative load balancing method for detecting a 12-inch wafer as an example, such as... Figure 2 As shown: First, the device parameters for this embodiment are as follows: 2D platform: Single wafer detection time is 180±1 seconds, and the cache capacity is 1 chip; 3D platform: Single wafer detection time X ± 2 seconds, buffer capacity 1 chip; Robotic arm: single movement takes 2 seconds, load acquisition cycle is 100ms; Weighting coefficients: α=0.6, β=0.4, load threshold Δ=5%.

[0068] The specific AIO dual-platform collaborative load balancing process in the system is as follows: Initial state: L2D=0, L3D=0, both platforms are idle.

[0069] First wafer: 00:00 Enters the 2D inspection platform, automatically calculates the inspection time, and updates L2D to 0.6×0 + 0.4×180=72.6.

[0070] 03:00: 2D inspection complete. At this time, L3D=0, L2D=0.6×1 (a new wafer enters the queue) + 0.4×0=0.6. Since L3D < L2D-Δ (0 < 0.6-0.03), the robot moves to the 3D inspection platform. The 3D platform inspection time is 250, and L3D is updated to 0.6×1 + 0.4×250=100.6.

[0071] 03:10: The second wafer enters the 2D inspection platform, L2D=0.6×1 + 0.4×180=72.6.

[0072] 06:10: The 2D inspection platform completes the inspection of the second wafer. At this time, the remaining inspection time of the 3D inspection platform is 250-190=60s. L3D=0.6×1 + 0.4×60=24.6, L2D=0.6×1 (the third wafer enters) + 0.4×0=0.6. Since L3D(4.6) ≥ L2D-Δ(0.6-0.03), the second wafer is temporarily stored in the cache location of the 2D inspection platform.

[0073] 11:10: The 3D platform completes the inspection of the first wafer, L3D=0, and immediately triggers the robotic arm to transfer the temporarily stored second wafer to the 3D inspection platform, achieving seamless connection.

[0074] The specific implementation method has been described in detail above and will not be repeated here.

[0075] To achieve the above objectives, the present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor runs the program, it can implement the steps of the AIO dual-platform collaborative load balancing method as described in any of the foregoing embodiments.

[0076] Processors and memory can be configured separately or integrated together, for example, integrated on a system-on-chip (SOC) in a terminal device.

[0077] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing computer-executable instructions or computer programs, which, when processed and executed, implement the AIO dual-platform collaborative load balancing method as described above.

[0078] The computer-readable storage medium is, for example, memory. Memory can be volatile or non-volatile, or it can include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM).

[0079] If the integrated units in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in the aforementioned computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause one or more computer devices (which may be personal computers, servers, or network devices, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0080] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A dual-platform collaborative load balancing method for AIO, characterized in that, The dual platform includes a 2D inspection platform and a 3D inspection platform, and includes the following steps: Step S1: Load quantification modeling; where the platform load value L is defined as a comprehensive index, and its formula is configured as follows: ； Where N is the length of the wafer queue currently waiting to be detected on the platform, in units of wafers; The remaining processing time of the currently monitored wafer is in seconds; α and β are adjustable weight coefficients that reflect the impact of wafer queue backlog and current task time, respectively. Step S2: Real-time load acquisition; whereby N and 3D inspection platforms are used for both the 2D and 3D inspection platforms. The values ​​are periodically collected to update the load values ​​L2D of the 2D inspection platform and L3D of the 3D inspection platform in real time. Step S3: Make LLF scheduling decisions based on real-time load conditions; wherein, when any detection platform completes wafer detection, the collaborative control unit compares the load of the other platform with the real-time load status at the time of completion, and determines whether the wafer should be moved across platforms or temporarily stored in the cache location according to the principle of minimum load priority. When there is already a wafer to be processed at the cache location, the intelligent transfer module is triggered based on the current real-time load status to prioritize the delivery of the cache wafer to the platform with a lower load. Step S4: Anomaly adaptation; whereby, when an anomaly occurs in the detection platform, its load status is automatically adjusted to avoid continuing to schedule wafers to that platform, thereby ensuring continuous system operation and avoiding stagnation.

2. The AIO dual-platform collaborative load balancing method according to claim 1, characterized in that, In step S3, when the 2D detection platform completes wafer detection, the collaborative control unit obtains and compares the real-time loads L2D and L3D of the two platforms at that moment: When L3D < L2D - Δ, the wafer is transferred from the 2D inspection platform to the 3D inspection platform, and L3D is updated to L3D + 1. When L3D ≥ L2D - Δ, the control wafer is temporarily stored in the cache position at the exit of the 2D detection platform, and the real-time load of the two platforms is re-compared at a preset period to determine whether to perform the transfer. Where Δ is the adjustable load threshold; When the 3D inspection platform completes wafer inspection, the collaborative control unit updates the real-time load status and prioritizes scheduling the next wafer to the 3D inspection platform if L2D < L3D.

3. The AIO dual-platform collaborative load balancing method according to claim 2, characterized in that, In step S4, when the 2D or 3D inspection platform malfunctions or a sensor alarm occurs, the collaborative control unit sets the real-time load value of the platform to infinity and temporarily schedules the subsequent wafers to be processed to another normally operating platform to avoid system shutdown and ensure continuous operation of the equipment.

4. The AIO dual-platform collaborative load balancing method according to claim 2, characterized in that, The adjustable weighting coefficients α and β, as well as the load threshold Δ, are dynamically adjusted according to the different detection time characteristics of the wafer to be detected, such as its type, size, or process node. Specifically, when 3D detection takes a relatively long time, the weight of the remaining detection time in the load calculation is increased by increasing β; when the 2D detection platform is more prone to queuing, the weight of the queue length in the load calculation is increased by increasing α; when the wafer detection process causes significant differences in the load between the two platforms, the sensitivity of cross-platform transfer is increased by reducing the load threshold Δ, so as to adapt to different wafer detection scenarios and maintain the load balance between the two platforms.

5. The AIO dual-platform collaborative load balancing method according to claim 2, characterized in that, The default value for the adjustable load threshold Δ is set to 5%, α=0.6, β=0.

4.

6. The AIO dual-platform collaborative load balancing method according to claim 2, characterized in that, The adjustable weighting coefficients α and β range from 0.2 to 0.8, and α+β=1. The load threshold Δ ranges from 2% to 15%.

7. The AIO dual-platform collaborative load balancing method according to claim 1, characterized in that, In step S2, N and 3D detection platforms are... The sampling period for periodically collecting values ​​is configured to be 100ms.

8. An AIO dual-platform collaborative load balancing system, characterized in that, The AIO dual-platform collaborative load balancing method as described in any one of claims 1 to 7 includes: dual platforms, an intelligent handling module, and a collaborative control unit; The dual platforms include: The 2D inspection platform is equipped with a 2D stage and an optical imaging module for performing surface defect inspection on wafers. The 3D inspection platform is equipped with a 3D stage using air-bearing positioning and a white light interferometry inspection module, used to perform height difference detection of the wafer; The intelligent handling module includes a robotic arm with a repeatability of ±3 μm and an anti-static vacuum adsorption assembly, configured to handle wafers between the 2D inspection platform and the 3D inspection platform; The collaborative control unit includes an industrial PC and a PLC, and is equipped with a load sensing module, an LLF scheduling module and an execution drive module. The load sensing module is used to collect the queue lengths of the 2D and 3D detection platforms and the remaining processing time of the wafers being detected, so as to generate real-time load L2D and L3D for both platforms. The LLF scheduling module is used to determine whether the wafer should be moved across platforms or temporarily stored in a cache location based on the real-time load status when wafer detection is completed on either detection platform, and to trigger the intelligent transfer module to prioritize the transfer of the wafer to the platform with a lower load when there are wafers to be processed in the cache location. The execution drive module is used to execute the corresponding wafer transfer operation after the scheduling strategy is determined, or to adjust the load status of the corresponding platform when an anomaly occurs on the detection platform, so as to maintain the continuous operation of the system.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor runs the program, it implements the AIO dual-platform collaborative load balancing method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions or computer programs, which, when processed and executed by a processor, implement the AIO dual-platform collaborative load balancing method as described in any one of claims 1 to 7.

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