Cross-clock domain data transmission circuit, method and system

Abstract

The invention relates to the technical field of digital circuits, and discloses a cross-clock domain data transmission circuit, method and system, and the circuit comprises a clock generation module which is configured to receive a transmitting clock signal of a transmitting clock domain and a capturing clock signal of a capturing clock domain, and generate a gated transmitting clock signal and a gated capturing clock signal which are the same in frequency; the phase alignment control module is connected with the clock generation module and is configured to adjust the phase of the gated capture clock signal so as to establish a fixed phase relationship between the gated capture clock signal and the gated emission clock signal; and the data sampling module is connected with the phase alignment control module and the clock generation module, and is configured to sample the multi-bit data of the transmitting clock domain to the capturing clock domain based on the fixed phase relationship. According to the method and the device, the technical problems of limited transmission rate and large delay caused by phase randomness of the asynchronous clock in related technologies are solved, and high-reliability and low-delay cross-clock-domain data transmission is realized.

Description

Technical Field

[0001] This application relates to the field of digital circuit technology, specifically to cross-clock domain data transmission circuits, methods, and systems. Background Technology

[0002] Modern complex digital systems typically contain multiple clock domains. When signals or data are transmitted from one clock domain to another asynchronous clock domain, the two clocks have no definite relationship in phase and frequency, leading to metastability problems. The propagation of metastability can cause a wider range of failures, such as incorrect calculations in logic or state machines entering illegal states, resulting in system malfunctions. Therefore, data transmission across clock domains must be handled by specialized circuitry, typically a synchronizer, to ensure correct data transmission.

[0003] Secondly, as high-speed circuits place increasingly higher demands on performance and require the lowest possible transmission delay, and since crossing clock domains takes relatively more time, further improvements are needed for asynchronous circuits to minimize their delay. Summary of the Invention

[0004] This application provides a cross-clock domain data transmission circuit, method, and system to solve the problems of limited cross-clock domain data transmission rate and large delay in related technologies.

[0005] In a first aspect, this application provides a cross-clock domain data transmission circuit, comprising: a clock generation module configured to receive a transmit clock signal in a transmit clock domain and a capture clock signal in a capture clock domain, and generate a gated transmit clock signal and a gated capture clock signal with the same frequency; a phase alignment control module connected to the clock generation module, configured to adjust the phase of the gated capture clock signal to establish a fixed phase relationship between the gated capture clock signal and the gated transmit clock signal; and a data sampling module connected to the phase alignment control module and the clock generation module, configured to sample multi-bit data from the transmit clock domain to the capture clock domain based on the fixed phase relationship.

[0006] Beneficial Effects: This application achieves fundamental optimization of cross-clock domain data transmission by setting up a collaborative architecture of a clock generation module, a phase alignment control module, and a data sampling module. The clock generation module converts raw clocks of different frequencies into gated clocks of the same frequency, laying the foundation for establishing a stable timing relationship; the phase alignment control module actively adjusts the phase of the acquisition clock to establish a fixed phase relationship between the transmit clock and the acquisition clock, effectively eliminating the problem of a narrow sampling timing window caused by phase uncertainty in traditional synchronizers; the data sampling module achieves data synchronization based on this fixed phase relationship, maximizing both the setup time and hold time margin of data transmission. These technical features work together to fundamentally solve the technical problems of limited transmission rate and large delay caused by the randomness of asynchronous clock phase in related technologies, achieving highly reliable and low-latency cross-clock domain data transmission.

[0007] In one alternative implementation, the fixed phase relationship is configured such that the rising edge of the gated capture clock signal is aligned with the falling edge of the gated transmit clock signal.

[0008] Beneficial effects: By specifically defining the fixed phase relationship as aligning the rising edge of the gated capture clock with the falling edge of the gated transmit clock, the sampling time is ensured to be located at the center of the valid data window, achieving an ideal state where the setup time margin and hold time margin are approximately equal. This not only guarantees sampling reliability but also stably controls the transmission delay to the minimum theoretical value of half a transmit clock cycle, which helps reduce transmission delay and improve timing margin.

[0009] In one optional implementation, the clock generation module includes: a frequency division unit configured to perform frequency division processing on the transmit clock signal and the capture clock signal respectively; and a gating unit connected to the frequency division unit configured to gating the frequency-divided transmit clock signal and the capture clock signal to generate a gated transmit clock signal and a gated capture clock signal with the same frequency.

[0010] Beneficial Effects: Through the collaborative design of the frequency divider and gating units, a flexible and reliable clock processing mechanism is achieved. The frequency divider unit performs configurable frequency division on the original clock, enabling this application to adapt to clock domain interaction scenarios with various frequency ratios; the gating unit ensures that the generated gated clock has pure timing characteristics. While achieving same-frequency clock generation, the adjustable frequency division ratio expands the application range of the circuit, and the gating process effectively avoids the impact of clock jitter on sampling accuracy, providing a high-quality timing foundation for subsequent phase alignment and data sampling.

[0011] In one optional implementation, the phase alignment control module includes: a digital control unit configured to receive the gated transmit clock signal and the gated capture clock signal, and generate and output digital control code based on the phase difference between the gated capture clock signal and the gated transmit clock signal; and a phase mixing unit connected to the digital control unit and the clock generation module, configured to receive the digital control code and the gated capture clock signal, and adjust the phase of the gated capture clock signal according to the digital control code, so as to establish the fixed phase relationship between the gated capture clock signal and the gated transmit clock signal.

[0012] Beneficial effects: The digital control unit detects the phase difference between two gated clocks in real time and generates precise control codes. The phase mixer fine-tunes the clock phase according to the codes, forming a complete feedback control loop. This scheme can automatically compensate for timing deviations caused by process, voltage, and temperature variations, ensuring that the fixed phase relationship remains stable under various operating conditions, significantly improving the robustness and reliability of the system.

[0013] In one optional implementation, the data sampling module includes a data splitting unit configured to split the sampled data located in the capture clock domain into N data segments when the frequency ratio between the transmit clock signal and the capture clock signal is 1:N, and output them sequentially over N consecutive clock cycles in the capture clock domain; wherein N is an integer greater than 1.

[0014] Beneficial Effects: For 1:N frequency ratio transmission scenarios, the data splitting unit helps achieve bandwidth matching while maintaining low latency. This unit splits the sampled wide-bit data into multiple data segments and outputs them sequentially over several consecutive capture clock cycles. This utilizes the low latency characteristics brought by the fixed phase relationship and solves the bit width mismatch problem through time-division multiplexing. This scheme significantly improves data transmission efficiency and avoids bandwidth waste.

[0015] In one optional implementation, the data splitting unit is further configured to generate a first intermediate signal in the capture clock domain, and select and sequentially output corresponding data segments according to the current value of the first intermediate signal; wherein the value of the first intermediate signal cyclically changes between 0 and N-1.

[0016] Beneficial effects: By introducing a cyclic tagging signal control mechanism, precise timing management of data splitting is achieved. The tagging signal cycles between 0 and N-1, providing a unique identifier for each data segment and ensuring that the split data is output in the correct order. This scheme prevents data misalignment or loss, simplifies the data reassembly logic at the receiving end, and further improves the system's reliability and ease of use.

[0017] In one optional implementation, the data sampling module includes a data splicing unit configured to splice multiple bits of data within N consecutive clock cycles of the transmit clock domain into a data block for sampling by the gated capture clock signal when the frequency ratio between the transmit clock signal and the capture clock signal is N:1; wherein N is an integer greater than 1.

[0018] Beneficial Effects: For N:1 frequency ratio transmission scenarios, the data splicing unit effectively integrates high-speed data streams. This unit splices data from multiple clock cycles into a single data block for one-time sampling by the capture clock domain, solving the data throughput matching problem between the high-speed and low-speed domains. This scheme fully utilizes the stable sampling window provided by the fixed phase relationship, avoiding the complex storage control logic required by traditional asynchronous FIFOs while ensuring reliability, thus reducing implementation complexity and area overhead.

[0019] In one alternative implementation, the data splicing unit is configured to delay the data through a delay chain consisting of N-1 flip-flops to achieve splicing, and to generate a second intermediate signal in the transmit clock domain, wherein the sampling timing is controlled by the second intermediate signal at the clock alignment edge determined by the fixed phase relationship.

[0020] Beneficial Effects: The splicing scheme employing a delay chain and marker signal co-control achieves an optimal balance between hardware efficiency and timing accuracy. The delay chain uses multi-stage triggers to ensure precise data alignment, while the marker signal triggers sampling at specific moments determined by a fixed phase relationship, ensuring that the spliced ​​data is captured within the optimal timing window. This scheme guarantees the reliability of data splicing while maximizing the advantages of the phase relationship through precise timing control.

[0021] In an optional implementation, the data sampling module is further configured to: when the frequency ratio between the transmit clock signal and the capture clock signal is 1:1, directly sample the multi-bit data of the transmit clock domain into the capture clock domain.

[0022] Beneficial Effects: For 1:1 same-frequency transmission scenarios, this application achieves extremely simple and efficient data transmission through a direct sampling mechanism. Under the condition of the same clock frequency, the data sampling module does not require additional splitting or splicing processing, and directly utilizes the fixed phase relationship for sampling. While simplifying the circuit structure, it still maintains the low latency and high reliability advantages brought by the fixed phase relationship, providing a reliable solution for same-frequency clock domain interaction.

[0023] Secondly, this application provides a method for cross-clock domain data transmission, comprising: processing a transmit clock signal in a transmit clock domain and a capture clock signal in a capture clock domain to generate a gated transmit clock signal and a gated capture clock signal with the same frequency; adjusting the phase of the gated capture clock signal to establish a fixed phase relationship between the gated capture clock signal and the gated transmit clock signal; and, based on the fixed phase relationship, sampling multi-bit data from the transmit clock domain to the capture clock domain under the control of the gated capture clock signal.

[0024] In one optional implementation, adjusting the phase of the gated capture clock signal includes: adjusting the phase of the gated capture clock signal so that the rising edge of the gated capture clock signal is aligned with the falling edge of the gated transmit clock signal.

[0025] In an optional implementation, the method further includes: when the frequency ratio between the transmit clock signal and the capture clock signal is 1:N, splitting the sampled data located in the capture clock domain into N data segments, and outputting them sequentially over N consecutive clock cycles in the capture clock domain.

[0026] In an optional implementation, the method further includes: when the frequency ratio between the transmit clock signal and the capture clock signal is N:1, concatenating multi-bit data within N consecutive clock cycles of the transmit clock domain into a data block.

[0027] In an optional implementation, the method further includes: when the frequency ratio between the transmit clock signal and the capture clock signal is 1:1, directly sampling the multi-bit data of the transmit clock domain into the capture clock domain.

[0028] Thirdly, this application provides a cross-clock domain data transmission system, comprising: a cross-clock domain data transmission circuit according to the first aspect above or any corresponding embodiment; a clock source for providing a transmit clock signal and a capture clock signal to the cross-clock domain data transmission circuit; and a data source for providing data to be transmitted to the cross-clock domain data transmission circuit. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1This is a schematic diagram of a cross-clock domain data transmission circuit according to an embodiment of this application; Figure 2 This is a structural block diagram of a cross-clock domain data transmission circuit according to an embodiment of this application; Figure 3 This is a timing diagram of a clock at the same frequency across asynchronous frequencies according to an embodiment of this application; Figure 4 This is a timing diagram for asynchronous operation with a slow clock to fast clock ratio of 1:3 according to an embodiment of this application; Figure 5 This is a structural block diagram of a fast-clock to slow-clock cross-clock domain data transmission circuit according to an embodiment of this application; Figure 6 This is a timing diagram of an asynchronous circuit with a fast clock to slow clock ratio of 3:1 according to an embodiment of this application; Figure 7 This is a flowchart illustrating a cross-clock domain data transmission method according to an embodiment of this application; Figure 8 This is a schematic diagram of a cross-clock domain data transmission system according to an embodiment of this application.

[0031] Explanation of the reference numerals in the figure: 1. Cross-time domain data transmission system; 10. Cross-time domain data transmission circuit; 20. Clock source; 30. Data source; 100. Clock generation module; 200. Phase alignment control module; 210. Digital control unit; 220. Phase mixing unit; 300. Data sampling module; 310. Data splitting unit; 320. Data splicing unit. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] It is understood that before using the technical solutions disclosed in the various embodiments of this application, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this application in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0034] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] Modern complex digital systems typically contain multiple clock domains. When signals or data are transmitted between asynchronous clock domains, the uncertainty of clock phase and frequency relationships can lead to metastability issues, potentially causing logic calculation errors or state machine anomalies, thus affecting system reliability. To ensure correct data transmission, dedicated circuits such as synchronizers must be used for processing. As the performance requirements of high-speed circuits continue to increase, reducing transmission delay has become a critical requirement, and the cross-clock domain transmission process often introduces significant delays, necessitating improvements.

[0037] Among related technologies, solutions for multi-bit cross-clock domain transmission mainly include two types: data distributor (Dmux) and asynchronous first-in-first-out (FIFO) processing. The Dmux scheme synchronizes the data by timing the effective control signal of the transmit clock domain, capturing multi-bit data after successful synchronization. However, this method requires data to remain on the transmitting side for at least four capture clock cycles, limiting the maximum transmission rate and resulting in significant transmission latency. The asynchronous FIFO scheme avoids read / write conflicts through Gray code conversion of read / write pointers and a synchronization mechanism. While capable of handling high-speed data streams, it still requires multiple synchronization operations, resulting in a read latency of at least four clock cycles after writing, leading to relatively high transmission latency.

[0038] It is evident that while achieving reliable transmission, the relevant technical solutions all struggle to simultaneously meet the demands for low latency and high bandwidth.

[0039] Reference Figure 1As shown in the embodiment of this application, a cross-clock domain data transmission circuit is provided, including a clock generation module 100, a phase alignment control module 200, and a data sampling module 300, wherein the phase alignment control module 200 is connected to the clock generation module 100, and the data sampling module 300 is connected to both the phase alignment control module 200 and the clock generation module 100.

[0040] Specifically, the clock generation module 100 is configured to receive the transmit clock signal in the transmit clock domain and the capture clock signal in the capture clock domain, and generate a gated transmit clock signal and a gated capture clock signal with the same frequency. The phase alignment control module 200 is configured to adjust the phase of the gated capture clock signal to establish a fixed phase relationship between the gated capture clock signal and the gated transmit clock signal; The data sampling module 300 is configured to sample multi-bit data from the transmit clock domain to the capture clock domain based on a fixed phase relationship.

[0041] Reference Figure 2 As shown, the clock generation module 100 corresponds to the clkgen module in the figure. It converts transmit clocks (clk1) and capture clocks (clk2) with potentially different frequencies into gated transmit clock signals (clk1_gated) and gated capture clock signals (clk2_gated) of the same frequency through frequency division and gating operations. Here, "gating" refers to generating clock signals with clean timing characteristics suitable for subsequent processing through logic control.

[0042] Corresponding to Figure 2 In the middle, the phase alignment control module 200 includes clk_align_ctrl and phase_mix. Through a closed-loop feedback mechanism, it dynamically adjusts the phase of clk2_gated, thereby establishing a fixed phase relationship between the two. This fixed phase relationship is used to ensure that the sampling point is located in the center of the data valid window.

[0043] The data sampling module 300 utilizes the established fixed phase relationship to achieve reliable data transmission from the transmit clock domain to the capture clock domain through circuits such as flip-flops (FF1, FF2).

[0044] This application achieves fundamental optimization of cross-clock domain data transmission by setting up a collaborative architecture of a clock generation module 100, a phase alignment control module 200, and a data sampling module 300. The clock generation module 100 converts raw clocks of different frequencies into gated clocks of the same frequency, laying the foundation for establishing a stable timing relationship. The phase alignment control module 200 actively adjusts the phase of the acquisition clock to establish a fixed phase relationship between the transmit and acquisition clocks, effectively eliminating the problem of a narrow sampling timing window caused by phase uncertainty in traditional synchronizers. The data sampling module 300 achieves data synchronization based on this fixed phase relationship, maximizing both the setup and hold time margins for data transmission. These combined technical features fundamentally solve the technical problems of limited transmission rate and high latency caused by the randomness of asynchronous clock phases in related technologies, achieving highly reliable and low-latency cross-clock domain data transmission.

[0045] Optionally, in some embodiments of this application, the fixed phase relationship is configured such that the rising edge of the gated capture clock signal is aligned with the falling edge of the gated transmit clock signal.

[0046] Corresponding to Figure 2 In this configuration, the rising edge of the gated capture clock (clk2_gated) is aligned with the falling edge of the gated transmit clock (clk1_gated). When data is latched by the transmitter on the rising edge of clk1_gated, its valid data window is approximately located between that rising edge and the next rising edge. The rising edge of clk2_gated is aligned with the falling edge of clk1_gated, i.e., aligned with the center of the valid data window. This alignment ensures that the sampling point is approximately half a clock cycle (T1 / 2) away from both boundaries of the data change (the previous rising edge of clk1_gated and the next rising edge of clk1_gated), thus making the setup time margin and hold time margin close to T1 / 2, achieving a balance and maximization of margins.

[0047] In these embodiments, by specifically defining the fixed phase relationship as aligning the rising edge of the gated capture clock with the falling edge of the gated transmit clock, it is ensured that the sampling time is located at the center of the valid data window, making the setup time margin and hold time margin approximately equal. This not only guarantees sampling reliability but also stably controls the transmission delay to the minimum theoretical value of half a transmit clock cycle, which helps to reduce transmission delay and improve timing margin.

[0048] Optionally, in some embodiments of this application, the clock generation module 100 includes a frequency division unit and a gating unit connected to the frequency division unit. The frequency division unit is configured to perform frequency division processing on the transmit clock signal and the capture clock signal respectively, and the gating unit is configured to gate the frequency-divided transmit clock signal and capture clock signal to generate a gated transmit clock signal and a gated capture clock signal with the same frequency.

[0049] More specifically, the frequency divider here functions to normalize frequencies across clock domains. For example, when the frequency ratio of the transmit clock (clk1) to the capture clock (clk2) is N:1, the higher-frequency clk1 can be divided by N, resulting in a gated transmit clock (clk1_gated) with the same frequency as the gated capture clock (clk2_gated) generated by dividing clk2 by 1 (i.e., keeping it unchanged). The gating circuit shapes and enables the divided clock, eliminating glitches and providing a stable clock signal that is easy for subsequent circuits to use. By configuring different division ratios (1:1, 1:N, N:1), this module allows the invention to flexibly adapt to various application scenarios.

[0050] In these embodiments, a flexible and reliable clock processing mechanism is achieved through the collaborative design of the frequency division unit and the gating unit. The frequency division unit performs configurable frequency division processing on the original clock, enabling this application to adapt to clock domain interaction scenarios with various frequency ratio relationships; the gating unit ensures that the generated gated clock has pure timing characteristics. While achieving the generation of clocks at the same frequency, the adjustable frequency division ratio expands the application range of the circuit, and the gating processing effectively avoids the impact of clock jitter on sampling accuracy, providing a high-quality timing foundation for subsequent phase alignment and data sampling.

[0051] Optionally, in some embodiments of this application, the phase alignment control module 200 includes a digital control unit 210 and a phase mixing unit 220, wherein the phase mixing unit 220 is connected to both the digital control unit 210 and the clock generation module 100.

[0052] Specifically, the digital control unit 210 is configured to receive a gating transmit clock signal and a gating capture clock signal, and generate and output digital control code based on the phase difference between the gating capture clock signal and the gating transmit clock signal.

[0053] The phase mixing unit 220 is connected to the digital control unit 210 and the clock generation module 100, and is configured to receive digital control codes and gated capture clock signals, and adjust the phase of the gated capture clock signal according to the digital control codes so as to establish a fixed phase relationship between the gated capture clock signal and the gated transmit clock signal.

[0054] It should be noted that the digital control unit 210 corresponds to Figure 2 The clk_align_ctrl in the code is essentially a combination of a phase detector and a digital controller. Its function is to quantify the phase difference between clk2_gated and clk1_gated and output a multi-bit wide digital control code (DAC_CODE). The value of this code is proportional to the magnitude and direction of the phase difference.

[0055] Phase mixing unit 220 corresponds to Figure 2 The Phase Mixer is a circuit that can finely adjust the clock phase. It can select or weight and synthesize an output clock from multiple clock sources 20 with small phase differences according to the input digital control code, thereby achieving precise and digital adjustment of the clk2_gated phase.

[0056] In these embodiments, the digital control unit 210 detects the phase difference between the two gated clocks in real time and generates precise control codes. The phase mixer fine-tunes the clock phase according to the codes, forming a complete feedback control loop. This scheme can automatically compensate for timing deviations caused by process, voltage, and temperature variations, ensuring that the fixed phase relationship remains stable under various operating conditions, significantly improving the robustness and reliability of the system.

[0057] Optionally, in some embodiments of this application, the data sampling module 300 is further configured to: directly sample multi-bit data from the transmission clock domain into the capture clock domain when the frequency ratio between the transmission clock signal and the capture clock signal is 1:1.

[0058] It should be noted that in a 1:1 same-frequency scenario, the data bandwidths of the transmit and acquire sides naturally match, so there is no need for data width conversion. The data sampling module 300 performs direct sampling, that is, using a fixed phase relationship established through phase alignment, the capture trigger (such as FF2) directly samples the output data of the transmit trigger (such as FF1). At this time, the fixed phase relationship ensures low latency and high timing margin of the circuit.

[0059] Reference Figure 3 As shown in the timing diagram, at the same frequency, the waveforms of clk1_gated and clk2_gated are identical to those of clk1 and clk2, respectively. When the rising edge of the clk2_gated clock aligns with the falling edge of the clk1_gated clock, the multi-bit data FF2_D in the clk1 clock domain can be directly sampled by clk2, and then transferred to the clk2 clock domain after T1 / 2. That is, the data path delay stabilizes at half a transmit clock cycle (T1 / 2), and the setup and hold time margin is maximized.

[0060] In these embodiments, for 1:1 same-frequency transmission scenarios, this application achieves extremely simple and efficient data transmission through a direct sampling mechanism. Under the condition of the same clock frequency, the data sampling module 300 does not require additional splitting or splicing processing, directly utilizing a fixed phase relationship for sampling. While simplifying the circuit structure, it still maintains the low latency and high reliability advantages brought by the fixed phase relationship, providing a reliable solution for same-frequency clock domain interaction.

[0061] Optionally, in some embodiments of this application, the data sampling module 300 includes: a data splitting unit 310, configured to split the sampled data located in the capture clock domain into N data segments when the frequency ratio between the transmit clock signal and the capture clock signal is 1:N, and output them sequentially in N consecutive clock cycles of the capture clock domain; wherein, N is an integer greater than 1.

[0062] It should be noted that data splitting unit 310 corresponds to Figure 2 The `comb_B` function in this unit performs data width conversion. When the capture clock frequency is N times the transmit clock frequency (1:N), the amount of data that the capture side can process per unit time is greater. This unit treats the wide-bit data sampled from the capture clock domain (whose bit width is N times that of the original transmit data) as being composed of N data segments. By sequentially outputting these data segments over N consecutive high-speed capture clock cycles (e.g., outputting the low 1 / N segment in the first cycle, the middle 1 / N segment in the second cycle, ..., and the high 1 / N segment in the Nth cycle), the conversion from "low-speed wide data" to "high-speed narrow data" is completed. This time-division multiplexing output mechanism ensures that after the cross-clock domain transmission is completed with low latency (only half a transmit clock cycle), the data can be continuously consumed at a rate matching the processing capacity of the capture side, thus achieving bandwidth matching.

[0063] In these embodiments, for 1:N frequency ratio transmission scenarios, the data splitting unit 310 helps to achieve bandwidth matching while maintaining low latency. This unit splits the sampled wide-bit data into multiple data segments and outputs them sequentially over multiple consecutive capture clock cycles. This utilizes the low latency characteristics brought by the fixed phase relationship and solves the bit width mismatch problem through time-division multiplexing. This solution significantly improves data transmission efficiency and avoids bandwidth waste.

[0064] Optionally, in some embodiments of this application, the data splitting unit 310 is further configured to generate a first intermediate signal in the capture clock domain, and select and sequentially output the corresponding data segments according to the current value of the first intermediate signal; wherein the value of the first intermediate signal cycles between 0 and N-1.

[0065] It should be noted that the first intermediate signal (mark signal) is a cyclic counter generated in the capture clock domain, which behaves similarly to a modulo-N counter, with its value cycling between 0, 1, 2, ..., N-1. This signal acts as the control signal for the data segment selector. For example, when mark=0, the data splitting unit 310 (typically a multiplexer MUX) selects the 0th 1 / N segment (e.g., the low bit) of the output wide-bit data; when mark=1, it selects the 1st 1 / N segment, and so on. This mechanism ensures the strict sequentiality of the data segment output, avoiding data errors caused by out-of-order sequences at the receiving end. Essentially, it is the control logic that converts the "spatial parallelism" of wide data into the "temporal serialism" of narrow data.

[0066] In these embodiments, a cyclic tagging signal control mechanism is introduced to achieve precise timing management of data splitting. The tagging signal cycles between 0 and N-1, providing a unique identifier for each data segment and ensuring that the split data is output in the correct order. This scheme prevents data misalignment or loss, simplifies the data reassembly logic at the receiving end, and further improves the reliability and ease of use of the system.

[0067] Based on this, in the scenario where the transmit clock to acquire clock frequency ratio is 1:N (N is an integer greater than 1) when switching from a slow clock to a fast clock, refer to... Figure 4 As shown, taking a frequency ratio of 1:3 as an example, the waveforms of clk1_gated are the same as those of clk1, and the frequency ratio of clk2_gated to clk2 is 1:3. When the rising edge of the clk2_gated clock aligns with the falling edge of the clk1_gated clock, the multi-bit data FF2_D in the clk1 clock domain can be directly sampled by clk2, and then transferred to the clk2 clock domain after T1 / 2. When mark is 0, data_o is the lower 1 / N bits of FF2_Q; when mark is 1, data_o is the middle 1 / N bits of FF2_Q; when mark is 2, data_o is the higher 1 / N bits of FF2_Q.

[0068] Optionally, in some embodiments of this application, the data sampling module 300 includes: a data splicing unit 320, configured to splice multi-bit data within N consecutive clock cycles of the transmit clock domain into a data block for sampling by the gated capture clock signal when the frequency ratio between the transmit clock signal and the capture clock signal is N:1; wherein, N is an integer greater than 1.

[0069] It should be noted that data splicing unit 320 corresponds to Figure 2The `comb_A` data concatenation unit 320 functions in the opposite way to the splitting unit, aiming to solve the data throughput matching problem between the high-speed and low-speed domains. When the transmit clock frequency is N times the capture clock frequency (N:1), the amount of data generated by the transmitter per unit time is larger. This unit temporarily stores and concatenates N data units generated in N consecutive cycles into a data block with a bit width N times that of the original data in the transmit clock domain. When the sampling time determined by the fixed phase relationship arrives, this complete wide data block is sampled all at once in the capture clock domain. This realizes the conversion from "high-speed narrow data" to "low-speed wide data". This avoids the need for deep memory and complex read / write pointer synchronization logic required by asynchronous FIFOs, saving area and power consumption.

[0070] In these embodiments, for N:1 frequency ratio transmission scenarios, the data splicing unit 320 effectively integrates high-speed data streams. This unit splices data from multiple clock cycles into a single data block for one-time sampling by the capture clock domain, solving the data throughput matching problem from the high-speed domain to the low-speed domain. This scheme fully utilizes the stable sampling window provided by the fixed phase relationship, and while ensuring reliability, avoids the complex storage control logic required by traditional asynchronous FIFOs through data splicing, reducing implementation complexity and area overhead.

[0071] Optionally, in some embodiments of this application, the data splicing unit 320 is configured to delay the data through a delay chain composed of N-1 level flip-flops to achieve splicing, and to generate a second intermediate signal in the transmit clock domain, wherein the sampling timing is controlled by the second intermediate signal at the clock alignment edge determined by a fixed phase relationship.

[0072] It should be noted that the delay chain composed of N-1 flip-flops is a reliable hardware structure for data concatenation. Each time the data stream passes through a flip-flop, it is delayed by one transmit clock cycle. By outputting the original data and the data delayed by 1, 2, ..., N-1 cycles in parallel, a wide data block containing N consecutive cycles of data can be concatenated. The second intermediate signal (also a mark signal, but generated in the transmit clock domain) is a single-cycle pulse signal, the timing of which is determined by a fixed phase relationship (i.e., at the transmit clock domain moment corresponding to the sampling edge of clk2_gated). This signal serves as a sampling enable signal, indicating that the data in the concatenated data block is complete and valid, and can be safely sampled by the capture clock domain. This ensures that the sampling action occurs within a stable data time window.

[0073] Reference Figure 5As shown, the bit width ratio of FF1_Q and FF2_D is 1:N. FF2_Q has the same bit width as data_o, so data concatenation is required. FF1_Q is clocked N-1 times, and then concatenated with the N-1 clock cycles to form {FF1_Q, FF1_Q_d1, ..., FF1_Q_d(N-2), FF1_Q_d(N-1)}. A transmit clock domain intermediate signal, mark, is generated. This signal is pulled high on the alignment edge and pulled low at other positions. When mark is 1, clk2_gated samples the concatenated data and outputs it directly to data_o.

[0074] In these embodiments, a splicing scheme employing coordinated control of delay chains and marker signals achieves an optimal balance between hardware efficiency and timing accuracy. The delay chain uses multi-stage triggers to ensure precise data alignment, while the marker signal triggers sampling at specific moments determined by a fixed phase relationship, ensuring that the spliced ​​data is captured within the optimal timing window. This scheme guarantees the reliability of data splicing while maximizing the advantages of the phase relationship through precise timing control.

[0075] Based on this, refer to Figure 6 As shown, taking a fast clock to slow clock ratio of 3:1 as an example, the frequency ratio of clk1_gated to clk1 is 1:3, and the waveforms of clk2_gated are the same as those of clk2. When the rising edge of the clk2_gated clock aligns with the falling edge of the clk1_gated clock, the multi-bit data FF2_D concatenated in the clk1 clock domain can be directly sampled by clk2, and can be transferred to the clk2 clock domain after passing through T1 / 2.

[0076] According to an embodiment of the present invention, a method for data transmission across clock domains is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0077] This embodiment provides a method for cross-clock domain data transmission, which can be used in the aforementioned cross-clock domain data transmission circuit. Figure 7 This is a flowchart of a cross-clock domain data transmission method according to an embodiment of the present invention, with reference to... Figure 7 As shown, the process includes the following steps: Step S401: Process the transmit clock signal in the transmit clock domain and the capture clock signal in the capture clock domain to generate a gated transmit clock signal and a gated capture clock signal with the same frequency.

[0078] Step S402: Adjust the phase of the gating capture clock signal to establish a fixed phase relationship between the gating capture clock signal and the gating transmit clock signal.

[0079] Optionally, in some embodiments of this application, step S402 includes: Step a1: Adjust the phase of the gating capture clock signal so that the rising edge of the gating capture clock signal is aligned with the falling edge of the gating transmit clock signal. Step S403: Based on a fixed phase relationship, under the control of the gated acquisition clock signal, multi-bit data from the transmit clock domain is sampled into the acquisition clock domain.

[0080] Optionally, in some embodiments, the cross-clock domain data transmission method of this application further includes: Step S404: When the frequency ratio between the transmit clock signal and the capture clock signal is 1:N, the sampled data located in the capture clock domain is divided into N data segments and output sequentially within N consecutive clock cycles in the capture clock domain.

[0081] Optionally, in some embodiments, the cross-clock domain data transmission method of this application further includes: Step S405: When the frequency ratio between the transmit clock signal and the capture clock signal is N:1, the multi-bit data in N consecutive clock cycles of the transmit clock domain is concatenated into a data block.

[0082] Optionally, in some embodiments, the cross-clock domain data transmission method of this application further includes: Step S406: When the frequency ratio between the transmit clock signal and the capture clock signal is 1:1, the multi-bit data in the transmit clock domain is directly sampled into the capture clock domain.

[0083] The cross-time domain data transmission method provided in this application can be executed based on the cross-time domain data transmission circuit 10 provided in any embodiment of this application, and has the corresponding beneficial effects of the cross-time domain data transmission circuit 10, which will not be described in detail here.

[0084] Reference Figure 8 As shown, according to an embodiment of this application, a cross-time domain data transmission system 1 is also provided, including a cross-clock domain data transmission circuit, a clock source 20, and a data source 30 corresponding to any of the foregoing embodiments, wherein the clock source 20 is used to provide a transmit clock signal and a capture clock signal to the cross-clock domain data transmission circuit; and the data source 30 is used to provide the data to be transmitted to the cross-clock domain data transmission circuit.

[0085] The cross-time domain data transmission system 1 provided in this embodiment of the invention includes the cross-time domain data transmission circuit 10 provided in any embodiment of the invention, and has corresponding functional modules and beneficial effects. Further functional descriptions of the above modules and units are the same as those in the aforementioned corresponding embodiments, and will not be repeated here.

[0086] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A cross-clock domain data transmission circuit, characterized in that, include: The clock generation module is configured to receive the transmit clock signal from the transmit clock domain and the capture clock signal from the capture clock domain, and generate a gated transmit clock signal and a gated capture clock signal with the same frequency. A phase alignment control module, connected to the clock generation module, is configured to adjust the phase of the gated capture clock signal to establish a fixed phase relationship between the gated capture clock signal and the gated transmit clock signal. The data sampling module, connected to the phase alignment control module and the clock generation module, is configured to sample multi-bit data from the transmit clock domain to the capture clock domain based on the fixed phase relationship.

2. The cross-clock domain data transmission circuit according to claim 1, characterized in that, The fixed phase relationship is configured such that the rising edge of the gated capture clock signal is aligned with the falling edge of the gated transmit clock signal.

3. The cross-clock domain data transmission circuit according to claim 1, characterized in that, The clock generation module includes: The frequency division unit is configured to perform frequency division processing on the transmit clock signal and the capture clock signal respectively; A gating unit, connected to the frequency division unit, is configured to gating the frequency-divided transmit clock signal and the capture clock signal to generate a gated transmit clock signal and a gated capture clock signal with the same frequency.

4. The cross-clock domain data transmission circuit according to claim 1, characterized in that, The phase alignment control module includes: The digital control unit is configured to receive the gated transmit clock signal and the gated capture clock signal, and generate and output digital control code based on the phase difference between the gated capture clock signal and the gated transmit clock signal; A phase mixing unit, connected to the digital control unit and the clock generation module, is configured to receive the digital control code and the gated capture clock signal, and adjust the phase of the gated capture clock signal according to the digital control code, so as to establish the fixed phase relationship between the gated capture clock signal and the gated transmit clock signal.

5. The cross-clock domain data transmission circuit according to claim 1, characterized in that, The data sampling module includes: The data splitting unit is configured to split the sampled data located in the capture clock domain into N data segments when the frequency ratio between the transmit clock signal and the capture clock signal is 1:N, and output them sequentially in N consecutive clock cycles of the capture clock domain. Where N is an integer greater than 1.

6. The cross-clock domain data transmission circuit according to claim 5, characterized in that, The data splitting unit is further configured to generate a first intermediate signal in the capture clock domain, and select and output the corresponding data segments in sequence according to the current value of the first intermediate signal; The value of the first intermediate signal cycles between 0 and N-1.

7. The cross-clock domain data transmission circuit according to claim 1, characterized in that, The data sampling module includes: The data splicing unit is configured to splice multiple bits of data within N consecutive clock cycles of the transmission clock domain into a data block for sampling by the gated acquisition clock signal when the frequency ratio between the transmission clock signal and the acquisition clock signal is N:

1. Where N is an integer greater than 1.

8. The cross-clock domain data transmission circuit according to claim 7, characterized in that, The data splicing unit is configured to delay the data through a delay chain consisting of N-1 level flip-flops to achieve splicing, and to generate a second intermediate signal in the transmit clock domain. The sampling timing is controlled by the second intermediate signal at the clock alignment edge determined by the fixed phase relationship.

9. The cross-clock domain data transmission circuit according to claim 1, characterized in that, The data sampling module is also configured to: When the frequency ratio between the transmit clock signal and the capture clock signal is 1:1, the multi-bit data of the transmit clock domain is directly sampled into the capture clock domain.

10. A method for data transmission across clock domains, characterized in that, include: The transmit clock signal in the transmit clock domain and the capture clock signal in the capture clock domain are processed to generate gated transmit clock signals and gated capture clock signals with the same frequency; The phase of the gated capture clock signal is adjusted to establish a fixed phase relationship between the gated capture clock signal and the gated transmit clock signal; Based on the fixed phase relationship, under the control of the gated acquisition clock signal, multi-bit data from the transmit clock domain is sampled into the acquisition clock domain.

11. The cross-clock domain data transmission method according to claim 10, characterized in that, Adjusting the phase of the gated capture clock signal includes: Adjust the phase of the gated capture clock signal so that the rising edge of the gated capture clock signal is aligned with the falling edge of the gated transmit clock signal.

12. The cross-clock domain data transmission method according to claim 10, characterized in that, The method further includes: When the frequency ratio between the transmit clock signal and the capture clock signal is 1:N, the sampled data located in the capture clock domain is divided into N data segments and output sequentially within N consecutive clock cycles of the capture clock domain.

13. The cross-clock domain data transmission method according to claim 10, characterized in that, The method further includes: When the frequency ratio between the transmit clock signal and the capture clock signal is N:1, the multi-bit data within N consecutive clock cycles of the transmit clock domain is concatenated into a data block.

14. The cross-clock domain data transmission method according to claim 10, characterized in that, The method further includes: When the frequency ratio between the transmit clock signal and the capture clock signal is 1:1, the multi-bit data of the transmit clock domain is directly sampled into the capture clock domain.

15. The cross-clock domain data transmission method according to claim 10, characterized in that... ， A cross-clock domain data transmission system, characterized in that, include: The cross-clock domain data transmission circuit according to any one of claims 1-9; A clock source is used to provide a transmit clock signal and a capture clock signal to the cross-clock domain data transmission circuit. A data source is used to provide the data to be transmitted to the cross-clock domain data transmission circuit.

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