Uninterruptible power supply circuit for memory hardware
By designing an uninterruptible power supply circuit for the memory hardware, efficient charging and discharging management of the backup power supply is achieved, solving the problem of insufficient backup power supply capacity for the memory hardware and ensuring stable power supply to the memory hardware when the motherboard loses power.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN VITEM SEMICONDUCTOR CO LTD
- Filing Date
- 2026-01-13
- Publication Date
- 2026-05-19
AI Technical Summary
Existing memory hardware backup power supplies have limited battery life and low charging and discharging efficiency, especially due to improper charging and discharging control of lithium batteries, which leads to reduced efficiency.
Design a memory hardware uninterruptible power supply circuit. Through a microcontroller module, control the backup power module to perform single-group, two-group, and full-group series constant current charging and parallel constant voltage charging of three backup batteries. Combined with a power detection module, adjust the voltage balance in real time to ensure stable power supply to the memory power module.
It improves the charging and discharging efficiency of the backup power supply, extends the uninterrupted power supply capability of the memory hardware, and ensures stable power supply when the motherboard loses power.
Smart Images
Figure CN122064210A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory hardware technology, specifically to an uninterruptible power supply circuit for memory hardware. Background Technology
[0002] Memory hardware is the physical device in a computer system used for temporary or permanent storage of data and programs. For DRAM memory hardware, data is stored using the charge of capacitors. However, capacitors naturally leak current and must be refreshed periodically. Therefore, a backup power supply is needed to switch power when the memory hardware is powered off, so as to achieve uninterrupted power supply. However, due to the limited capacity of the backup power supply, the battery life of the backup power supply is limited. Moreover, the backup power supply is half lithium battery, and unreasonable charging and discharging control reduces the charging and discharging efficiency of the backup power supply. Therefore, it needs to be improved. Summary of the Invention
[0003] This invention provides an uninterruptible power supply circuit for memory hardware to solve the problems mentioned in the background art.
[0004] According to an embodiment of the present invention, a memory hardware uninterruptible power supply circuit is provided, comprising: The motherboard module is used to connect to the main power supply, detect power failure of the main power supply, and output the first detection signal when power fails. The backup power module is connected to the main board module and is used to regulate the power of the main power and sequentially charge the three sets of backup batteries in series with constant current, in series with constant current, in series with constant current, in series with constant current, and in constant voltage parallel charging, and to balance the voltage of the three sets of backup batteries. The memory power module is connected to the motherboard module and is used to regulate the voltage of the main power, the power provided by the individual backup batteries in the three sets of backup batteries in sequence, or the power provided by the three sets of backup batteries in series, and to power the connected memory hardware. The power detection module is connected to the backup power module and is used to detect the low power of the three sets of backup batteries according to the set low power threshold. When the first set of backup batteries, the second set of backup batteries, or the third set of backup batteries are at low power, the module outputs a first low voltage signal, a second low voltage signal, and a third low voltage signal, respectively. The microcontroller module, connected to the motherboard module, memory power module, backup power module, and power detection module, controls the backup power module to perform series constant current charging or constant voltage parallel charging. Based on the power status of the three backup batteries, it controls the backup power module to perform voltage equalization adjustment. It also controls the memory power module to receive main power. Upon receiving the first detection signal, it controls the memory power module to receive power from the first backup battery; upon receiving the first low-voltage signal, it controls the memory power module to receive power from the second backup battery; upon receiving the second low-voltage signal, it controls the memory power module to receive power from the third backup battery; and upon receiving the third low-voltage signal, it controls the memory power module to receive power from the three backup batteries connected in series.
[0005] As a further embodiment of the present invention: the motherboard module includes a motherboard interface and a first capacitor; the memory power supply module includes a sixth power transistor, a voltage regulator, a second capacitor and a memory interface; the microcontroller module includes a first controller; Preferably, the first end of the motherboard interface is connected to the drain of the sixth power transistor and is connected to the second end of the motherboard interface, the ground end of the voltage regulator, the second end of the memory interface, one end of the second capacitor and the ground end through the first capacitor. The output end of the voltage regulator is connected to the first end of the memory interface and the other end of the second capacitor. The source of the sixth power transistor is connected to the input end of the voltage regulator, and the gate of the sixth power transistor is connected to the IO6 end of the first controller.
[0006] As a further embodiment of the present invention: the backup power module includes a first power transistor, a second power transistor, a third power transistor, a third battery, a fifth power transistor, a second battery, a fourth power transistor, and a first battery; Preferably, the drain of the first power transistor is connected to the drain of the second power transistor, the drain of the third power transistor, and the first terminal of the motherboard interface; the source of the first power transistor is connected to the first terminal of the third battery; the second terminal of the third battery is connected to the source of the fifth power transistor; the drain of the fifth power transistor is connected to the first terminal of the second battery; the second terminal of the second battery is connected to the source of the fourth power transistor; the drain of the fourth power transistor is connected to the first terminal of the first battery; the second terminal of the first battery is connected to the second terminal of the motherboard interface; and the gates of the first power transistor, the second power transistor, the third power transistor, the fourth power transistor, and the fifth power transistor are respectively connected to the IO1, IO2, IO3, IO4, and IO5 terminals of the first controller.
[0007] As a further embodiment of the present invention: the backup power module also includes a seventh power transistor, an eighth power transistor, and a twelfth power transistor; Preferably, the drain of the seventh power transistor and the drain of the eighth power transistor are connected to the second terminal of the second battery and the second terminal of the third battery, respectively. The source of the eighth power transistor is connected to the source of the seventh power transistor and the drain of the twelfth power transistor. The source of the twelfth power transistor is connected to the second terminal of the first battery. The gates of the eighth power transistor, the seventh power transistor, and the twelfth power transistor are connected to the IO8, IO7, and IO12 terminals of the first controller, respectively.
[0008] As a further embodiment of the present invention: the memory power module further includes a ninth power transistor, a tenth power transistor, an eleventh power transistor, a first diode, a second diode, and a third diode; Preferably, the drains of the ninth, tenth, and eleventh power transistors are connected to the first terminal of the third battery, the first terminal of the second battery, and the first terminal of the first battery, respectively. The source of the ninth power transistor is connected to the source of the tenth and eleventh power transistors and the input terminal of the voltage regulator. The cathodes of the first and second diodes are connected to the gate of the fifth and fourth power transistors, respectively. The anode of the first diode is connected to the anode of the second and third diodes and the IO13 terminal of the first controller. The cathode of the third diode is connected to the gate of the ninth power transistor and the IO9 terminal of the first controller. The gates of the tenth and eleventh power transistors are connected to the IO10 and IO11 terminals of the first controller, respectively.
[0009] As a further embodiment of the present invention: the power detection module includes a first resistor, a second resistor, a first reference power supply, a first comparator, a first detector, and a second detector; Preferably, the inverting input of the first comparator is connected to the first terminal of the second resistor and then connected to the first terminal of the first battery through the first resistor. The second terminal of the second resistor is connected to the second terminal of the first battery. The non-inverting input of the first comparator is connected to the first reference power supply. The first and second detection terminals of the first detector are respectively connected to the first and second terminals of the second battery. The first and second detection terminals of the second detector are respectively connected to the first and second terminals of the third battery. The output terminals of the first comparator, the first detector, and the second detector are respectively connected to the IO14, IO15, and IO16 terminals of the first controller.
[0010] As a further embodiment of the present invention: the motherboard module further includes a third resistor, a first optocoupler, a fourth resistor, and a first voltage regulator; Preferably, the first end of the first optocoupler is connected to the first end of the motherboard interface through the third resistor, the second end of the first optocoupler is connected to the second end of the motherboard interface, the third end of the first optocoupler is connected to the IO17 terminal of the first controller and connected to the first voltage regulator through the fourth resistor, and the fourth end of the first optocoupler is grounded.
[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: The uninterruptible power supply circuit for memory hardware of the present invention can be controlled by the microcontroller module to power the motherboard module to the backup power module and the memory power module. It performs single-cell series constant current charging, two-cell series constant current charging, three-cell series constant current charging, and three-cell constant voltage parallel charging on the three backup batteries in the backup power module, and performs voltage equalization adjustment on the three backup batteries, thereby improving the charging and discharging efficiency of the backup power module. The memory power module provides voltage regulation for the memory hardware. When the motherboard module loses power, based on the power status of the individual backup batteries in the three backup battery groups detected by the power detection module, it controls the individual backup batteries in the three backup battery groups to supply power to the memory power module sequentially. When all three backup batteries are low on power, it controls the three backup batteries to be connected in series and supply power to the memory power module, achieving uninterrupted power supply while improving the backup power endurance. Attached Figure Description
[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a schematic block diagram of a memory hardware uninterruptible power supply circuit provided in an embodiment of the present invention.
[0014] Figure 2 This is a circuit diagram of an uninterruptible power supply circuit for memory hardware provided in an embodiment of the present invention.
[0015] Figure 3 The circuit diagram of the power detection module provided in the embodiment of the present invention.
[0016] Figure 4 The circuit diagram of the motherboard module provided in the embodiment of the present invention. Detailed Implementation
[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] In one embodiment, see Figure 1 An uninterruptible power supply circuit for memory hardware, comprising: Mainboard module 1 is used to connect to the main power supply, detect power failure of the main power supply, and output a first detection signal when power failure occurs; Backup power module 2 is connected to the main board module and is used to regulate the main power and sequentially charge the three backup batteries in series with constant current, in series with constant current, in series with constant current, in series with constant current, and in constant voltage parallel charging, and to balance the voltage of the three backup batteries. The memory power module 3 is connected to the motherboard module 1 and is used to regulate the voltage of the main power, the power provided by the individual backup batteries in the three sets of backup batteries in sequence, or the power provided by the three sets of backup batteries in series, and to power the connected memory hardware. The power detection module 4 is connected to the backup power module 2 and is used to detect the low power of the three sets of backup batteries according to the set low power threshold. When the first set of backup batteries, the second set of backup batteries, or the third set of backup batteries are at low power, the module outputs a first low voltage signal, a second low voltage signal, and a third low voltage signal, respectively. The microcontroller module 5 is connected to the motherboard module 1, the memory power module 3, the backup power module 2, and the power detection module 4. It is used to control the backup power module 2 to perform series constant current charging or constant voltage parallel charging, and to control the backup power module 2 to perform voltage equalization adjustment according to the power status of the three sets of backup batteries. It controls the memory power module 3 to receive main power. When it receives the first detection signal, it controls the memory power module 3 to receive power from the first set of backup batteries. When it receives the first low voltage signal, it controls the memory power module 3 to receive power from the second set of backup batteries. When it receives the second low voltage signal, it controls the memory power module 3 to receive power from the third set of backup batteries. When it receives the third low voltage signal, it controls the memory power module 3 to receive power from the three sets of backup batteries connected in series.
[0019] In a specific embodiment, the aforementioned motherboard module 1 can be a motherboard circuit composed of a motherboard interface, optocouplers, resistors, etc., which can be connected to the motherboard power supply, receive the main power provided by the motherboard power supply, and perform power failure detection on the main power supply; the aforementioned backup power module 2 can be a backup power circuit composed of field-effect transistors, diodes, and three sets of backup batteries, which can control the three sets of backup batteries to sequentially perform single-set series constant current charging, two-set series constant current charging, three-set series constant current charging, and three-set constant voltage parallel charging during charging, performing voltage equalization regulation control; the aforementioned memory power module 3 can be a memory power circuit composed of field-effect transistors, voltage regulators, memory interfaces, etc., which can change the received power path to achieve [the desired effect]. The main power supply and the power provided by the individual backup batteries in the three backup battery groups sequentially or by the three backup battery groups connected in series are regulated and the regulated power is transmitted to the power supply section of the connected memory hardware; the power detection module 4 can be a power detection circuit composed of resistors, comparators, detectors, etc., which can sample the power of the three backup battery groups to know the power information of each backup battery group, compare the sampled signal with the set low power threshold, and then know the low power status of each backup battery group; the microcontroller module 5 can be a microcontroller circuit composed of a single-chip microcomputer, which integrates many components such as arithmetic unit, controller, memory and input / output device, and realizes functions such as signal processing, data storage, module control and timing control.
[0020] In this embodiment, please refer to Figure 2 , Figure 3 and Figure 4 The motherboard module 1 includes a motherboard interface and a first capacitor C1; the memory power supply module 3 includes a sixth power transistor Q6, a voltage regulator, a second capacitor C2, and a memory interface; the microcontroller module 5 includes a first controller U1; Specifically, the first end of the motherboard interface is connected to the drain of the sixth power transistor Q6 and is connected to the second end of the motherboard interface, the ground end of the voltage regulator, the second end of the memory interface, one end of the second capacitor C2 and the ground end through the first capacitor C1. The output end of the voltage regulator is connected to the first end of the memory interface and the other end of the second capacitor C2. The source of the sixth power transistor Q6 is connected to the input end of the voltage regulator, and the gate of the sixth power transistor Q6 is connected to the IO6 end of the first controller U1.
[0021] In a specific embodiment, the sixth power transistor Q6 can be an N-channel MOSFET; the voltage regulator can be selected according to the operating voltage of the internal charging hardware; and the first controller U1 can be an STM32 microcontroller.
[0022] Furthermore, the backup power module 2 includes a first power transistor Q1, a second power transistor Q2, a third power transistor Q3, a third battery, a fifth power transistor Q5, a second battery, a fourth power transistor Q4, and a first battery; Specifically, the drain of the first power transistor Q1 is connected to the drain of the second power transistor Q2, the drain of the third power transistor Q3, and the first terminal of the motherboard interface. The source of the first power transistor Q1 is connected to the first terminal of the third battery. The second terminal of the third battery is connected to the source of the fifth power transistor Q5. The drain of the fifth power transistor Q5 is connected to the first terminal of the second battery. The second terminal of the second battery is connected to the source of the fourth power transistor Q4. The drain of the fourth power transistor Q4 is connected to the first terminal of the first battery. The second terminal of the first battery is connected to the second terminal of the motherboard interface. The gates of the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fourth power transistor Q4, and the fifth power transistor Q5 are respectively connected to the IO1, IO2, IO3, IO4, and IO5 terminals of the first controller U1.
[0023] In a specific embodiment, the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fifth power transistor Q5, and the fourth power transistor Q4 can all be N-channel field-effect transistors, which can perform constant current charging control of three sets of backup batteries in series; the first battery, the second battery, and the third battery can be used as the first set of backup batteries, the second set of backup batteries, and the third set of backup batteries, respectively, and all of them can be lithium batteries.
[0024] Furthermore, the backup power module 2 also includes a seventh power transistor Q7, an eighth power transistor Q8, and a twelfth power transistor Q12; Specifically, the drain of the seventh power transistor Q7 and the drain of the eighth power transistor Q8 are connected to the second terminal of the second battery and the second terminal of the third battery, respectively. The source of the eighth power transistor Q8 is connected to the source of the seventh power transistor Q7 and the drain of the twelfth power transistor Q12. The source of the twelfth power transistor Q12 is connected to the second terminal of the first battery. The gates of the eighth power transistor Q8, the seventh power transistor Q7, and the twelfth power transistor Q12 are connected to the IO8, IO7, and IO12 terminals of the first controller U1, respectively.
[0025] In a specific embodiment, the seventh power transistor Q7, the eighth power transistor Q8, and the twelfth power transistor Q12 can all be N-channel field-effect transistors. Together with the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fifth power transistor Q5, and the fourth power transistor Q4, they can perform constant current charging of a single set of backup batteries in series, constant current charging of two sets of backup batteries in series, or constant voltage parallel charging of three sets of backup batteries.
[0026] Furthermore, the memory power module 3 also includes a ninth power transistor Q9, a tenth power transistor Q10, an eleventh power transistor Q11, a first diode D1, a second diode D2, and a third diode D3; Specifically, the drains of the ninth power transistor Q9, the tenth power transistor Q10, and the eleventh power transistor Q11 are connected to the first terminal of the third battery, the first terminal of the second battery, and the first terminal of the first battery, respectively. The source of the ninth power transistor Q9 is connected to the source of the tenth power transistor Q10, the source of the eleventh power transistor Q11, and the input terminal of the voltage regulator. The cathodes of the first diode D1 and the second diode D2 are connected to the gate of the fifth power transistor Q5 and the gate of the fourth power transistor Q4, respectively. The anode of the first diode D1 is connected to the anode of the second diode D2, the anode of the third diode D3, and the IO13 terminal of the first controller U1. The cathode of the third diode D3 is connected to the gate of the ninth power transistor Q9 and the IO9 terminal of the first controller U1. The gates of the tenth power transistor Q10 and the eleventh power transistor Q11 are connected to the IO10 and IO11 terminals of the first controller U1, respectively.
[0027] In a specific embodiment, the ninth power transistor Q9, the tenth power transistor Q10, and the eleventh power transistor Q11 can all be N-channel field-effect transistors, which control the discharge state of the third battery, the second battery, and the first battery, respectively, and supply power to the voltage regulator.
[0028] Furthermore, the power detection module 4 includes a first resistor R1, a second resistor R2, a first reference power supply VF1, a first comparator A1, a first detector, and a second detector; Specifically, the inverting input of the first comparator A1 is connected to the first terminal of the second resistor R2 and connected to the first terminal of the first battery through the first resistor R1. The second terminal of the second resistor R2 is connected to the second terminal of the first battery. The non-inverting input of the first comparator A1 is connected to the first reference power supply VF1. The first and second detection terminals of the first detector are respectively connected to the first and second terminals of the second battery. The first and second detection terminals of the second detector are respectively connected to the first and second terminals of the third battery. The output terminals of the first comparator A1, the first detector, and the second detector are respectively connected to the IO14, IO15, and IO16 terminals of the first controller U1.
[0029] In a specific embodiment, the first comparator A1 can be an LM358 comparator; the first resistor R1 and the second resistor R2 can perform voltage division sampling and detect the power information of the first battery, or it can be received by the IO port of the first controller U1; the first reference power supply VF1, the first detector and the second detector can all be set with a low power threshold, which is the minimum input voltage of the voltage regulator; the circuit composition structure of the first detector and the circuit composition structure of the second detector are the same as the circuit composition structure of the first resistor R1, the second resistor R2, the first reference power supply VF1 and the first comparator A1, and the power information of the second battery and the power information of the third battery detected by the first detector and the second detector can also be received by the IO port of the first controller U1.
[0030] Furthermore, the motherboard module 1 also includes a third resistor R3, a first optocoupler U2, a fourth resistor R4, and a first voltage regulator VCC1; Specifically, the first end of the first optocoupler U2 is connected to the first end of the motherboard interface through the third resistor R3, the second end of the first optocoupler U2 is connected to the second end of the motherboard interface, the third end of the first optocoupler U2 is connected to the IO17 terminal of the first controller U1 and connected to the first voltage regulator VCC1 through the fourth resistor R4, and the fourth end of the first optocoupler U2 is grounded.
[0031] In a specific embodiment, the first optocoupler U2 can be a PC817 optocoupler.
[0032] The present invention discloses the working principle of an uninterruptible power supply circuit for memory hardware. The main power supply is connected to the motherboard power supply via the motherboard interface. At this time, the IO6 terminal of the first controller U1 controls the sixth power transistor Q6 to conduct. The main power is regulated and filtered by a voltage regulator and the second capacitor C2, providing voltage regulation for the memory hardware connected to the memory interface. Simultaneously, in one stage, the IO1, IO8, and IO12 terminals of the first controller U1 control the first power transistor Q1, the eighth power transistor Q8, and the twelfth power transistor Q12 to conduct, thereby controlling the third battery to perform constant current charging of a single backup battery in series. In the second stage, the IO1, IO5, IO7, and IO12 terminals of the first controller U1 are connected to the first power transistor Q1, the fifth power transistor Q8, the eighth power transistor Q8, and the twelfth power transistor Q12, respectively. In the third stage, power transistors Q5, Q7, and Q12 are turned on, controlling the third and second batteries to perform constant current charging of two sets of backup batteries in series. In the fourth stage, terminals IO1, IO5, and IO4 of the first controller U1 control power transistors Q1, Q5, and Q4 to turn on, controlling the third, second, and first batteries to perform constant current charging of three sets of backup batteries in series. The first, second, and third batteries are charged in parallel under constant voltage, forming three sets of backup batteries. The first, second, and third batteries are controlled to perform balanced charging. The first resistor R1, the second resistor R2, the first comparator A1, and the first reference power supply VF1 detect the state of charge of the first battery. The first detector and the second detector detect the state of charge of the second and third batteries, respectively. When the main power supply to the motherboard interface stops, the first optocoupler U2 is turned off. The IO17 pin of the first controller U1 is provided with a high level by the first voltage regulator VCC1 and the fourth resistor R4. At this time, the IO6 pin of the first controller U1 stops working, and the IO11 pin of the first controller U1 controls the eleventh power transistor Q11 to conduct, thereby controlling the first battery to charge the voltage regulator separately. In the backup power supply scenario, if the first comparator A1 outputs a first low-voltage signal and this signal is received by the IO14 terminal of the first controller U1, it indicates that the first battery is low. A path switching mechanism is then activated: the IO11 terminal of the first controller U1 stops operating, and the IO10 terminal controls the tenth power transistor Q10 to conduct. This creates a circuit consisting of the second battery, the tenth power transistor Q10, the voltage regulator, the twelfth power transistor Q12, and the seventh power transistor Q7, maintaining power supply to the voltage regulator. Similarly, when the first detector detects a low battery in the second battery, and its output terminal outputs a second low-voltage signal, the IO9 terminal of the first controller U1 controls the ninth power transistor Q9 to conduct, allowing the third battery to power the voltage regulator independently. If the second detector outputs a third low-voltage signal...The IO13 terminal of the first controller U1 controls the ninth power transistor Q9, the fifth power transistor Q5, and the fourth power transistor Q4 to conduct, thereby connecting the first, second, and third batteries in series and supplying power to the voltage regulator. Furthermore, during the self-balancing control of the first, second, and third batteries, the charging control of the high-capacity backup battery to the low-capacity backup battery can be achieved by controlling the field-effect transistors at the positive and negative terminals of the three backup batteries. Specifically, when the third battery is the backup battery with the lowest capacity, the first controller U1 can control the first power transistor Q1 and the eighth power transistor Q8 to conduct. When the first battery is at its highest charge level, the first controller U1 controls the twelfth power transistor Q12 to conduct, allowing the first battery to provide charging voltage to the third battery. Similarly, when the second battery is at its lowest charge level, the first controller U1 can control the second power transistor Q2 and the seventh power transistor Q7 to conduct, thereby charging the second battery. When the first battery is at its lowest charge level, the first controller U1 can control the third power transistor Q3 to conduct, thereby charging the first battery, thus achieving self-balancing regulation of the three sets of backup batteries.
[0033] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0034] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A memory hardware uninterruptible power supply circuit, characterized in that, The circuit includes: The motherboard module is used to connect to the main power supply, detect power failure of the main power supply, and output the first detection signal when power fails. The backup power module is connected to the main board module and is used to regulate the power of the main power and sequentially charge the three sets of backup batteries in series with constant current, in series with constant current, in series with constant current, in series with constant current, and in constant voltage parallel charging, and to balance the voltage of the three sets of backup batteries. The memory power module is connected to the motherboard module and is used to regulate the voltage of the main power, the power provided by the individual backup batteries in the three sets of backup batteries in sequence, or the power provided by the three sets of backup batteries in series, and to power the connected memory hardware. The power detection module is connected to the backup power module and is used to detect the low power of the three sets of backup batteries according to the set low power threshold. When the first set of backup batteries, the second set of backup batteries, or the third set of backup batteries are at low power, the module outputs a first low voltage signal, a second low voltage signal, and a third low voltage signal, respectively. The microcontroller module, connected to the motherboard module, memory power module, backup power module, and power detection module, controls the backup power module to perform series constant current charging or constant voltage parallel charging. Based on the power status of the three backup batteries, it controls the backup power module to perform voltage equalization adjustment. It also controls the memory power module to receive main power. Upon receiving the first detection signal, it controls the memory power module to receive power from the first backup battery; upon receiving the first low-voltage signal, it controls the memory power module to receive power from the second backup battery; upon receiving the second low-voltage signal, it controls the memory power module to receive power from the third backup battery; and upon receiving the third low-voltage signal, it controls the memory power module to receive power from the three backup batteries connected in series.
2. The uninterruptible power supply circuit for memory hardware according to claim 1, characterized in that, The motherboard module includes a motherboard interface and a first capacitor; the memory power module includes a sixth power transistor, a voltage regulator, a second capacitor, and a memory interface; the microcontroller module includes a first controller; The first end of the motherboard interface is connected to the drain of the sixth power transistor and is connected to the second end of the motherboard interface, the ground end of the voltage regulator, the second end of the memory interface, one end of the second capacitor, and the ground end through the first capacitor. The output end of the voltage regulator is connected to the first end of the memory interface and the other end of the second capacitor. The source of the sixth power transistor is connected to the input end of the voltage regulator, and the gate of the sixth power transistor is connected to the IO6 end of the first controller.
3. The uninterruptible power supply circuit for memory hardware according to claim 2, characterized in that, The backup power module includes a first power transistor, a second power transistor, a third power transistor, a third battery, a fifth power transistor, a second battery, a fourth power transistor, and a first battery. The drain of the first power transistor is connected to the drain of the second power transistor, the drain of the third power transistor, and the first terminal of the motherboard interface. The source of the first power transistor is connected to the first terminal of the third battery. The second terminal of the third battery is connected to the source of the fifth power transistor. The drain of the fifth power transistor is connected to the first terminal of the second battery. The second terminal of the second battery is connected to the source of the fourth power transistor. The drain of the fourth power transistor is connected to the first terminal of the first battery. The second terminal of the first battery is connected to the second terminal of the motherboard interface. The gates of the first power transistor, the second power transistor, the third power transistor, the fourth power transistor, and the fifth power transistor are respectively connected to the IO1, IO2, IO3, IO4, and IO5 terminals of the first controller.
4. The uninterruptible power supply circuit for memory hardware according to claim 3, characterized in that, The backup power module also includes a seventh power transistor, an eighth power transistor, and a twelfth power transistor; The drain of the seventh power transistor and the drain of the eighth power transistor are respectively connected to the second terminal of the second battery and the second terminal of the third battery. The source of the eighth power transistor is connected to the source of the seventh power transistor and the drain of the twelfth power transistor. The source of the twelfth power transistor is connected to the second terminal of the first battery. The gate of the eighth power transistor, the gate of the seventh power transistor, and the gate of the twelfth power transistor are respectively connected to the IO8, IO7, and IO12 terminals of the first controller.
5. The uninterruptible power supply circuit for memory hardware according to claim 4, characterized in that, The memory power module also includes a ninth power transistor, a tenth power transistor, an eleventh power transistor, a first diode, a second diode, and a third diode; The drains of the ninth, tenth, and eleventh power transistors are respectively connected to the first terminal of the third battery, the first terminal of the second battery, and the first terminal of the first battery. The source of the ninth power transistor is connected to the source of the tenth and eleventh power transistors and the input terminal of the voltage regulator. The cathodes of the first and second diodes are respectively connected to the gate of the fifth and fourth power transistors. The anode of the first diode is connected to the anode of the second and third diodes and the IO13 terminal of the first controller. The cathode of the third diode is connected to the gate of the ninth power transistor and the IO9 terminal of the first controller. The gates of the tenth and eleventh power transistors are respectively connected to the IO10 and IO11 terminals of the first controller.
6. The uninterruptible power supply circuit for memory hardware according to claim 3, characterized in that, The power detection module includes a first resistor, a second resistor, a first reference power supply, a first comparator, a first detector, and a second detector; The inverting input of the first comparator is connected to the first terminal of the second resistor and then connected to the first terminal of the first battery through the first resistor. The second terminal of the second resistor is connected to the second terminal of the first battery. The non-inverting input of the first comparator is connected to the first reference power supply. The first and second detection terminals of the first detector are respectively connected to the first and second terminals of the second battery. The first and second detection terminals of the second detector are respectively connected to the first and second terminals of the third battery. The output terminals of the first comparator, the first detector, and the second detector are respectively connected to the IO14, IO15, and IO16 terminals of the first controller.
7. The uninterruptible power supply circuit for memory hardware according to claim 2, characterized in that, The motherboard module also includes a third resistor, a first optocoupler, a fourth resistor, and a first voltage regulator; The first end of the first optocoupler is connected to the first end of the motherboard interface through the third resistor, the second end of the first optocoupler is connected to the second end of the motherboard interface, the third end of the first optocoupler is connected to the IO17 terminal of the first controller and is connected to the first voltage regulator through the fourth resistor, and the fourth end of the first optocoupler is grounded.