SSD multi-queue timeout low-cost control method and device and medium

Abstract

The invention discloses an SSD multi-queue timeout low-cost control method and device and a medium, and relates to the technical field of SSDs. The method comprises the steps that global system master time is provided; when a command operation occurs, taking the system main time as a timestamp of the command operation, and storing the timestamp to a storage position corresponding to a command identifier of the command operation; reading a timestamp corresponding to the uncompleted command operation from the storage position in a polling mode; according to the current system main time and the read timestamp, the executed duration of the command operation is calculated; and comparing the executed duration with a preset overtime threshold to judge whether the command operation is overtime or not. Under a multi-queue concurrent command processing scene, the area cost and the dynamic power consumption of hardware implementation can be effectively reduced, the expandability of the system is improved, and the problem that an existing scheme is difficult to expand due to too large resource occupation is solved.

Description

Technical Field

[0001] This invention relates to the field of SSD technology, and in particular to a low-cost method, device and medium for controlling SSD multi-queue timeout. Background Technology

[0002] In the command processing of solid-state drives (SSDs), in order to ensure that the system can promptly identify and process operations that are not completed on time, it is usually necessary to monitor the execution time of each command and determine the timeout.

[0003] Existing technologies typically employ a scheme that allocates independent timing resources to each command. This means that when a command arrives, a dedicated counter corresponding to that command is started to begin timing, and during command execution, the real-time value of the counter is continuously compared with a preset timeout threshold. If the command is completed within the timeout threshold, the counter is cleared; if the comparison finds that the count value exceeds the threshold, the command execution is determined to have timed out.

[0004] While the aforementioned methods are applicable in scenarios with a single or small number of commands, in modern SSD controllers that require support for multi-queue, high-concurrency command processing, each command necessitates an independent counter and corresponding comparison logic. This leads to a linear increase in hardware resource overhead with the number of commands, significantly increasing chip area and power consumption. Furthermore, the large number of distributed timing and comparison modules complicates circuit timing convergence, limiting the overall system scalability. Therefore, existing technologies suffer from drawbacks such as high resource consumption, high power consumption, and insufficient scalability in multi-queue environments. Summary of the Invention

[0005] This invention provides a low-cost SSD multi-queue timeout control method, device, and medium, aiming to solve the technical problem of how to provide a command timeout control scheme that can achieve high efficiency and low resource consumption in multi-queue concurrent scenarios.

[0006] To address the aforementioned issues, this invention employs a single global counter to generate the system master time, replacing the scheme of allocating an independent counter for each command, thereby reducing hardware resource overhead.

[0007] In a first aspect, embodiments of the present invention provide a low-cost SSD multi-queue timeout control method, comprising: Provides global system master time; When a command operation occurs, the system master time is used as the timestamp of the command operation and stored in the storage location corresponding to the command identifier of the command operation; The timestamps corresponding to incomplete command operations are read from the storage location in a polling manner. Calculate the execution duration of the command operation based on the current system master time and the read timestamp; The execution time is compared with a preset timeout threshold to determine whether the command operation has timed out.

[0008] Optionally, storing the system master time as the timestamp of the command operation in the storage location corresponding to the command identifier of the command operation includes: In response to a command operation, obtain the command identifier corresponding to the command operation; Based on the command identifier, the target storage address in the storage structure is generated; Write the current system master time as a timestamp to the target storage address.

[0009] Optionally, the storage structure is a register file, and the step of writing the current system master time as a timestamp to the target storage address includes: Input the timestamp into the data input port of the register file; Enter the target memory address into the address selection port of the register file; A write enable signal is sent to the register file to store the timestamp into the target memory address.

[0010] Optionally, the step of reading the timestamps corresponding to incomplete command operations from the storage location in a polling manner includes: The polling process is initiated periodically according to a preset polling cycle; During each polling process, read addresses corresponding to each of the aforementioned storage locations are generated sequentially. Based on the read address, read the timestamps from the storage locations sequentially.

[0011] Optionally, calculating the execution duration of the command operation based on the current system master time and the read timestamp includes: The read timestamp is input to the first input terminal of the preset shared subtractor circuit; The current system master time is input to the second input terminal of the shared subtractor circuit; wherein, the shared subtractor circuit performs the operation of subtracting the value of the first input terminal from the value of the second input terminal, and outputs the execution duration.

[0012] Optionally, comparing the executed duration with a preset timeout threshold includes: The execution time output by the shared subtractor circuit is input to the first comparison terminal of the preset shared comparator circuit; The pre-configured timeout threshold is input to the second comparison terminal of the shared comparator circuit, wherein the shared comparator circuit performs a comparison operation, and outputs a timeout indication signal when the execution time is greater than or equal to the timeout threshold.

[0013] Optionally, after determining whether the command operation has timed out, the method further includes: If the command operation is determined to have timed out, a preset timeout processing logic is triggered to generate a timeout alarm signal; Based on the command identifier corresponding to the current polling, generate the storage address to be cleared; A clear command is issued to the storage structure to clear the timestamp stored in the storage address to be cleared.

[0014] Optionally, the method further includes: In response to the completion of a command operation, obtain the command identifier corresponding to the completed command operation; Generate a cleanup address based on the command identifier corresponding to the completed command operation; A clear command is issued to the storage structure to clear the timestamp stored in the cleared address.

[0015] Secondly, embodiments of the present invention also provide a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0016] Thirdly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the above-described method.

[0017] This invention provides a low-cost method, device, and medium for controlling timeouts in multiple queues of an SSD. The method includes: providing a global system master time; when a command operation occurs, storing the system master time as a timestamp of the command operation in a storage location corresponding to the command identifier of the command operation; retrieving the timestamps corresponding to incomplete command operations from the storage location in a polling manner; calculating the execution duration of the command operation based on the current system master time and the retrieved timestamps; and comparing the execution duration with a preset timeout threshold to determine whether the command operation has timed out. This invention replaces the existing scheme of setting independent dynamic counters for each command by introducing a globally unified system master time reference and centrally storing static timestamps for each command operation. This eliminates the reliance on distributed counter circuits proportional to the number of command queues for timing, significantly reducing the number of triggers, incrementing logic, and associated wiring in the hardware. Furthermore, by employing a centralized polling mechanism and a shared computational comparison unit to handle timeout judgments for all queues, redundant construction of logic resources is avoided. Therefore, in scenarios involving concurrent command processing across multiple queues, this invention can effectively reduce the area cost and dynamic power consumption of hardware implementation, and improve the scalability of the system, solving the problem that existing solutions are difficult to expand due to excessive resource consumption. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a low-cost timeout control method for SSD multi-queues provided in an embodiment of the present invention; Figure 2 This is a schematic block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0022] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0025] Please see Figure 1 This invention provides a low-cost SSD multi-queue timeout control method, which includes the following steps: S1 provides the global system master time.

[0026] In practice, a global system master time is provided, which is continuously generated by a global counter. This global counter is driven by the system clock and continuously increments from its initial value after power-on or reset. The output value of the global counter constitutes a unified system master time base within the entire SSD controller.

[0027] S2, When a command operation occurs, the system master time is used as the timestamp of the command operation and stored in the storage location corresponding to the command identifier of the command operation.

[0028] In practice, when a command operation occurs, such as a host read / write command being distributed to the processing unit by the scheduler, the system captures the current value of the global counter. This current value serves as the timestamp for this command operation. Simultaneously, the system obtains a unique command identifier associated with this command operation.

[0029] The system maps the command identifier to the target storage location in the storage structure. Subsequently, the captured timestamp data is transmitted through the data write path and stored in the target storage location, completing the recording of the moment the event occurred.

[0030] In some preferred embodiments, storing the system master time as the timestamp of the command operation in a storage location corresponding to the command identifier of the command operation includes: in response to the occurrence of the command operation, obtaining the command identifier corresponding to the command operation; generating a target storage address in the storage structure based on the command identifier; and writing the current system master time as the timestamp into the target storage address.

[0031] In practice, in response to an event signal indicating a command operation has occurred, the system first extracts the command identifier corresponding to the command operation from the command scheduling logic or command descriptor. The command identifier is typically a unique numerical index within a multi-command context.

[0032] The system inputs the command identifier to the address generation logic unit. The address generation logic calculates the target storage address in the physical storage space according to preset mapping rules, such as adding a fixed base address before the command identifier, or directly using the command identifier as an offset.

[0033] While generating the target memory address, the system latches the current global counter value as a timestamp. Subsequently, the system places the timestamp data on the data bus and the target memory address on the address bus, while issuing a write command to write the timestamp to the memory cell specified by the target memory address.

[0034] In this embodiment of the invention, by explicitly defining the steps for generating the target storage address based on the command identifier, a clear and feasible path is provided for the efficient and ordered storage of timestamps. This ensures that, in a multi-command concurrent environment, the occurrence time of each command can be accurately recorded in independent, non-conflicting storage units, avoiding data overwriting or corruption. This identifier-based address mapping mechanism has simple logic and can usually be implemented through direct addressing or simple calculations, eliminating the need for complex address management logic and reducing control complexity.

[0035] In some preferred embodiments, the storage structure is a register file, and the step of writing the current system master time as a timestamp to the target storage address includes: inputting the timestamp to the data input port of the register file; inputting the target storage address to the address selection port of the register file; and issuing a write enable signal to the register file to store the timestamp into the target storage address.

[0036] In practice, the storage structure is implemented using a register file. The register file contains a set of memory cells with independent addresses, a data input port, an address selection port, and a write enable control port.

[0037] When writing a timestamp, the system applies the timestamp value to be written to the data input port of the register file. This timestamp value is derived from the latched current system master time.

[0038] Furthermore, the system applies the generated target memory address to the address selection port of the register file. The signals on the address selection port are used to decode and select a specific register in the register file as the write target.

[0039] Furthermore, the system then sends a valid pulse signal to the write enable control port of the register file. During the validity of this write enable pulse, the internal circuitry of the register file latches the timestamp value on the data input port and stores it in the register selected by the address selection port, thus completing the data writing.

[0040] S3, in a polling manner, read the timestamps corresponding to incomplete command operations from the storage location.

[0041] In practice, the timestamp reading is performed by a polling control unit. This control unit periodically initiates the scanning process at preset time intervals. Within each polling cycle, the control unit generates a series of consecutive read addresses in a predetermined order, with each address corresponding to a location in the storage structure that may contain a valid timestamp.

[0042] In some preferred embodiments, the step of reading the timestamps corresponding to incomplete command operations from the storage location in a polling manner includes: starting the polling process periodically according to a preset polling cycle; generating read addresses corresponding to each storage location in sequence during each polling process; and reading the timestamps from the storage location sequentially according to the read addresses.

[0043] In practice, the system is configured with a polling timer that operates based on the system clock and has a preset configurable period value. When the timer expires, it generates a periodic polling trigger signal.

[0044] The polling control unit responds to the polling trigger signal and initiates a complete scan process. During the scan, the state machine or counter inside the control unit starts working, sequentially generating a continuous address sequence from the start address to the end address.

[0045] Each generated address is used as a read address and output to the address port of the memory structure. At the same time, the control unit sends a read enable signal to the memory structure.

[0046] After receiving the read enable signal and read address, the storage structure outputs the data stored in the corresponding address unit, i.e. the timestamp, to its data output port after one or more clock cycles, for subsequent modules to read.

[0047] This embodiment achieves a balance between flexibility and system overhead in timeout detection by introducing a configurable polling cycle and a sequential address generation mechanism. The configurable polling cycle allows system designers or administrators to adjust the frequency of timeout detection according to actual application scenarios. In scenarios requiring rapid response, the cycle can be shortened; in scenarios prioritizing lower power consumption, the cycle can be extended, thereby dynamically optimizing system performance and energy efficiency. The sequential address generation mechanism has simple and reliable control logic, is easy to implement using a hardware state machine, and avoids the additional overhead caused by complex random access or search logic.

[0048] S4. Calculate the execution duration of the command operation based on the current system master time and the read timestamp.

[0049] In practice, for each generated read address, the system retrieves the stored timestamp data from the corresponding location in the storage structure via the data read path. This data is then output for subsequent calculations.

[0050] The calculation of the execution duration of the command operation is performed by a shared subtractor circuit. This circuit receives two input data: one is a timestamp read from a storage location, and the other is the current system master time. The subtractor performs an arithmetic operation by subtracting the timestamp from the current system master time.

[0051] The difference result generated by the operation is sent out from the output of the subtractor. This result is the execution time of the command operation from the start to the current moment.

[0052] In some preferred embodiments, calculating the execution duration of the command operation based on the current system master time and the read timestamp includes: inputting the read timestamp to the first input terminal of a preset shared subtractor circuit; inputting the current system master time to the second input terminal of the shared subtractor circuit; wherein the shared subtractor circuit performs the operation of subtracting the value of the first input terminal from the value of the second input terminal, and outputs the execution duration.

[0053] In practice, the system includes a shared subtractor circuit. This circuit has a first input terminal, a second input terminal, and an output terminal.

[0054] Furthermore, when calculating the execution time, the system will read the timestamp value from the storage structure and transmit it to the first input of the shared subtractor circuit.

[0055] Furthermore, the system simultaneously transmits the current count value of the global counter, i.e. the current system master time, to the second input of the shared subtractor circuit.

[0056] Furthermore, the shared subtractor circuit is enabled to perform subtraction operations. Its internal logic performs the operation of subtracting the value at the first input from the value at the second input.

[0057] Furthermore, after the calculation is completed, the resulting difference is output from the subtractor circuit. This output value is defined as the execution time of the command operation and is passed to the next processing stage.

[0058] In this embodiment, a high degree of reuse of critical computing hardware is achieved by using a shared subtractor circuit to centrally calculate the execution time. Compared with the traditional approach of equipping each command queue with an independent timing and difference calculation unit, this embodiment only requires one shared subtractor to serve the timeout checking needs of all commands. This directly results in a significant saving of hardware resources, especially the area of ​​the arithmetic logic unit.

[0059] S5, compare the execution time with a preset timeout threshold to determine whether the command operation has timed out.

[0060] In practice, the comparison between the executed duration and a preset timeout threshold is performed by a shared comparator circuit. The comparator receives two inputs: the executed duration output from the subtractor, and a fixed timeout threshold read from the configuration register. The comparator circuit compares the two input values. If the executed duration is greater than or equal to the timeout threshold, the comparator outputs a valid timeout indication signal; otherwise, the signal remains invalid. This timeout indication signal is the final judgment result.

[0061] In this embodiment of the invention, a globally unified system master time is used as the time base, combined with a method of recording and centrally storing static timestamps for each command operation, replacing the traditional approach of allocating independent dynamic counters for each command. This fundamental change brings significant resource optimization effects. Since the timestamp is only written once when the command occurs, and only needs to be read and used for calculation afterward, there is no need to maintain a continuously running timing circuit for each command, thus saving a significant amount of hardware resources that would otherwise be used to implement multiple independent counters, such as triggers, incrementing logic, and associated wiring. At the same time, the calculation (time difference calculation) and comparison operation required for timeout judgment are changed from distributed to centralized processing, allowing the system to reuse the same set of calculation and comparison logic units to process commands in all queues, avoiding redundant construction of logic resources. This architecture makes the system hardware resource overhead, especially area and number of logic gates, no longer linearly related to the number of command queues, thus achieving significantly lower hardware implementation costs and power consumption in scenarios supporting high-concurrency command processing in multiple queues, and improving the scalability of hardware design.

[0062] In some preferred embodiments, comparing the executed duration with a preset timeout threshold includes: inputting the executed duration output by the shared subtractor circuit to the first comparison terminal of the preset shared comparator circuit; inputting the pre-configured timeout threshold to the second comparison terminal of the shared comparator circuit, wherein the shared comparator circuit performs the comparison operation, and outputs a timeout indication signal when the executed duration is greater than or equal to the timeout threshold.

[0063] In practice, the system includes a shared comparator circuit. This circuit has a first comparison terminal, a second comparison terminal, and a comparison result output terminal.

[0064] Furthermore, during the comparison operation, the system transmits the execution duration value output by the shared subtractor circuit to the first comparison terminal of the shared comparator circuit.

[0065] Furthermore, the system transmits the value pre-stored in the timeout threshold configuration register to the second comparison terminal of the shared comparator circuit.

[0066] Furthermore, the shared comparator circuit is enabled to perform comparison operations. Its internal logic continuously determines whether the value at the first comparison terminal is greater than or equal to the value at the second comparison terminal.

[0067] Furthermore, if the condition is met, the shared comparator circuit generates and maintains a valid timeout indication signal at its output, such as a logic high level. If the condition is not met, it outputs an invalid signal, such as a logic low level.

[0068] In this embodiment, the centralized threshold comparison using a shared comparator circuit further enhances the advantages of hardware resource reuse. Comparator circuits, especially wide digital comparators, also require logic gate resources for their hardware implementation. This embodiment allows timeout judgments for all command queues to reuse the same comparator, completely eliminating the resource overhead of equipping each independent counter with a dedicated comparator. This centralized processing not only saves the logic resources required for the comparator itself and its input / output interfaces but also unifies the comparison logic and judgment criteria, ensuring consistency in timeout judgments throughout the entire system.

[0069] It should be noted that, in this embodiment of the invention, the shared subtractor circuit and the shared comparator circuit are driven sequentially by a polling controller, and each time only the timestamp of one command and the current system master time are processed for calculation and comparison.

[0070] In some preferred embodiments, after determining whether the command operation has timed out, the method further includes: if the command operation is determined to have timed out, triggering a preset timeout processing logic to generate a timeout alarm signal; generating a storage address to be cleared based on the command identifier corresponding to the current polling; and issuing a clearing instruction to the storage structure to clear the timestamp stored in the storage address to be cleared.

[0071] In practice, when the shared comparator outputs a valid timeout indication signal, the signal triggers the system's timeout processing state machine.

[0072] Furthermore, after the timeout handling state machine enters the active state, the first step it performs is to generate a timeout alarm signal. This signal is then sent to the system's error management unit or host interface controller.

[0073] Furthermore, the system records the command identifier corresponding to the command that is currently being processed and has triggered a timeout. This identifier originates from the read address used in the current polling cycle or its associated context information.

[0074] Furthermore, the system uses this command identifier to calculate the corresponding storage address to be cleared through address generation logic. This address is the same as the address used when the command timestamp was initially written.

[0075] Furthermore, the system finally issues a clearing operation command to the storage structure for the storage address to be cleared. This command is typically a write command that writes a preset invalid value (such as all zeros) to the address, thereby overwriting the original timestamp data and achieving clearing.

[0076] This embodiment specifies the system response and resource cleanup mechanism after timeout determination, ensuring the integrity of the timeout control process and the sustainable utilization of system resources. Automatically triggering timeout processing logic ensures that upon detecting a timeout event, the system can take timely and automatic predetermined measures, such as reporting errors or initiating fault-tolerant processing, improving the system's autonomy and reliability. The step of generating the address to be cleared based on the command identifier and executing the clearing operation is crucial. It accurately locates and releases the storage resources occupied by timestamp records that have expired due to command timeout, preventing storage space from being occupied by invalid data for a long time, thus preventing resource exhaustion.

[0077] In some preferred embodiments, the method further includes: in response to the completion of a command operation, obtaining a command identifier corresponding to the completed command operation; generating a completion clear address based on the command identifier corresponding to the completed command operation; and issuing a clear instruction to a storage structure to clear the timestamp stored in the completion clear address.

[0078] In practice, when the command execution unit completes all operations of a command and generates a completion status, the system will capture the completion event.

[0079] The system extracts the command identifier corresponding to the completed command operation from the notification information of the completion event.

[0080] The system inputs the command identifier into the address generation logic to calculate the corresponding completion clear address. This address points to the physical location in the storage structure where the timestamp of the command is recorded.

[0081] The system then issues a clear operation command to the storage structure for this cleared address. This command is also a command that writes an invalid value to clear the old timestamp data stored in that address unit.

[0082] In this embodiment of the invention, a proactive cleanup mechanism is added when a command completes normally, thereby optimizing the management efficiency of storage resources. In a high-concurrency SSD processing environment, command completion is a more frequent event. This embodiment ensures that once a command completes normally, its corresponding historical timestamp record can be immediately cleared, rather than passively clearing it only after polling detects a timeout. This significantly shortens the average time storage units are occupied and accelerates the turnover rate of storage resources.

[0083] Please see Figure 2 , Figure 2 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 can be a terminal or a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.

[0084] The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0085] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. When the computer program 5032 is executed, it causes the processor 502 to execute a low-cost SSD multi-queue timeout control method.

[0086] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0087] The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a low-cost SSD multi-queue timeout control method.

[0088] The network interface 505 is used for network communication with other devices. Those skilled in the art will understand that the above structure is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. A specific computer device 500 may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements.

[0089] The processor 502 is used to run a computer program 5032 stored in the memory to perform the following steps: Provides global system master time; When a command operation occurs, the system master time is used as the timestamp of the command operation and stored in the storage location corresponding to the command identifier of the command operation; The timestamps corresponding to incomplete command operations are read from the storage location in a polling manner. Calculate the execution duration of the command operation based on the current system master time and the read timestamp; The execution time is compared with a preset timeout threshold to determine whether the command operation has timed out.

[0090] Optionally, storing the system master time as the timestamp of the command operation in the storage location corresponding to the command identifier of the command operation includes: In response to a command operation, obtain the command identifier corresponding to the command operation; Based on the command identifier, the target storage address in the storage structure is generated; Write the current system master time as a timestamp to the target storage address.

[0091] Optionally, the storage structure is a register file, and the step of writing the current system master time as a timestamp to the target storage address includes: Input the timestamp into the data input port of the register file; Enter the target memory address into the address selection port of the register file; A write enable signal is sent to the register file to store the timestamp into the target memory address.

[0092] Optionally, the step of reading the timestamps corresponding to incomplete command operations from the storage location in a polling manner includes: The polling process is initiated periodically according to a preset polling cycle; During each polling process, read addresses corresponding to each of the aforementioned storage locations are generated sequentially. Based on the read address, read the timestamps from the storage locations sequentially.

[0093] Optionally, calculating the execution duration of the command operation based on the current system master time and the read timestamp includes: The read timestamp is input to the first input terminal of the preset shared subtractor circuit; The current system master time is input to the second input terminal of the shared subtractor circuit; wherein, the shared subtractor circuit performs the operation of subtracting the value of the first input terminal from the value of the second input terminal, and outputs the execution duration.

[0094] Optionally, comparing the executed duration with a preset timeout threshold includes: The execution time output by the shared subtractor circuit is input to the first comparison terminal of the preset shared comparator circuit; The pre-configured timeout threshold is input to the second comparison terminal of the shared comparator circuit, wherein the shared comparator circuit performs a comparison operation, and outputs a timeout indication signal when the execution time is greater than or equal to the timeout threshold.

[0095] Optionally, after determining whether the command operation has timed out, the method further includes: If the command operation is determined to have timed out, a preset timeout processing logic is triggered to generate a timeout alarm signal; Based on the command identifier corresponding to the current polling, generate the storage address to be cleared; A clear command is issued to the storage structure to clear the timestamp stored in the storage address to be cleared.

[0096] Optionally, the method further includes: In response to the completion of a command operation, obtain the command identifier corresponding to the completed command operation; Generate a cleanup address based on the command identifier corresponding to the completed command operation; A clear command is issued to the storage structure to clear the timestamp stored in the cleared address.

[0097] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0098] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program may be stored in a storage medium, which is a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0099] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program. When executed by a processor, the computer program causes the processor to perform the following steps: Provides global system master time; When a command operation occurs, the system master time is used as the timestamp of the command operation and stored in the storage location corresponding to the command identifier of the command operation; The timestamps corresponding to incomplete command operations are read from the storage location in a polling manner. Calculate the execution duration of the command operation based on the current system master time and the read timestamp; The execution time is compared with a preset timeout threshold to determine whether the command operation has timed out.

[0100] Optionally, storing the system master time as the timestamp of the command operation in the storage location corresponding to the command identifier of the command operation includes: In response to a command operation, obtain the command identifier corresponding to the command operation; Based on the command identifier, the target storage address in the storage structure is generated; Write the current system master time as a timestamp to the target storage address.

[0101] Optionally, the storage structure is a register file, and the step of writing the current system master time as a timestamp to the target storage address includes: Input the timestamp into the data input port of the register file; Enter the target memory address into the address selection port of the register file; A write enable signal is sent to the register file to store the timestamp into the target memory address.

[0102] Optionally, the step of reading the timestamps corresponding to incomplete command operations from the storage location in a polling manner includes: The polling process is initiated periodically according to a preset polling cycle; During each polling process, read addresses corresponding to each of the aforementioned storage locations are generated sequentially. Based on the read address, read the timestamps from the storage locations sequentially.

[0103] Optionally, calculating the execution duration of the command operation based on the current system master time and the read timestamp includes: The read timestamp is input to the first input terminal of the preset shared subtractor circuit; The current system master time is input to the second input terminal of the shared subtractor circuit; wherein, the shared subtractor circuit performs the operation of subtracting the value of the first input terminal from the value of the second input terminal, and outputs the execution duration.

[0104] Optionally, comparing the executed duration with a preset timeout threshold includes: The execution time output by the shared subtractor circuit is input to the first comparison terminal of the preset shared comparator circuit; The pre-configured timeout threshold is input to the second comparison terminal of the shared comparator circuit, wherein the shared comparator circuit performs a comparison operation, and outputs a timeout indication signal when the execution time is greater than or equal to the timeout threshold.

[0105] Optionally, after determining whether the command operation has timed out, the method further includes: If the command operation is determined to have timed out, a preset timeout processing logic is triggered to generate a timeout alarm signal; Based on the command identifier corresponding to the current polling, generate the storage address to be cleared; A clear command is issued to the storage structure to clear the timestamp stored in the storage address to be cleared.

[0106] Optionally, the method further includes: In response to the completion of a command operation, obtain the command identifier corresponding to the completed command operation; Generate a cleanup address based on the command identifier corresponding to the completed command operation; A clear command is issued to the storage structure to clear the timestamp stored in the cleared address.

[0107] The storage medium is a physical, non-transient storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk, or any other physical storage medium capable of storing program code. The computer-readable storage medium can be non-volatile or volatile.

[0108] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0109] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0110] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0111] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0112] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0113] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0114] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-cost timeout control method for SSD multi-queue systems, characterized in that, include: Provides global system master time; When a command operation occurs, the system master time is used as the timestamp of the command operation and stored in the storage location corresponding to the command identifier of the command operation; The timestamps corresponding to incomplete command operations are read from the storage location in a polling manner. Calculate the execution duration of the command operation based on the current system master time and the read timestamp; The execution time is compared with a preset timeout threshold to determine whether the command operation has timed out.

2. The SSD multi-queue timeout low-cost control method according to claim 1, characterized in that, The step of using the system master time as the timestamp of the command operation and storing it in the storage location corresponding to the command identifier of the command operation includes: In response to a command operation, obtain the command identifier corresponding to the command operation; Based on the command identifier, the target storage address in the storage structure is generated; Write the current system master time as a timestamp to the target storage address.

3. The SSD multi-queue timeout low-cost control method according to claim 2, characterized in that, The storage structure is a register file, and the step of writing the current system master time as a timestamp to the target storage address includes: Input the timestamp into the data input port of the register file; Enter the target memory address into the address selection port of the register file; A write enable signal is sent to the register file to store the timestamp into the target memory address.

4. The SSD multi-queue timeout low-cost control method according to claim 1, characterized in that, The step of reading the timestamps corresponding to incomplete command operations from the storage location in a polling manner includes: The polling process is initiated periodically according to a preset polling cycle; During each polling process, read addresses corresponding to each of the aforementioned storage locations are generated sequentially. Based on the read address, read the timestamps from the storage locations sequentially.

5. The SSD multi-queue timeout low-cost control method according to claim 1, characterized in that, The step of calculating the execution duration of the command operation based on the current system master time and the read timestamp includes: The read timestamp is input to the first input terminal of the preset shared subtractor circuit; The current system master time is input to the second input terminal of the shared subtractor circuit; wherein, the shared subtractor circuit performs the operation of subtracting the value of the first input terminal from the value of the second input terminal, and outputs the execution duration.

6. The SSD multi-queue timeout low-cost control method according to claim 5, characterized in that, The step of comparing the executed time with a preset timeout threshold includes: The execution time output by the shared subtractor circuit is input to the first comparison terminal of the preset shared comparator circuit; The pre-configured timeout threshold is input to the second comparison terminal of the shared comparator circuit, wherein the shared comparator circuit performs a comparison operation, and outputs a timeout indication signal when the execution time is greater than or equal to the timeout threshold.

7. The SSD multi-queue timeout low-cost control method according to claim 1, characterized in that, After determining whether the command operation has timed out, the method further includes: If the command operation is determined to have timed out, a preset timeout processing logic is triggered to generate a timeout alarm signal; Based on the command identifier corresponding to the current polling, generate the storage address to be cleared; A clear command is issued to the storage structure to clear the timestamp stored in the storage address to be cleared.

8. The SSD multi-queue timeout low-cost control method according to claim 1, characterized in that, The method further includes: In response to the completion of a command operation, obtain the command identifier corresponding to the completed command operation; Generate a cleanup address based on the command identifier corresponding to the completed command operation; A clear command is issued to the storage structure to clear the timestamp stored in the cleared address.

9. A computer device, characterized in that, The computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, can implement the method as described in any one of claims 1-8.

Images