Memory access method and switch

Abstract

The invention provides a memory access method and a switch. The method comprises the following steps: receiving at least one memory access message sent by a target computing node in a plurality of computing nodes; different switching domain destination addresses are carried in the memory access messages; different switching domain destination addresses belong to a switching domain address space, and switching domain addresses in the switching domain address space are logic address spaces formed by uniformly addressing physical addresses in physical address spaces of a plurality of storage nodes; different switching domain destination addresses are discretely distributed in the switching domain address space; converting each switching domain destination address into a corresponding first physical address based on a one-to-one linear mapping relationship between a switching domain address in the switching domain address space and a physical address in the physical address space; and forwarding each memory access message to a first storage node corresponding to each first physical address based on the first physical address corresponding to each switching domain destination address.

Description

Technical Field

[0001] This application relates to data storage technology, and more particularly to a memory access method and a switch. Background Technology

[0002] With the surge in demand for video memory capacity and access bandwidth from large-scale artificial intelligence (AI) models, related technologies face fundamental challenges. Mainstream memory pooling solutions tightly couple computing and storage units, resulting in a lack of flexibility in the allocation of computing and memory resources, making dynamic optimization of resource configuration difficult. While data offloading solutions can expand capacity by moving inactive data out of memory to free up space, they are limited by the PCIe (Peripheral Component Interconnect Express) bus and external network bandwidth, leading to high data access latency and impacting overall computing efficiency. Summary of the Invention

[0003] This application provides a memory access method and a switch.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides a memory access method applied to a switch connected to multiple compute nodes and multiple storage nodes; the method includes: The system receives at least one memory access message sent by a target computing node among the plurality of computing nodes; each memory access message carries a different swap domain destination address; the different swap domain destination addresses belong to a swap domain address space, and the swap domain addresses in the swap domain address space are logical address spaces formed by uniformly addressing the physical addresses in the physical address spaces of the plurality of storage nodes; the different swap domain destination addresses are discretely distributed in the swap domain address space. Based on the one-to-one linear mapping relationship between the switch domain address in the switch domain address space and the physical address in the physical address space, each of the switch domain destination addresses is converted into the corresponding first physical address; Based on the first physical address corresponding to each of the switching domain destination addresses, each memory access message is forwarded to the first storage node corresponding to each of the first physical addresses.

[0005] This application embodiment provides a switch that connects multiple computing nodes and multiple storage nodes, the switch comprising: Input / output ports The memory is used to store a one-to-one linear mapping relationship between the switch domain addresses in the switch domain address space and the physical addresses in the physical address spaces of the multiple storage nodes; the switch domain addresses in the switch domain address space are the logical address space formed by uniformly addressing the physical addresses in the physical address spaces of the multiple storage nodes. A processor, coupled to the input / output port and the memory, is configured to: receive at least one memory access message sent by a target computing node among the plurality of computing nodes; each memory access message carries a different switching domain destination address; the different switching domain destination addresses belong to the switching domain address space; the different switching domain destination addresses are discretely distributed in the switching domain address space; based on the one-to-one linear mapping relationship stored in the memory, convert each switching domain destination address into a corresponding first physical address; and forward each memory access message to a first storage node corresponding to each of the first physical addresses based on the first physical addresses corresponding to each of the switching domain destination addresses. Attached Figure Description

[0006] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0007] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0008] Figure 1 This is a schematic diagram of a system architecture for GPU direct-attached storage provided by related technologies; Figure 2 This is a flowchart illustrating a memory access method provided in an embodiment of this application; Figure 3 This is a topology diagram of an on-net storage solution provided in an embodiment of this application; Figure 4 This is a schematic diagram of the hardware composition of a storage node provided in an embodiment of this application; Figure 5 This is a schematic diagram of storage space allocation provided in an embodiment of this application; Figure 6This is a schematic diagram illustrating the hardware-level execution process of a write memory barrier mechanism provided in an embodiment of this application. Figure 7 This is a schematic diagram of the structure of a memory access device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a switch provided in an embodiment of this application. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of this application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0010] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0011] In the following description, references to "some embodiments," "this embodiment," "this application embodiment," and examples, etc., describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subset of all possible embodiments and may be combined with each other without conflict.

[0012] The terms "first," "second," and "third" appearing in the embodiments of this application do not have a specific meaning (e.g., there is no order, nor does it indicate a special limitation on the number of devices in the embodiments of this application), but are merely for the purpose of clearly describing the embodiments of this application and do not constitute any limitation on the embodiments of this application. The term "multiple" appearing in the embodiments of this application refers to two or more integers.

[0013] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies or terms of the embodiments of this application are described below. The following related technologies or related terms are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and all of them fall within the protection scope of the embodiments of this application.

[0014] In the current training and inference of large models, the problem of insufficient GPU memory resources is becoming increasingly prominent. Due to the exponential growth in the number of model parameters, the GPU memory of a single graphics card is insufficient to support the complete model structure and intermediate computational data. Taking tensor parallelism as an example, model layers need to be split into different Graphics Processing Units (GPUs), but the intermediate data such as activation values ​​and gradients generated by each layer still require a large amount of GPU memory. Furthermore, the intermediate results of the forward computation need to be retained during backpropagation, further squeezing GPU memory space. To improve inference efficiency, commonly used optimization techniques (such as key-value caching, quantization, and operator fusion) introduce additional GPU memory overhead.

[0015] In related technologies, the problem of insufficient video memory resources is mainly alleviated in two ways: one is a video memory pooling scheme based on supernodes, and the other is a temporary data storage scheme relying on offloading mechanisms. The video memory pooling scheme based on supernodes interconnects XPUs (accelerated processors with computing capabilities, such as GPUs, TPUs, and FPGAs) on different compute nodes at high speed through a scale-up bus. XPUs can directly access the video memory of any other XPU on the supernode. Taking the GB200 NVL72 integrated rack system as an example, the bandwidth for GPU compute units accessing local video memory is 4.1TB / s, and the bandwidth for accessing remote video memory is 1.8TB / s. This scheme can combine the video memory of all XPUs within the supernode into a huge virtual video memory or video memory pool, greatly alleviating the problem of insufficient video memory for a single XPU. However, it also has the drawback of inflexible allocation of computing and video memory resources. For example, in long-context inference scenarios, XPU computing power is excessive, while video memory resources are scarce, and each XPU faces a situation of insufficient video memory. Video memory pooling cannot achieve the mutual exchange of video memory. Data temporary storage solutions that rely on offloading mechanisms temporarily store data that the XPU will not use for a short period of time on local or remote storage. A typical example of this solution is NVIDIA's GPU Direct Storage (GDS) technology. Figure 1 As shown, node A and node B are connected and communicate via the network, enabling them to share resources and collaboratively complete complex computing tasks. GDS technology supports a direct memory access (DMA) data path between video memory and storage, avoiding buffer bounces through the central processing unit (CPU), thereby improving system bandwidth and reducing latency. However, the problem with this approach is that data transfer bandwidth is limited by the PCIe bus and external network, typically being an order of magnitude lower than that of memory pooling solutions.

[0016] To address at least one of the aforementioned problems in the related technologies, this application proposes a memory access method based on a supernode-oriented on-network storage mechanism. This mechanism introduces a switch to directly connect to storage nodes, enabling computing nodes to directly access the physical address space of remote storage nodes, significantly improving bandwidth utilization and the flexibility of storage resource allocation.

[0017] It should be noted that the memory access methods provided in the embodiments of this application can be executed by a switch, wherein the switch connects multiple computing nodes and multiple storage nodes. That is, the memory access methods in the embodiments of this application can achieve efficient access to remote storage space through a switch.

[0018] Figure 2 This is a flowchart illustrating a memory access method provided in an embodiment of this application. The method is applied to a switch connected to multiple compute nodes and multiple storage nodes. Figure 2 As shown, the method may include the following steps 201 to 203: Step 201: Receive at least one memory access message sent by the target computing node among the plurality of computing nodes; each memory access message carries a different swap domain destination address; the different swap domain destination addresses belong to a swap domain address space, and the swap domain addresses in the swap domain address space are logical address spaces formed by uniformly addressing the physical addresses in the physical address spaces of the plurality of storage nodes; the different swap domain destination addresses are discretely distributed in the swap domain address space.

[0019] It is understood that the switch in this embodiment connects multiple computing nodes and multiple storage nodes, and can be used to route access requests within the physical address space of shared memory formed by multiple storage nodes. Multiple storage nodes provide storage resources and can be accessed by multiple computing nodes, where multiple computing nodes can be understood as multiple XPUs (such as GPUs, TPUs, and FPGAs).

[0020] It should be noted that the Fabric Address (FA) within the switching domain address space is a logical address within a uniformly addressed logical address space. The FA is used to identify the physical address on a storage node and is routed and forwarded through a switch, enabling cross-node data access. The FA does not have physical meaning; rather, it serves as part of the unified addressing mechanism, facilitating access to shared storage resources by multiple compute nodes. The switching domain address space covers the physical address spaces of multiple storage nodes.

[0021] It should be noted that the Physical Address (PA) refers to the address of the actual hardware device (such as a memory chip) inside the storage node. Each storage node has its own independent physical address space, and the PA is the hardware location where data is ultimately written to or read from.

[0022] It's important to note that memory access packets are data packets sent by compute nodes to the switch to request read or write operations on specific physical address locations within storage nodes. The destination address carried in each packet represents the logical location of the destination address to be accessed. These destination addresses are not contiguous in the switch domain address space; they are discretely distributed. This discrete distribution means that multiple packets can be concurrently distributed to multiple storage nodes without overloading any single storage node, thus maximizing the utilization of all storage resources.

[0023] In this embodiment, the switch can receive a memory access request from any target computing node from multiple computing nodes. The memory access request is sent in the form of a memory access packet. Each memory access packet contains a switching domain destination address. Unlike traditional local physical addresses, the switching domain destination address does not have physical meaning, but is part of the logical addressing mechanism for cross-node data access.

[0024] It should be noted that when the target compute node needs to write a small amount of data, it generates and sends a single memory access message. When the amount of data to be written is large, the target compute node divides the large data block into multiple smaller data blocks and generates multiple memory access messages accordingly. Each message carries a small data block, and these multiple memory access messages are sent to the switch. The target compute node can be any one of multiple compute nodes. The target compute node refers to the XPU device that needs to request remote storage resources, such as a GPU or CPU.

[0025] Step 202: Based on the one-to-one linear mapping relationship between the switch domain address in the switch domain address space and the physical address in the physical address space, convert each of the switch domain destination addresses into the corresponding first physical address.

[0026] It's important to note that a one-to-one linear mapping refers to the one-to-one correspondence established between the address space of the switching domain and the physical address space of each storage node. That is, each switching domain address can be uniquely identified by this mapping relationship in terms of its physical address on a specific storage node; in other words, each switching domain address FA corresponds to a unique physical address PA. This mapping relationship can be established during the switch initialization phase and remains stable throughout the entire system operation, ensuring efficient and consistent memory access. Linear mapping implies the absence of complex jumps or non-linear translations. The relationship between each switching domain destination address and its physical address is direct and unique. Linear mapping significantly simplifies the switch's routing logic and improves data transmission efficiency.

[0027] For example, suppose a certain switching domain destination address is FA-001, and FA-001 is mapped to the starting address PA-1000 of a certain storage node. When the switch receives a memory access packet for the switching domain destination address FA-001, the switch will look up a pre-established one-to-one linear mapping table between switching domain addresses and physical addresses, find the corresponding PA-1000 for the switching domain destination address FA-001, and replace the switching domain destination address FA-001 in the memory access packet with PA-1000 for subsequent data forwarding operations. This method allows the switch to quickly locate the target storage location, reducing addressing latency.

[0028] In some embodiments, the switch can maintain a complete one-to-one linear mapping table between switching domain addresses and physical addresses, and load the capacity information of storage nodes during each initialization phase to construct a global address mapping relationship. Due to the use of linear mapping, the switch does not need to perform complex address calculations; it only needs to perform a simple table lookup operation to complete the address translation. The linear mapping design significantly reduces the processing overhead of the switch and improves the overall system response speed.

[0029] Step 203: Based on the first physical address corresponding to each of the switching domain destination addresses, forward each memory access packet to the first storage node corresponding to each of the first physical addresses.

[0030] In this embodiment, the switch forwards the memory access packet to the corresponding first storage node based on the first physical address obtained in step 202. After receiving the corresponding memory access packet, the first storage node can process the corresponding read / write request based on the received memory access packet.

[0031] In some embodiments, the switch can leverage the multi-channel and high-bandwidth characteristics of a scale-up network to access the storage space of storage nodes by employing interleaving and multi-queue methods, thereby improving data transmission efficiency.

[0032] It should be noted that a scale-up network is a high-speed interconnect network that supports low-latency, high-bandwidth communication between multiple compute and storage nodes. It forms the basis for building supernode systems, enabling compute nodes to directly access remote storage resources without relying on CPUs or PCIe buses for intermediate forwarding.

[0033] The memory access method provided in this application receives at least one memory access message from a target computing node among multiple computing nodes via a switch. Each memory access message carries a different destination address of a switching domain. These different destination addresses are discretely distributed in the switching domain address space. Based on the one-to-one linear mapping relationship between switching domain addresses and physical addresses, the switch converts the different destination addresses of the switching domains into the physical addresses of each storage node. This allows access to continuous logical data to be automatically decomposed and concurrently distributed to multiple physical storage nodes, achieving load balancing and bandwidth aggregation of storage resources, effectively breaking through the bandwidth bottleneck of a single storage device. Simultaneously, because computing nodes and storage nodes are loosely interconnected through the switch, computing resources and storage resources can be independently and elastically expanded. This provides high-bandwidth, low-latency remote memory direct access capabilities while overcoming the rigid resource allocation of traditional pooling schemes and the long access paths and high latency of data offloading schemes.

[0034] In some embodiments, the different swap domain destination addresses carried in each memory access message are obtained by the target computing node converting the virtual addresses in the target virtual address segment to be accessed by the target computing node based on a specific mapping relationship; the specific mapping relationship is configured to: map continuous virtual addresses in the virtual address space to discrete swap domain addresses in the swap domain address space based on a specific interleaving strategy.

[0035] It's important to note that a Virtual Address (VA) is an address used during program execution. A target virtual address range refers to a contiguous range of virtual addresses accessed by the target computing node during program execution. The target virtual address range represents the location where data, parameters, or intermediate results required by the program are stored. By mapping virtual addresses in the target virtual address range to the swap address space, remote direct access operations across computing nodes can be achieved, thereby improving data access efficiency.

[0036] In this embodiment, a specific mapping relationship is configured to map contiguous virtual addresses in the virtual address space to discrete switch domain addresses in the switch domain address space based on a specific interleaving strategy. Specifically, the specific interleaving strategy distributes originally contiguous virtual address blocks across multiple independent switch domain addresses according to a certain pattern. For example, low-order interleaving can be used to allocate adjacent virtual addresses to different physical storage locations, reducing the pressure of single-point access, alleviating performance degradation caused by single-path congestion, and simultaneously improving parallel access capabilities.

[0037] It should be noted that contiguous virtual addresses in the virtual address space are mapped to discrete switch domain addresses in the switch domain address space. This means that each contiguous virtual address block no longer corresponds to the same physical storage unit, but is distributed across multiple different storage nodes. This fully utilizes the high bandwidth characteristics of the Scale-Up interconnect architecture to improve the concurrency and efficiency of data access.

[0038] In some embodiments, the target compute node can establish a specific mapping relationship during the initialization phase and record this specific mapping relationship in its local page table. Before performing memory access operations, the target compute node can query the specific mapping relationship recorded in its local page table to obtain the swap domain address corresponding to the virtual address within the target virtual address segment to be accessed by the target compute node, thereby enabling the XPU program to access the storage resources of the remote storage node as if it were accessing local video memory.

[0039] This application's embodiments map consecutive virtual addresses to discrete addresses in the swap domain address space based on a specific interleaving strategy when the target computing node initiates memory access. This design reduces frequent accesses from the same computing node to the same storage node, mitigating local hotspot issues, and also facilitates subsequent parallel data writing and reading, improving memory access efficiency and load balancing capabilities.

[0040] In some embodiments, the memory access method further includes: The system receives a memory barrier instruction message sent by the target computing node; the memory barrier instruction message is used to instruct sequential consistency constraints on memory access to swap domain addresses within the target swap domain address set; the swap domain addresses within the target swap domain address set are swap domain addresses that the target computing node can access in memory; Based on the one-to-one linear mapping relationship, determine the second physical address corresponding to each switching domain address in the target switching domain address set; The memory barrier instruction message is forwarded to the second storage node corresponding to each of the second physical addresses; After receiving confirmation messages from each of the second storage nodes, a memory barrier completion message is sent to the target computing node; the confirmation message indicates that the second storage node that sent the confirmation message has completed memory access for the swap domain address within the target swap domain address set.

[0041] It should be noted that a memory barrier instruction message is a control instruction issued by a compute node to ensure the consistency of memory access order for a specific memory region. In this embodiment, the function of the memory barrier instruction message is to ensure that read and write operations on all swap domain addresses within the target swap domain address set are completed in the order expected by the program, thereby avoiding data inconsistency problems caused by asynchronous access. When a memory barrier instruction is executed, it suspends the execution of subsequent instructions until all previously issued memory operations are completed and acknowledged by the target storage node.

[0042] It should be noted that the target swap domain address set refers to a range of swap domain addresses designated for synchronization operations. The swap domain addresses within the target swap domain address set can be distributed across different storage nodes, and are the swap domain addresses that the target compute node can access in memory.

[0043] It is understood that the second physical address in this embodiment refers to the actual location where data is stored within the storage node. The switch, by converting each switch domain address within the target switch domain address set into its corresponding second physical address, can correctly route memory barrier instruction messages to the target storage location.

[0044] It should be noted that forwarding the memory barrier instruction message to the second storage node corresponding to each second physical address is essentially about broadcasting or forwarding the memory barrier instruction message to all storage nodes related to the target swap domain address set, so as to ensure that the corresponding storage nodes can receive the memory barrier instruction message and suspend or process the current read and write operations accordingly.

[0045] It should be noted that the acknowledgment message is a feedback signal sent by each secondary storage node after completing a memory access to a switch domain address within the target switch domain address set. It serves to notify the target compute node that the secondary storage node has completed the specified operation. The acknowledgment message may include information such as the operation status, timestamp, and error code to help the system determine whether a retry or other measures are needed. The memory barrier completion message is a notification returned by the switch to the target compute node that initiated the memory barrier instruction message after confirming that all secondary storage nodes have successfully processed the memory barrier instruction. The memory barrier completion message indicates that the current memory barrier operation has been completed, and the target compute node can continue to perform subsequent read and write operations.

[0046] In this embodiment, the target compute node sends a memory barrier instruction message to the switch. Upon receiving the message, the switch determines the second storage node corresponding to each second physical address within the target switching domain address set based on a one-to-one linear mapping relationship, and forwards the memory barrier instruction message to the corresponding second storage node. Subsequently, the second storage node corresponding to each second physical address processes memory accesses for switching domain addresses within the target switching domain address set and sends back confirmation information. Finally, the switch aggregates the confirmation information, generates a memory barrier completion message, and returns it to the target compute node. This series of operations constitutes a complete memory barrier control process, ensuring memory access order and data consistency in a distributed environment.

[0047] This application's embodiments introduce a memory barrier mechanism to ensure data consistency when multiple compute nodes concurrently access shared storage resources. When the target compute node issues a memory barrier instruction message, the switch broadcasts this message to the relevant storage nodes and waits for all related operations to complete before notifying the target compute node to continue executing subsequent tasks. This achieves consistent access control for memory access to switch domain addresses within the target switch domain address set, avoiding data conflicts caused by parallel access.

[0048] In some embodiments, the switch domain addresses within the target switch domain address set are allocated to the target computing node from the switch domain address space by a structure manager that is communicatively connected to the target computing node in response to a storage resource allocation request sent by the target computing node.

[0049] It's important to note that the Fabric Manager is a resource management component used to coordinate resource allocation and management between compute nodes and storage nodes. The Fabric Manager establishes communication connections with each compute node, receives storage resource allocation requests from them, and allocates specific switch domain addresses to the compute nodes within the switch domain address space based on the current load and available resources. The Fabric Manager interacts with each compute node through a pre-defined communication protocol (e.g., Scalable Unified Ethernet (SUE)).

[0050] In some embodiments, the structure manager can be integrated into the switch, giving it a global perspective to enable fine-grained resource management.

[0051] In this embodiment, a storage resource allocation request refers to a message initiated by the target computing node to request the use of remote storage resources. The storage resource allocation request may include the required storage space size, access permissions, and other relevant parameters. After receiving the storage resource allocation request, the structure manager can select a suitable address range in the switching domain address space for allocation according to a preset resource allocation strategy (such as round-robin, on-demand allocation, etc.), and return the allocation result to the target computing node.

[0052] In some embodiments, when a target compute node needs to access remote storage resources, it first sends a storage resource allocation request to the structure manager. The structure manager allocates a corresponding switching domain address to the target compute node based on the current load and available resources, and then feeds back the switching domain address information to the target compute node. The target compute node uses the switching domain address to perform data read and write operations, thereby achieving efficient distributed storage access.

[0053] In some embodiments, when performing large-scale model training or inference tasks, the target compute node can request additional storage resources from the structure manager to meet its video memory requirements. The target compute node initiates a storage resource allocation request through a local agent, which includes information such as the required storage space size and its intended use. The structure manager determines whether to approve the storage resource allocation request based on its content and the current resource status, and returns the selected FA address from the swap domain address space to the target compute node.

[0054] This application embodiment introduces a structure manager to respond to storage resource allocation requests and allocates a switching domain address to the target computing node from the switching domain address space, which can achieve more flexible and efficient storage resource management.

[0055] In some embodiments, the switch domain addresses within the target switch domain address set are allocated to the target computing node by the structure manager from the switch domain address space based on the big page mechanism in response to a storage resource allocation request sent by the target computing node.

[0056] It should be noted that the big-page mechanism is a memory management strategy that improves memory access efficiency and reduces page table overhead by dividing memory into larger pages (e.g., pages are set to 1GB in size). In this embodiment, to reduce the overhead of global resource allocation and improve storage resource utilization, the structure manager uses the big-page mechanism for storage resource allocation. For example, the structure manager allocates storage resources using 1GB big pages.

[0057] It is understood that in this embodiment of the application, the target computing node, as a resource user, actively initiates a storage resource allocation request; the structure manager, as the resource scheduling hub, is responsible for receiving storage resource allocation requests, evaluating the availability of storage resources, and allocating FA address ranges; the big page mechanism is used as an optimization method to improve the efficiency and performance of address allocation; the swap domain address space is the actual carrying area of ​​the resources, providing scalable remote storage capabilities.

[0058] In this embodiment, the structure manager uses a big-page mechanism for storage resource allocation, which can not only improve storage resource utilization, but also reduce the number of page table entries, reduce address translation overhead, and thus reduce the overhead of global storage resource allocation.

[0059] In some embodiments, the switch domain addresses within the target switch domain address set are allocated to the target computing node from the switch domain address space by the structure manager in response to a storage resource allocation request sent by the target computing node, based on a specific interleaving strategy.

[0060] It should be noted that when the structure manager allocates storage resources to the target compute node, it does not simply allocate a contiguous block of space. Instead, based on a specific interleaving strategy (such as low-order interleaving), it allocates a segment of logical address resources with inherent parallel access attributes to the target compute node. The purpose is to ensure that future sequential accesses to this address by applications can be automatically and evenly converted into concurrent accesses to multiple physical storage nodes.

[0061] For example, when an application on a compute node (such as a server running AI training tasks) needs to request remote storage resources (such as 4GB of video memory), it can send a storage resource allocation request to the structure manager through the local driver. This request includes the size of the required resource (such as 4GB). Upon receiving the request, the structure manager does not simply allocate a contiguous 4GB FA space. Instead, it executes an intelligent allocation strategy designed to enable high-performance access in the future. Taking a low-order interleaving strategy as an example, the structure manager allocates an address for this 4GB request from the global FA space. Within the FA subspace associated with storage node 0, the structure manager allocates a 512MB contiguous FA segment, denoted as Segment_0; from the FA subspace associated with storage node 1, it allocates a 512MB contiguous FA segment, denoted as Segment_1; and so on, allocating 512MB for each of the eight storage nodes.

[0062] The structure manager logically interleaves these eight segments, forming a "virtual" contiguous FA address range. Specifically, the first 1MB of this virtual contiguous segment originates from Segment_0, the second from Segment_1, ..., the eighth from Segment_7, and the ninth returns to Segment_0, repeating this cycle until 4GB is filled. Ultimately, the target switching domain address set generated by the structure manager for the compute node is this virtual, logically contiguous, but physically interleaved FA segment range of 4GB. It returns the starting FA address and size of this range to the compute node.

[0063] In some embodiments, the structure manager can record the physical address (PA) of all storage nodes and their corresponding switching domain address (FA), and when it receives a storage resource allocation request from a target computing node, it can allocate addresses using a low-bit interleaving strategy based on the current load and available resources.

[0064] In this embodiment, the structure manager uses a specific interleaving strategy to allocate switching domain addresses, which helps to distribute access pressure, avoid overloading of a single storage node, and thus improve the overall system throughput and stability.

[0065] In some embodiments, the method further includes: Obtain the storage capacity information of each of the aforementioned storage nodes; Based on the storage capacity information of each storage node, the one-to-one linear mapping relationship is established.

[0066] It should be noted that storage capacity information refers to the size and distribution of available storage space possessed by each storage node. The establishment of a linear mapping relationship depends on the storage capacity information of the storage nodes. In this embodiment, the switch obtains the storage capacity information of each storage node and establishes a one-to-one linear mapping relationship between the switching domain address and the physical address based on this information.

[0067] This application embodiment collects the capacity information of each storage node and establishes a one-to-one linear mapping relationship between the switching domain address and the physical address accordingly. This ensures a reasonable distribution of addresses in the switching domain address space and prevents certain storage nodes from becoming bottlenecks. Compared with a fixed mapping method, this application embodiment can better adapt to combinations of storage nodes of different sizes and configurations, improving the scalability and compatibility of the system.

[0068] In some embodiments, establishing the one-to-one linear mapping relationship based on the storage capacity information of each of the storage nodes includes: Based on the storage capacity information of each storage node, the base address offset value corresponding to each storage node in the exchange domain address space is determined; The one-to-one linear mapping relationship is established based on the physical address in the physical address space of each storage node and the base address offset value.

[0069] It's important to note that the base address offset refers to the starting address offset allocated to each storage node in the switching domain address space, used to construct a globally unified address mapping relationship. The base address offset is independent of the actual physical address of the storage node; instead, it is dynamically calculated by the switch based on storage capacity information, ensuring that addresses between different storage nodes do not overlap, thus achieving linear mapping. By using this base address offset-based method, the independent address spaces of multiple storage nodes can be integrated into a logically contiguous switching domain address space, improving address management efficiency.

[0070] In this embodiment, the physical address and base offset value within the physical address space of a storage node are combined to form a final one-to-one linear mapping relationship. For example, if the physical address within the physical address space of a storage node is 0x10000000 and the base offset value is 0x20000000, then the physical address 0x10000000 can be mapped to the swap domain address 0x30000000 in the swap domain address space, i.e., physical address 0x10000000 + base offset value 0x20000000 = swap domain address 0x30000000.

[0071] This application's embodiments introduce a combined mapping mechanism of base address offset and physical address within the physical address space. This allows for the efficient construction of a one-to-one linear mapping between physical addresses and switching domain addresses during the initialization phase, simplifying the subsequent address translation process. This not only reduces the complexity and improves the efficiency of address resolution but also provides fundamental support for subsequent storage resource management and scheduling.

[0072] In some embodiments, the method further includes: The storage capacity information and the one-to-one linear mapping relationship are sent to the structure manager, which is connected to the switch, so that the structure manager can allocate storage resources to the multiple storage nodes based on the storage capacity information and the one-to-one linear mapping relationship.

[0073] In this embodiment, the structure manager is also communicatively connected to a switch. The switch can send the storage capacity information of each storage node and the one-to-one linear mapping relationship between the physical address and the switching domain address to the structure manager, enabling the structure manager to allocate storage resources based on the storage node capacity information and the one-to-one linear mapping relationship between the physical address and the switching domain address. Based on the storage capacity information and the one-to-one linear mapping relationship between the physical address and the switching domain address, the structure manager can ensure that different computing nodes can efficiently access the shared remote storage space, thereby improving the overall system resource utilization and performance.

[0074] It should be noted that communication between the structure manager and the switch relies on high-speed interconnect protocols, such as SUE or other data transmission protocols that support low latency and high bandwidth. Communication between the structure manager and the switch avoids the bandwidth bottlenecks associated with traditional PCIe buses or external networks, thus improving data access efficiency.

[0075] In some embodiments, the structure manager maintains communication connections with each storage node and each compute node. The structure manager receives storage resource allocation requests from compute nodes and, based on the current storage resource usage status, allocates swap domain addresses according to the big-page mechanism and a specific interleaving strategy. Simultaneously, the structure manager can maintain and update the one-to-one linear mapping between physical addresses and swap domain addresses, ensuring that all compute nodes can accurately access the corresponding physical storage addresses.

[0076] This application embodiment synchronizes storage capacity information and mapping relationships to the structure manager, enabling the structure manager to perform resource scheduling and optimization from a global perspective, thereby further improving the utilization rate of storage resources and the operating efficiency of the system.

[0077] The following examples illustrate possible implementation schemes of the memory access method described in one or more of the above embodiments.

[0078] This solution proposes an on-network storage mechanism for supernodes. By introducing scale-up switches to directly connect storage nodes and designing a high-performance memory access mechanism, this mechanism achieves flexible computing power / storage ratios and higher memory access bandwidth. Compared to traditional temporary data storage solutions that rely on offloading mechanisms, this solution can utilize network bandwidth resources more efficiently and meet the needs of different application scenarios.

[0079] Figure 3 This is a topology diagram of an on-network storage solution provided in an embodiment of this application, such as... Figure 3As shown in the diagram, this topology includes N compute nodes (XPU 0 to XPU N-1), K storage nodes (MEM 0 to MEM K-1), and M switching nodes (Switch 0 to Switch M-1), forming an (N+K)×M interconnection topology. These K storage nodes collectively constitute a common storage pool, and all N XPUs can directly access any address space within the storage pool through the scale-up network. The "Port" in the diagram represents input / output (IO) ports.

[0080] It should be noted that, Figure 3 The M switching nodes in the above embodiments represent one implementation of the switch. Figure 3 In the topology diagram shown, a single switch entity is deconstructed into a network consisting of M switching nodes. Access requests from computing nodes can be processed in parallel by multiple switching nodes, and forwarding paths can be selected from multiple links, thus avoiding a single switching chip becoming a performance bottleneck.

[0081] Figure 4 This is a schematic diagram of the hardware composition of a storage node provided in an embodiment of this application, as shown below. Figure 4 As shown, a storage node comprises multiple independently operating storage cards and a management system. Each storage card consists of an I / O port, a storage controller, and a storage chip. Taking the SUE protocol as an example, the I / O port can be an 800G or 1.6T Ethernet interface, the storage controller is a Double Data Rate (DDR) controller, and the storage chip is a DDR chip. Since each storage card operates independently and is connected to the Scale-Up interconnect system through a single I / O port, this solution uses a supernode structure manager to manage the allocation and release of directly connected storage space.

[0082] In some embodiments, the storage allocation and memory access process of the on-network storage mechanism for supernodes may include the following steps 1 to 7: Step 1: Before the program allocates remote storage space, the switching node obtains the capacity information of the directly connected storage card during the initialization phase and establishes a unique mapping relationship between the FA (Functional Provider) within the switching domain and the PA (Parent) on the local storage node. Then, it aggregates the capacity information and mapping relationship to the structure manager and synchronizes the complete information to each compute node. The FA is uniformly allocated by the supernode structure manager. Step 2: When the XPU program calls the remote video memory allocation function, it first sends a storage resource allocation request to the supernode structure manager through the local agent program; Step 3: The structure manager allocates storage space from the FA space in a low-order interleaving manner based on the current storage resource status. Considering the overhead of global resource allocation and the limited resources of storage nodes, the allocation of remote video memory uses a big-page mechanism, with each page set to 1GB in size. Taking K storage nodes as an example, each storage node is allocated 1 / K GB of FA space; Step 4: After obtaining the globally unique FA address segment returned by the structure manager, the XPU program allocates a VA address segment of the same size in the program's VA space and updates the XPU Page Table Entry (PTE) table to record the mapping relationship between VA and FA. All memory access permission related attributes are recorded in the XPU PTE table; Step 5: When the VA address accessed by the XPU program's Load (read) / Store (write) command falls within the range corresponding to the FA, the XPU completes the mapping from VA to FA based on the PTE entry. In the data writing scenario, the XPU distributes large blocks of data across M IO ports using low-order interleaving. Taking SUE as an example, the XPU evenly encapsulates large blocks of data in Ethernet packet sequences of up to 256 bytes and interleaves these packets before sending them to various switching nodes; Step 6: After receiving a write message for a specific FA address, the switching node modifies the write address field in the message header according to the FA-PA mapping relationship recorded by the switching node during the initialization phase, fills in the specific PA space address segment, and finally sends the message to the corresponding memory card. Step 7: After receiving the data packet, the memory card's I / O port parses information such as the destination address and data payload. The memory controller then writes the data into the memory chip of the specific memory card.

[0083] Figure 5 This diagram illustrates a storage space allocation method provided in an embodiment of this application. The PA Space represents the physical address space, which is the private physical memory address within each storage node (e.g., Mem 0, Mem 1). The PA spaces of different storage nodes are independent and repetitive (e.g., each storage node has its own address 0). The FA Space represents the switching domain address space, a globally unique logical address space managed uniformly by the structure manager. It weaves the PA spaces of all storage nodes into a unified "large memory" as seen from the XPU's perspective. The VA Space represents the virtual address space, which is the logical address used during program execution. XPU A is the compute node, and Switch 0 and Switch 1 are switching nodes.

[0084] To fully utilize the multi-channel and high-bandwidth characteristics of the Scale-Up bus, access to remote storage space is implemented using interleaving and multiple queues, which cannot strictly guarantee the consistency between data storage order and program order. In streaming data processing, this lack of consistency between data storage order and program order does not pose a problem. However, for scenarios with strict memory order dependencies, this solution designs a memory fence mechanism based on I / O port queue management.

[0085] Consider the following code snippet as an example: Initialize a=0, b=0; a and b are global variables located in the storage node. The XPU0 program executes function fun1: a=1; b=1; the XPU1 program executes function fun2: while(b==0) continue; assert(a==1). In the write operations of XPU0 on variables a and b, if no order-preserving measures are taken, XPU1 may not maintain the order of visibility when reading variables a and b. In the absence of order-preserving measures in the write operations of XPU0 on variables a and b, this solution introduces a write barrier instruction to ensure the consistency of the data write order. Therefore, in the corrected code, the XPU0 program executes function fun1: a=1; write_fence(); b=1; the XPU1 program executes function fun2: while (read_fence(), b==0) continue; assert(a==1).

[0086] Figure 6 This is a schematic diagram illustrating the hardware-level execution process of a write memory barrier mechanism provided in an embodiment of this application, as shown below. Figure 6 As shown, this demonstrates how the compute node XPU A ensures that all its "in transit" write data has been received and persisted by the storage node through a special barrier operation, thereby establishing a global order across multiple parallel I / O ports.

[0087] In some embodiments, the implementation of the memory barrier mechanism includes the following steps a to d: Step a: To ensure that the data write operation is completed, XPU appends a Write Fence instruction after the store instruction. This instruction is used to pause the execution of subsequent instructions and send a queue append Write Fence message to all IO ports. Step b: After receiving the Write Fence message, the switching node connected to the XPU multicasts the Write Fence message to all IO ports connected to the storage node. Step c: Once all Write Fence messages have been successfully processed, i.e., the current exchange node confirms that the in-transit write data has been processed, it returns a Fence Ack message to the XPU that initiated the Write Fence operation. Step d: After all Write Fence messages are confirmed, the XPU continues to execute subsequent instructions.

[0088] It's worth noting that the Read Fence command achieves a similar synchronization effect to the Write Fence command, but the difference is that the Read Fence command clears any data in transit in the read direction. Using the Write Fence and Read Fence commands together ensures consistent access to the same remote storage space by different XPUs.

[0089] Understandably, the advantage of this solution lies in its highly flexible resource allocation capabilities and superior memory access bandwidth. On the one hand, it allows for flexible configuration of the ratio of computing power to storage space according to actual application needs, thereby better adapting to diverse scenarios; on the other hand, compared to traditional data offloading solutions that rely on the PCIe bus or external networks, this solution achieves significantly higher memory access bandwidth through a tighter integration mechanism, providing more efficient underlying support for high-performance computing and storage-intensive tasks.

[0090] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps; or steps from different embodiments may be combined into a new technical solution.

[0091] Based on the same inventive concept as the foregoing embodiments, this application provides a memory access device.

[0092] Figure 7 This is a schematic diagram of a memory access device provided in an embodiment of this application. The device is applied to a switch connected to multiple compute nodes and multiple storage nodes, such as... Figure 7 As shown, the memory access device 700 includes: a receiving module 710, a conversion module 720, and a transmitting module 730; wherein: The receiving module 710 is configured to receive at least one memory access message sent by a target computing node among the plurality of computing nodes; each memory access message carries a different swap domain destination address; the different swap domain destination addresses belong to a swap domain address space, and the swap domain addresses in the swap domain address space are a logical address space formed by uniformly addressing the physical addresses in the physical address spaces of the plurality of storage nodes; the different swap domain destination addresses are discretely distributed in the swap domain address space. The conversion module 720 is used to convert each of the switching domain destination addresses into corresponding first physical addresses based on the one-to-one linear mapping relationship between the switching domain addresses in the switching domain address space and the physical addresses in the physical address space. The sending module 730 is used to forward each memory access message to a first storage node corresponding to each of the first physical addresses, based on the first physical address corresponding to each of the destination addresses of the switching domains.

[0093] In some embodiments, the different swap domain destination addresses carried in each memory access message are obtained by the target computing node converting the virtual addresses in the target virtual address segment to be accessed by the target computing node based on a specific mapping relationship; the specific mapping relationship is configured to: map continuous virtual addresses in the virtual address space to discrete swap domain addresses in the swap domain address space based on a specific interleaving strategy.

[0094] In some embodiments, the receiving module 710 is further configured to: receive a memory barrier instruction message sent by the target computing node; the memory barrier instruction message is used to instruct sequential consistency constraints on memory access to swap domain addresses within the target swap domain address set; the swap domain addresses within the target swap domain address set are swap domain addresses that the target computing node can access in memory; The conversion module 720 is further configured to: determine, based on the one-to-one linear mapping relationship, the second physical address corresponding to each switching domain address in the target switching domain address set; The sending module 730 is further configured to: forward the memory barrier instruction message to the second storage node corresponding to each of the second physical addresses; after confirming that the receiving module 710 has received the confirmation message sent by each of the second storage nodes, send a memory barrier completion message to the target computing node; the confirmation message is used to indicate that the second storage node that sent the confirmation message has completed memory access for the swap domain address in the target swap domain address set.

[0095] In some embodiments, the switch domain addresses within the target switch domain address set are allocated to the target computing node from the switch domain address space by a structure manager that is communicatively connected to the target computing node in response to a storage resource allocation request sent by the target computing node.

[0096] In some embodiments, the switch domain addresses within the target switch domain address set are allocated to the target computing node by the structure manager from the switch domain address space based on the big page mechanism in response to a storage resource allocation request sent by the target computing node.

[0097] In some embodiments, the memory access device 700 further includes: The acquisition module is used to acquire the storage capacity information of each of the storage nodes; A module is established to establish the one-to-one linear mapping relationship based on the storage capacity information of each storage node.

[0098] In some embodiments, the establishing module is further configured to: determine the base address offset value corresponding to each storage node in the exchange domain address space based on the storage capacity information of each storage node; and establish the one-to-one linear mapping relationship based on the physical address in the physical address space of each storage node and the base address offset value.

[0099] In some embodiments, the sending module 730 is further configured to: send the storage capacity information and the one-to-one linear mapping relationship to a structure manager that is communicatively connected to the switch, so that the structure manager allocates storage resources of the plurality of storage nodes based on the storage capacity information and the one-to-one linear mapping relationship.

[0100] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0101] Based on the same inventive concept as the foregoing embodiments, this application provides a switch.

[0102] Figure 8 This is a schematic diagram of the structure of a switch provided in an embodiment of this application. The switch connects multiple computing nodes and multiple storage nodes. Figure 8 The switch 800 shown includes: Input / output port 801; The memory 802 is used to store a one-to-one linear mapping relationship between the switch domain addresses in the switch domain address space and the physical addresses in the physical address spaces of the plurality of storage nodes; the switch domain addresses in the switch domain address space are a logical address space formed by uniformly addressing the physical addresses in the physical address spaces of the plurality of storage nodes. A processor 803, coupled to the input / output port 801 and the memory 802, is configured to: receive at least one memory access message sent by a target computing node among the plurality of computing nodes; each memory access message carries a different switching domain destination address; the different switching domain destination addresses belong to the switching domain address space; the different switching domain destination addresses are discretely distributed in the switching domain address space; based on the one-to-one linear mapping relationship stored in the memory 802, each switching domain destination address is converted into a corresponding first physical address; based on the first physical address corresponding to each switching domain destination address, each memory access message is forwarded to a first storage node corresponding to each first physical address.

[0103] It should be noted that input / output port 801 is a hardware interface used for receiving and sending data packets, supporting communication with external devices (such as compute nodes and storage nodes). Input / output port 801 features high bandwidth and low latency, and is compatible with various network protocols. In this embodiment, the input port of input / output port 801 is responsible for receiving memory access messages from the compute node, while the output port is responsible for forwarding the processed messages to the storage node. The parallel processing capability of input / output port 801 can effectively improve the overall system throughput and response speed.

[0104] It should be noted that the processor 803 is the core control unit of the switch, responsible for performing critical tasks such as packet parsing, address translation, and routing decisions. The processor 803 is connected to the input / output ports 801 and the memory 802 via an internal bus or dedicated interconnect structure, ensuring efficient collaboration among the three. For example, when the processor 803 receives a memory access packet, it can query the mapping relationship in the memory 802 to determine the target physical address and select the appropriate output port for forwarding according to the routing policy.

[0105] Understandably, the tight coupling between the processor 803, the input / output port 801, and the memory 802 enables the switch to achieve efficient address translation and data forwarding functions on a single hardware platform, thereby improving the overall system response speed and enhancing system stability.

[0106] In some embodiments, processor 803 may call and run computer programs from memory 802 to implement the methods in the embodiments of this application.

[0107] In some embodiments, the memory 802 may be a separate device independent of the processor 803, or it may be integrated into the processor 803.

[0108] This application also provides a computer-readable storage medium for storing computer programs.

[0109] Optionally, the computer-readable storage medium can be applied to the switch in the embodiments of this application, and the computer program causes the processor or switch to execute the various methods of the embodiments of this application, which will not be described in detail here for the sake of brevity.

[0110] This application also provides a computer program product, including computer program instructions.

[0111] Optionally, the computer program product can be applied to the switch in the embodiments of this application, and the computer program instructions cause the processor or switch to execute the various methods of the embodiments of this application. For the sake of brevity, they will not be described in detail here.

[0112] This application also provides a computer program.

[0113] Optionally, the computer program can be applied to the switch in the embodiments of this application. When the computer program runs on the processor or the switch, it causes the processor or the switch to execute the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0114] It should be noted that the descriptions of the devices, storage media, computer program products, and computer program embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the device, storage media, computer program products, and computer program embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0115] It should be understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0116] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0117] It should be understood that the above-described memory is exemplary and not a limiting description. For example, the memory in the embodiments of this application may also be static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DR RAM), etc. That is to say, the memory in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0118] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0119] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0121] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0122] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0123] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause the switch to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0124] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory access method, applied to a switch connected to multiple compute nodes and multiple storage nodes; the method comprising: Receive at least one memory access message sent by the target computing node among the plurality of computing nodes; Each memory access message carries a different destination address for the swap field; The different destination addresses of the switching domains belong to the switching domain address space. The switching domain addresses in the switching domain address space are the logical address space formed by uniformly addressing the physical addresses in the physical address spaces of the multiple storage nodes. The different destination addresses of the switching domains are discretely distributed in the switching domain address space. Based on the one-to-one linear mapping relationship between the switch domain address in the switch domain address space and the physical address in the physical address space, each of the switch domain destination addresses is converted into the corresponding first physical address; Based on the first physical address corresponding to each of the switching domain destination addresses, each memory access message is forwarded to the first storage node corresponding to each of the first physical addresses.

2. The method according to claim 1, wherein the different destination addresses of the switching domains carried in each memory access message are obtained by the target computing node converting the virtual addresses in the target virtual address segment to be accessed by the target computing node based on a specific mapping relationship; the specific mapping relationship is configured to: map continuous virtual addresses in the virtual address space to discrete switching domain addresses in the switching domain address space based on a specific interleaving strategy.

3. The method according to claim 1 or 2, further comprising: Receive the memory barrier instruction message sent by the target computing node; The memory barrier instruction message is used to instruct sequential consistency constraints on memory access to swap domain addresses within the target swap domain address set; the swap domain addresses within the target swap domain address set are swap domain addresses that the target computing node can access in memory; Based on the one-to-one linear mapping relationship, determine the second physical address corresponding to each switching domain address in the target switching domain address set; The memory barrier instruction message is forwarded to the second storage node corresponding to each of the second physical addresses; After receiving confirmation messages from each of the second storage nodes, a memory barrier completion message is sent to the target computing node; the confirmation message indicates that the second storage node that sent the confirmation message has completed memory access for the swap domain address within the target swap domain address set.

4. The method according to claim 3, wherein the switch domain addresses in the target switch domain address set are allocated to the target computing node from the switch domain address space by the structure manager, which is communicatively connected to the target computing node, in response to a storage resource allocation request sent by the target computing node.

5. The method according to claim 4, wherein the switch domain addresses in the target switch domain address set are allocated to the target computing node by the structure manager from the switch domain address space based on the big page mechanism in response to the storage resource allocation request sent by the target computing node.

6. The method according to claim 4, wherein the switch domain addresses in the target switch domain address set are allocated to the target computing node from the switch domain address space by the structure manager in response to a storage resource allocation request sent by the target computing node, based on a specific interleaving strategy.

7. The method according to claim 1 or 2, further comprising: Obtain the storage capacity information of each of the aforementioned storage nodes; Based on the storage capacity information of each storage node, the one-to-one linear mapping relationship is established.

8. The method according to claim 7, wherein establishing the one-to-one linear mapping relationship based on the storage capacity information of each of the storage nodes includes: Based on the storage capacity information of each storage node, the base address offset value corresponding to each storage node in the exchange domain address space is determined; The one-to-one linear mapping relationship is established based on the physical address in the physical address space of each storage node and the base address offset value.

9. The method according to claim 7, further comprising: The storage capacity information and the one-to-one linear mapping relationship are sent to the structure manager, which is connected to the switch, so that the structure manager can allocate storage resources to the multiple storage nodes based on the storage capacity information and the one-to-one linear mapping relationship.

10. A switch connecting multiple compute nodes and multiple storage nodes, the switch comprising: Input / output ports The memory is used to store a one-to-one linear mapping relationship between the switch domain addresses in the switch domain address space and the physical addresses in the physical address spaces of the multiple storage nodes; the switch domain addresses in the switch domain address space are the logical address space formed by uniformly addressing the physical addresses in the physical address spaces of the multiple storage nodes. A processor coupled to the input / output port and the memory, configured to: receive at least one memory access message sent by a target computing node among the plurality of computing nodes; Each memory access message carries a different swap domain destination address; the different swap domain destination addresses belong to the swap domain address space; the different swap domain destination addresses are discretely distributed in the swap domain address space; based on the one-to-one linear mapping relationship stored in the memory, each swap domain destination address is converted into a corresponding first physical address; Based on the first physical address corresponding to each of the switching domain destination addresses, each memory access message is forwarded to the first storage node corresponding to each of the first physical addresses.

Images