Storage controller for self-reconfiguration and self-evolution AI chip and chip thereof

Abstract

The invention relates to a storage controller for a self-reconfiguration and self-evolution AI chip and a chip thereof, in particular to the technical field of chips, the storage controller comprises a plurality of data cache modules, and each data cache module is configured to manage storage and access of a three-dimensional data block in an on-chip SRAM array; each data caching module comprises an instruction decoding unit which is configured to receive and analyze an input instruction, and if it is determined that the instruction is a configuration instruction, configuration parameters analyzed from the instruction are updated to a corresponding configuration register in the instruction decoding unit; if it is determined that the instruction is a working instruction, working parameters analyzed from the instruction are updated to a corresponding configuration register in the instruction, and after the parameters are updated, starting control signals are sent to a DDR address generation unit and an SRAM management unit respectively, so that efficient and configurable access to data blocks in the three-dimensional space can be achieved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a memory controller and chip for a self-reconfigurable and self-evolving AI chip. Background Technology

[0002] As artificial intelligence (AI) models rapidly iterate and become increasingly complex, they place extremely high demands on the computing power and storage bandwidth of computing platforms. Under the traditional von Neumann architecture, the performance gap between the processor and memory is widening, creating the so-called "memory wall" problem, which severely restricts the overall performance of AI chips. This is particularly true when processing algorithms such as convolutional neural networks (CNNs), where data exists in the form of multidimensional tensors, while physical memory is one-dimensional and linear. This mismatch leads to enormous data access overhead and low data transfer efficiency.

[0003] Furthermore, typical AI algorithms in complex scenarios require AI chips to flexibly adapt to the needs of various algorithms, such as convolutional layers of different sizes, different data reuse strategies, and diverse data precision. However, the data storage structures in existing AI accelerators are mostly designed for specific applications, lacking sufficient flexibility and configurability, making it difficult to efficiently cope with the diverse challenges of algorithms and scenarios.

[0004] Therefore, there is an urgent need for a storage controller that can be flexibly configured and supports efficient transmission of multi-dimensional data blocks to improve the energy efficiency and adaptability of AI chips. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a memory controller and chip for a self-reconfigurable and self-evolving AI chip, which solves the technical problems of insufficient flexibility and configurability in the prior art.

[0007] (II) Technical Solution

[0008] To achieve the above objectives, the main technical solutions adopted by the present invention include:

[0009] In a first aspect, embodiments of the present invention provide a storage controller for a self-reconfigurable and self-evolving AI chip, including multiple data cache modules, each of which is configured to manage the storage and access of three-dimensional data blocks in an on-chip SRAM array;

[0010] Each data cache module includes: an instruction decoding unit, configured to receive and parse input instructions; if the instruction is determined to be a configuration instruction, it updates the configuration parameters parsed from the instruction into its corresponding internal configuration register; if the instruction is determined to be a working instruction, it updates the working parameters parsed from the instruction into its corresponding internal configuration register, and after the parameters are updated, sends start control signals to the DDR address generation unit and the SRAM management unit respectively; the DDR address generation unit is configured to be responsible for address calculation tasks related to off-chip DDR memory; the SRAM management unit is configured to be responsible for access control and address generation of the on-chip SRAM array; wherein, the SRAM management unit includes the on-chip SRAM array.

[0011] In one possible embodiment, the size of the three-dimensional data block is the width dimension W, the height dimension H, and the channel dimension C; the on-chip SRAM array includes m groups, each group includes n banks, and each bank includes k SRAM chips. The SRAM array can simultaneously read and write consecutive m groups, and each group can simultaneously read and write consecutive n banks; m, n, and k are all preset positive integers.

[0012] Each group is associated with C, and each group is configured to manage data for C / m channels; each bank is associated with H, and each bank is configured to manage data for H / n heights; the number of SRAM chips is associated with W to enable physical storage of the three-dimensional data blocks.

[0013] In one possible embodiment, the SRAM management unit includes: an SRAM logical coordinate generation unit, configured to generate a logical coordinate sequence traversed in a specified dimensional order within the three-dimensional space of the three-dimensional data block based on the configured sub-data block cell sliding step size and cell data read / write order, and to perform boundary checks in real time, dynamically calculating the actual three-dimensional data size for each access to ensure that the access does not exceed the preset three-dimensional data block boundary; the sub-data block cell is the data block read / written each time in the three-dimensional data block;

[0014] The SRAM physical address generation unit is configured to map a sequence of logical coordinates into two-dimensional physical address parameters; wherein the two-dimensional physical address parameters include group ID, bank ID, SRAM internal address, bit select signal, address space occupied by the three-dimensional data block, number of consecutively accessed groups, and number of consecutively accessed banks.

[0015] In one possible embodiment, the logical coordinate generation unit needs to generate a logical coordinate sequence including the channel logical coordinate pos_c corresponding to the sub-data block Cell in channel dimension C; the group ID is obtained by taking the modulo of pos_c and group_num; where group_num is the number of groups occupied by the current data block.

[0016] In one possible embodiment, the logical coordinate generation unit needs to generate a logical coordinate sequence including the logical height coordinate pos_h corresponding to the height dimension H of the sub-data block Cell; the bank ID is determined by the logical height coordinate pos_h, the bit width of the SRAM, the preset data precision, and the number of banks occupied by the height dimension H.

[0017] In one possible embodiment, the three-dimensional data block is divided into C blocks according to the channel dimension C, and each of the C blocks includes W columns col; the internal address of the SRAM is determined by the block offset address, the col offset address, and the column offset generated by the H dimension within the current logical column; wherein, the block offset address represents the offset address in the channel dimension C; the col offset address represents the offset address in different logical columns col within the same block; and the column offset generated by the H dimension within the current logical column represents the offset address within the same col.

[0018] In one possible embodiment, the logical coordinate generation unit needs to generate a logical coordinate sequence including the channel logical coordinate pos_c corresponding to the channel dimension C of the sub-data block Cell, the height logical coordinate pos_h corresponding to the height dimension H of the sub-data block Cell, and the width logical coordinate pos_w corresponding to the width dimension W of the sub-data block Cell; the block offset address is jointly determined by the block number, W, H, and the total number of banks in the group accessed under the current pos_c, the bit width of the SRAM, and the preset data precision; wherein, the block number is the quotient of pos_c and group_num; the col offset address is jointly determined by pos_w, H, the total number of banks, the bit width of the SRAM, and the preset data precision; the column offset generated by the H dimension within the current logical column is jointly determined by pos_h, the total number of banks, the bit width of the SRAM, and the preset data precision.

[0019] In one possible embodiment, the DDR address generation unit includes: a DDR logical coordinate generation unit configured to calculate the logical coordinates of the feature map data stored in the DDR storage space for each read or write of a sub-data block Cell in the DDR storage space; the sub-data block Cell is a data block read or written in each three-dimensional data block; wherein the feature map data is an off-chip three-dimensional data block; and a DDR physical address generation unit configured to convert the logical coordinates into physical byte addresses in the DDR storage space using a three-dimensional to one-dimensional address mapping formula.

[0020] In one possible embodiment, the three-dimensional to one-dimensional address mapping formula is:

[0021] phy_addr=featuremap_addr+c_position*TW*Maxheight+w_position*Maxheight+h_position*(DW / DDR_WIDTH);

[0022] In the formula, phy_addr represents the physical byte address; featuremap_addr represents the address of the top-left corner of the currently processed feature map data in DDR, and the feature map data is an off-chip 3D data block; c_position represents the logical coordinate of the current channel; TW represents the total width of the currently processed feature map; Maxheight represents the memory size of each column; w_position represents the logical coordinate of the current data column; h_position represents the logical coordinate within the column of the current data element; DW represents the preset data precision; and DDR_WIDTH represents the bit width of DDR.

[0023] In a second aspect, embodiments of the present invention provide a self-reconfigurable and self-evolving AI chip, including a memory controller for a self-reconfigurable and self-evolving AI chip as described in any of the first aspects.

[0024] To make the above-mentioned objectives, features and advantages to be achieved by the embodiments of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This illustration shows an interaction diagram between a self-reconfigurable and self-evolving AI chip and an off-chip DDR, as provided in an embodiment of this application.

[0027] Figure 2 This illustration shows a schematic diagram of a storage controller performing data reading or writing according to an embodiment of this application;

[0028] Figure 3 A schematic diagram of a data caching module provided in an embodiment of this application is shown;

[0029] Figure 4 This illustration shows a schematic diagram of the arrangement of three-dimensional input feature map data in DDR according to an embodiment of this application;

[0030] Figure 5 This illustration shows a schematic diagram of SRAM partitioning within a memory controller according to an embodiment of this application. Detailed Implementation

[0031] To better explain and facilitate understanding of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] To address the issues of insufficient data management flexibility and low transmission efficiency in existing self-reconfigurable and self-evolving AI chips, this application proposes a storage controller and chip for self-reconfigurable and self-evolving AI chips. This controller can manage 3D data with configurable "data shape," adjustable storage space, multi-dimensional data transmission, and diverse data precision, thus meeting the data organization requirements of self-reconfigurable and self-evolving AI chips in complex scenarios, demanding high bandwidth, multiple shapes, and high energy efficiency. Furthermore, this application designs dedicated configuration instructions for configuring the shape, step size, and sequence of data transmission. It also designs dedicated operating instructions for configuring certain signals and initiating data transmission, thereby enabling efficient and configurable access to data blocks in the three-dimensional space.

[0033] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention can be understood more clearly and thoroughly, and that the scope of the present invention can be fully conveyed to those skilled in the art.

[0034] Please see Figure 1 , Figure 1 This diagram illustrates the connection between a self-reconfigurable and self-evolving AI chip and an off-chip DDR (Double Data Rate Synchronous Dynamic Random Memory) according to an embodiment of this application. Figure 1As shown, this self-reconfigurable and self-evolving AI chip includes a central controller, a computing unit, and a storage controller, with the storage controller connected to an external DDR memory. Data path ① moves data from the external DDR to the storage controller; data path ② moves data from the storage controller to the computing unit; data path ③ moves data from the computing unit to the storage controller; and data path ④ moves data from the storage controller to the external DDR. The storage controller receives instructions from the central controller, determines which data path to use, updates relevant configuration information, and determines the amount of data to be moved each time.

[0035] In addition, such as Figure 2 As shown, the storage controller can be defined to manage three-dimensional data blocks of sizes W, H, and C. Here, W represents the width dimension of the three-dimensional data block; H represents the height dimension; and C represents the channel dimension. Data is written to or read from data blocks of sizes WCell, HCell, and CCell, and each read / write operation is referred to as a Cell. Furthermore, W, H, C, WCell, HCell, and CCell are all defined in units of the number of elements.

[0036] Furthermore, based on the characteristics of convolutional sliding window operations, each read / write operation of the Cell data block can be performed in six directions (WHC, HWC, WCH, CWH, HCW, CHW) and slide within the three-dimensional data block with different step sizes (WCellstep, HCellstep, CCellstep). Data transfer across the four pathways is completed through configuration and operation commands.

[0037] It should be noted that this application mainly improves the on-chip memory controller on the AI ​​chip, which will be described below through specific embodiments.

[0038] Specifically, the storage controller may include multiple data cache modules, and each data cache module is configured to manage the storage and access of three-dimensional data blocks in the on-chip SRAM array. That is, the data cache module is responsible for managing the SRAM array within its own memory and for address calculation. Furthermore, the specific number of data cache modules in the storage controller can be set according to actual needs. For example, the storage controller may include 10 data cache modules.

[0039] And, such as Figure 3As shown, the data caching module includes a decoding unit, a DDR address generation unit, and an SRAM management unit. The decoding unit is configured to receive and parse input instructions. If the instruction is determined to be a configuration instruction, it updates the corresponding configuration register with the configuration parameters parsed from the instruction. If the instruction is determined to be a working instruction, it updates the corresponding configuration register with the working parameters parsed from the instruction. After updating the parameters, it sends start control signals to the DDR address generation unit and the SRAM management unit respectively. In other words, the decoding unit decodes the input instructions, updates the configuration register according to the instruction parameters, and sends control signals to the DDR address generation unit and the SRAM management unit according to the instruction.

[0040] In addition, a DDR address generation unit is configured to handle address calculation tasks related to off-chip DDR memory. This DDR address generation unit includes: a DDR logical coordinate generation unit, configured to calculate the logical coordinates of the feature map data stored in the DDR memory space for each read or write operation of a Cell data block; wherein the Cell data block is the data block read or written from a three-dimensional data block each time; and a DDR physical address generation unit, configured to convert the logical coordinates into physical byte addresses in the DDR memory space using a three-dimensional to one-dimensional address mapping formula. In other words, the DDR logical coordinate generation unit receives configuration information and a start signal from the decoding unit, calculates the logical coordinates for each burst transmission, and sends the logical coordinates to the DDR physical address generation unit when the handshake signal is valid; the DDR physical address generation unit calculates the physical address in the DDR address space using the address mapping formula.

[0041] And, an SRAM management unit is configured to be responsible for access control and address generation of the on-chip SRAM array. This SRAM management unit includes: an SRAM logical coordinate generation unit, configured to generate a logical coordinate sequence traversing in a specified dimensional order within the three-dimensional space of the three-dimensional data block defined by W, H, and C, based on the configured cell sliding step size and cell data read / write order, and to perform boundary checks in real time, dynamically calculating the actual three-dimensional data size for each access to ensure that the access does not exceed the preset three-dimensional data block boundary; and an SRAM physical address generation unit, configured to map the logical coordinate sequence to two-dimensional physical address parameters; wherein the two-dimensional physical address parameters include groupID, bank ID, SRAM internal address, bit select signal, address space occupied by the three-dimensional data block, number of consecutively accessed groups, and number of consecutively accessed banks. In other words, the SRAM logical coordinate generation unit is responsible for calculating the coordinates when reading and writing 3D data blocks, as well as the size of each 3D data block read or written. When the read or write operation of this instruction is completed, an end signal is generated and returned to the decoding unit. The SRAM physical address generation unit generates the address and enable of reading and writing SRAM, group ID, bank ID, SRAM internal address, bit select signal bit_select, address space occupied by the 3D data block block_offset_o, number of consecutively accessed groups group_access_num, and number of consecutively accessed banks bank_access_num, etc., based on the logical coordinates sent by the SRAM logical coordinate generation unit.

[0042] Furthermore, after the decoding unit receives the instruction, it uniformly schedules and starts the DDR address generation unit and the SRAM management unit. Path 1 and Path 4 serve as channels for interaction with DDR, and both the DDR address generation unit and the SRAM management unit are working, because the interaction with DDR is essentially a data transfer between the "off-chip DDR" and the "on-chip SRAM array". Path 2 and Path 3 serve as channels for interaction with the computing unit. Since the data interaction is entirely within the chip (between the memory controller and the computing unit) and does not involve access to the external DDR, the DDR address generation unit does not participate in the work and remains idle.

[0043] Furthermore, by issuing different configuration and operation instructions to the on-chip memory controller, three-dimensional data blocks are read and written to the memory controller with configurable data block shapes, configurable sliding step sizes, and sliding sequences. The memory controller parses the received instructions; if it is a configuration instruction, it updates its internal configuration register; if it is an operation instruction, it updates the corresponding configuration parameters and generates a start signal to trigger subsequent address generation and data transmission processes. Moreover, the specific instructions contained in the operation instructions and the specific instructions contained in the configuration instructions can be set according to actual needs, and this application embodiment is not limited to this. For example, please refer to the contents of Table 1 below.

[0044] Table 1

[0045]

[0046]

[0047]

[0048]

[0049] To facilitate understanding of the relevant content in Table 1 above, specific embodiments will be described below.

[0050] Optionally, during the execution of path ①, assuming the feature map data size TW is 64, TH is 64, and TC is 10, data with W = 32, H = 32, and C = 10 is moved from the off-chip DDR to the memory controller.

[0051] In the working instructions, the data cache module _id can be configured as 0001, the working instruction id as 00, and the data path selection configuration as 00, indicating that the current data path selected is from off-chip DDR to the memory controller. Because data in off-chip DDR is placed in HWC order, the read / write order is fixed at HWC (configuration value 001). The compute unit id selects which compute unit to choose when the memory controller interacts with the compute unit on the chip; it is configured to 0 by default in the DDR interaction path. WCell, HCell, and CCell can be configured as 1, 8, and 1, respectively, meaning that a 1×8×1 three-dimensional data block is sent to the memory controller at a time, selecting the position of the three-dimensional data block to be moved in the feature map from W0=0, H0=0, and C0=0.

[0052] In configuration instruction 1, the data cache module _id can be configured as 0001, the configuration instruction 1 id is 01, and the data path selection is configured as 03, indicating that the current selected data path is from the storage controller to the computing unit. Since TH is specified as 64, and Maxheight is the storage space occupied by a column of feature map data in DDR, measured in bytes, and one address space in DDR can store 8 bits of data, and its data processing precision is specified as 16 bits, therefore, two address spaces are used to store one piece of data, and Maxheight needs to be configured as 128.

[0053] In configuration instruction 2, `featuremap_addr` is configured as the starting position of the current feature map in DDR, in bytes. `WCellstep`, `HCellstep`, and `CCellstep` are the step sizes for sliding the Cell data block along the W, H, and C dimensions, respectively. Since data transfer from DDR to storage does not involve data reuse, the step sizes are set to 1, 8, and 1. `Lens` is the burst transfer length, which specifies that each burst transfer can retrieve a maximum of one H range of data, therefore it is limited to 128 / DW *(Lens+1) <= H. The maximum configuration for `Lens` is 011, and the actual value is 4.

[0054] In configuration instruction 3, W is specified as 32, H as 32, C as 10, and the data precision is selected as 16, which means the configuration is 1111, and the actual value is the configuration value plus one.

[0055] The above instructions can be used to move the three-dimensional data block at the positions where W0 is 0, H0 is 0, and C0 is 0 in the feature map to the data cache module 0 of the storage controller.

[0056] Optionally, during the execution of path ②, the previous step has already achieved the transfer from the off-chip DDR to the memory controller. The following configuration is the relevant instruction configuration for sending this data block to the computing unit in chunks.

[0057] First, the configuration of W=32, H=32, and C=10 in configuration instruction 3 must be used (the size of the three-dimensional data block written to the storage controller and the size of the three-dimensional data block read out must be equal).

[0058] Secondly, since it does not interact with the external DDR, the featuremap_addr and Lens in configuration instruction 2, Maxheight, TW, TH, TC in configuration instruction 1, and W0, H0, C0 in configuration instruction 1 do not need to be configured; that is, they can all be set to 0.

[0059] The remaining configurations, WCel, HCell, CCell, and WCellstep, HCellstep, CCellstep, can be configured according to the data requirements of the computing unit. It should be noted that, since there are 8 groups and 16 banks, the maximum values ​​of WCel, HCell, and CCell are limited to 1, 16, and 8, respectively.

[0060] Optionally, during the execution of path ③, the three-dimensional data block when writing to the storage controller is assumed to be 16×16×10. At this time, W is configured as 16, H as 16, and C as 10, and the configuration for interaction with DDR is not required.

[0061] The remaining WCel, HCell, CCell and WCellstep, HCellstep, CCellstep can be configured according to the needs of the write storage controller. It should be noted that since there are 8 groups and 16 banks, the maximum values ​​of WCel, HCell, and CCell are limited to 1, 16, and 8, respectively.

[0062] Optionally, during the execution of path ④, the data of the storage controller is written back to DDR, and the specific configuration is the same as that for reading DDR.

[0063] By configuring the instructions for the above four paths, it is possible to move data from the off-chip DDR to the memory controller, provide the data in the memory controller to the computing unit, write the output data of the computing unit to the memory controller, and finally move it to the DDR in the conventional way.

[0064] Therefore, this application can implement four data paths through the configuration of the above instructions. Furthermore, this application can configure the data size on the feature map according to the TW, TH, and TC fields in the designed instructions; the feature map data address field configures the starting physical address of the data in DDR; the W0 / H0 / C0 configuration fields represent the upper-left corner coordinates of W / H / C in the feature map data block, respectively. Since the feature map is usually very large and cannot be placed into the data cache module all at once, the W0 / H0 / C0 configuration fields implement the function of feature map block processing. The Maxheight field configures the storage space occupied by each column of the currently processed feature map data in DDR; the Lens field configures the burst transmission length of a burst read / write; the W / H / C configuration fields represent the size of the data block read or written by the data cache module this time; the WCell / HCell / CCell configuration fields represent the size of the data block read / written each time; and the WCellstep / HCellstep / CCellstep configuration fields are used to implement sliding window reading of data to support data reuse operations such as convolution. When the sliding step size WCellstep / HCellstep / CCellstep is set to the same as WCell / HCell / CCell, it indicates sequential reading without data multiplexing. The data precision configuration field specifies the number of bits used for the data, supporting three precisions: 4, 8, and 16.

[0065] It should be noted that the above-mentioned working instructions and configuration instructions can be set according to actual needs, and the embodiments of this application are not limited thereto.

[0066] Furthermore, to facilitate understanding of the data transmission process of this application, the decoding unit, DDR address generation unit, SRAM management unit, and SRAM array are described below.

[0067] Optionally, the on-chip memory controller in this embodiment of the invention includes multiple independent data cache modules, and each data cache module is equipped with an independent instruction decoding unit. This design ensures that each data cache module can receive and execute instruction tasks in parallel and independently.

[0068] Furthermore, the instruction decoding unit identifies working instructions and configuration instructions, parses the parameter fields in the instructions and updates them to the corresponding configuration registers. If the identified instruction is a working instruction, it will trigger the state machine and send a start signal to the DDR address generation unit and the SRAM management unit to execute the data transfer task.

[0069] Optionally, considering that the DDR address generation unit includes two units, the DDR logical coordinate generation unit and the DDR physical address generation unit, they will be described separately below.

[0070] For the DDR logical coordinate generation unit, when the data cache module interacts with the external DDR, the DDR logical coordinate generation unit calculates the logical coordinates of the feature map data stored in the external DDR for each read / write operation of the Cell data block. The address space in the external DDR is arranged in one dimension, and one address space can store 8 bits of data (this can also be set according to actual needs, and the embodiments of this application are not limited to this). However, the input feature map is three-dimensional data, so the feature map data needs to be stored in the DDR according to a certain mapping method.

[0071] Furthermore, the arrangement of the 3D input feature map data in DDR can be as follows: Figure 4 As shown. Figure 4 The image illustrates the mapping of a 16×16×3 input feature map with 8-bit precision to DDR. Since addresses in DDR are contiguous, data reads and writes to DDR are performed sequentially in the order H, W, C. For example... Figure 4 After the data in the blue section is written, it means that all column data of one channel has been written to DDR. Then the data of the next channel is written, and the data arrangement of the next channel is the same as in the example in the figure.

[0072] Based on the above structure, the DDR logical coordinate generation unit starts working after receiving the start signal gen_addr_start sent by the decoding unit, and calculates the logical position of the Cell data block of DDR each time it is written or read according to the configuration information sent by the decoding unit.

[0073] Specifically, its core structure includes three counters: a column counter configured to generate and iterate the logical coordinates of data blocks in the column (H) dimension; a row counter configured to generate and iterate the logical coordinates of data blocks in the row (W) dimension; and a channel counter configured to generate and iterate the logical coordinates of data blocks in the channel (C) dimension. It also includes handshake interfaces (such as logic_vld and logic_rdy) for interaction with the DDR physical address generation unit, used to control the output of the logical coordinates.

[0074] First, upon receiving the start signal from the decoding unit, the three counters load their initial values ​​from the configuration register: the column counter h_position is initialized to H0, the row counter w_position to W0, and the channel counter c_position to C0. The logic coordinate valid signal (logic_vld) goes high, indicating that the first set of logic coordinates is ready to be output. When the ready signal (logic_rdy) of the handshake interface is valid, it indicates that the downstream physical address calculation unit can receive data, and at this time, the enable signal of the column counter h_position is valid.

[0075] Afterwards, the column counter h_position is incremented by a preset increment ΔH, where ΔH = (burst size / data bit width) × burst length. For example, if the burst size is configured to be 128 bits and the data precision is configured to be 16 bits, a transmission with a burst length of 1 will increase h_position by 8.

[0076] When the column counter h_position has completed traversing a complete data column (defined by H), the counter will generate a column full pulse signal (h_full_puls) and reset its count value to the initial value H0, preparing for the column traversal of the next row of data.

[0077] When the column full pulse signal (h_full_puls) goes high, the row counter w_position increments its count value by 1. When the count value of w_position has completed traversing a complete data row (defined by W, the count value reaches W0+W-1), the counter will generate a row full pulse signal (w_full_puls) and reset its count value to the initial value W0.

[0078] When the full pulse signal (w_full_puls) goes high, the channel counter c_position increments its count value by 1.

[0079] Once all three counters have completed traversing the specified range (defined by W / H / C), a task completion signal is generated for the decoding unit, indicating that the logical coordinates of all data blocks transmitted this time have been generated.

[0080] For the DDR address generation unit, the DDR physical address generation unit receives the logical coordinate sequence (w_position, h_position, c_position) passed in by the DDR logical coordinate generation unit, and accurately converts it into the physical byte address in the DDR memory space according to a set of preset parameters. After completing the address calculation of the entire data block, it sends an address calculation completion signal (gen_addr_done) to the instruction decoding unit to indicate that the address generation task of the current working instruction has been completed.

[0081] Furthermore, a linear address mapping method based on the base address plus a three-dimensional offset is used for calculation, so that the physical address phy_addr corresponding to any logical coordinate can be calculated using the following general formula:

[0082] ;

[0083] In the formula, featuremap_addr is the address of the top-left corner of the currently processed feature map data in DDR, and the feature map data includes a three-dimensional data block; c_offset is the channel offset, which represents the offset of the current channel relative to the base address of the feature map; w_offset is the row offset, which represents the offset of the current data column relative to the starting address of its channel; h_offset is the column offset, which represents the offset of the current data element relative to the starting address of its data column.

[0084] Furthermore, c_offset is obtained by multiplying the logical coordinate c_position of the current channel by the total byte space occupied by a single channel plane. The total byte space of a single channel plane is determined by the total width TW of the feature map and the memory size Maxheight of each column. Therefore, the formula for calculating c_offset is:

[0085] ;

[0086] Furthermore, w_offset is obtained by multiplying the logical coordinate w_position of the current data column by the preset Maxheight. Maxheight represents the physical byte space actually occupied by each column of data to ensure address alignment. The formula for calculating w_offset is:

[0087] ;

[0088] Furthermore, `h_offset` is obtained by multiplying the logical coordinate `h_position` within the column of the current data element by the byte size of a single data element, and the byte size of a single data element is determined by the data precision (DW). For example, when the data precision (DW) is 16 bits, one data element is two bytes; when the data precision (DW) is 8 bits, one data element is one byte; and when the data precision (DW) is 4 bits, one data element is 1 / 2 byte. The formula for calculating `h_offset` is:

[0089] ;

[0090] Where DDR_WIDTH is the bit width of DDR.

[0091] Therefore, the calculation of phy_addr can be represented as follows:

[0092] ;

[0093] First, the system determines whether to enable the write address channel or the read address channel based on the DDR_wr signal transmitted by the decoding unit. A high level DDR_wr indicates a write operation, and a low level DDR_wr indicates a read operation. Second, after calculating the write / read address for a burst transmission, the system sends the address to the data arbitration module in the memory controller to perform data reading.

[0094] The system continues to operate until the entire data block defined for the working instruction (the range of which is determined by W, H, and C) has been generated and all corresponding burst transmission start addresses have been transmitted. After completing the transmission of the last address, the system sends an address calculation end signal (gen_addr_done) to the decoding unit to unblock the system.

[0095] Optionally, considering that the SRAM management unit includes two units, the SRAM logical coordinate generation unit and the SRAM physical address generation unit, they will be described separately below.

[0096] For the SRAM logical coordinate generation unit, this module generates a precise logical coordinate sequence (pos_w, pos_h, pos_c) with a configurable read / write order for cells within a space of size W, H, and C, to perform read / write operations on sub-data blocks (cells). It also possesses boundary handling capabilities, dynamically calculating the actual data block size (access_w, access_h, access_c) for each access to ensure that the access does not exceed the preset three-dimensional data block boundaries.

[0097] Furthermore, the SRAM logical coordinate generation unit is activated upon receiving the start signal (RWdata_start) and executes the following coordinate generation method based on the current operation mode (read or write) and the cell's read / write order configuration: First, it determines whether the current operation mode is read or write based on the read / write control signal (SRAM_wr_i). Simultaneously, it determines the nested traversal priority of the three logical dimensions W, H, and C (e.g., multiple combinations such as WHC, CWH) based on the cell's read / write order configuration signal.

[0098] In write / read operation mode, the sliding step size (WCellstep, HCellstep, CCellstep) is used as an increment and mapped to three general-purpose cascaded counters (count1, count2, count3). Here, count1 is the least significant bit (fastest changing) counter; count2 is the middle bit counter; and count3 is the most significant bit (slowest changing) counter. Furthermore, a carry is generated to count2 when count1 is full, and a carry is generated to count3 when count2 is full.

[0099] For example, when the Cell read / write order is configured as "WHC", WCellstep is mapped to the increment of count1, HCellstep to the increment of count2, and CCellstep to the increment of count3, thus enabling configurable data read / write in multiple directions.

[0100] First, after system startup, count1 accumulates with the mapped increment. When count1 completes its traversal of the mapped dimension (i.e., the count value reaches the boundary of the 3D data block in that dimension), count1 resets and generates a pulse signal to count2. count2 then accumulates with its mapped increment. This process is repeated between count2 and count3. Simultaneously, the current count values ​​of count1, count2, and count3 are dynamically mapped to the output values ​​of logical coordinates (pos_w, pos_h, pos_c). For example, when the Cell's read / write order is configured as "WHC", the output of count1 is mapped to pos_w, the output of count2 to pos_h, and the output of count3 to pos_c.

[0101] When the highest bit count3 completes its final traversal, it indicates that the entire Block space has been completely traversed in the configured order. At this time, a logic generation end signal is generated and sent to the decoding unit so that it can receive the next instruction.

[0102] In addition, during each iteration of the calculation, the system also performs boundary checks in parallel to calculate the actual dimensions access_w, access_h, and access_c for this access:

[0103] If the current logical coordinate pos plus the increment step does not reach the three-dimensional data block boundary B (i.e., pos+step≤B), then the size of this access is equal to the preset sub-block size (access_w=WCell).

[0104] If the current logical coordinate pos plus the increment step will cross the boundary B of the 3D data block (i.e., pos + step > B), then the size of this access is dynamically clipped to the remaining size from the current coordinate to the boundary (e.g., access_w = W - pos_w) to ensure that all data access is strictly limited to the pre-configured Block space.

[0105] For the SRAM physical address generation unit, it receives the logical coordinates (pos_w, pos_h, pos_c) and the size of the cell block for each read / write operation (access_w, access_h, access_c) from the SRAM logical coordinate generation unit via the Valid-Ready handshake mechanism. Then, it generates the groupID, bank ID, and SRAM address of the top-left corner of the cell block according to the SRAM physical address mapping formula. The SRAM physical address generation unit also generates the number of consecutive groups and banks to be read: group_access_num and bank_access_num. Furthermore, it generates the bit select signal (bit_select) in one address space within the SRAM and the address space (block_offset_o) occupied by one block within the single SRAM chip, based on the DW (Data Wrapper). After processing, the generated physical access parameters are output to the SRAM array for data access.

[0106] To facilitate understanding of group ID and bank ID, the partitioning of on-chip SRAM is described below.

[0107] Specifically, based on the data read / write requirements of the computing units on the self-reconfigurable and self-evolving AI chip, the SRAM is first divided into m groups, then each group is divided into n banks, and each bank includes at least one SRAM. Here, m and n are positive integers, and the values ​​of m, n, and the specific number of SRAMs in each bank can be set according to actual needs. For example, the SRAM is divided into 8 groups, and each group is then divided into 16 banks. Since the current PE array requires an access bit width (AW) of 1, one SRAM is allocated to each bank.

[0108] It should be noted that, for ease of description, the following description assumes m = 8, n = 16, and each bank includes one SRAM chip. However, those skilled in the art should understand that the configuration can be adjusted according to actual needs.

[0109] Specifically, this application may specify that the storage controller contains 128 SRAM chips, and logically divide the physically two-dimensionally arranged SRAM into three dimensions to achieve the purpose of storing three-dimensional data in a two-dimensional storage space. The two-dimensional SRAM space is divided into x-dimensional and y-dimensional dimensions, such as... Figure 5As shown, the SRAM is divided into 8 groups along the x-axis, each group being called a column group, resulting in a total of 8 groups. Each group contains 16 SRAM chips. These 16 chips are then divided into 16 banks along the y-axis, each bank containing 1 SRAM chip. Therefore, each memory controller contains a total of 1 × 16 × 8, or 128 SRAM chips.

[0110] Additionally, 128 SRAM chips are used to store 3D data blocks. Furthermore, each group can be defined to manage data across C / 8 channels. And each bank contains one SRAM chip, managing data across H / 16 heights.

[0111] Finally, it is stipulated that each SRAM has one address space to store 16 bits of data, and the data elements used in the design are 16 bits, so one data item is stored in one address space. The SRAM depth is specified as 512, meaning each SRAM has 512 address spaces.

[0112] By physically partitioning the SRAM array into layers for parallel access, efficient parallel access to three-dimensional data blocks at the logical level is supported. Parallel access to eight groups is supported, as well as parallel access to 16 consecutive banks within each group and contiguous address spaces within each bank. A three-dimensional logical data block with a maximum size of 1 (W) × 16 (H) × 8 (C) can be read and written in parallel within a single cycle. This partitioning achieves the mapping of three-dimensional logical data to a two-dimensional SRAM array.

[0113] In dimension C, the data of one channel (two-dimensional data of W×H) is defined as a block within a group. In dimension W, each column of data is called a column (same as col), which is used in the SRAM physical address calculation part.

[0114] Based on the above physical layer division, the method for calculating physical addresses in SRAM is described below. It should be noted that the following calculation formulas are described using a data precision of 16 bits as an example, but other data precisions (e.g., 4 bits or 8 bits) are also within the scope of protection of this application.

[0115] Optionally, the two-dimensional physical address parameter includes a group ID, and the calculation process for the group ID is as follows:

[0116] When the logical coordinate sequence includes the channel logical coordinate pos_c corresponding to the channel dimension, the group ID is related to the channel logical coordinate pos_c, and its value is equal to the remainder of the channel logical coordinate pos_c divided by group_num. And pos_c is calculated starting from 0 and the group ID is numbered starting from 0. group_num represents the number of groups occupied by the current data block. When C < m, group_num is equal to C. When C ≥ m, group_num is equal to m (the total number of groups).

[0117] Optionally, the two-dimensional physical address parameter includes a bank ID, and the calculation process of the bank ID is as follows:

[0118] The bank ID is related to the data bit width DW, the SRAM bit width SRAM_WIDTH, the bank_num, and the height logical coordinate pos_h. SRAM_WIDTH divided by DW is the number of data stored in one SRAM address space. pos_h is calculated starting from 0 and the bank ID is numbered starting from 0. And bank_ID in the formula is the bank ID, and its calculation formula is:

[0119] ;

[0120] In the formula, pos_h represents the height logical coordinate; SRAM_WIDTH bit width is the physical bit width of the SRAM (for example, 16bit); DW represents the preset data precision. For example, the DW can be any value among 4, 8, 16bit, etc.; SRAM_WIDTH / DW represents the number of data elements that can be stored in one physical address space; % represents integer division; bank_num is the number of banks occupied by the H dimension. The determination method of bank_num is similar to that of group_num and is conditionally determined by the configuration of H. Among them, H represents the height dimension length of the three-dimensional data block, and n is the configured number of banks: when H < n * (SRAM_WIDTH / DW), bank_num is equal to H / (SRAM_WIDTH / DW); when H ≥ n * (SRAM_WIDTH / DW), bank_num is equal to n.

[0121] In addition, since the data precision DW can support 4, 8, 16bit, each address space of the SRAM stores 16 / DW consecutive data elements. In this application, the 16 / DW data stored in one address space of the SRAM is defined as the data of the H dimension.

[0122] Therefore, when calculating the bank ID, it is necessary to divide pos_h by the number of data elements in an address space. For example, if pos_h is 4, when the DW is 16 bits, bank4 is selected; when the DW is 8 bits, bank2 is selected; and when the DW is 4 bits, bank1 is selected.

[0123] Optionally, when the two-dimensional physical address parameters include the number of consecutively accessed groups and the number of consecutively accessed banks, the calculation process for group_access_num and bank_access_num is as follows:

[0124] `group_access_num` and `bank_access_num` represent the number of groups and banks that need to be accessed for reading or writing a Cell data block, respectively. The expressions for calculating `group_access_num` and `bank_access_num` are as follows:

[0125] ;

[0126] ;

[0127] Among them, group_access_num is determined by access_c sent by the SRAM logical coordinate generation unit; bank_access_num is determined by access_h sent by the SRAM logical coordinate generation unit. Since there may be multiple data in an address space, the actual bank_access_num is obtained by dividing access_h by the number of data in an address space.

[0128] Optionally, for ease of understanding, the following description of the SRAM internal address calculation process will use a 16-bit DW as an example. Correspondingly, the process is similar when DW is other values, and the relevant formulas can be adjusted, which will not be elaborated upon here.

[0129] When the two-dimensional physical address parameters include the internal physical address of the SRAM, the calculation process of the internal physical address of the SRAM includes:

[0130] The physical address (SRAM_addr) inside the SRAM is calculated using a base address plus multiple offsets, ensuring the correct mapping from three-dimensional logical coordinates to one-dimensional physical addresses.

[0131] Here, `block` represents the block number in the accessed group at the current c-coordinate `pos_c`. Its value is obtained by dividing the currently accessed c-dimensional coordinate by the total number of groups, `group_num`. Therefore, the calculation expression for this block is:

[0132] ;

[0133] Furthermore, `block_offset` represents the offset address of the channel within the data block, also known as the block offset address. Its value is obtained by multiplying the block number in the currently accessed group by the address offset of a block. Therefore, the expression for calculating `block_offset` is:

[0134] ;

[0135] In the formula, W and H are the width and height of the data block size processed by the data cache module, respectively; bank_num represents the total number of banks; SRAM_WIDTH represents the bit width of the SRAM; and DW represents the preset data precision.

[0136] Furthermore, `col_offset` represents the offset address of `col` within the currently read / written block, and its value is obtained by multiplying the currently accessed W-dimensional coordinate by the address offset of a `col`. Therefore, the expression for calculating `col_offset` is:

[0137] ;

[0138] In the formula, pos_w represents the width logical coordinate; H is the height of the data block size processed by the data cache module; bank_num represents the total number of banks; SRAM_WIDTH represents the bit width of the SRAM; and DW represents the preset data precision.

[0139] Furthermore, the expression for calculating the column offset generated by dimension H within the current logical column is as follows:

[0140] ;

[0141] In the formula, col_same represents the column offset generated by the H dimension within the current logical column (i.e., the column offset generated by the H dimension within the current logical column); pos_h represents the height logical coordinate; bank_num represents the total number of banks; SRAM_WIDTH represents the bit width of the SRAM; and DW represents the preset data precision.

[0142] Furthermore, the SRAM internal address is determined by the block offset address block_offset, the col offset address col_offset, and the column offset col_same generated by the H dimension within the current logical column. The formula for calculating the SRAM internal address is as follows:

[0143] SRAM_addr=col_same+col_offset+block_offset;

[0144] In the formula, SRAM_addr represents the internal address of SRAM.

[0145] For example, when pos_w is 1, pos_h is 1, and pos_c is 8, the address to be calculated is the first column of block1 and col1, and the offset address of block is the address space occupied by block0. The offset address of col is the address space occupied by col.

[0146] Optionally, the formula for calculating the address space block_offset_o occupied by a block is:

[0147] ;

[0148] In the formula, W and H are the width and height of the data block size processed by the data cache module, respectively; bank_num represents the number of banks accessed by the Cell block; SRAM_WIDTH represents the bit width of the SRAM; and DW represents the preset data precision.

[0149] Furthermore, SRAM_WIDTH / DW represents the number of data elements that can be stored in one address space of SRAM. For example, when DW is 16 bits, one data element is stored in one address space; when DW is 8 bits, two data elements are stored in one address space; and when DW is 4 bits, four data elements are stored in one address space.

[0150] Furthermore, the bit selection signal is obtained by taking the modulo of the H-dimensional coordinates of the currently accessed address with respect to the data in the H-dimensional space, i.e., its calculation expression is:

[0151] ;

[0152] In the formula, bit_select represents the bit selection signal; pos_h represents the height logic coordinate; % represents integer division; SRAM_WIDTH represents the bit width of the SRAM; and DW represents the preset data precision.

[0153] Therefore, by utilizing the above technical solutions, the embodiments of this application can manage 3D data with configurable "data shape," adjustable storage space, multi-dimensional data transmission, and diverse data precision. This addresses the data organization requirements of self-reconfigurable and self-evolving AI chips in complex scenarios, demanding high bandwidth, multiple shapes, and high energy efficiency. Furthermore, this application also designs dedicated configuration instructions for configuring the shape, step size, and sequence of data transmission. Simultaneously, dedicated operating instructions are designed for configuring certain signals and initiating data transmission, thereby enabling efficient and configurable access to data blocks in the three-dimensional space.

[0154] It should be understood that the above-described memory controller and chip for self-reconfigurable and self-evolving AI chips are merely exemplary. Those skilled in the art can make various modifications based on the above method, and the modified solutions also fall within the protection scope of this application.

[0155] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0156] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions.

[0157] It should be noted that the word "a" or "an" preceding a component does not preclude the existence of multiple such components. This invention can be implemented using hardware comprising several different components and using a suitably programmed computer. Among the listed devices, several of these devices may be embodied by the same hardware. The use of terms such as "first," "second," "third," etc., is merely for convenience and does not indicate any order. These terms can be understood as part of the component names.

[0158] Furthermore, it should be noted that in the description of this specification, the terms "one embodiment," "some embodiments," "embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0159] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the technical solution should be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0160] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the invention's technical solutions and their equivalents, then this invention should also include these modifications and variations.

Claims

1. A memory controller for a self-reconfigurable and self-evolving AI chip, characterized in that, It includes multiple data caching modules, each of which is configured to manage the storage and access of 3D data blocks in the on-chip SRAM array; Each data caching module includes: The instruction decoding unit is configured to receive and parse the input instruction. If the instruction is determined to be a configuration instruction, the configuration parameters parsed from the instruction are updated in the corresponding configuration register. If the instruction is determined to be a working instruction, the working parameters parsed from the instruction are updated in the corresponding configuration register. After the parameters are updated, the start control signal is sent to the DDR address generation unit and the SRAM management unit respectively. The DDR address generation unit is configured to be responsible for address calculation tasks related to off-chip DDR memory; The SRAM management unit is configured to be responsible for access control and address generation of the on-chip SRAM array; wherein the SRAM management unit includes the on-chip SRAM array.

2. The storage controller according to claim 1, characterized in that, The size of the three-dimensional data block is defined by width dimension W, height dimension H, and channel dimension C; the on-chip SRAM array comprises m groups, each group includes n banks, and each bank includes k SRAM chips; the SRAM array is capable of simultaneously reading and writing consecutive m groups, and each group is capable of simultaneously reading and writing consecutive n banks; m, n, and k are all preset positive integers. Each group is associated with C, and each group is configured to manage data for C / m channels; Each bank is associated with H, and each bank is configured to manage data at H / n heights; The number of SRAM chips is associated with W to enable physical storage of the three-dimensional data blocks.

3. The storage controller according to claim 2, characterized in that, The SRAM management unit includes: The SRAM logical coordinate generation unit is configured to generate a logical coordinate sequence that traverses in a specified dimensional order within the three-dimensional space of the three-dimensional data block based on the configured sub-data block cell sliding step size and cell data read / write order. It also performs boundary checks in real time and dynamically calculates the actual three-dimensional data size for each access to ensure that the access does not exceed the preset three-dimensional data block boundary. The sub-data block cell is the data block that is read and written in each step of the three-dimensional data block. The SRAM physical address generation unit is configured to map the logical coordinate sequence into two-dimensional physical address parameters; wherein the two-dimensional physical address parameters include group ID, bank ID, SRAM internal address, bit select signal, address space occupied by the three-dimensional data block, number of consecutively accessed groups, and number of consecutively accessed banks.

4. The storage controller according to claim 3, characterized in that, The logical coordinate generation unit needs to generate a logical coordinate sequence including the channel logical coordinate pos_c corresponding to the channel dimension C of the sub-data block Cell; The group ID is obtained by taking the modulo of pos_c with group_num; where group_num is the number of groups occupied by the current data block.

5. The storage controller according to claim 3, characterized in that, The logical coordinate generation unit needs to generate a logical coordinate sequence including the logical height coordinate pos_h of the sub-data block Cell in the height dimension H; The bank ID is determined by the height logical coordinate pos_h, the bit width of the SRAM, the preset data precision, and the number of banks occupied by the height dimension H.

6. The storage controller according to claim 3, characterized in that, The three-dimensional data block is divided into C blocks according to the channel dimension C, and each of the C blocks includes W columns col; The SRAM internal address is determined by the block offset address, the col offset address, and the column offset generated by the H dimension within the current logical column; wherein, the block offset address represents the offset address in the channel dimension C; the col offset address represents the offset address in different logical columns col within the same block; and the column offset generated by the H dimension within the current logical column represents the offset address within the same col.

7. The storage controller according to claim 6, characterized in that, The logical coordinate generation unit needs to generate a logical coordinate sequence including the channel logical coordinate pos_c corresponding to the channel dimension C of the sub-data block Cell, the height logical coordinate pos_h corresponding to the height dimension H of the sub-data block Cell, and the width logical coordinate pos_w corresponding to the width dimension W of the sub-data block Cell. The block offset address is determined by the block number in the group accessed under the current pos_c, the W, the H, the total number of banks, the bit width of the SRAM, and the preset data precision; wherein, the block number is the quotient of the pos_c and the group_num; The col offset address is determined by the pos_w, the H, the total number of banks, the bit width of the SRAM, and the preset data precision. The column offset generated by the H dimension within the current logical column is determined by the pos_h, the total number of banks, the bit width of the SRAM, and the preset data precision.

8. The storage controller according to claim 1, characterized in that, The DDR address generation unit includes: The DDR logical coordinate generation unit is configured to calculate the logical coordinates of the feature map data stored in the DDR storage space for each read or write operation of a sub-data block Cell in the DDR storage space; the sub-data block Cell is the data block read or written in each three-dimensional data block; wherein, the feature map data is an off-chip three-dimensional data block; The DDR physical address generation unit is configured to convert the logical coordinates into physical byte addresses in the DDR memory space using a three-dimensional to one-dimensional address mapping formula.

9. The storage controller according to claim 8, characterized in that, The formula for the three-dimensional to one-dimensional address mapping is: phy_addr=featuremap_addr+c_position*TW*Maxheight+w_position*Maxheight+h_position*(DW / DDR_WIDTH); In the formula, phy_addr represents the physical byte address; featuremap_addr represents the address of the top-left corner of the currently processed feature map data in DDR, and the feature map data is an off-chip three-dimensional data block; c_position represents the logical coordinate of the current channel; TW represents the total width of the currently processed feature map; Maxheight represents the memory size of each column; w_position represents the logical coordinate of the current data column; h_position represents the logical coordinate within the column of the current data element; DW represents the preset data precision; and DDR_WIDTH represents the bit width of the DDR.

10. A self-reconfigurable and self-evolving AI chip, characterized in that, Includes a memory controller for a self-reconfigurable and self-evolving AI chip as described in any one of claims 1-9.

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