Data processing apparatus and data processing method

Abstract

The embodiment of the invention discloses a data processing device and a data processing method. The data processing device comprises a processor and a memory, the memory comprises a control unit, a storage unit and a computing unit, the storage unit comprises a first storage partition and a second storage partition, and each storage partition is used for executing different data operations; the control unit is used for receiving a first request instruction and a second request instruction sent by the processor, and selecting a corresponding storage partition from the plurality of storage partitions based on a request address and a request operation in the request instruction; the first storage partition is used for executing data operation corresponding to a first request instruction, and the first request instruction comprises the step of transmitting data of the first storage partition to a computing unit of a memory so as to compute the data through the computing unit; the second storage partition is used for executing data operation corresponding to a second request instruction, and the second request instruction comprises data of the processor accessing the second storage partition.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of data processing technology, and in particular to a data processing apparatus and a data processing method. Background Technology

[0002] With the rapid development of artificial intelligence and big data technologies, the requirements for data processing capabilities are constantly increasing. Therefore, in-memory computing has been proposed, which can realize local data processing by integrating computing units inside the memory, thereby reducing the performance bottleneck caused by data movement.

[0003] However, in related technologies, when data processing is performed using in-memory computing, computation and access operations are not mutually exclusive. One mode must be completed before switching to another, resulting in low overall system efficiency. Summary of the Invention

[0004] In view of this, embodiments of this application provide at least one data processing apparatus and a data processing method.

[0005] The technical solution of this application embodiment is implemented as follows: On one hand, embodiments of this application provide a data processing apparatus, including a processor and a memory. The memory includes a control unit, a storage unit, and a computing unit. The storage unit includes a first storage partition and a second storage partition, each used to perform different data operations. The control unit is used to receive a first request instruction and a second request instruction sent by the processor, and select a corresponding storage partition from multiple storage partitions based on the request address and request operation in the request instruction. The first storage partition is used to execute the data operation corresponding to the first request instruction, the first request instruction including transferring data from the first storage partition to the computing unit of the memory for calculation by the computing unit. The second storage partition is used to execute the data operation corresponding to the second request instruction, the second request instruction including the processor accessing data in the second storage partition.

[0006] In some embodiments, the control unit receives the second request instruction simultaneously with the first request instruction.

[0007] In some embodiments, the control unit is configured to obtain corresponding computing context data from the first storage partition according to the first request instruction, and send it to the computing unit; the computing unit is configured to obtain the computing context data of the first storage partition, and perform the computing operation corresponding to the first request instruction based on the computing context data to obtain the computing result.

[0008] In some embodiments, the memory further includes a mode register; the control unit is configured to update the operating state in the mode register to a first state in response to the first request instruction sent by the processor; the mode register is configured to configure the first storage partition into a computing mode based on the first state, so as to transfer the data of the first storage partition to the computing unit and perform calculations on the data by the computing unit.

[0009] In some embodiments, the control unit is further configured to update the working state in the mode register to a second state in response to the completion of the calculation by the computing unit; the mode register is further configured to configure the first storage partition into an access mode based on the second state, so that the processor can access the data in the first storage partition.

[0010] In some embodiments, the memory further includes a multiplexer, wherein one end of the multiplexer is connected to the first storage partition, and the other end of the multiplexer is connected to the computing unit and the input / output buffer of the first storage partition, respectively; the multiplexer is configured to: when the operating state in the mode register is a first state, establish a first data transmission path between the computing unit and the first storage partition; and when the operating state in the mode register is a second state, establish a second data transmission path between the input / output buffer and the first storage partition, wherein the input / output buffer is an area accessible by the processor.

[0011] In some embodiments, the computing unit is configured to store the calculation result back to the first storage partition or the input / output buffer after the calculation is completed; the processor is configured to access the calculation result stored in the first storage partition or the input / output buffer through the second data transmission path.

[0012] In some embodiments, the control unit is configured to acquire access data corresponding to the second request instruction and store the access data in the second storage partition; the second storage partition is configured to store the access data so that the processor can access the access data in the second storage partition.

[0013] In some embodiments, the memory further includes a request queue; the control unit is further configured to: store multiple acquired request instructions into the request queue; and dynamically schedule different request instructions to be executed concurrently in the corresponding storage partitions based on the request address, request operation, and status information of each request instruction in the request queue.

[0014] This application provides a data processing method applied to a memory in a data processing device, the memory being connected to a processor. The method includes: receiving a request instruction sent by the processor; the request instruction includes a first request instruction and a second request instruction; selecting a corresponding storage partition from a plurality of storage partitions based on a request address and a request operation in the request instruction; executing a data operation corresponding to the first request instruction, the first request instruction including transferring data from the first storage partition to a computing unit of the memory for computation by the computing unit; and executing a data operation corresponding to the second request instruction, the second request instruction including the processor accessing data in the second storage partition.

[0015] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a data processing method provided in an embodiment of this application; Figure 3 This is a schematic diagram of a near-memory computing module provided in the background technology of this application; Figure 4 This is a schematic diagram of a data reading process for a memory subsystem provided in the background technology of this application; Figure 5 This is a schematic diagram of the data calculation process of a memory subsystem provided in the background technology of this application; Figure 6 This is a schematic diagram of the structure of an in-memory computing device provided in an embodiment of this application; Figure 7 This is a flowchart of a data processing method provided in an embodiment of this application.

[0017] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0021] Currently, with the rapid development of artificial intelligence and big data technologies, the requirements for data processing capabilities are constantly increasing. Therefore, Processing in Memory (PIM) has been proposed, which can realize local data processing by integrating computing units inside the memory, thereby reducing the performance bottleneck caused by data transfer.

[0022] In related technologies, when data processing is performed using in-memory computing, especially in analog computing based on DRAM (Dynamic Random Access Memory) or SRAM (Static Random-Access Memory) arrays, the operation relies on precise sensing and manipulation of the charge state of memory cells (such as capacitors and transistors). The physical hardware used for computing and the hardware used for data access are the same memory array and its peripheral circuits. This sharing leads to fundamental operational mutual exclusion.

[0023] For example, in access mode, the word lines, bit lines, and sensitive amplifiers of the memory array are configured to perform read or write operations. For instance, during a read operation, the word lines are activated, and the bit lines detect minute current or voltage changes, which are then amplified by the sensitive amplifier to output a digital value. In compute mode, the same set of word lines and bit lines is used to apply specific voltage / current vectors and utilize the physical characteristics of the memory cells (such as charge sharing, current superposition, and resistor voltage division) to directly perform matrix-vector multiplication and other operations in the analog domain. The results are also read out through a sensitive amplifier or analog-to-digital converter.

[0024] These two modes have completely different requirements for the electrical state of the memory array, the timing of control signals, and the configuration of peripheral circuits (such as the bias of the sensitive amplifier and the reference voltage), and they interfere with each other. For example, after a calculation operation, residual charge may remain on the bit lines, and the memory cell may be in a non-standard logic state. If a read operation is forcibly switched at this time, it will lead to data errors.

[0025] In related technologies, when a memory switches from the computation phase to the access phase, computation must first be stopped to allow all units of the array to return to a stable static storage state. Then, the multiplexer and sensitive amplifier are reconfigured to the standard memory mode before data loading or result reading can be performed.

[0026] This leads to several problems. First, it reduces the effective utilization of computing power, resulting in significant idle time for computing units. For algorithms that require frequent weight exchanges (such as model depth or mixed-precision calculations) or intermediate results, system performance will be dominated by the slow mode switching frequency, rather than peak computational throughput. Second, frequent mode switching itself consumes energy (power consumption of circuit state switching) and increases static power consumption by lengthening task completion time. Third, serial computation and access on the same hardware in the same location will cause severe latency, affecting data processing efficiency.

[0027] In view of the above problems, this application provides a data processing device. The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0028] To better understand the technical solution of this application, the key concepts involved will be explained below: 1) PIM (Processing in Memory): refers to integrating processing units (PUs) inside memory to enable local computation of data in memory, reducing latency and energy consumption caused by data movement. It is suitable for large-scale parallel computing scenarios, such as artificial intelligence and high-performance computing.

[0029] 2) Storage Partition: This refers to different regions divided within the memory. Each region can be configured to perform specific types of data operations, such as computation or access operations. In this application, the memory is divided into at least two storage partitions, each used to perform different data processing tasks.

[0030] 3) Mode Register: This register records the current operating status of the storage partition, such as whether it is in compute mode or access mode. By setting the mode register, the control unit can dynamically adjust the functional configuration of the storage partition to adapt to different operational needs.

[0031] 4) Multiplexer: A data transmission controller that selects different data paths for transmission based on input signals. In this application, the multiplexer is used to switch data transmission paths between computing mode and access mode to ensure that data is sent to the correct destination at the correct time.

[0032] 5) Request Queue: Used to temporarily store multiple received request instructions. The control unit can dynamically schedule requests based on the request address, operation type, and status information of each storage partition to achieve concurrent execution of multiple requests.

[0033] The data processing apparatus provided in the embodiments of this application can be used to achieve PIM (Processing in Memory) and random access compatible operations. The apparatus includes a processor and a memory, wherein the memory includes a control unit, a storage unit, and a computing unit. The storage unit is further divided into a first storage partition and a second storage partition, each storage partition being used to perform different data operations.

[0034] Figure 1 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application, as shown below. Figure 1 As shown, the data processing device 100 provided in this application embodiment may include a processor 101 and a memory 102.

[0035] The memory 102 includes a control unit 1021, a storage unit 1022, and a computing unit 1023. The storage unit 1022 includes a first storage partition and a second storage partition, each of which is used to perform different data operations.

[0036] In some embodiments, the processor 101 can be connected to the memory 102 via a system bus. The processor 101 can send request instructions to the memory 102, which can be ordinary read / write commands or extended in-memory computation instructions. The system bus can include, but is not limited to, AXI (Advanced eXtensible Interface), PCIe (Peripheral Component Interconnect Express), or a specific in-memory computation instruction extension bus.

[0037] Inside the memory 102, the control unit 1021 can be connected to the system bus through the interface of the memory 102, directly receiving commands and data from the processor 101, and connecting and controlling the storage unit 1022 and the computing unit 1023 through the internal control bus and data path to perform data processing operations. Specifically, the control unit 1021 can parse the request instructions sent by the processor 101 to map the logical address in the request instructions to the physical storage partition (first / second storage partition) and generate the corresponding access timing.

[0038] In this embodiment, the control unit 1021 can be used to receive a first request instruction and a second request instruction sent by the processor 101, and select the corresponding storage partition from multiple storage partitions based on the request address and request operation in the request instruction.

[0039] The control unit 1021 can be used to convert the calculation / access instructions of the processor 101 into low-level control signals for the timing of the memory array and the computing unit 1023.

[0040] The requested address can be the memory address carried by the instruction, which can be used to locate data in the global logical address space of the storage unit 1022. The address mapping logic maintained internally by the control unit 1021 can be a preset strategy to map this logical address to a specific physical storage partition (first storage partition or second storage partition) according to the preset strategy.

[0041] In actual implementation, the control unit 1021 can receive instruction packets from the processor 101 through a dedicated instruction interface or memory-mapped I / O channel. Then, it can parse the request instruction through the control instruction decoder to extract key fields in the instruction: opcode (determined to be a first or second type of request), logical address, data length, etc.

[0042] When parsing a request instruction, the memory address in the request instruction can be determined to belong to either the first or second storage partition according to a preset address mapping rule. If the memory address determines it to be a first request instruction (computation request), its data operation can be routed to the partition currently configured as a computation work area (e.g., the first storage partition), which has a direct data path to the computation unit 1023. If the memory address determines it to be a second request instruction (access request), its data operation can be routed to the partition currently configured as a data exchange area (e.g., the second storage partition). This partition has a data interface connection to the processor 101.

[0043] In one possible implementation, in addition to memory address attribution, further judgment can be made based on the request operation (i.e., opcode type) of the request instruction; in another possible implementation, after determining the storage partition to which the request instruction belongs, arbitration judgment can be made based on the status of the storage partition (such as whether it is free or ready).

[0044] After the control unit 1021 obtains the storage partition corresponding to the request command, it can generate a selection signal to trigger the switching of the internal data path, so as to route the data operation corresponding to the request command to the corresponding storage partition according to the selection signal.

[0045] It should be noted that the micro-operation sequences and control signals generated by the control unit 1021 differ for different storage partitions. Specifically, for requests routed to the first storage partition (computation working area), the control unit 1021 can schedule the word lines and bit lines of that partition into computation sensing mode to convert operand addresses into specific row / column activation signals for the storage array, coordinate the startup of the computation unit 1023, and manage the write-back of computation results. For requests routed to the second storage partition (data exchange area), the control unit 1021 can schedule the circuitry of that partition into standard access mode. It generates timing control compatible with conventional DDR or HBM interface protocols to complete data reading or writing.

[0046] In this embodiment, the first storage partition can be used to perform data operations corresponding to the first request instruction.

[0047] The first request instruction includes transferring data from the first storage partition to the computation unit 1023 of the memory 102, so that the computation unit 1023 can perform computation on the data. The first request instruction can be used to trigger an in-memory computation operation, and its instruction semantics may include, but are not limited to, an opcode (such as PIM_VMAC, vector multiplication and accumulation), the address of the source operand in the memory 102 (such as weights and input data), and the destination address (used to store the computation result).

[0048] In actual implementation, after the control unit 1021 parses the received first request instruction, it can check the status register of the first storage partition to determine whether it is in a "ready" or "computable" state. Simultaneously, it can also check whether the computing unit 1023 is idle. Then, the control unit 1021 can configure the operating mode of the computing unit 1023 (such as precision, accumulator clearing) according to the parsed instruction parameters. At the same time, the control unit 1021 can send a pre-activation signal to the first storage partition, causing its peripheral circuitry to enter a computing sensing mode; specifically, this may include, but is not limited to, configuring the sensitive amplifier to integration or current sensing mode, setting the reference voltage / current to match the required calculation range, and enabling the analog or digital data path connected to the computing unit 1023.

[0049] After configuration, data operations corresponding to the first request instruction can be executed in the first storage partition. Specifically, the control unit 1021 can apply a voltage pulse sequence representing the input vector to one or more word lines corresponding to the source operand address to generate a calculation signal on the bit line. The digital part converted by the ADC at the front end of each bit line and the digital back end (such as a digital accumulator or activation function module) sent to the calculation unit 1023 are finally accumulated, compared, or nonlinearly transformed to generate the final calculation result.

[0050] In this embodiment, the second storage partition can be used to perform data operations corresponding to the second request instruction.

[0051] The second request instruction includes the processor 101 accessing data in the second storage partition. The second request instruction can be used to complete a pure data transfer operation between the processor 101 and the memory 102. Its instruction semantics can be a standard memory read (LOAD) or write (STORE) operation, including but not limited to accessing addresses and data. The second storage partition can be implemented using storage cells 1022 with the same structure as the first storage partition, but its peripheral circuitry is in standard digital access mode.

[0052] In actual implementation, after the control unit 1021 parses the received second request instruction, it can check the status register of the second storage partition to determine whether it is undergoing other access or refresh. Then, the control unit 1021 can convert the system bus transaction of the processor 101 (such as an AXI read transaction) into a DRAM / SRAM command sequence that the second partition can recognize. According to the command sequence, it sends the row address and activation command to the second storage partition, selects the corresponding word line, reads the data on the second storage partition, or, through the input buffer, overwrites the bit line signal under the drive of the write driver, rewriting the content of the activated memory cell 1022 with a new value, so as to realize the data operation corresponding to the second request instruction on the second storage partition.

[0053] By adopting the above technical solution, the physical division of the first storage partition and the second storage partition achieves physical concurrency of computation and data transfer at the hardware level. This allows the processor 101 to load the next batch of data to be computed or write the previous batch of computation results through the second storage partition while the computing unit 1023 is processing data from the first storage partition. This can greatly eliminate the idle time of the computing unit 1023, improve the overall throughput of the system, and enhance the overall effective computing power utilization and task completion speed of the system.

[0054] In some embodiments, the control unit 1021 may receive a second request instruction at the same time as receiving a first request instruction.

[0055] In this embodiment, the controller can be configured to simultaneously receive two independent request commands, namely a first request command and a second request command. The two independent request commands can correspond to different data paths and storage areas, respectively.

[0056] Specifically, when the controller receives the first request instruction, it identifies the target storage partition based on the request address and operation type, and prepares the corresponding PU (Process Unit) for calculation. At the same time, if a second request instruction is received, the controller can forward the second request instruction to a reserved non-PU bank or other channels that support random access, so that the controller can take this measure to ensure that the second request instruction will not interfere with the currently ongoing PIM calculation operation.

[0057] In this way, by adopting the above-mentioned parallel processing mechanism, the controller significantly improves the overall throughput of the system and reduces the performance bottleneck caused by mode switching.

[0058] However, considering the possibility of receiving multiple requests for the same storage partition consecutively within a short period (e.g., multiple consecutive computation requests), although they can be received simultaneously, the first storage partition can only process one computation operation at a time, and subsequent requests must wait, which can lead to resource conflicts. Therefore, in some embodiments, the memory 102 also includes a request queue. The request queue can be used as a buffer pool for all received first and second request instructions, to decouple the instruction reception and execution phases.

[0059] In this embodiment, the control unit 1021 can store multiple request instructions acquired into a request queue; then, it can dynamically schedule different request instructions to be executed concurrently in the corresponding storage partitions based on the request address, request operation, and status information of each request instruction in the request queue.

[0060] Dynamic scheduling refers to the control unit 1021 dynamically allocating requests to the most suitable storage partition for processing based on the content of the request instruction (such as the request address and request operation type) and the current status of each storage partition (such as whether it is idle or under load). This enables concurrent execution, allowing multiple request instructions to be processed simultaneously on different storage partitions, thereby effectively utilizing the parallel processing capability of the memory 102.

[0061] In this embodiment, the dynamic scheduler in the control unit 1021 can decode each instruction in the request queue, extract its request opcode, and determine whether the instruction belongs to a first request instruction that calls the computation execution path or a second request instruction that calls the data access path. Then, based on the request address in the instruction, the address mapping logic integrated in the control unit 1021 can convert the logical address into the corresponding physical storage partition identifier. This mapping explicitly indicates whether the target data of the instruction resides in the first storage partition or the second storage partition. At the same time, the status register values ​​of the first and second storage partitions can be monitored and obtained in real time. The status includes at least "idle", "busy", and "configuring".

[0062] The dynamic scheduler can continuously scan one or more instruction entries to be scheduled in the request queue and simultaneously read the real-time status information of the first and second storage partitions. Then, it can perform logical judgment on each scanned instruction to select one from all "currently dispatchable instructions" as the dispatch instruction.

[0063] The logical judgment can be implemented using parallel comparison and selection circuits. For each instruction slot in the request queue, the scheduler can calculate its dispatchability conditions in parallel. The dispatchability conditions can be that the operation type of the instruction matches the state of the target partition and that the target partition is idle.

[0064] After determining the dispatch instruction, the selected dispatch instruction can be removed from the request queue, and a series of micro-operation control signals can be sent to the target partition (and associated computing unit 1023 or data interface) corresponding to the instruction to initiate instruction execution, update the target partition's status to busy, and achieve resource locking. When any storage partition completes its current operation, its state machine automatically updates its status register to idle and sends a completion event notification to the control unit 1021. This notification triggers the dynamic scheduler to immediately start a new cycle of monitoring, evaluation, and dispatch.

[0065] By adopting the above technical solution, a dynamic scheduling mechanism can rationally allocate tasks based on the content of the request instruction and the state of the storage partition. This dynamic scheduling mechanism enables efficient matching between request instructions and storage partitions, thereby reducing system waiting time and increasing throughput. Consequently, the memory 102 can significantly enhance its compatibility and performance in both computation and random access modes.

[0066] In some embodiments, the control unit 1021 may be used to obtain corresponding computing context data from the first storage partition according to the first request instruction, and send it to the computing unit 1023. After obtaining the computing context data of the first storage partition, the computing unit 1023 may perform the computing operation corresponding to the first request instruction based on the computing context data to obtain the computing result.

[0067] The computational context data refers to the set of state information and parameters required when performing a computational task. This data includes, but is not limited to, input vectors, weight matrices, and configuration parameters of activation functions.

[0068] In this embodiment, after decoding the first request instruction, the control unit 1021 can extract the address of the computation context descriptor. This address is used to point to the starting position of the first storage partition where the complete context data structure for this computation is stored. Then, the control unit 1021 initiates one or more dedicated context read transactions to the first storage partition. After reading the context data, the control unit 1021 can send the entire context data packet to the computation unit 1023.

[0069] The computation unit 1023 may have internal context decoding logic. After receiving a data packet, the computation unit 1023 can automatically parse out various fields: extracting operand pointers, reading metadata, etc. Then, based on the parsed operand addresses, the computation unit 1023 can directly send micro-operation requests to the first storage partition, and load the required data blocks into the internal registers or cache of the computation unit 1023 in a pipelined manner. At the same time, it configures the internal computation pipeline according to the metadata: setting the connection method of the multiplier array, selecting the activation function module, configuring the accumulator depth and rounding mode, etc.

[0070] After configuration, the computing unit 1023 starts to perform calculations according to the configured pipeline, and after the calculation is completed, it writes the result directly back to the specified location of the first storage partition according to the result destination pointer in the context.

[0071] In one possible implementation, after the calculation unit 1023 completes its execution, it can send a calculation completion interrupt to the control unit 1021, along with a status code (such as overflow or completion status). The control unit 1021 can then update the relevant status of the first partition and notify the processor 101 of the calculation result being ready.

[0072] By adopting the above technical solution, when the control unit 1021 acquires and dispatches the computing context for the computing task, this is itself part of the computing task preparation phase, mainly interacting with the first storage partition. Simultaneously, the second storage partition can independently and in parallel execute the processor 101's data access requests (second request instructions) and exchange data. This allows not only parallel execution of computation and data access, but also parallel preparation of the computing task (context acquisition) with data access. This hides the delays in data movement and task preparation, resulting in higher overall system throughput and less resource idle time.

[0073] In some embodiments, the memory 102 further includes a mode register. The mode register is a special register within the memory 102 used to store the current operating state and configuration information of the memory 102. The mode register can be read or updated by the control unit 1021, thereby switching different operating modes of the memory 102, such as computation mode or random access mode. The mode register typically contains multiple bit fields, each representing a different functional configuration, such as whether the computation unit 1023 is enabled, the currently used storage unit 1022, and the data transfer path selection.

[0074] In this embodiment, the control unit 1021 may update the working state in the mode register to the first state in response to the first request instruction sent by the processor 101.

[0075] The first state can be a specific encoded value in the mode register that represents the computation mode. When the mode register is updated to this state, it can serve as a global enable signal to trigger the first storage partition to switch from the standard memory access mode to a dedicated mode optimized for in-memory computation.

[0076] In this embodiment, the mode register can configure the first storage partition into a computing mode based on a first state, so as to transmit the data of the first storage partition to the computing unit 1023, and perform calculations on the data through the computing unit 1023.

[0077] In practice, configuring the first storage partition as a computing mode can mean that when the mode register is in the "first state", its output signal directly controls the analog / digital circuits of the first storage partition, so that its electrical characteristics and connection relationships are adapted to computing operations.

[0078] Specifically, after the decoder of control unit 1021 recognizes the first request instruction and completes the scheduling decision (deciding to use the first storage partition), before initiating any data operation on the first storage partition, control unit 1021 can generate a write operation to write a specific value representing the "first state" (computation mode) into the corresponding field of the mode register.

[0079] The output signal of the mode register can be directly connected to the mode selection terminal of the relevant circuitry in the first storage partition. When the register value is updated to "first state", the operating point and connection of the relevant circuitry can be switched by triggering a switching signal. After the mode switch is completed, the control unit 1021 can read the computation context data from the first storage partition and send it to the computation unit 1023. The computation unit 1023 then drives the first storage partition in computation mode to perform actual calculations (e.g., applying an input voltage vector, reading the computation current from the bit line, etc.) based on this context data.

[0080] By employing the above technical solution and using the mode register as the mode control point, it is possible to ensure that all relevant circuits switch to the target mode synchronously and consistently. Furthermore, by writing to a single register, a globally predefined reconfiguration sequence can be triggered, simplifying the control logic and reducing mode switching latency and power consumption.

[0081] In some embodiments, the control unit 1021 may also update the working state in the mode register to the second state in response to the completion of the calculation by the computing unit 1023; in this case, the mode register may configure the first storage partition into an access mode based on the second state, so that the processor 101 can access the data in the first storage partition.

[0082] The second state can be a specific encoded value representing the access mode in the mode register. In this state, all circuits of the first memory partition are configured to support standard read and write operations of the processor 101.

[0083] In this embodiment, after the calculation unit 1023 completes the instruction execution, it can send a calculation completion interrupt or completion status signal to the control unit 1021 to update the working state in the mode register to the second state.

[0084] Specifically, after the computing unit 1023 has completed all operations specified in the context, its internal state machine can trigger a completion event. For example, the completion event can be triggered by setting a flag bit in a status register and / or pulling an interrupt signal line high. After the control unit 1021 captures the completion signal (interrupt signal), the control unit 1021 can write a second state to the mode register before allowing any new access instructions to the first partition. In this way, it can be ensured that no access operation is erroneously executed on the first storage partition before the circuit switching is completed.

[0085] After updating the operating state in the mode register to the second state, the circuitry of the first storage partition can be driven to switch in reverse. After the switch stabilizes, the first storage partition logically becomes a standard storage block. The processor 101 can then issue access instructions to it, such as reading the calculation results of the previous round or writing new weights and input data for the next round of calculation.

[0086] By adopting the above technical solution, the first storage partition is no longer just a static computing-dedicated area. During computation breaks, it can be quickly restored to standard memory that can be directly accessed by the processor 101. In this way, the processor 101 can directly read the computation results with extremely low latency, without needing to forward them through the computing unit 1023. Moreover, it realizes the dual role of computing memory and program-visible memory in the time dimension, improving silicon utilization.

[0087] Considering that the first storage partition needs to switch between computing mode and access mode in this application, when it serves as a local register file / cache of computing unit 1023, it needs to exchange data with computing unit 1023 with high bandwidth, low latency, and possibly analog signals to support computing; while when it serves as standard memory 102 addressable by processor 101, it needs to exchange data with processor 101 (or system bus) digitally and in accordance with bus protocol through standard storage interface. However, if the two data paths coexist without control, the analog voltage / current of the bit line driven by computing unit 1023 and the digital I / O drive of processor 101 may act on the same signal line simultaneously, leading to signal confusion, circuit overload, or even damage; and since the timing requirements (such as precharge time and sensing time) of computing mode and access mode for the storage array are completely different, allowing both access modes simultaneously will disrupt timing regularity.

[0088] In some embodiments, the memory 102 further includes a multiplexer.

[0089] In this embodiment, one end of the multiplexer is connected to the first storage partition, and the other end is connected to the computing unit 1023 and the input / output buffer of the first storage partition, respectively. The multiplexer can be a digital circuit element used to select one of multiple input signals as the output based on a control signal. In this embodiment, the multiplexer switches data transmission paths in different operating modes, thereby achieving efficient communication between the computing unit 1023 and the first storage partition, as well as flexible interaction between the input / output buffer and the first storage partition.

[0090] In this embodiment, one end of the multiplexer can be connected to the internal data bus of the first storage partition; the other end of the multiplexer can be provided with at least two ports, one of which can be connected to the dedicated data interface of the computing unit 1023, and the other port can be connected to a standard input / output buffer, the other end of which is connected to the system bus of the processor 101 or the memory 102 controller. The control terminal of the multiplexer can be directly controlled by the output of the mode register.

[0091] In actual execution, when the working state in the mode register is in the first state, the first data transmission path between the computing unit 1023 and the first storage partition can be established through the multiplexer. And when the working state in the mode register is in the second state, the second data transmission path between the input / output buffer and the first storage partition is established; the input / output buffer is an area accessible by the processor 101.

[0092] The input / output buffer (I / O buffer) is a memory area accessible to the processor 101, and it has the function of temporarily storing data from external devices or sending data to external devices. In this scheme, a data connection is established between the I / O buffer and the first storage partition through a multiplexer. This connection method allows the system to complete external access requests directly through the data connection path between the I / O buffer and the first storage partition in non-computing mode.

[0093] Specifically, when the mode register is in the first state (i.e., computing mode), the control signal can cause the multiplexer to select port A connected to the dedicated data interface of the computing unit 1023, so as to establish a first data transmission path between the first storage partition and the computing unit 1023. At this time, the path to the I / O buffer (port B) is completely cut off, and the processor 101 cannot access the partition, thus physically eliminating interference.

[0094] When the mode register is in the second state (i.e., access mode), the control signal can cause the multiplexer to select port B connected to the input / output buffer to establish a second data transmission path between the first storage partition and the I / O buffer. At this time, the path to the computing unit 1023 (port A) is completely cut off, and computing activities cannot affect normal access to the memory 102.

[0095] By employing the above technical solution, when in the first state (computation mode), the multiplexer exclusively connects the first data transmission path, connecting the first storage partition to the computing unit 1023, while physically disconnecting it from the input / output buffer. This avoids interference, overload, and even damage to the analog or customized signal circuits sensitive to the computing unit 1023 caused by standard digital drive signals from the processor 101 bus. When in the second state (access mode), the second data transmission path is exclusively connected, restoring the first storage partition to standard memory 102 and connecting it to the input / output buffer, while physically isolating the computing unit 1023. Thus, through hardware-forced mutual exclusion, the possibility of data errors, decreased circuit reliability, and even permanent hardware damage caused by signal conflicts can be eliminated, improving the stability of the mixed-signal in-memory computing system.

[0096] In some embodiments, the calculation unit 1023 may also store the calculation result back to the first storage partition or input / output buffer after the calculation is completed, and the processor 101 may access the calculation result stored in the first storage partition or input / output buffer through the second data transmission path.

[0097] The calculation result is the final data output generated by the calculation unit 1023 after it has completed all the operations specified by a calculation context.

[0098] In this embodiment, when writing the calculation result back to the first storage partition, the calculation unit 1023 can write the result data back to a specified location in the first storage partition through the first data transmission path. This specified location can be an address predefined in the calculation context (such as the "result destination address" field). After the write-back operation is completed, the calculation unit 1023 notifies the control unit 1021. Subsequently, the control unit 1021 switches the mode register from the first state (calculation mode) back to the second state (access mode). After the mode switch, the multiplexer activates the second data transmission path. The processor 101 can then obtain the calculation result by initiating a read request to the corresponding address in the first storage partition, just like accessing ordinary memory.

[0099] In this way, if the calculation result will be used as the input for the next calculation, it can be stored locally (in the first storage partition) and accessed very quickly by the computing unit 1023, reducing data movement.

[0100] When writing the calculation result back to the input / output buffer, a bypass path can exist within the calculation unit 1023 or between it and the input / output buffer. After the calculation is completed, the calculation result can be written directly to the input / output buffer through this bypass instead of passing through the first storage partition. The input / output buffer can have a status flag bit. After the calculation result is written, this flag bit can be set to trigger an interrupt to notify the processor 101. The processor 101 can always access the input / output buffer (which is mapped to the processor 101's address space) through its standard memory interface. When the buffer status is found to be valid, it can be read directly.

[0101] In this way, for lightweight results (such as a comparison result or a scalar) that need to be quickly fed back to the processor 101, this path avoids the overhead of mode switching and first partition access, achieving the fastest output speed.

[0102] By adopting the above technical solution and supporting two result storage paths, a matching data backflow path can be selected according to the data reuse mode, result size and real-time requirements, thereby minimizing data movement overhead and access latency and optimizing the overall data flow.

[0103] In some embodiments, the control unit 1021 may acquire access data corresponding to the second request instruction and store the access data in a second storage partition; the second storage partition may be used to store the access data so that the processor 101 can access the access data in the second storage partition.

[0104] In this context, accessed data refers to the data object requested by the second request instruction. Depending on the instruction type, accessed data can be divided into loaded data and stored data. When the second request instruction is a "read" operation, the accessed data refers to the data that the processor 101 needs to read from other parts of the system (such as main memory or other accelerators) and ultimately expects to obtain; when the second request instruction is a "write" operation, the accessed data refers to the data that the processor 101 wants to write to the target address.

[0105] In this embodiment, when the second request instruction is a "read" operation, the control unit 1021 receives the read request (second request instruction) from the processor 101, parses the external source address and data size to be read, and initiates a read transaction for the source address through its external memory 102 interface. After the data is read, the data returned from the external memory is directly written by the control unit 1021 into the free area of ​​the second storage partition.

[0106] In one possible implementation, the control unit 1021 maintains an address mapping table that records the correspondence between "external source address" and "internal second partition buffer address". Based on this correspondence, data returned from the outside can be written to the corresponding area in the second storage partition.

[0107] After the data is written, the control unit 1021 notifies the processor 101 that the data is ready and that the data is stored at address X of the second storage partition via an interrupt or status register update. In this case, the processor 101 then initiates a read operation on address X of the second storage partition to read the required data.

[0108] In this embodiment, when the second request instruction is a "write" operation, the processor 101 initiates a write request. The data is first written to a buffer location of the second storage partition, and then the control unit 1021 asynchronously and in batches writes the accumulated write data in the second partition back to the final external target address.

[0109] By adopting the above technical solution, when the computing unit 1023 is processing the data in the first partition, the control unit 1021 can exchange large amounts of data with the external memory in parallel through the second partition (prefetch the next batch of computing data or write back the previous batch of results), hiding the high-latency external data transfer behind the long-term computing operation, so that the overall throughput of the system is no longer limited by the external memory bandwidth and latency.

[0110] Based on the foregoing embodiments, this application provides a data processing method, which can be applied to the data processing apparatus 100 described in any of the foregoing embodiments, such as... Figure 2 As shown, the method may include the following steps S201 to S204.

[0111] Step S201: Receive a request instruction sent by the processor; the request instruction includes a first request instruction and a second request instruction. Step S202: Select the corresponding storage partition from multiple storage partitions based on the request address and request operation in the request instruction; Step S203: Execute the data operation corresponding to the first request instruction. The first request instruction includes transferring the data of the first storage partition to the computing unit of the memory so that the computing unit can perform calculations on the data. Step S204: Execute the data operation corresponding to the second request instruction, which includes the processor accessing data in the second storage partition.

[0112] In the embodiments of this application, specific implementation methods can be referred to the description of any of the foregoing data processing devices. The descriptions of the above method embodiments are similar to the descriptions of the above device embodiments and have similar beneficial effects. For technical details not disclosed in the method embodiments of this application, please refer to the descriptions of the device embodiments of this application for understanding.

[0113] The following describes the application of the data processing device provided in the embodiments of this application in a real-world scenario, mainly involving a device with PIM and random access memory compatible design.

[0114] Due to the memory bandwidth requirements of Large Language Models (LLMs), Processing in Memory (PIM) is a highly feasible solution for edge computing, offering advantages such as high energy efficiency, low latency, and high memory bandwidth (>1TB / s) that traditional memory lacks. However, PIM also has an inherent technical drawback: during computation, it requires opening all internal banks and interfaces between them and the processing units (PUs) to perform calculations. After the calculations are completed, the results are directly stored in the corresponding memory. During this period, external I / O (input / output) is suspended, and the CPU's random access is unavailable, making it unsuitable for traditional x86 / ARM architectures. Based on this, this application proposes two architectures that can simultaneously address the computational and random access requirements of PIM.

[0115] Figure 3 This is a schematic diagram of a near-memory computing module 300 provided in the background art of this application, such as... Figure 3 As shown, externally input computation or access instructions (CMDs) are first parsed by command decoder 301. The resulting control signals are sent to row decoder 302 and column decoder 303 to locate specific rows and columns in the memory bank. The selected memory bank 304 (BANK) performs data read or write operations under the control of the row and column addresses. Data is transmitted on the internal bus with a 256-bit width; data read from memory bank 304 is transmitted via global input / output line 307. Data can be temporarily stored in global buffer 305 or exchanged with the outside of the chip via external input / output interface 306; data used for computation is sent to processing unit 308. After being temporarily stored in registers, the multiply-accumulate unit performs the core multiplication and accumulation operations to complete the computation task.

[0116] However, the PIM solution, by adding a process unit to standard memory, complicates the data path. It must maintain compatibility with standard DRAM to ensure random data access while also supporting GEMV (Generalized Matrix-Vector Multiplication) computation and data read / write operations. Current PIM designs require disabling external I / O data exchange when performing GEMV, which delays random access and causes some user requests to fail to respond promptly.

[0117] Figure 4 This is a schematic diagram of the data reading process of a memory subsystem 400 provided in the background technology of this application, such as... Figure 4 As shown, firstly, the row decoder 401 selects a specific row based on the address. The bank / bank group control unit 402 then determines which specific column (e.g., Rank0 or Rank1) and which bank (Bank0-7) within it to access.

[0118] Once the target row is activated, the data in all storage units 403 of that row is transmitted to the bit line and read and amplified by the inductive amplifier, converting it into a stable logic level. Subsequently, the column decoder 404 selects one or more columns of data from the entire row of data latched by the inductive amplifier based on the column address. The selected data is driven and buffered through the input / output buffer 405 and finally output through the data bus. The diagram shows that the data is directed to the computing unit array 406 on the right, indicating that this is an architecture designed for near-memory computing or in-memory computing, where data read from memory is directly supplied to the computing units.

[0119] Figure 5 This is a schematic diagram of the data calculation process of a memory subsystem 500 provided in the background technology of this application, such as... Figure 5 As shown, when an access request is received, the row decoder 401 parses the row address and selects a specific memory bank and a Bank within it via the memory bank / memory bank group control unit 402. The specific row in the selected Bank is activated, and the data from all memory cells in that row is transmitted to the inductive amplifier for signal amplification and temporary storage. Next, the column decoder 404 selects the target data column from the entire row of data temporarily stored by the inductive amplifier based on the column address. The selected data is driven by the input / output buffer 405. The data read here is directly transmitted to multiple computing units 406 adjacent to the memory array via a high-speed data path.

[0120] based on Figure 4 , Figure 5 The in-memory computing architecture and its working principle shown in the current technical solution have the following inherent defects: First, during in-memory computation operations, to ensure the exclusivity of the computation data path, dedicated computation interfaces between all memory banks and corresponding processing units must be enabled. This operation forces the standard input / output buffers of the memory array to be suspended, preventing external processors from performing random access to memory cells during this period. This behavior fundamentally conflicts with the memory usage model of the traditional von Neumann architecture, making it difficult to be compatible with mainstream x86 / ARM processor architectures.

[0121] Second, after the in-memory computation task is completed, the host processor needs to explicitly send a mode switching instruction to reconstruct the memory from computation mode to standard random access mode. This switching process requires operations such as disconnecting the computation interface and re-enabling the standard input / output buffer. During this period, the memory cannot respond to any access requests, resulting in an operational gap.

[0122] Third, the aforementioned architecture mandates serial switching between computation mode and random access mode. The host processor must wait for all operations in the current mode to complete before initiating a mode-switching instruction. This serial switching mechanism incurs significant performance overhead in applications that frequently alternate between memory computation and data access, leading to a decrease in effective memory bandwidth utilization. Furthermore, because mode switching involves reconfiguration of underlying hardware interfaces, it imposes non-standardized compatibility requirements on the operating system and drivers, further limiting its applicability in the general-purpose computing ecosystem.

[0123] Based on this, this application proposes an in-memory computing device that achieves efficient data processing by integrating computing units and dedicated data paths within the memory. Figure 6 This is a schematic diagram of the structure of an in-memory computing device provided in an embodiment of this application, as shown below. Figure 6 As shown.

[0124] The in-memory computing device includes a control logic unit 601 (i.e., the control unit in the above embodiment), mode registers 602, a column address decoder 603, a row address decoder 604, a refresh counter 605, memory banks 606 (rank, such as rank0 and rank1), sense amplifiers 607, an input / output buffer 608, a multiplexer (Mux) 609, read / write drivers 610, a PIM processing unit 611, a PIM computing data path 612, a random access data path 613, and a memory controller 614.

[0125] The control logic unit 601 is responsible for receiving and decoding commands from the external memory controller (such as the CS# chip select signal, CLK clock signal, CKE clock enable signal, etc.), and generating timing and control signals to coordinate the operation of all other modules. It can schedule data flow according to the current operating mode (set by the mode register 602). The mode register 602 can store device configuration and status information, such as the operating mode (random access mode or PIM calculation mode), timing parameters, etc. The control logic dynamically adjusts the behavior of each module based on its contents. The column address decoder 603 and row address decoder 604 are used to decode the input row and column addresses, activate a corresponding row of memory cells in the memory bank 606, connect the data therein to the sensing amplifier 607, and select one or more specific columns of data from the large amount of data in the activated row for read / write or calculation operations.

[0126] A refresh counter 605 initiates refresh operations at fixed intervals; the control logic suspends other accesses to perform the refresh. Memory bank 606 is the core memory array, divided into multiple independent memory banks 606, allowing parallel operation to improve bandwidth. Each memory bank 606 contains an array of memory cells and its local read / write circuitry. A sense amplifier 607, located at the edge of each memory bank 606, amplifies the weak electrical signals read from the memory cells and converts them into stable digital signals. An input / output buffer 608 serves as the interface between the device and the external data bus (DQ), responsible for temporarily storing, driving, and receiving data, and performing necessary level conversion and timing synchronization.

[0127] Multiplexer 609 receives data from one or more memory banks 606. This data can be a digital signal amplified and recovered by sense amplifier 607, and can issue instructions in response to scheduling by control logic unit 601. Specifically, in random access mode (standard memory mode), multiplexer 609 switches the data from upstream memory bank 606 to random access data path 613. In this mode, the storage system functions as a standard memory module, and the processor can read and write to it like ordinary memory. The computation data path and processing unit 611 are disconnected. In PIM computation mode (in-memory computation mode), multiplexer 609 switches the data from upstream memory bank 606 to computation data path. Data read from memory bank 606 is directly and at high speed transmitted to the dedicated processing unit 611 integrated within the memory for computation (such as matrix multiplication and addition). In this mode, the standard data path to the outside is suspended, and the processor cannot randomly access this storage area.

[0128] In PIM calculation mode, after the processing unit 611 finishes its calculation, it generates a calculation completion signal. This signal is sent to the control logic unit 601 via the control path. If the calculation instruction requires the result to be written back to memory, the control logic unit 601 will instruct the processing unit 611 to send the result data in reverse through the calculation data path (via the multiplexer 609). The data is finally written to the designated memory address 606 via the write driver 610. The processing unit 611 is the calculation unit in the above embodiment.

[0129] After confirming the completion of the calculation and the necessary result write-back operations, the control logic unit 601 prepares to switch the system from PIM calculation mode back to random access mode. Specifically, it first updates the status bit in the mode register 602, changing it from a value representing the calculation mode to a value representing the access mode. Based on the updated status of the mode register 602, the control logic unit 601 sends a control signal to the multiplexer 609. The multiplexer 609 then changes its internal connections, disconnecting the connection from the sense amplifier 607 to the calculation data path and reconnecting the connection from the sense amplifier 607 to the random access data path 613. At this point, the data flow is restored to the standard memory access path, and the calculation results can be transmitted back to the memory controller and processor through the standard memory access path.

[0130] The PIM processing unit 611 can be a dedicated computing unit integrated within the memory. It acquires data from the sense amplifier 607 via the PIM calculation data path 612 and performs specific calculation operations such as multiply-accumulate (MAC). The PIM calculation data path 612 can be a dedicated, high-speed internal data path connecting the sense amplifier 607 and the PIM processing unit 611. It is used to directly and with low latency transmit data from the memory 606 to the PIM processing unit 611 in PIM calculation mode.

[0131] Random access data path 613 can be a standard data path connecting the sense amplifier 607 and the I / O buffer. It is used for data exchange with an external processor (CPU / GPU) in conventional memory access mode. The memory controller can generate control commands and address signals sent to this PIM device, managing system access requests to memory and PIM computation task scheduling.

[0132] In this embodiment, the memory bank 609 connected to the multiplexer 609 supports two main workflows through the switching of modules such as the multiplexer 609: Process 1: Random access mode (standard memory mode).

[0133] An external processor initiates a read / write request, which the memory control unit translates into a standard memory command. The control logic decodes the command, activating the corresponding row and column of memory cell 606. Data is read from the memory cell, amplified by the sensing amplifier 607, and then routed by the multiplexer to the random access data path 613. Finally, it interacts with the external bus through the input / output buffer and read / write driver 610. At this time, the PIM calculation data path 612 is closed, and the PIM processing unit 611 goes into sleep mode.

[0134] Process 2, PIM Calculation Mode (In-Store Calculation Mode).

[0135] An external processor or memory controller issues a PIM calculation command. Control logic unit 601 configures the device to PIM mode. Subsequently, data in the activated memory 606 is read by the sensing amplifier 607 and, instead of being sent externally, is switched by the multiplexer to the PIM calculation data path 612, and directly transmitted to the PIM processing unit 611 for calculation via the read / write driver 610. The calculation result can be directly stored back in the original memory 606 or at a specified location. During this process, the I / O buffer and random access path are suspended, and external random access requests must wait.

[0136] In some embodiments, in addition to being divided into independent Ranks (such as Rank0 and Rank1), the storage bank 606 can also divide multiple Banks into the same BG.

[0137] By adopting the above technical solution, the overhead of mode switching is reduced through hardware isolation: when switching from computing mode back to access mode, there is no need to reset the entire storage array, only to switch the multiplexer and reconnect the standard control timing, thereby significantly reducing mode switching latency and improving overall efficiency under mixed loads.

[0138] In some embodiments, Figure 7 This is a flowchart of a data processing method provided in an embodiment of this application, such as... Figure 7 As shown, the method includes the following steps.

[0139] S701 retrieves request instructions sent by the processor to identify the type of command issued by the memory controller.

[0140] S702 checks the definition and configuration status of the mode register to determine the operating mode of the target memory region.

[0141] S703 determines whether the target of the current access request is the first storage partition.

[0142] If not: Execute S704 to access the specified Rank for regular random data access operations. The process can then terminate or return to wait for a new command.

[0143] If so: Enter the PIM calculation access process and continue executing S705.

[0144] S704 then accesses other storage partitions for random data access.

[0145] S705 reads the mode register to check if the first memory partition is currently idle.

[0146] If not: Execute S704.

[0147] If so: Continue executing S706.

[0148] S706, write the computing task instruction and the corresponding input data to the first storage partition.

[0149] S707 activates the power supply and related control signals of the first storage partition and connects its internal dedicated computing data path.

[0150] S708 reads the mode register to check whether the computation task in the first storage partition has been completed.

[0151] If not: Return to execute S704, during which time other storage partitions are accessed for random data access, thus realizing resource utilization during the waiting period.

[0152] If so: Continue executing S709.

[0153] S709 reads the calculated result data from the first storage partition via the data bus.

[0154] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The methods described above are similar to the device embodiments described above and have similar beneficial effects. For technical details not disclosed in the methods of this application, please refer to the descriptions of the device embodiments of this application for understanding.

[0155] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0156] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0157] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0158] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0159] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0160] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0161] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A data processing apparatus, comprising a processor and a memory, the memory including a control unit, a storage unit and a computing unit, the storage unit including a first storage partition and a second storage partition, each storage partition being used to perform different data operations; The control unit is configured to receive a first request instruction and a second request instruction sent by the processor, and select a corresponding storage partition from multiple storage partitions based on the request address and request operation in the request instruction. The first storage partition is used to execute data operations corresponding to the first request instruction. The first request instruction includes transferring data from the first storage partition to a computing unit in the memory, so that the computing unit can perform calculations on the data. The second storage partition is used to execute the data operation corresponding to the second request instruction, which includes the processor accessing data in the second storage partition.

2. The data processing apparatus according to claim 1, wherein the control unit receives the second request instruction simultaneously with the first request instruction.

3. The data processing apparatus according to claim 2, The control unit is configured to retrieve the corresponding computing context data from the first storage partition according to the first request instruction, and send it to the computing unit; The computing unit is configured to acquire the computing context data of the first storage partition and execute the computing operation corresponding to the first request instruction based on the computing context data to obtain the computing result.

4. The data processing apparatus according to claim 3, wherein the memory further includes a mode register; The control unit is configured to update the operating state in the mode register to a first state in response to the first request instruction sent by the processor. The mode register is used to configure the first storage partition into a computing mode based on the first state, so as to transmit the data of the first storage partition to the computing unit and perform calculations on the data by the computing unit.

5. The data processing apparatus according to claim 4, The control unit is further configured to update the working state in the mode register to the second state in response to the completion of the calculation by the computing unit; The mode register is further configured to set the first storage partition to an access mode based on the second state, so that the processor can access the data in the first storage partition.

6. The data processing apparatus according to claim 5, wherein the memory further comprises a multiplexer, wherein, One end of the multiplexer is connected to the first storage partition, and the other end of the multiplexer is connected to the computing unit and the input / output buffer of the first storage partition, respectively. The multiplexer is used for: When the working state in the mode register is the first state, the first data transmission path between the computing unit and the first storage partition is connected. When the working state in the mode register is the second state, the second data transmission path between the input / output buffer and the first storage partition is established, and the input / output buffer is a region that the processor can access.

7. The data processing apparatus according to claim 6, The computing unit is used to store the calculation result back to the first storage partition or the input / output buffer after the calculation is completed. The processor is configured to access the calculation results stored in the first storage partition or the input / output buffer via the second data transmission path.

8. The data processing apparatus according to any one of claims 1-7, The control unit is used to acquire the access data corresponding to the second request instruction and store the access data in the second storage partition; A second storage partition is provided for storing the access data, so that the processor can access the access data in the second storage partition.

9. The data processing apparatus according to any one of claims 1-7, wherein the memory further comprises a request queue; and the control unit is further configured to: The acquired request instructions are stored in the request queue; Dynamic scheduling is performed based on the request address, request operation, and status information of each request instruction in the request queue, so as to schedule different request instructions to the corresponding storage partitions for concurrent execution.

10. A data processing method applied to a memory in a data processing device, the memory being connected to a processor, the method comprising: Receive the request instruction sent by the processor; The request instruction includes a first request instruction and a second request instruction; Based on the request address and request operation in the request instruction, the corresponding storage partition is selected from multiple storage partitions; Execute the data operation corresponding to the first request instruction, wherein the first request instruction includes transferring the data of the first storage partition to the computing unit of the memory, so as to perform calculations on the data by the computing unit; The processor performs the data operation corresponding to the second request instruction, which includes the processor accessing data in the second storage partition.

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