Via hole pitch parameter calculation method, computer equipment, medium and product

Abstract

The invention relates to a via hole pitch parameter calculation method, computer equipment, a medium and a product. The calculation method comprises the following steps of: obtaining netlist structure information in the design of the super-large-scale integrated circuit, and filtering disconnected parts of a line net and parts where no current passes actually; starting from an input pin of each line network, searching for interconnection lines and via holes in contact with the line network, marking an initial node, recording the position of a contact point, and recursively searching for the associated interconnection lines or via holes until returning to an output pin of the line network; according to the central point positions of the interconnection lines and the via holes and the metal layer where the interconnection lines are located, the relative connection relation between the interconnection lines and the via holes is determined, and a tree-shaped network structure is constructed; constructing a virtual interconnection line; and performing bidirectional traversal on any intermediate node of the tree network structure, traversing all nodes in the path upwards and downwards along the tree network structure, and calculating the sum of the distances among all via hole nodes in the traversal path to obtain the via hole pitch.

Description

Technical Field

[0001] This invention relates to the field of very large-scale integrated circuit design technology, and in particular to a method for calculating via spacing parameters, a computer device, a medium, and a product. Background Technology

[0002] Electromigration, a phenomenon discovered in the field of microelectronics in the 1950s, refers to the movement of metal atoms caused by the flow of electrons. In conductors with high current density, the flow of electrons generates momentum. When this momentum acts on metal atoms, it can cause the metal atoms to detach from the metal surface and move, resulting in an uneven surface on the originally smooth metal wire and causing permanent damage.

[0003] As the integration density of VLSI chips continues to increase during the design process, the interconnects used become thinner, narrower, and more delicate, leading to a corresponding increase in current density. Under higher current densities, the metal atoms in the interconnects migrate along the direction of electron movement, causing voids or whiskers to appear in certain parts of the wires, resulting in open circuits or short circuits and causing chip malfunction. This phenomenon is known as electromigration. With the continuous advancement of modern technology and the increasing complexity of circuit designs, improvements in wiring techniques mean that the net between two pins may consist of interconnects of different widths and lengths, or interconnects from different metal layers or through different vias. The situations requiring analysis are more complex, and accurately calculating the maximum mean square current density that the interconnect can pass through is a crucial step in checking for electromigration effects.

[0004] In the design of very large-scale integrated circuit (VLSI) chips, via spacing is the distance between vias at both ends of an interconnect. It is also an important parameter in the calculation rules for the maximum mean square current density. As the connection methods between interconnects have become more diversified with the improvement of wiring technology, the calculation of via spacing has also become more complex and needs to adapt to more new situations. When performing electromigration analysis of vias and interconnects in the circuit design process under advanced process nodes, if the net is directly divided according to vias, the interconnect branches that do not pass through vias may be ignored. If the net is divided according to interconnects, the influence between some interconnects may be ignored, resulting in inaccurate calculation results. In subsequent inspections, incorrect results are obtained, which in turn affects the reliability of the product. Summary of the Invention

[0005] To address the technical problem of poor accuracy in electromigration analysis of vias and interconnects during traditional circuit design, this invention provides a method for calculating via spacing parameters, a computer device, a medium, and a product.

[0006] The solution to the technical problem of this invention is to provide a via spacing parameter calculation method, applied to very large-scale integrated circuit (VLSI) design, comprising the following steps: obtaining netlist structure information in VLSI design, including the position and size of nets, filtering out disconnected parts and parts where no current actually flows through the nets; starting from the input pin of each net, searching for interconnects and vias in contact with that net, marking the initial node tag=0 and recording the corresponding contact point position, recursively searching for associated interconnects or vias until returning to the output pin of the net; based on the center point position of the interconnect and the via and the interconnect... The metal layer at the location determines the relative connection relationship between interconnects and vias. During recursive search, each time an interconnect undergoes a branch, turn, pass through a via, or change in width, the node tag is incremented by 1 and its coordinates are recorded. The nodes are prioritized according to their tag values ​​from smallest to largest to construct a tree network structure. When the connection position between an interconnect, via, and pin deviates from the center point, a virtual interconnect is constructed. A bidirectional traversal is performed from any intermediate node in the tree network structure, traversing all nodes along the path upwards and downwards until the nearest via node is found. The sum of the distances between all via nodes in the traversal path is calculated to obtain the via spacing.

[0007] Preferably, when the connection positions between interconnects and vias, between vias, and between pins are deviated from the center point of the interconnect, via, or pin, a virtual interconnect is constructed; the width of the virtual interconnect is equal to the width of the geometric rectangular area where the via is located.

[0008] Preferably, when the connection position between the interconnect, via, and pin is off-center, a virtual interconnect is constructed, including the following steps: when the interconnect does not contact the center point of the via, and the direction of the geometric rectangular area where the interconnect and the via are located is inconsistent, a virtual interconnect with endpoints at the center point of the via and the endpoint of the interconnect is constructed, and the interconnect is adjusted so that its endpoint is aligned with the center point of the via; when the interconnect does not contact the center point of the via, and the direction of the interconnect and the geometric rectangular area where the via are located is consistent, a virtual interconnect with endpoints at the center point of the via and the midpoint of the boundary of the geometric rectangular area where the via is located is constructed, and the interconnect is adjusted so that its endpoint contacts the midpoint of the boundary of the via; when there is direct contact between vias or between a via and a pin, and the center points do not coincide, two virtual interconnects are constructed, with endpoints at the center point of the via or pin and the midpoint of the boundary of the geometric rectangular area where the via or pin is located, respectively. If the distance between the boundary of the geometric rectangular area where the via is located and the center point of the via is greater than the horizontal projection distance between the center points of the vias, then the endpoints of the virtual interconnects are the projection points of the two via center points in the horizontal direction.

[0009] Preferably, the via spacing is obtained by bidirectional traversal from any intermediate node of the tree network structure, traversing all nodes along the upward and downward paths of the tree network structure until the nearest via node is found, and calculating the sum of the distances between all nodes in the traversal path. This includes the following steps: providing any intermediate node of the tree network structure, traversing upward along the tree network structure from the intermediate node, and selecting the via node closest to the intermediate node; if no via node is found among all nodes traversed upward, traversing downward along the tree network structure from the intermediate node, and selecting the via node closest to the intermediate node; calculating the sum of the distances between the intermediate node and its nearest via node as the via spacing of the interconnect segment.

[0010] Preferably, when constructing a tree network structure, if the intersection point between two interconnects has no branching, no turning, or no width change, the corresponding two interconnects are merged into one interconnect, and the via spacing is calculated together.

[0011] Preferably, after calculating the sum of distances between all nodes in the traversal path to obtain the via spacing, the method further includes the following step: providing an electron migration rule, and calculating the maximum mean square current density J of the interconnect based on the electron migration rule. max And J max =n× , n is the rated multiplier determined based on the via spacing, w is the width of the interconnect, delta_T is the operating ambient temperature of the external receiver, and C1, C2, C3, C4, C5, and C6 are a set of circuit design parameters for the external receiver.

[0012] Preferably, the storage content within each node of the tree network structure includes the location coordinates of the corresponding interconnect, via and / or pin, tag value, and associated interconnect information.

[0013] The present invention also provides a computer device, including a storage device, a processor, and a computer program stored in the storage device, wherein the processor executes the computer program to implement the steps of the above-described via spacing parameter calculation method.

[0014] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described via spacing parameter calculation method.

[0015] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described via spacing parameter calculation method.

[0016] Compared with the prior art, the via spacing parameter calculation method, computer equipment, medium, and product provided by the present invention have the following advantages: 1. This invention provides a via spacing parameter calculation method that can be applied to very large-scale integrated circuit design. It reduces redundant calculations by filtering out disconnected wires that do not actually carry current, marks nodes based on the key features of interconnects and constructs a tree network structure, combines virtual interconnects to correct connections that are off-center, and performs bidirectional traversal to locate and search for the nearest via node, thereby achieving accurate via spacing calculation in complex wiring scenarios and adapting to the design requirements of very large-scale integrated circuits.

[0017] 2. In the via spacing parameter calculation method provided in the embodiments of the present invention, by clarifying the triggering conditions for constructing virtual interconnects, limiting the width standard of virtual interconnects, and unifying the parameter basis for connection deviation correction, the consistency and accuracy of via spacing calculation are further ensured.

[0018] 3. In the via spacing parameter calculation method provided in the embodiments of the present invention, specific virtual interconnect construction rules are formulated for different scenarios where the connection position between interconnects, vias and pins deviates from the center point. This comprehensively covers the center point deviation between interconnects and vias, between vias and vias, and between vias and pins, avoiding calculation errors caused by connection deviations and improving the calculation accuracy of via spacing.

[0019] 4. In the via spacing parameter calculation method provided in the embodiments of the present invention, by refining the logic of bidirectional traversal and the selection rules of the via node closest to the intermediate node, the target node can be located quickly and accurately, and the shortest interconnect line with both the starting point and the ending point being vias can be obtained, ensuring that the via spacing calculation result is efficient and reliable, so as to facilitate the subsequent calculation of the maximum mean square current density.

[0020] 5. In the via spacing parameter calculation method provided in the embodiments of the present invention, interconnects without key feature changes are merged, so that two interconnects with no bifurcation, no turning or width change at the intersection can be merged when calculating the via spacing, which simplifies the tree network structure, reduces redundant calculation steps and improves the calculation efficiency of via spacing parameters.

[0021] 6. In the via spacing parameter calculation method provided in the embodiments of the present invention, the via spacing parameter is combined with the electron migration rule, and J is applied. max =n× The calculation formula yields the maximum mean square current density, which can provide complete data support for chip electromigration reliability analysis.

[0022] 7. In the via spacing parameter calculation method provided in the embodiments of the present invention, by clarifying the content stored in the nodes of the tree network structure, sufficient data foundation is provided for traversing the nodes of the tree network structure and calculating the via spacing, ensuring that the calculation process and the final result are traceable.

[0023] 8. The present invention also provides a computer device that has the same beneficial effects as the above-described via spacing parameter calculation method, and will not be described in detail here.

[0024] 9. The present invention also provides a computer-readable storage medium that has the same beneficial effects as the above-described via spacing parameter calculation method, and will not be described in detail here.

[0025] 10. The present invention also provides a computer program product that has the same beneficial effects as the above-described via spacing parameter calculation method, which will not be elaborated here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart illustrating steps S1 to S5 in the via spacing parameter calculation method provided in this embodiment of the invention.

[0028] Figure 2 This is a flowchart illustrating steps S51 to S53 in the via spacing parameter calculation method provided in this embodiment of the invention.

[0029] Figure 3 This is a flowchart illustrating steps S41 to S43 of the via spacing parameter calculation method provided in this embodiment of the invention.

[0030] Figure 4 This is a schematic diagram of constructing virtual interconnects in the via spacing parameter calculation method provided in this embodiment of the invention. Figure 1 .

[0031] Figure 5 This is a schematic diagram of constructing virtual interconnects in the via spacing parameter calculation method provided in this embodiment of the invention. Figure 2 .

[0032] Figure 6 This is a schematic diagram of constructing virtual interconnects in the via spacing parameter calculation method provided in this embodiment of the invention. Figure 3 .

[0033] Figure 7 This is a flowchart illustrating steps S1 to S6 in the via spacing parameter calculation method provided in this embodiment of the invention.

[0034] Figure 8This is a schematic diagram of the tree network structure constructed in the via spacing parameter calculation method provided in this embodiment of the invention. Figure 1 .

[0035] Figure 9 This is a schematic diagram of the tree network structure constructed in the via spacing parameter calculation method provided in this embodiment of the invention. Figure 2 .

[0036] Figure 10 This is a schematic diagram of the tree network structure constructed in the via spacing parameter calculation method provided in this embodiment of the invention. Figure 3 .

[0037] Figure 11 This is a schematic diagram of the framework of a computer device provided in an embodiment of the present invention.

[0038] Figure 12 This is a schematic diagram of the framework of a computer-readable storage medium provided in an embodiment of the present invention.

[0039] Figure 13 This is a schematic diagram of the framework of a computer program product provided in an embodiment of the present invention.

[0040] Explanation of reference numerals in the attached diagram: 1. Computer equipment; 11. Storage device; 12. Processor; 2. Computer-readable storage medium; 3. Computer program products; 100. Computer program. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0043] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0044] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0045] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0046] Please see Figure 1 This invention provides a method for calculating via spacing parameters, applicable to very large-scale integrated circuit design, comprising the following steps: S1: Obtain the netlist structure information in VLSI design. The netlist structure information includes the location and size of the nets and filters out the broken parts and parts that do not actually have current flowing through them. S2: Starting from the input pin of each net, search for interconnects and vias that are in contact with the net, mark the initial node tag=0 and record the corresponding contact point position, recursively search for associated interconnects or vias until returning to the output pin of the net to end; S3: Based on the center point of the interconnect and the via and the metal layer where the interconnect is located, determine the relative connection relationship between the interconnect and the via. During the recursive search, each time the interconnect undergoes a branch, turn, pass through a via, or change in width, the node tag is incremented by 1 and the coordinates are recorded. The priority is sorted according to the tag value from smallest to largest to construct a tree network structure. S4: When the connection position between interconnects, vias and pins is off-center, a virtual interconnect is constructed; S5: Perform a bidirectional traversal from any intermediate node in the tree network structure, traversing all nodes along the path upwards and downwards until the nearest via node is found. Calculate the sum of the distances between all via nodes in the traversal path to obtain the via spacing.

[0047] The via spacing parameter calculation method provided in this invention reduces redundant calculations by filtering out disconnected wires that do not actually carry current. It marks nodes based on the key features of interconnects and constructs a tree network structure. It combines virtual interconnects to correct connections that are off-center and uses bidirectional traversal to locate and search for the nearest via node. This enables accurate calculation of via spacing in complex wiring scenarios, adapts to the design requirements of very large-scale integrated circuits, and improves the accuracy of electromigration analysis in the design process of very large-scale integrated circuit chips.

[0048] Specifically, in step S1, the netlist structure information in the current VLSI design is read. The netlist structure information stores data such as the position coordinates and size of the nets. This data is stored in the form of Verilog files and can be designed in the routing stage of EDA (Electronic Design Automation) tools. Then, the broken parts in the nets are filtered out. In each part of the semiconductor devices contained in each net, the parts that do not actually carry current are searched and filtered out. It can be understood that in the embodiments of the present invention, some interconnects are found to form loops, and in this case, no current flows through them, which need to be distinguished from the broken nets.

[0049] In this embodiment of the invention, after executing step S1 to obtain netlist structure information and before executing step S2 to search for interconnects and vias in contact with the net, the disconnected parts and the parts in which no current actually flows through the net are filtered in sequence. That is, the disconnected parts in the net are filtered first, and then the parts in the net in which no current actually flows through are filtered.

[0050] Furthermore, in steps S2 and S3, starting from the input pin of each net, the search is performed on the interconnects and vias that directly contact it within the net. The corresponding initial node is marked as tag=0, and the current contact point position is recorded. The search is performed recursively on the associated interconnects or vias. If the search cannot continue for the last interconnect or via, the search is reversed to the previous interconnect or via until the search is resumed at the output pin. Here, interconnect refers to a metal wire, and contact point position refers to the position where the interconnect contacts the net and the via contacts the net. Starting from the input pin of the net, the first interconnect or via that contacts the net is marked as the initial node tag=0. Subsequently, the search continues within the range of the net for the previous interconnect or via connected to the interconnect or via. The interconnects and vias found later are prioritized and then marked with the corresponding tags in sequence. The current coordinates are saved and added to the tree network structure.

[0051] The recursive search method in this embodiment of the invention determines the relative connection relationship between the interconnect and the via by judging the center point position of the interconnect and the metal layer where the interconnect is located. The basic principle followed is: if the interconnect branches or turns, or passes through a via, a corresponding node record should be established; in particular, if the width of the interconnect changes, since the interconnect width is an important parameter required in the electron migration analysis method to calculate the maximum mean square current density, a new node should also be established for recording.

[0052] In step S3, priority sorting refers to the actual current flow direction in the network. The sorting should be based on the actual current flow direction and cannot be reversed. If there are several branches in the actual current flow direction, all interconnects and vias of one branch should be arranged and assigned tag values ​​before the remaining branches are arranged in sequence and assigned larger tag values. The order of branches generated at the same contact point is not distinguished.

[0053] In step S4, when the connection positions between interconnects and vias, between vias, and between pins deviate from the center point of the interconnect, via, or pin, a virtual interconnect is constructed. In the via spacing parameter calculation method provided in this embodiment of the invention, virtual interconnects are added to address situations where the connection positions between certain interconnects, vias, or pins deviate from the center point. By clarifying the triggering conditions for constructing virtual interconnects, defining the width standard of virtual interconnects, and unifying the parameter basis for connection deviation correction, the consistency and accuracy of via spacing calculation are further ensured.

[0054] It should be noted that the width of the virtual interconnect is equal to the width of the geometric rectangle containing the via. By constructing virtual interconnects, the electron migration effect of vias or pins can be better simulated, avoiding the neglect of the maximum current density limit of some vias or pins, thus obtaining accurate results for via spacing. If this step is skipped, the maximum current density limit will be ignored, affecting the accuracy of the calculation.

[0055] Please see Figure 2 In step S5, a bidirectional traversal is performed from any intermediate node of the tree network structure, traversing all nodes along the path upwards and downwards until the nearest via node is found. The sum of the distances between all nodes in the traversal path is calculated to obtain the via spacing, including the following steps: S51: Provide any intermediate node of the tree network structure, start from the intermediate node and traverse upwards along the tree network structure. If there is a via node among all the nodes traversed upwards, select the via node that is closest to the intermediate node. S52: If there are no via nodes among all nodes traversed upwards, start from the middle node and traverse downwards along the tree network structure to select the via node closest to the middle node. S53: Calculate the sum of the distances between the intermediate node and its nearest via node, and use it as the via spacing for this interconnect segment.

[0056] In the via spacing parameter calculation method provided in this embodiment of the invention, by refining the logic of bidirectional traversal and the selection rules of the via node closest to the intermediate node, the target node can be located quickly and accurately, and the shortest interconnect line with both the starting point and the ending point being vias can be obtained, ensuring that the via spacing calculation result is efficient and reliable, so as to facilitate the subsequent calculation of the maximum mean square current density.

[0057] Specifically, in step S51, any intermediate node of the tree network structure is selected as the current node. Starting from the current node, the search nodes are traversed upward along the tree network structure until the node corresponding to a certain via is found, so that the distances between all nodes traversed upward can be added together later.

[0058] In step S52, if the current node's parent node does not correspond to a specific via, and the current node also has other child nodes, then it is necessary to traverse downwards to search for the corresponding via node. The node ultimately selected should be the closest via node. Starting from the current node, traverse downwards along the tree network structure until a node corresponding to a specific via is found, which facilitates the summation of the distances between all nodes traversed upwards. It should be noted that if the current node has multiple via nodes among its child nodes, the closest child node should be selected to obtain the shortest interconnect with both the starting and ending points being vias.

[0059] In step S53, by calculating the sum of the distances between the intermediate node and the nearest via node, the via spacing parameter corresponding to the shortest interconnect can be calculated, so as to calculate the maximum mean square current density by introducing electron migration rules.

[0060] For further details, please refer to Figure 3 When the connection position between interconnects, vias, and pins is off-center, a virtual interconnect is constructed, including the following steps: S41: When the interconnect line does not contact the center point of the via and the direction of the geometric rectangular area where the interconnect line and the via are not consistent, construct a virtual interconnect line. The endpoints of the virtual interconnect line are the center point of the via and the endpoints of the interconnect line. Adjust the interconnect line so that its endpoints are aligned with the center point of the via. S42: When the interconnect does not contact the center point of the via and the direction of the interconnect and the geometric rectangular area where the via is located are consistent, construct a virtual interconnect. The endpoint of the virtual interconnect is the midpoint between the center point of the via and the boundary of the geometric rectangular area where the via is located, and adjust the interconnect so that its endpoint contacts the midpoint of the via boundary. S43: When there is direct contact between vias or between a via and a pin, and the center points do not coincide, two virtual interconnects are constructed. The endpoints of the virtual interconnects are the center point of the via or pin and the midpoint of the boundary of the geometric rectangular area where the via or pin is located. If the distance between the boundary of the geometric rectangular area where the via is located and the center point of the via is greater than the horizontal projection distance between the center points of the vias, then the endpoints of the virtual interconnects are the projection points of the two via center points in the horizontal direction.

[0061] The via spacing parameter calculation method provided in this embodiment of the invention formulates specific virtual interconnect construction rules for different scenarios where the connection position between interconnects, vias and pins deviates from the center point. This comprehensively covers the center point deviation between interconnects and vias, between vias and vias, and between vias and pins, avoiding calculation errors caused by connection deviations and improving the calculation accuracy of via spacing.

[0062] Specifically, in step S41, when the interconnect line does not contact the center position of the via and the direction of the geometric rectangular area where the interconnect line and the via are not consistent, a virtual interconnect line is constructed, the endpoint of which is the center point of the via and the endpoint of the interconnect line. The width of the virtual interconnect line is equal to the width of the geometric rectangular area where the via is located. At the same time, the endpoint of the original interconnect line should be adjusted to be aligned with the center point of the via.

[0063] like Figure 4As shown, the horizontally placed rectangle is a via, and the intersection of the diagonals of the rectangle is the center point of the via. The vertically placed rectangle is an interconnect. When the interconnect and the via satisfy the conditions of step S41 above, the constructed virtual interconnect is the red bold line in the figure. One end of the virtual interconnect is the center point of the via, and the other end is the midpoint of the boundary of the rectangular area. Then, the original interconnect is shortened to the blue bold line in the figure and adjusted so that its endpoint is aligned with the center point of the via.

[0064] In step S42, when the interconnect line does not contact the center of the via and the direction of the geometric rectangular area where the interconnect line and the via are aligned, a virtual interconnect line is constructed. Its endpoint is the midpoint between the center point of the via and the boundary of the geometric rectangular area where the via is located. The width of the virtual interconnect line is equal to the width of the geometric rectangular area where the via is located. At the same time, the endpoint of the original interconnect line should be adjusted to contact the midpoint of the via boundary.

[0065] like Figure 5 As shown, two rectangles are placed in the same direction, representing vias and interconnects respectively. The intersection of the diagonals of the larger rectangle is the center point of the via. When the interconnect and the via satisfy the conditions of step S42 above, the constructed virtual interconnect is the red bold line in the figure. One end of the virtual interconnect is the center point of the via, and the other end is the midpoint of the boundary of the rectangular area. Then, the original interconnect is shortened to the blue bold line in the figure and adjusted so that its endpoint contacts the midpoint of the via boundary.

[0066] In step S43, when there is direct contact between vias and between a via and a pin, and the center points do not coincide, two virtual interconnects are constructed. One endpoint of each virtual interconnect is the center point of the corresponding via or pin, and the other endpoint is the midpoint of the boundary of the geometric rectangular area where the corresponding via or pin is located. In particular, if the distance between the boundary of the geometric rectangular area where the via is located and the center point of the via is greater than the horizontal projection distance between the center points of the vias, then the endpoint of the virtual interconnect is the projection point of the two center points of the vias in the horizontal direction.

[0067] like Figure 6 As shown, two rectangles are placed in the same direction, indicating direct contact between vias or between vias and pins. The intersection of the diagonals of the rectangles is the center point of the via or pin. When the conditions of step S43 above are met between vias / vias and pins, the endpoint of the constructed virtual interconnect is the center point of the corresponding via or pin, and the other endpoint is the midpoint of the boundary of the geometric rectangle area where the corresponding via or pin is located. The two virtual interconnects are the red bold line and the yellow bold line in the figure, respectively. It should be noted that when the center points of vias and vias and pins coincide, the coordinates of the intersection of the diagonals of the rectangles coincide completely.

[0068] In some embodiments, when constructing a tree network structure, if the intersection of two interconnects has no branching, no turning, or no width change, the corresponding two interconnects are merged into one interconnect, and the via spacing is calculated together.

[0069] In the via spacing parameter calculation method provided in this embodiment of the invention, interconnects without key feature changes are merged, so that two interconnects with no bifurcation, no turning, or no width change at their intersection can be merged when calculating the via spacing, which simplifies the tree network structure, reduces redundant calculation steps, and improves the calculation efficiency of via spacing parameters.

[0070] Please see Figure 7 After calculating the sum of distances between all nodes in the traversal path to obtain the via spacing, the following steps are also included: S6: Provides electron migration rules, and calculates the maximum mean square current density J of interconnects based on these rules. max And J max =n× , n is the rated multiplier determined based on the via spacing, w is the width of the interconnect, delta_T is the operating ambient temperature of the external receiver, and C1, C2, C3, C4, C5, and C6 are a set of circuit design parameters for the external receiver.

[0071] In the via spacing parameter calculation method provided in this embodiment of the invention, steps S1 to S5 can calculate the via spacing parameter corresponding to the shortest interconnect line, and step S6 combines the via spacing parameter with the electron migration rule, applying J max =n× The calculation formula yields the maximum mean square current density, providing complete data support for chip electromigration reliability analysis. Specifically, the via spacing parameter and the maximum mean square current density J of the interconnect are calculated sequentially. max Afterwards, the performance indicators such as reliability and accuracy of electromigration effect in the VLSI design can be directly analyzed, and the actual current value of the interconnect segment can be calculated to compare the magnitude of the actual current value.

[0072] Understandably, root mean square current density (RMS) refers to the effective value of current, a metric for measuring the magnitude of a current signal and reflecting the impact of signal changes on the system; among which, The calculated result is a rough value of the maximum mean square current density. The via parameters calculated in step S5 will be expressed as a piecewise function to obtain a rated multiplier n. This rated multiplier n, multiplied by the rough value of the maximum mean square current density, yields the correction value corresponding to the maximum mean square current density, i.e., J. maxThe value is a correction made to the maximum mean square current density.

[0073] In this embodiment of the invention, the via spacing refers to the space between vias, that is, the sum of the lengths of the interconnects between the vias. The rated multiplier n can be determined based on the value of the via spacing, and the piecewise function of the rated multiplier n will vary depending on the metal layer and / or process node. As a first optional implementation method: ① When the via spacing is ≥9.8μm, n=1.0; ② When 9.8μm > via spacing > 2.94μm, n = 1.05; ③ When the value of 2.94μm ≥ via spacing > 0.98μm, n = 1.3; ④ When 0.98μm ≥ via spacing > 0.294μm, n = 2.0; ⑤ When the via spacing is ≤0.294μm, n=2.2; The first implementation described above can be used to calculate the rated rate n of the 12nm process and Metal 1 layer.

[0074] As a second alternative implementation: ① When the via spacing is ≥10μm, n=1.0; ② When the value of 10μm > via spacing > 3μm, n = 1.05; ③ When the value of 3μm ≥ via spacing > 1μm, n = 1.3; ④ When the value of 1μm ≥ via spacing > 0.3μm, n = 2.0; ⑤ When the via spacing is ≤0.3μm, n=2.2; The second embodiment described above can be used to calculate the rated rate n of the 7nm process and Metal 1 layer. The two embodiments are only used to illustrate the changes in the value of the rated rate n and are not intended to limit the present invention.

[0075] It should be noted that w is the width of the interconnect, referring to the width of the metal wire. The temperature value of delta_T can be input through external commands. C1, C2, C3, C4, C5, and C6 can be a set of parameters provided by the chip manufacturer. There can be multiple sets of different circuit design parameters for different metal layers. A single parameter C1, C2, C3, C4, C5, or C6 does not have actual physical meaning.

[0076] In some embodiments, the storage content within each node of the tree network structure includes the location coordinates of the corresponding interconnect, via and / or pin, tag value, and associated interconnect information.

[0077] The via spacing parameter calculation method provided in this embodiment of the invention provides a sufficient data foundation for traversing the nodes of the tree network structure and calculating the via spacing by clarifying the content stored in the nodes of the tree network structure, thus ensuring that the calculation process and the final result are traceable.

[0078] The following will further explain the inventive purpose, technical solution and technical effect of the via spacing parameter calculation method with reference to exemplary embodiments. It should be noted that the exemplary embodiments are only used to explain the present invention and do not limit the scope of application of the present invention.

[0079] like Figure 8 As shown, an example of the first net is given here to facilitate understanding the steps of the via spacing parameter calculation method. The cross-shaped squares in the figure represent vias. The first via 2p1 is searched from the input pin of the net, and then vias 2h1 and 2a1 are searched through the interconnects. 2a1 is searched to the right to the input pin. The position coordinates of the pin and the above three vias are recorded, and each is assigned a tag value. The record of the upper part of the net is shown in Table 1.

[0080]

[0081] Table 1 Furthermore, since no other interconnects or vias in contact with the pin can be found at the pin, the search proceeds backward along interconnect 2a1-Cell 1 to 2a1, and continues downward to 2h2 and another pin, resulting in the record of the lower half of the net as shown in Table 2.

[0082]

[0083] Table 2 Each interconnecting line constituting the network can be used to calculate the maximum mean square current density, and the line length is the straight-line distance between its own recorded endpoint and the corresponding previous endpoint.

[0084] like Figure 9 As shown, a second example of a mesh is given here, which can also yield similar results, the difference being that... Figure 9 Although there is no via at the interconnect intersection 2d1, the interconnect has branched, so 2d1 still needs to be recorded as a node in the tree network structure. The interconnect intersection between the interconnect intersection 2d1 and the via 2h4 does not have any change in the direction or width of the interconnect, so it does not need to be recorded in the tree network structure. The two interconnects here can be merged into one interconnect, and the via spacing parameter is also merged and calculated. The final net record is shown in Table 3.

[0085]

[0086] Table 3 like Figure 10 As shown, here is an example of the third net. Although interconnects 2b1-2b2 are not connected to other interconnects 2h6-2b1 and 2b2-2h7 through vias and there is no change in direction, the width of interconnects 2b1-2b2 is significantly different from that of other interconnects. Even though the connection method of interconnects 2b1-2b2 is exactly the same as that of normal wires, it needs to be listed separately in the calculation of the maximum mean square current density. Therefore, 2b1 and 2b2 need to be recorded as nodes in the tree network structure. The final net record is shown in Table 4.

[0087]

[0088] Table 4 Please see Figure 11 The present invention also provides a computer device 1, including a storage 11, a processor 12, and a computer program 100 stored on the storage 11. The processor 12 executes the computer program 100 to implement the steps of the above-described via spacing parameter calculation method.

[0089] It is understood that when the computer device 1 provided in the embodiments of the present invention is running, the via spacing parameter calculation method described in the above embodiments can be implemented when the processor 12 executes the computer program 100. The computer device 1 provided in the embodiments of the present invention has the same beneficial effects as the via spacing parameter calculation method provided in the above embodiments.

[0090] In some embodiments, computer device 1 is a computer device applied in the field of very large-scale integrated circuit design technology, including but not limited to the construction of tree network structures, the construction of virtual interconnects, and the calculation of via spacing and the maximum mean square current density. These will not be elaborated upon here. Theoretically, all method steps related to the technical solution of this invention can be implemented through the control of computer device 1, and the relevant parameters can also be adjusted accordingly through computer device 1. These relevant parameters include, but are not limited to, the maximum mean square current density J of the interconnects. max Each node in the tree network structure stores parameters such as the coordinates of interconnects, vias and / or pins, tag values, and associated interconnect information.

[0091] In some embodiments of the present invention, the processor 12 provided is a general-purpose processor, which is a microprocessor or any conventional processor, such as a central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, which can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of this application.

[0092] In some embodiments, the method steps disclosed in this application may be executed by a hardware processor, or by a combination of hardware and software modules in the processor.

[0093] Please see Figure 12 The present invention also provides a computer-readable storage medium 2, on which a computer program 100 is stored. When the computer program 100 is executed by a processor, it implements the steps of the above-described via spacing parameter calculation method.

[0094] It is understood that the computer-readable storage medium 2 provided in the embodiments of the present invention stores a computer program 100, and the computer program 100 can be called by a processor to execute the via spacing parameter calculation method described in the above embodiments. The computer-readable storage medium 2 provided in the embodiments of the present invention has the same beneficial effects as the via spacing parameter calculation method provided in the above embodiments.

[0095] Specifically, the computer-readable storage medium 2 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, disk, optical disk, etc.

[0096] In some embodiments, the computer-readable storage medium 2 includes a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs, and modules.

[0097] Specifically, the computer-readable storage medium 2 provided in this embodiment of the invention has storage space for computer programs 100 that perform any of the method steps in the above-described via spacing parameter calculation method. These programs can be read from or written to one or more computer program products. In some embodiments, the computer program 100 can be compressed in an appropriate form.

[0098] Please see Figure 13The present invention also provides a computer program product 3, including a computer program 100, which implements the steps of the above-described via spacing parameter calculation method when executed by a processor.

[0099] It is understood that the computer program product 3 provided in the embodiments of the present invention includes a computer program 100, and the computer program 100 can be called by a processor to execute the via spacing parameter calculation method described in the above embodiments, which will not be repeated here.

[0100] The foregoing provides a detailed description of the via spacing parameter calculation method, computer equipment, medium, and product disclosed in the embodiments of the present invention. Specific examples are used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for calculating via spacing parameters, applied to very large-scale integrated circuit design, characterized in that, Includes the following steps: To obtain netlist structure information in VLSI design, including the location and size of nets, and to filter out broken parts and parts through which no current actually flows in the nets. Starting from the input pin of each net, search for interconnects and vias that are in contact with that net, mark the initial node tag=0 and record the corresponding contact point position, recursively search for associated interconnects or vias until returning to the output pin of the net to end; Based on the center point of the interconnect and the via and the metal layer where the interconnect is located, the relative connection relationship between the interconnect and the via is determined. During the recursive search, the node tag is incremented by 1 and the coordinates are recorded every time the interconnect undergoes a branch, turn, pass through a via or the width changes. The priority is sorted according to the tag value from small to large to construct a tree network structure. When the connection between interconnects, vias, and pins is off-center, a virtual interconnect is constructed. Starting from any intermediate node in the tree network structure, a bidirectional traversal is performed, traversing all nodes along the path upwards and downwards until the nearest via node is found. The sum of the distances between all via nodes in the traversal path is then calculated to obtain the via spacing.

2. The via spacing parameter calculation method as described in claim 1, characterized in that: When the connection position between an interconnect and a via, between two vias, and between a pin and a via is off-center from the center point of the interconnect, via, or pin, a virtual interconnect is constructed. The width of the virtual interconnect is equal to the width of the geometric rectangle containing the via.

3. The via spacing parameter calculation method as described in claim 2, characterized in that, When the connection between interconnects, vias, and pins is off-center, virtual interconnects are constructed, including the following steps: When the interconnect does not contact the center point of the via, and the orientation of the geometric rectangular area where the interconnect and the via are not the same, construct a virtual interconnect with the endpoints of the via center point and the interconnect endpoints, and adjust the interconnect so that its endpoints are aligned with the center point of the via. When the interconnect does not contact the center point of the via, and the direction of the interconnect and the geometric rectangular region where the via is located are consistent, construct a virtual interconnect with the endpoints of the center point of the via and the midpoint of the boundary of the geometric rectangular region where the via is located, and adjust the interconnect until its endpoints contact the midpoint of the via boundary. When there is direct contact between vias or between a via and a pin, and the center points do not coincide, two virtual interconnects are constructed, with the endpoints being the center point of the via or pin and the midpoint of the boundary of the geometric rectangle containing the via or pin, respectively. If the distance between the boundary of the geometric rectangle containing the via and the center point of the via is greater than the horizontal projection distance between the center points of the vias, then the endpoints of the virtual interconnects are the projection points of the two via center points in the horizontal direction.

4. The via spacing parameter calculation method as described in claim 1, characterized in that, Starting from any intermediate node in the tree network structure, a bidirectional traversal is performed, visiting all nodes along the path upwards and downwards until the nearest via node is found. The sum of the distances between all nodes along the traversal path is then calculated to obtain the via spacing. This process includes the following steps: Given any intermediate node in the tree network structure, start from the intermediate node and traverse upwards along the tree network structure to select the via node that is closest to the intermediate node; If no via node is found among all nodes traversed upwards, start from the middle node and traverse downwards along the tree structure to select the via node closest to the middle node. Calculate the sum of the distances between the intermediate node and its nearest via node, and use this as the via spacing for that interconnect segment.

5. The via spacing parameter calculation method as described in claim 1, characterized in that: When constructing a tree network structure, if the intersection of two interconnects has no branching, no turning, or no width change, the corresponding two interconnects are merged into one interconnect, and the via spacing is calculated together.

6. The via spacing parameter calculation method as described in claim 1, characterized in that, After calculating the sum of distances between all nodes in the traversal path to obtain the via spacing, the following steps are also included: Provide electron migration rules, and calculate the maximum mean square current density J of the interconnect based on the electron migration rules. max And J max =n× , n is the rated multiplier determined based on the via spacing, w is the width of the interconnect, delta_T is the operating ambient temperature of the external receiver, and C1, C2, C3, C4, C5, and C6 are a set of circuit design parameters for the external receiver.

7. The via spacing parameter calculation method as described in claim 1, characterized in that: The storage content within each node of the tree network structure includes the location coordinates of the corresponding interconnect, via and / or pin, tag value, and associated interconnect information.

8. A computer device, characterized in that, It includes a storage device, a processor, and a computer program stored on the storage device, wherein the processor executes the computer program to implement the steps of the via spacing parameter calculation method as described in any one of claims 1-7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the via spacing parameter calculation method as described in any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the via spacing parameter calculation method as described in any one of claims 1-7.

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