Automatic construction method of analog circuit 3DIC-RC test case
By using parameterized scenario description scripts and pre-bound process design rules, 3DIC-RC test cases are automatically constructed, solving the problems of low efficiency and data distortion in 3DIC design and achieving efficient and accurate test layout generation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU YIFANG DIGITAL INNOVATION TECHNOLOGY CO LTD
- Filing Date
- 2026-02-05
- Publication Date
- 2026-05-19
AI Technical Summary
Existing technologies are inefficient in constructing RC test layouts for 3DIC design, human error leads to distorted test data, and it is difficult to adapt to customized requirements in multiple scenarios. Traditional methods cannot meet the needs of high-precision analysis and verification.
Using a parameterized scenario description script, TSV, HB array, and GuardRing geometry are generated. Through pre-bound target process design rules, test circuit layout is automatically constructed and verified to output standard format files.
It enables the rapid generation of complex 3DIC test structure layouts, reduces design violations, improves data design efficiency, ensures accuracy and process compliance, and supports the flexible construction of diverse RC test scenarios.
Smart Images
Figure CN122065764A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of EDA (Electronic Design Automation), specifically relating to an automated method for constructing test cases for analog circuit 3DIC-RC (Three-dimensional integrated circuit-resistor-capacitor). Background Technology
[0002] With the continuous shrinking of semiconductor process nodes and the rapid development of 3DIC technology, chip integration density and system complexity have significantly increased. The RC parasitic effect of physical layout has become one of the key factors affecting circuit performance, signal integrity, and power consumption. In 3DIC design, the parasitic parameters introduced by multilayer interconnect structures such as TSV (Through Silicon Via), HB (Hybrid Bonding), and BRDL (Redistribution Layer) are more complex and difficult to predict. Traditional RC extraction and testing methods based on two-dimensional planes can no longer meet the requirements of high-precision analysis and verification, which increases the difficulty of developing and testing EDA software.
[0003] Manual layout construction using EDA tools allows designers to draw metal interconnect patterns, TSV vertical via structures, and hybrid bonding layer regions layer by layer according to RC test requirements. They also manually define the interconnect relationships and verification geometry rules between layers, ultimately exporting the required layout data. This method is primarily used for RC testing of simple 3DIC analog circuits with limited testing scenarios, such as basic interconnect testing with a single TSV and two layers of metal.
[0004] Currently, the design of test structure layouts required for RC parameter extraction relies heavily on manual drawing and experience-based adjustments. This not only results in a lengthy generation cycle for a single test structure, typically requiring several days, but also introduces unavoidable human biases, such as alignment errors between metal layers, mismatched TSV vertical interconnect ports, or inaccurate HB contact area definitions. These subtle geometric deviations are amplified in subsequent parasitic parameter extraction, leading to distorted resistance and capacitance values that fail to accurately reflect the true electrical characteristics after manufacturing, thus rendering circuit simulation and performance verification meaningless. Secondly, existing methods suffer from extremely poor scalability and reusability. Manually drawn layout data is highly specific and cannot flexibly adapt to the rapidly evolving complex scenarios in 3DIC, such as asymmetric multilayer metal stacks, TSV array combinations with different pitches and aspect ratios, and customized test patterns for hybrid bonding layers in ultra-high-density interconnects. Whenever a process node is upgraded, interconnect materials change, or new test dimension requirements arise, a complete redesign is almost always necessary, resulting in enormous repetitive work and a lack of knowledge accumulation.
[0005] Existing technologies are insufficient in addressing the multi-physics domain and multi-level coupling effects of 3DIC. Most treat layout construction as an isolated geometric generation task, failing to form an effective closed loop with circuit performance indicators, process design rules, and subsequent extraction and simulation processes. This disconnect from design intent and manufacturing constraints means that the generated test layout may miss critical parasitic effects or contain redundant structures, wasting test chip area. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides an automated method for constructing 3DIC-RC test cases for analog circuits.
[0007] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides an automated method for constructing 3DIC-RC test cases for analog circuits, the automated construction method comprising: Receive parameterized scenario description script; the parameterized scenario description script includes TSV configuration parameters, HB array configuration parameters and GuardRing configuration parameters; Based on the parameterized scenario description script and the pre-bound target process design rules, the TSV geometry, HB array geometry and GuardRing geometry are generated. The TSV geometry, the HB array geometry, and the GuardRing geometry are each encapsulated as parameterized units. Instantiate each parameterized unit in the top-level layout and arrange them according to the parameterized scenario description script to construct the test circuit layout; Verify the test circuit layout and output a standard format file.
[0008] Secondly, the present invention provides an automated construction device for 3DIC-RC test cases of analog circuits, the automated construction device comprising: The receiving module is used to receive the parameterized scene description script; the parameterized scene description script includes TSV configuration parameters, HB array configuration parameters and GuardRing configuration parameters; The generation module is used to generate TSV geometry, HB array geometry and GuardRing geometry based on the parameterized scenario description script and pre-bound target process design rules. An encapsulation module is used to encapsulate the TSV geometry, the HB array geometry, and the GuardRing geometry into parameterized units, respectively. The building module is used to instantiate each parameterized unit in the top-level layout and arrange them according to the parameterized scenario description script to build the test circuit layout; The verification module is used to verify the test circuit layout and output a standard format file.
[0009] Thirdly, the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; When a processor executes a computer program stored in memory, it implements the steps described in the method for automatically constructing any of the above-mentioned analog circuit 3DIC-RC test cases.
[0010] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in the automated construction method of any of the above-described analog circuit 3DIC-RC test cases.
[0011] This invention provides an automated method for constructing 3DIC-RC test cases for analog circuits. Using a parameterized scenario description script, it can generate complex 3DIC test structure layouts that would otherwise require days of manual drawing within minutes. Through pre-bound target process design rules, the parameterized modeling and automatic placement processes can refer to process constraints in real time, reducing design violations from the outset. The parameterized scenario description script includes TSV configuration parameters, HB array configuration parameters, and GuardRing configuration parameters, thus supporting a rapid construction system for diverse RC test scenarios. By modifying the parameterized script, test circuit layouts with different TSV shapes, HB array densities, and guard ring configurations can be flexibly generated, meeting the wide range of needs for EDA tool testing and process characteristic analysis. This not only greatly improves the data design efficiency for testing and verifying RC extraction algorithms in EDA software, but also ensures high data accuracy, process compliance, and flexibility in handling different test scenarios through parameterized driving and automatic rule checking.
[0012] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description
[0013] Figure 1 This is a flowchart illustrating an automated construction method for 3DIC-RC test cases of analog circuits provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the TSV geometry provided in an embodiment of the present invention; Figure 3This is a schematic diagram of the aligned HB array geometry provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the interleaved HB array geometry provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the GuardRing geometry of vertically stacked multilayer metals provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the GuardRing geometry surrounded by multiple metal layers provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of example layout data provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation
[0014] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0015] To address the problems of low efficiency, data distortion due to human error, and difficulty in adapting to customized requirements across multiple scenarios in existing 3DIC-RC test layout construction methods, this invention provides an automated method for constructing 3DIC-RC test cases for analog circuits. (See also...) Figure 1 , Figure 1 This is a flowchart illustrating an automated method for constructing 3DIC-RC test cases for analog circuits according to an embodiment of the present invention, specifically including the following steps: Step S101: Receive the parameterized scenario description script; the parameterized scenario description script includes TSV configuration parameters, HB array configuration parameters and GuardRing configuration parameters.
[0016] In this embodiment of the invention, the parameterized scenario description script can refer to a structured data configuration file or a program written in a specific domain scripting language, used to fully define the generation requirements of the 3DIC-RC test structure.
[0017] The TSV configuration parameters define the various geometric and physical characteristics of the TSV. The HB array configuration parameters define the array layout scheme of the HB connection points. The GuardRing configuration parameters define the metal ring structure surrounding the TSV for isolation and protection.
[0018] Step S102: Based on the parameterized scenario description script and the pre-bound target process design rules, generate the TSV geometry, HB array geometry and GuardRing geometry.
[0019] In this embodiment of the invention, a basic design environment bound to the process can be established under the target process node through pre-bound target process design rules. The specific process is as follows: First, create a process binding library. Using a general layout drawing tool as the design platform, create a new layout library within a specific PDK (Process Design Library) environment and bind it to the target process layer mapping file.
[0020] For example, in the Cadence Virtuoso design platform, the PDK for the target process node can be loaded. Then, the script uses the dbCreateLib() function to create a new layout library (the name can be customized), and binds this library to the layermap file provided by the process.
[0021] Then, according to the 3DIC process design rules, the required layer structures are predefined and configured in the script file. The required layer structures may include: ① TSV-related layers: defining via conductors, insulating layers, barrier layers, etc. ② HB-related layers: defining microbumps, connection pads, dielectric layers, etc. ③ GuardRing: defining the metal layer structure for isolation and protection.
[0022] For example, according to the process design manual, in the skill script configuration area used to drive automation, the critical process layers required for subsequent modeling are predefined and configured using the list() function. These include TSV-related layers, HB-related layers, and metal guard ring layers.
[0023] Finally, set up design rule references: associate the process's DRC (Design Rule) file with the script file to reduce violations in automated design.
[0024] Based on this initialization, graphical parametric modeling is performed.
[0025] In this embodiment of the invention, a TSV geometry is generated based on a parameterized scenario description script and pre-bound target process design rules, including: Read TSV configuration parameters from the parameterized scene description script; TSV configuration parameters include type identifier indicators and size parameters; the type identifier indicator is used to specify the geometry of the TSV; Based on the type identifier, the corresponding geometry generation function is called and combined with the size parameters to dynamically generate the TSV through-hole structure, thus forming the TSV geometry.
[0026] During the TSV structure parameterization generation process, the type identifier in the TSV configuration parameters in the script is read to automatically generate TSV profile geometry of different shapes to match diverse test requirements. In this embodiment of the invention, through holes of various shapes are preset, such as regular octagonal through holes, which can optimize manufacturing process tolerance and ensure the uniformity of parasitic parameter distribution; if the test scenario has strict requirements for capacitance symmetry, circular through holes can be generated; in addition, it also supports the generation of elliptical through holes with different ratios of major and minor axes, which are specifically used to simulate the changes in electrical characteristics under anisotropic process stress or specific electric field distribution.
[0027] In this embodiment of the invention, the corresponding geometry generation function is invoked to dynamically generate the TSV via structure according to the type identifier indication, including: When the type identifier indicates an octagon, the corresponding geometry generation function is called to generate an octagonal TSV through-hole structure based on the size parameters; When the type identifier indicates a circle, the corresponding geometry generation function is called to generate a circular TSV through-hole structure based on the size parameters; When the type identifier indicates an ellipse, the corresponding geometry generation function is called to generate an elliptical TSV through-hole structure based on the size parameters.
[0028] Specifically, based on the type identifier, the script can automatically call different geometry generation functions as follows: When the type identifier is specified as "octagon", the corresponding geometry generation function is called to generate an octagonal TSV through-hole structure with a circumscribed circle diameter of the given size parameter.
[0029] When the type identifier indicates "circle", the corresponding geometry generation function is called to generate a circular TSV through-hole structure based on the diameter given by the size parameters.
[0030] When the type identifier indicates "ellipse", the corresponding geometry generation function is called to generate an elliptical TSV through-hole structure based on the major axis and minor axis values in the dimension parameters.
[0031] See Figure 2 , Figure 2 This is a schematic diagram of the TSV geometry provided in the embodiment of the present invention. The complete TSV geometry includes multiple layers, such as the BCB dielectric layer and the BMT bump metal layer. After obtaining the parameter configuration of the TSV via structure, the insulating layer, barrier layer and other polygons are automatically generated by offsetting outward according to the pre-bound target process design rules. These layers are then aligned and stacked in the vertical direction to form a complete TSV geometry.
[0032] In this embodiment of the invention, based on a parameterized scenario description script and pre-bound target process design rules, an HB array geometry is generated, including: Read the HB array configuration parameters from the parameterized scene description script. The HB array configuration parameters include the layout mode identifier, the X-axis / Y-axis spacing, and the row and column values. The layout mode identifier is used to specify the array mode of the HB array. The HB array geometry is generated by determining the position of each HB connection point in the HB array based on the HB array configuration parameters.
[0033] In this embodiment of the invention, there are two array modes for the HB array: an aligned array and an interleaved array. An aligned array refers to the HB connection points being evenly distributed in the X and Y directions; an interleaved array is a staggered arrangement of HB connection points in adjacent rows / columns to improve connection density or uniformity.
[0034] In this embodiment of the invention, the script generates a hybrid bonding point array within a specified area based on the layout mode identifier, X-axis / Y-axis spacing, and row and column values in the HB array configuration parameters.
[0035] In this embodiment of the invention, the HB array geometry is generated by determining the position of each HB connection point in the HB array based on the HB array configuration parameters, including: When the layout mode identifier indicates alignment, an HB array geometry is generated based on the HB array configuration parameters, in which all HB connection points are evenly distributed in the X and Y directions. When the layout mode identifier indicates staggered, the HB array geometry is generated with the HB connection points of adjacent rows and columns staggered, based on the HB array configuration parameters.
[0036] See Figure 3 , Figure 3 This is a schematic diagram of the aligned HB array geometry provided in an embodiment of the present invention. When the layout mode identifier is indicated as "aligned", an array in which all HB connection points are uniformly distributed in the X and Y directions is generated. The spacing between HB connection points is controlled by the spacing in the X-axis direction and the spacing in the Y-axis direction. See Figure 4 , Figure 4 This is a schematic diagram of the geometric structure of the staggered HB array provided in the embodiment of the present invention. When the layout mode identifier indicates "staggered", an array is generated in which the HB connection points of adjacent rows and columns are staggered. The positions of the HB connection points of adjacent rows and columns are staggered by half a spacing to improve the connection density or distribution uniformity. During the generation process, the starting position, offset, and step value of the array can be adjusted according to the HB array configuration parameters, and the pre-bound target process design rules can be referenced in real time to ensure that the size, spacing, and arrangement of the HB connection points meet the manufacturing constraints and avoid geometric violations.
[0037] In this embodiment of the invention, a GuardRing geometry is generated based on a parameterized scene description script and pre-bound target process design rules, including: Read the GuardRing configuration parameters from the parameterized scene description script; the GuardRing configuration parameters include Boolean parameters, structure type identifier indication, ring width parameters, spacing parameters with TSV edges, and a list of metal layers used; Determine whether to generate GuardRing geometry based on Boolean parameters; If so, the corresponding GuardRing geometry is generated based on the GuardRing configuration parameters, according to the structure type identifier.
[0038] In this embodiment of the invention, Boolean parameters are typically used to represent logical values. They have only two basic forms: True and False. When True, a GuardRing geometry is generated; when False, no GuardRing geometry is generated.
[0039] In this embodiment of the invention, the corresponding GuardRing geometry is generated based on GuardRing configuration parameters according to the structure type identifier, including: When the structure type identifier indicates "stacked", multiple concentric ring structures with the same geometric dimensions are generated with the TSV geometry as the center, resulting in the GuardRing geometry. When the structure type identifier is specified as "concentric", multiple concentric ring structures with different geometric sizes are generated with the TSV geometry as the center, resulting in the GuardRing geometry.
[0040] See Figure 5 , Figure 5 This is a schematic diagram of the GuardRing geometry of a multi-layered vertically stacked metal structure provided in an embodiment of the present invention. The script calculates the inner and outer boundaries of the guard ring with the TSV geometry as the center, and generates a closed guard ring with the same potential on each specified metal layer. The number of metal layers is a configurable parameter variable, and all metal layers are set to the same potential.
[0041] See Figure 6 , Figure 6This is a schematic diagram of the multi-metal-layered GuardRing geometry provided in an embodiment of the present invention. The script generates at least two concentric rings. The inner ring is connected to the GND network through a contact hole, while the outer ring remains floating. Continuous, closed metal rings of a specific shape are generated by setting script parameters. The spacing between the two rings strictly follows the ring spacing parameters and DRC rules.
[0042] During the generation process, the distance between the GuardRing and the nearest TSV edge is strictly controlled according to the spacing parameters, and the pre-bound target process design rules are referenced in real time to ensure that the ring width, spacing and layer relationship meet the manufacturing constraints, so as to effectively suppress noise coupling and latch-up effect.
[0043] Step S103: The TSV geometry, HB array geometry, and GuardRing geometry are encapsulated as parameterized units.
[0044] In this embodiment of the invention, the generated underlying geometry can be encapsulated into a reusable and easily managed high-level P-Cell (parameterized unit).
[0045] First, parameterized units are created. The TSV geometry, HB array geometry, and GuardRing geometry are encapsulated as independent parameterized units: “PCELL_TSV”, “PCELL_HB_ARRAY”, and “PCELL_GUARDRING”, respectively.
[0046] These P-Cells have explicit parameter interfaces. After module encapsulation, the P-Cells can be directly called via skill scripts to implement top-level data construction.
[0047] Specifically, the TSV geometry, HB array geometry, and GuardRing geometry are encapsulated to form a reusable module that can be flexibly called and configured at higher levels. Its core parameter set covers three aspects: First, TSV parameters, including type identifiers for switching between octagonal, circular, or elliptical shapes, axis length (or diameter) that determines the size, and stacking information describing the vertical stacking structure; second, HB array cell parameters, including layout modes that specify alignment or staggered arrangement, X / Y direction spacing and offset that control the density of connection points, and the number of rows and columns that define the array size; and third, GuardRing parameters, including an enable switch that controls whether the array is generated, the width of the metal ring used to suppress noise, and the guard spacing with the TSV edge.
[0048] Then, perform basic DRC (Design Rule) checks on the generated P-Cell to ensure its usability as an independent module.
[0049] Specifically, three P-cells are instantiated in the Virtuoso environment and assigned different typical parameter combinations. The DRC rule check of the parameter cells is performed using the calibre tool to check the minimum width of the metal, spacing, etc., to verify the geometric correctness and basic compliance of each cell as an independent module.
[0050] Step S104: Instantiate each parameterized unit in the top-level layout and arrange them according to the parameterized scenario description script to construct the test circuit layout.
[0051] In this embodiment of the invention, according to design requirements, the P-Cell is parameterized in the script, the corresponding cell structure is instantiated in the top-level layout, and then the precise arrangement of the design cells is completed in the specified position, which can build a large-scale test circuit layout.
[0052] In this embodiment of the invention, the top-level layout script describes a test structure containing approximately 5 million HB-aligned arrays of 2236×2236 pixels, 2×2 TSV vias corresponding to four circuit ports, and each TSV surrounded by a guard ring. The script will perform the following operations: First, the “PCELL_TSV” cell is called to generate 2×2 TSV vias of different shapes, and a “PCELL_GUARDRING” cell is instantiated for each TSV. The TSV vias are located at the center of the guard ring.
[0053] Next, set the HB array parameters: HB is a rectangle with a size of 0.5um × 0.5um, and the X and Y axis step spacing is 0.5um.
[0054] Based on the layout pattern identifier, the HB array cells are arranged on a large scale: When the layout mode identifier indicates alignment, HB connection points are evenly arranged according to the spacing parameters of the X-axis and Y-axis directions, with the starting coordinates as the reference. When the layout mode identifier indicates staggered, the HB connection points of adjacent rows or columns are staggered based on the starting coordinates and the offset parameter is used. In the top-level layout, call the parameterized scene description script to instantiate all parameterized units sequentially from position (0,0) in the manner described above, thus constructing a complete test layout.
[0055] Step S105: Verify the test circuit layout and output a standard format file.
[0056] In this embodiment of the invention, final verification is performed based on the test circuit layout, and a standard format file is automatically output.
[0057] The script automatically calls DRC (Design Rule Check) tools, such as Calibre, to perform design rule checks on the overall design layout, ensuring it fully complies with the manufacturing requirements of the target process. If violations are found, users can choose to perform simple routing manually or use a script file to call a software interface for automatic routing.
[0058] After successful verification, the final layout file is automatically generated according to predefined standardized naming rules, typically in the format of "Process Node_Test Structure Name_Date". The file is exported in industry-standard formats such as GDSII or OASIS and can be directly used for subsequent RC parasitic parameter extraction, simulation verification, and tape-out processes. The generated complete RC test layout data is as follows: Figure 7 As shown, Figure 7 This is a schematic diagram of example layout data provided in an embodiment of the present invention.
[0059] In this embodiment of the invention, a parameterized scenario description script can generate complex 3DIC test structure layouts that would otherwise require several days of manual drawing within minutes. Through pre-bound target process design rules, the parameterized modeling and automatic placement processes can refer to process constraints in real time, reducing design violations from the outset. The parameterized scenario description script includes TSV configuration parameters, HB array configuration parameters, and GuardRing configuration parameters, thus supporting a rapid construction system for diverse RC test scenarios. By modifying the parameterized script, test circuit layouts with different TSV shapes, HB array densities, and guard ring configurations can be flexibly generated, meeting the wide range of needs for EDA tool testing and process characteristic analysis. This not only greatly improves the data design efficiency for testing and verification of RC extraction algorithms in EDA software, but also ensures high data accuracy, process compliance, and flexibility in handling different test scenarios through parameterized driving and automatic rule checking.
[0060] This invention provides an automated generation method for 3DIC-RC test structures based on parametric scripts. By defining test requirements through high-level parametric scripts, it achieves an end-to-end automated process from process initialization and geometric modeling to layout integration, generating physical layout data that conforms to process rules. Through techniques such as constructing a parametric template library for RC test scenarios, automatically generating collaborative interconnects between TSV-metal layers and hybrid bonding layers, and automatically verifying layout geometric rules and interconnect relationships, it achieves rapid and accurate automated construction of RC test layout data in multiple scenarios. This significantly improves the construction efficiency of 3DIC analog circuit RC test layout data and reduces test deviations caused by human error. It is particularly suitable for efficiently, accurately, and automatically generating key test structure layout data for parasitic parameter extraction, signal integrity analysis, and performance verification in advanced 3DIC processes, representing a key technical link in the design and test co-optimization of the EDA toolchain.
[0061] Based on the same inventive concept, embodiments of the present invention also provide an automated construction device for 3DIC-RC test cases of analog circuits, the automated construction device comprising: The receiving module is used to receive the parameterized scene description script; the parameterized scene description script includes TSV configuration parameters, HB array configuration parameters and GuardRing configuration parameters; The generation module is used to generate TSV geometry, HB array geometry and GuardRing geometry based on the parameterized scenario description script and pre-bound target process design rules. An encapsulation module is used to encapsulate the TSV geometry, the HB array geometry, and the GuardRing geometry into parameterized units, respectively. The building module is used to instantiate each parameterized unit in the top-level layout and arrange them according to the parameterized scenario description script to build the test circuit layout; The verification module is used to verify the test circuit layout and output a standard format file.
[0062] In this embodiment of the invention, a parameterized scenario description script can generate complex 3DIC test structure layouts that would otherwise require several days of manual drawing within minutes. Through pre-bound target process design rules, the parameterized modeling and automatic placement processes can refer to process constraints in real time, reducing design violations from the outset. The parameterized scenario description script includes TSV configuration parameters, HB array configuration parameters, and GuardRing configuration parameters, thus supporting a rapid construction system for diverse RC test scenarios. By modifying the parameterized script, test circuit layouts with different TSV shapes, HB array densities, and guard ring configurations can be flexibly generated, meeting the wide range of needs for EDA tool testing and process characteristic analysis. This not only greatly improves the data design efficiency for testing and verification of RC extraction algorithms in EDA software, but also ensures high data accuracy, process compliance, and flexibility in handling different test scenarios through parameterized driving and automatic rule checking.
[0063] This invention also provides an electronic device, such as... Figure 8 As shown, it includes a processor 801, a communication interface 802, a memory 803, and a communication bus 804. The processor 801, communication interface 802, and memory 803 communicate with each other via the communication bus 804. Memory 803 is used to store computer programs; The processor 801, when executing the program stored in the memory 803, implements the method steps for automatically constructing any of the above-mentioned analog circuit 3DIC-RC test cases.
[0064] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus.
[0065] The communication interface is used for communication between the aforementioned electronic devices and other devices.
[0066] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.
[0067] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0068] The present invention also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the method steps for automatically constructing any of the above-described analog circuit 3DIC-RC test cases.
[0069] Optionally, the computer-readable storage medium may be non-volatile memory (NVM), such as at least one disk storage device.
[0070] Optionally, the aforementioned computer-readable storage medium may also be at least one storage device located remotely from the aforementioned processor.
[0071] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the steps of the method described in the automated construction method of any of the above analog circuit 3DIC-RC test cases.
[0072] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.
[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0074] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.
[0075] The method provided in this invention can be applied to electronic devices. Specifically, the electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc. No limitation is made herein; any electronic device that can implement this invention falls within the protection scope of this invention.
[0076] For the embodiments of the device / electronic device / storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and relevant parts can be referred to in the description of the method embodiments.
[0077] It should be noted that the device, electronic device, and storage medium in the embodiments of the present invention are respectively devices, electronic devices, and storage media that apply the above-mentioned automated construction method for 3DIC-RC test cases of analog circuits. Therefore, all embodiments of the above-mentioned automated construction method for 3DIC-RC test cases of analog circuits are applicable to the device, electronic device, and storage medium, and can achieve the same or similar beneficial effects.
[0078] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. An automated method for constructing 3DIC-RC test cases for analog circuits, characterized in that, The automated construction method includes: Receive parameterized scenario description script; the parameterized scenario description script includes TSV configuration parameters, HB array configuration parameters and GuardRing configuration parameters; Based on the parameterized scenario description script and the pre-bound target process design rules, the TSV geometry, HB array geometry and GuardRing geometry are generated. The TSV geometry, the HB array geometry, and the GuardRing geometry are each encapsulated as parameterized units. Instantiate each parameterized unit in the top-level layout and arrange them according to the parameterized scenario description script to construct the test circuit layout; Verify the test circuit layout and output a standard format file.
2. The automated construction method according to claim 1, characterized in that, Based on the parameterized scenario description script and the pre-bound target process design rules, a TSV geometry is generated, including: Read TSV configuration parameters from the parameterized scene description script; the TSV configuration parameters include a type identifier indicator and size parameters; the type identifier indicator is used to specify the geometry of the TSV; Based on the type identifier, the corresponding geometry generation function is invoked and combined with the size parameters to dynamically generate the TSV through-hole structure, thereby forming the TSV geometry.
3. The automated construction method according to claim 2, characterized in that, Based on the type identifier, the corresponding geometry generation function is invoked to dynamically generate the TSV via structure, including: When the type identifier indicates an octagon, the corresponding geometry generation function is called to generate an octagonal TSV through-hole structure based on the size parameters; When the type identifier indicates a circle, the corresponding geometry generation function is called to generate a circular TSV through-hole structure based on the size parameters; When the type identifier indicates an ellipse, the corresponding geometry generation function is invoked to generate an elliptical TSV through-hole structure based on the size parameters.
4. The automated construction method according to claim 1, characterized in that, Based on the parameterized scenario description script and pre-bound target process design rules, the HB array geometry is generated, including: Read HB array configuration parameters from the parameterized scene description script. The HB array configuration parameters include layout mode identifier indication, X-axis / Y-axis spacing and row and column values, wherein the layout mode identifier indication is used to specify the array mode of the HB array. The HB array geometry is generated by determining the position of each HB connection point in the HB array based on the HB array configuration parameters.
5. The automated construction method according to claim 4, characterized in that, Based on the HB array configuration parameters, the position of each HB connection point in the HB array is determined to generate the HB array geometry, including: When the layout mode identifier indicates alignment, an HB array geometry is generated based on the HB array configuration parameters, in which all HB connection points are evenly distributed in the X and Y directions. When the layout mode identifier indicates staggered, an HB array geometry is generated based on the HB array configuration parameters, in which the HB connection points of adjacent rows and columns are staggered.
6. The automated construction method according to claim 1, characterized in that, Based on the parameterized scene description script and the pre-bound target process design rules, the GuardRing geometry is generated, including: Read the GuardRing configuration parameters from the parameterized scene description script; the GuardRing configuration parameters include Boolean parameters, structure type identifier indication, ring width parameters, spacing parameters with TSV edges, and a list of metal layers used; Determine whether to generate the GuardRing geometry based on the Boolean parameter; If so, the corresponding GuardRing geometry is generated based on the GuardRing configuration parameters, according to the structure type identifier.
7. The automated construction method according to claim 6, characterized in that, Based on the structure type identifier, the corresponding GuardRing geometry is generated according to the GuardRing configuration parameters, including: When the structure type identifier indicates stacked, multiple concentric ring structures with the same geometric size are generated with the TSV geometry as the center to obtain the GuardRing geometry. When the structure type identifier indicates a wraparound type, multiple concentric ring structures with different geometric sizes are generated around the TSV geometry to obtain the GuardRing geometry.
8. An automated construction device for 3DIC-RC test cases of analog circuits, characterized in that, The automated construction device includes: The receiving module is used to receive the parameterized scene description script; the parameterized scene description script includes TSV configuration parameters, HB array configuration parameters and GuardRing configuration parameters; The generation module is used to generate TSV geometry, HB array geometry and GuardRing geometry based on the parameterized scenario description script and pre-bound target process design rules. An encapsulation module is used to encapsulate the TSV geometry, the HB array geometry, and the GuardRing geometry into parameterized units, respectively. The building module is used to instantiate each parameterized unit in the top-level layout and arrange them according to the parameterized scenario description script to build the test circuit layout; The verification module is used to verify the test circuit layout and output a standard format file.
9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a computer program stored in memory, implements an automated construction method for an analog circuit 3DIC-RC test case as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements an automated construction method for 3DIC-RC test cases of an analog circuit as described in any one of claims 1-7.