EMIR analysis-oriented multi-dimensional circuit data enhancement method and device
By using a multi-dimensional circuit data augmentation method, basic circuit code is generated using a large language model and circuit feature library, and data augmentation is performed on the logic and physical sides. This solves the problems of high labor costs and single dimension in existing technologies, and achieves efficient generation of multi-dimensional EMIR analysis data.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU YIFANG DIGITAL INNOVATION TECHNOLOGY CO LTD
- Filing Date
- 2026-02-05
- Publication Date
- 2026-05-19
AI Technical Summary
Existing data construction methods for EMIR analysis are costly, inefficient, lack feature-oriented features, and struggle to generate multi-dimensional, specialized data. Furthermore, existing enhancement methods are limited in scope, making it difficult to achieve targeted enhancement and ensure the physical realization of the circuit.
A multi-dimensional circuit data augmentation method is adopted. Through a large language model and circuit feature library, basic circuit code that meets the requirements of circuit augmentation is generated, and data augmentation on the logic side and/or physical side is performed, including parallel architecture, introduction of redundant logic, physical timing constraints and power network planning, to generate diverse enhanced EMIR index data.
While ensuring circuit functional equivalence and physical feasibility, diverse logic variant circuit data are generated, improving data generation efficiency, achieving targeted enhancement and feature orientation, and meeting the needs of EMIR analysis.
Smart Images
Figure CN122065766A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design automation, specifically relating to a multi-dimensional circuit data enhancement method and apparatus for EMIR (Electromigration and IR Drop) analysis. Background Technology
[0002] As semiconductor manufacturing processes continue to evolve to the nanometer scale, EMIR analysis is crucial for the functional correctness and long-term reliability of chips. Current EDA (Electronic Design Automation) tools require a large amount of high-coverage use case data for functional testing in electromigration and voltage drop scenarios to verify the correctness of software tools in logic-physical interaction scenarios. However, the currently available publicly available data is severely insufficient and suffers from problems such as limited scenario coverage and a lack of physical data files.
[0003] Currently, the main data construction and data augmentation methods in the field of EMIR analysis are as follows: In terms of test case construction, the main process is as follows: For the specific functional points to be tested, manually select physical unit devices and define connection relationships, manually modify the netlist file, then manually define power networks and complete the placement and routing work in the physical design tool, export the layout and other files, and then use the tool to perform electromigration and voltage drop analysis. If violations are found, manually modify them again and run the above process again.
[0004] In terms of data augmentation techniques, current methods generally only make single-point modifications at the logical or physical layers, resulting in a limited scope of change. For example, they may repeatedly instantiate simple logical templates to generate large-scale but structurally homogeneous test cases, or add random perturbations.
[0005] Current data construction methods are labor-intensive and inefficient, failing to quickly generate large amounts of specialized analytical data. Furthermore, existing enhancement methods are dimensionally limited, lack feature-driven approaches, and are difficult to design specifically for EMIR functionalities or generate dedicated data.
[0006] In the field of EMIR, existing circuit enhancement methods are relatively one-dimensional, focusing only on logic code or physical layout. Most methods employ logic mutation or the addition of random perturbations, making it difficult to achieve targeted enhancement and ensure the physical implementation of the circuit. This often leads to violations and makes it difficult to extract effective EMIR metrics for verification using EDA tools. Summary of the Invention
[0007] To address the aforementioned problems in the prior art, this invention provides a multidimensional circuit data enhancement method and apparatus for EMIR analysis.
[0008] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a multidimensional circuit data enhancement method for EMIR analysis, the method comprising: S1. Determine the circuit enhancement target requirements for the target EMIR function points; S2. Based on the circuit enhancement target requirements, select corresponding circuit structure features from the pre-built circuit feature library and combine them to obtain combined features that meet the circuit enhancement target requirements; S3. Obtain the basic circuit code that meets the circuit enhancement target requirements through the large language model and the combined features; S4. After performing logic-side and / or physical-side data enhancement on the basic circuit code according to the circuit enhancement target requirements, perform physical implementation and index extraction in sequence to obtain enhanced EMIR index data. S5. If the enhanced EMIR index data does not meet the circuit enhancement target requirements, return to S3 for iterative enhancement; otherwise, output the enhanced EMIR index data as the final enhanced EMIR data to analyze and optimize the target EMIR function points.
[0009] Optionally, S3 includes: The combined features are converted into model prompt words and input into the large language model to obtain the initial circuit code; The initial circuit code is verified for execution logic and syntax, and invalid code is filtered out to obtain the filtered circuit code. When the filtered circuit code does not meet the structural complexity condition, the model prompt words are adjusted and the filtered circuit code is regenerated until the filtered circuit code meets the structural complexity condition, thus obtaining the basic circuit code.
[0010] Optionally, the process of performing logic-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: The architecture of the basic circuit code is converted into a parallel architecture to obtain the parallel architecture circuit code; Redundant logic is introduced into the non-critical paths, redundant signal paths, and internal control paths of the basic circuit code to obtain redundant circuit code. Modify the clock gating unit of the control circuit switch control logic in the basic circuit code to obtain circuit code with enhanced control logic; The parallel architecture circuit code, the redundant circuit code, and the control logic enhancement circuit code are physically implemented to obtain the enhanced EMIR index data.
[0011] Optionally, the process of performing physical-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: Dynamic physical timing constraints are applied to the design constraint file corresponding to the basic circuit code to obtain constraint parameters; Based on the process library file corresponding to the basic circuit code, cell layout hotspot enhancement is performed to obtain the enhanced layout. Parametric power network planning is performed based on the process library file corresponding to the basic circuit code to obtain the planned power network. The enhanced EMIR index data is obtained by physically implementing the system based on the constraint parameters, the enhanced layout, and the planned power network.
[0012] Optionally, the process of performing logic-side and physical-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: The architecture of the basic circuit code is converted into a parallel architecture to obtain the parallel architecture circuit code; Redundant logic is introduced into the non-critical paths, redundant signal paths, and internal control paths of the basic circuit code to obtain redundant circuit code. Modify the clock gating unit of the control circuit switch control logic in the basic circuit code to obtain circuit code with enhanced control logic; Dynamic physical timing constraints are applied to the design constraint file corresponding to the basic circuit code to obtain constraint parameters; Based on the process library file corresponding to the basic circuit code, cell layout hotspot enhancement is performed to obtain the enhanced layout. Parametric power network planning is performed based on the process library file corresponding to the basic circuit code to obtain the planned power network. The parallel architecture circuit code, the redundant circuit code, the control logic enhancement circuit code, the constraint parameters, the enhanced layout, and the planned power network are physically implemented to obtain the enhanced EMIR index data.
[0013] Optionally, the step of enhancing cell placement hotspots based on the process library file corresponding to the basic circuit code to obtain an enhanced layout includes: By analyzing the process library file provided by the user, the high-power cells in the process library file are obtained; The high-power unit is locked in a preset constraint region to obtain the enhanced layout.
[0014] Optionally, the step of performing parametric power network planning based on the process library file corresponding to the basic circuit code to obtain the planned power network includes: The PDN variable space is constructed based on the process library file provided by the user; wherein, the parameters of the PDN variable space include: the metal width of the power strip, the center-to-center spacing of adjacent power strips, the metal layers used, the density of interlayer vias, and the decoupling capacitor fill ratio; The density and connection method of the power grid in the PDN variable space are adjusted according to the metal width of the power strip, the center-to-center spacing of adjacent power strips, the metal layers used, the density of interlayer vias and the decoupling capacitor filling ratio to obtain power networks with different impedances. The planned power network is obtained based on the power networks with different impedances.
[0015] Secondly, the present invention provides a multidimensional circuit data enhancement device for EMIR analysis, the device comprising: The requirements determination module is used to determine the circuit enhancement target requirements for the target EMIR function points. The feature combination module is used to select and combine corresponding circuit structure features from a pre-built circuit feature library according to the circuit enhancement target requirements, so as to obtain combined features that meet the circuit enhancement target requirements. The code acquisition module is used to obtain the basic circuit code that meets the circuit enhancement target requirements through the large language model and the combined features; The data augmentation module is used to perform logic-side and / or physical-side data augmentation on the basic circuit code according to the circuit augmentation target requirements, and then perform physical implementation and index extraction in sequence to obtain enhanced EMIR index data. The data output module is used to return to the code acquisition module for iterative enhancement if the enhanced EMIR index data does not meet the circuit enhancement target requirements; otherwise, the enhanced EMIR index data is output as the final enhanced EMIR data to analyze and optimize the target EMIR function points.
[0016] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: In the above technical solution, under the premise of ensuring circuit functional equivalence and physical implementation feasibility, the present invention configures and schedules data enhancement on the logic side and the physical side based on a unified control platform, and uses a large language model to assist in structural transformation of circuit code to generate enhanced circuit data with diverse logic variants; depending on different needs, the logic side enhancement subsystem and the physical side enhancement subsystem can be enabled independently or work together.
[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0018] Figure 1 This is a flowchart of a multi-dimensional circuit data enhancement method for EMIR analysis provided in an embodiment of the present invention; Figure 2 This is a flowchart of mode A provided in an embodiment of the present invention; Figure 3 This is a flowchart of Mode B provided in an embodiment of the present invention; Figure 4 This is a flowchart of mode C provided in an embodiment of the present invention; Figure 5 This is a block diagram of a multi-dimensional circuit data enhancement device for EMIR analysis provided in an embodiment of the present invention. Detailed Implementation
[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0020] Figure 1 This is a flowchart of a multi-dimensional circuit data enhancement method for EMIR analysis provided in an embodiment of the present invention, such as... Figure 1 As shown, the method may include the following steps: S1. Determine the circuit enhancement target requirements for the target EMIR function points.
[0021] Understandably, for the specific EMIR functional points to be tested and verified, detailed EMIR circuit enhancement target requirements should be formulated, including analysis of targets and design use case requirements, determination of the design description of specific circuit functions and expected results of feature index extraction, and presentation of expected enhancement requirement targets.
[0022] For example, the analysis objective in the circuit enhancement target requirements is to test the circuit's power network's ability to drive high fan-out nodes, verifying the risk of voltage drop and electromigration under conditions of simultaneous switching of a large number of loads. The design use case requirement in the circuit enhancement target requirements is to design a Verilog module containing a specific master control signal of width W that drives at least [NUM] parallel-operating submodules; all submodules must be triggered on the same clock edge to maximize transient fan-out loads and create extreme current scenarios.
[0023] S2. Based on the circuit enhancement target requirements, select the corresponding circuit structure features from the pre-built circuit feature library and combine them to obtain the combined features that meet the circuit enhancement target requirements.
[0024] Understandably, a circuit feature library is constructed based on circuit structure characteristics, signal switching characteristics, and power network load characteristics to store circuit structure module features highly correlated with voltage drop or electromigration problems. This circuit feature library is used to characterize typical circuit structure patterns that are prone to causing EMIR problems in integrated circuit design.
[0025] For example, the circuit feature library can be represented as: F = {F_fanout, F_toggle, F_pipeline, F_depth, F_acitivity, F_power ...}. The meanings of each feature include, but are not limited to: F_fanout represents a high fan-out network structure; F_toggle represents a high-flip-rate node group; F_pipeline represents a deep pipeline structure; F_depth represents logical depth; F_acitivity represents time-dependent signal activity; and F_power represents high power consumption distribution.
[0026] S3. Obtain the basic circuit code that meets the circuit enhancement target requirements through large language models and combination features.
[0027] Optionally, S3 may include: The combined features are converted into model prompt words and input into the large language model to obtain the initial circuit code; The initial circuit code is validated for execution logic and syntax, and invalid code is filtered out to obtain the filtered circuit code. If the filtered circuit code does not meet the structural complexity condition, adjust the model prompts and regenerate the filtered circuit code until the filtered circuit code meets the structural complexity condition, thus obtaining the basic circuit code.
[0028] Understandably, the process involves determining whether the user terminal possesses basic circuit code that meets the circuit enhancement target requirements. If it does, the process proceeds directly to step S4 or compares the user terminal's basic circuit code with the basic circuit code generated in step S3, selecting the more suitable input for step S4. If no basic circuit code exists or the existing basic circuit code does not meet the circuit enhancement target requirements, then basic circuit code is generated based on the combined features. The specific steps are as follows: a. The instruction synthesis unit transforms the combinatorial features into prompts that are easily understood by the large language model, and inputs these prompts into the large language model to generate the corresponding Verilog initial circuit code. These prompts require the model to generate RTL (Register-Transfer Level) circuit code that deviates from the conventional optimization objective and has significant combinatorial features, while ensuring the correctness of the circuit's logical function.
[0029] b. Perform functional and syntax checks on the initial circuit code output by the large language model. Use synthesis tools to verify the syntax and logical function correctness of the code, and filter out invalid code with syntax or function errors.
[0030] c. When the verification results show that the generated filtered circuit code structure is too simple (the number of logic units, fan-out size, pipeline stages, or parallel path width are lower than the preset indicators), the prompt words are adjusted to guide the large language model to regenerate the RTL circuit code. This process is repeated iteratively until an RTL circuit code with correct syntax, functional requirements, and structural complexity that meets preset conditions is obtained (for example, if the user wants to verify the impact of a high fan-out structure on EMIR, the fan-out of key control signals can be required to be greater than 64; when testing large-scale concurrent logic, the total number of logic units can be required to be no less than 5000). This code is then used as the basic circuit code.
[0031] S4. After performing logic-side and / or physical-side data enhancement on the basic circuit code according to the circuit enhancement target requirements, perform physical implementation and index extraction in sequence to obtain enhanced EMIR index data.
[0032] It is understandable that the enhancement mode is selected based on the circuit enhancement target requirements, including: Mode A: Logic-only enhancement. Based on the expected performance requirements, different dimensions are selected to perform multi-dimensional logic enhancement on the basic circuit code, resulting in various enhanced codes that are "functionally equivalent but have different logic structures." After logic verification, the enhanced codes are subjected to the default physical design process to obtain enhanced EMIR performance data. The specific process is as follows: Figure 2 As shown.
[0033] Optionally, the process of performing logic-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: The basic circuit code architecture is converted into a parallel architecture to obtain the parallel architecture circuit code; Redundant logic is introduced into the non-critical paths, redundant signal paths, and internal control paths of the basic circuit code to obtain redundant circuit code. Modify the clock gating unit of the control circuit switch control logic in the basic circuit code to obtain circuit code with enhanced control logic; Physical implementations were performed on the parallel architecture circuit code, redundant circuit code, and control logic enhancement circuit code to obtain enhanced EMIR metric data.
[0034] Understandably, using LLM to identify the loop structure or state machine of the basic circuit code transforms the original serial architecture into a parallel architecture, increasing its transient current peak. By reconstructing the accumulation operation, which requires multiple cycles, into a single-cycle structure, the transistor switching density per unit area is changed, significantly reflecting performance characteristics. Without changing the circuit function, the logic path implementation is changed. Equivalent but physically different redundant logic is introduced into non-critical paths, redundant signal paths, or internal control paths that do not directly affect the function, increasing the number of logic units and switching activities while keeping the input / output functions unchanged, thus introducing additional static and dynamic power consumption. The switching control logic during circuit operation is changed, and clock gating units in the design are removed or disabled. In the generated circuit code, synthesis attributes are explicitly added, or specific synthesis constraint scripts are generated to force the synthesis tool to directly connect the clock terminals of all registers to the master clock and prohibit the insertion of clock gating units, resulting in circuit code with enhanced control logic. Physically implementing this enhanced control logic circuit code yields enhanced EMIR performance data.
[0035] Mode B: Physical design-only enhancement. Based on the basic circuit code and circuit enhancement target requirements, and while ensuring functional equivalence, key parameters are specifically adjusted during the physical design process to obtain enhanced EMIR performance data. The specific process is as follows: Figure 3 As shown.
[0036] Optionally, the process of performing physical-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: Dynamic physical timing constraints are applied to the design constraint file corresponding to the basic circuit code to obtain constraint parameters; Based on the process library file corresponding to the basic circuit code, the cell layout hotspots are enhanced to obtain the enhanced layout. Parametric power network planning is performed based on the technology library file corresponding to the basic circuit code to obtain the planned power network. Physical implementation is performed based on constraint parameters, the enhanced layout, and the planned power network to obtain enhanced EMIR index data.
[0037] Optionally, cell placement hotspot enhancement is performed based on the technology library file corresponding to the basic circuit code to obtain an enhanced layout, including: By analyzing the process library files provided by the user, high-power cells in the process library files can be obtained. By locking high-power cells within a preset constraint region, an enhanced layout is obtained.
[0038] Optionally, parametric power network planning is performed based on the technology library file corresponding to the basic circuit code to obtain the planned power network, including: The PDN (Power Distribution Network) variable space is constructed based on the process library files and basic circuit code provided by the user. The parameters of the PDN variable space include: the metal width of the power strip, the center-to-center spacing of adjacent power strips, the metal layers used, the density of interlayer vias, and the decoupling capacitor fill ratio. The density and connection method of the power grid in the PDN variable space are adjusted according to the metal width of the power strip, the center-to-center spacing of adjacent power strips, the metal layers used, the density of interlayer vias and the decoupling capacitor filling ratio to obtain power networks with different impedances. The planned power network is obtained based on power networks with different impedances.
[0039] Understandably, a dynamically parameterized constraint generator is designed to replace the standard design constraint file with fixed values. This generator produces different constraint parameters (frequency and flip-flop time, etc.) for each design iteration based on a preset probability distribution. During iteration, the command `set_switching_activity -static_probability 0.5 -toggle_rate [RATE]` is used, where `RATE` iterates between 0.1 and 1.0 to simulate data patterns from low to high load. The transition time value is also dynamically adjusted, causing the placement and routing tools to adopt different optimization strategies (e.g., inserting numerous large buffers to meet stringent transition time requirements). This results in significant voltage drop and electromigration characteristics, leading to the constraint parameters.
[0040] By analyzing the process library files, high-power-density cells (such as large clock buffers and registers) are identified. A very small constraint region is defined at the core of the layout, and commands are used to force these high-power cells to be locked within this region, improving the utilization of this region and creating a local hotspot effect. During the Clock Tree Synthesis (CTS) stage, the Skew parameters are modified via script to force the tool to execute clock signals that arrive simultaneously (zero deviation); or negative Skew is intentionally introduced to cause local logic blocks to operate simultaneously, resulting in an enhanced layout.
[0041] Define an iterable PDN variable space to automatically generate power networks with different impedance characteristics by changing the density and connection method of the power grid. Model the power network as a multi-dimensional configurable variable set S_PDN={Width,Pitch,Layer,ViaDensity,DecapRatio,ViaGen}. Here, Width is the metal width of the power strip, Pitch is the center-to-center spacing between adjacent power strips, Layer is the number of metal layers used, ViaDensity is the density of vias between layers, DecapRatio is the decoupling capacitor fill ratio, and ViaGen is the density rule for via generation. Control the number of vias (Via) generated at the intersections of different metal layers in the power network. Use the Via generation rule command of the EDA tool to limit the number of rows and columns of the via array. For example, forcibly reduce a standard 4x4 via array to 1x1 or 1x2, artificially creating a vertical power supply bottleneck. When generating the power grid, a loop script is used to automatically change the width of the power lines and the spacing between adjacent lines by step size to obtain power networks with different impedances, and thus obtain the planned power network.
[0042] Mode C: Logic-Physical Side Co-enhancement Mode. Based on the basic circuit code, directional enhancement is first performed on the logic side. After the logic verification passes, the logic enhancement code is obtained. Then, directional enhancement is performed on the physical side, and enhanced EMIR index data is obtained through cooperative transformation. The specific process is as follows: Figure 4 As shown.
[0043] Specifically, the process of performing logic-side and physical-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: The basic circuit code architecture is converted into a parallel architecture to obtain the parallel architecture circuit code; Redundant logic is introduced into the non-critical paths, redundant signal paths, and internal control paths of the basic circuit code to obtain redundant circuit code. Modify the clock gating unit of the control circuit switch control logic in the basic circuit code to obtain circuit code with enhanced control logic; Dynamic physical timing constraints are applied to the design constraint file corresponding to the basic circuit code to obtain constraint parameters; Based on the process library file corresponding to the basic circuit code, the cell layout hotspots are enhanced to obtain the enhanced layout. Parametric power network planning is performed based on the technology library file corresponding to the basic circuit code to obtain the planned power network. Physical implementations are performed on the parallel architecture circuit code, redundant circuit code, control logic enhancement circuit code, constraint parameters, enhanced layout, and planned power network to obtain enhanced EMIR index data.
[0044] Understandably, the specific implementation process can refer to the data augmentation process on the logical and physical sides mentioned above, and will not be repeated here.
[0045] It is worth mentioning that the obtained code and parameter configuration files are subjected to synthesis, placement and routing, and voltage drop / electromigration analysis to extract relevant index data, such as static / dynamic IR drop, EM violation count, transient current peak, static and dynamic power, transistor switching / flip density, and power network resistance, to obtain enhanced EMIR index data.
[0046] S5. If the enhanced EMIR index data does not meet the circuit enhancement target requirements, return to S3 for iterative enhancement; otherwise, output the enhanced EMIR index data as the final enhanced EMIR data to analyze and optimize the target EMIR function points.
[0047] Understandably, the indicator data extracted by S5 is filtered, and the changes in EMIR indicator data before and after enhancement are analyzed to determine whether the expected goals have been achieved. Data that does not meet the goals will be returned to S3 for further enhancement iterations. Enhanced data that meets the expectations is then labeled and processed to output the final enhanced EMIR data for analysis and optimization of the target EMIR functional points.
[0048] In one implementation, since high fan-out nodes are prone to voltage drop and electromigration problems in circuits, which are typical causes of EMIR issues, the high fan-out (F_fanout) feature is selected from the circuit feature library as an enhancement target. The high fan-out feature is converted into prompts for an AI large language model, with the goal of "testing the power network's ability to drive high fan-out nodes." The system call template is: "Please design a Verilog module that contains a master control signal with a bit width of [WIDTH], which drives at least [NUM] parallel sub-modules. All sub-modules must be triggered on the same clock edge to maximize fan-out load." The generated basic circuit code is subjected to syntax and functional verification to ensure that the generated basic circuit code functions as expected and can be synthesized. For the high fan-out structural feature, logic-side enhancement strategies are selected, including replicating the signal drive path, introducing additional load nodes on the high fan-out signal path, and adjusting the signal fan-out hierarchy. In the physical design process, high-power cells are concentrated near the high-fan-out signal drive area to create local hotspots. For interconnects, the line width or spacing of critical high-fan-out paths is reduced, forcing long high-fan-out traces to run on lower metal layers. Decoupling capacitors are prohibited from being inserted around these traces. These measures achieve targeted enhancement, resulting in enhanced features. By uniformly scheduling the execution of physical implementations and index extraction, multiple sets of functionally equivalent but physically different high-fan-out EMIR enhancement data are obtained, which can be used for EMIR analysis or functional evaluation using EDA tools.
[0049] In the above technical solution, under the premise of ensuring circuit functional equivalence and physical implementation feasibility, the present invention configures and schedules data enhancement on the logic side and the physical side based on a unified control platform, and uses a large language model to assist in structural transformation of circuit code to generate enhanced circuit data with diverse logic variants; depending on different needs, the logic side enhancement subsystem and the physical side enhancement subsystem can be enabled independently or work together.
[0050] Figure 5 This is a block diagram of a multi-dimensional circuit data enhancement device for EMIR analysis provided in an embodiment of the present invention, such as... Figure 5 As shown, the device 500 may include: The requirement determination module 501 is used to determine the circuit enhancement target requirements for the target EMIR function point; The feature combination module 502 is used to select and combine corresponding circuit structure features from a pre-built circuit feature library according to the circuit enhancement target requirements to obtain combined features that meet the circuit enhancement target requirements. The code acquisition module 503 is used to obtain basic circuit code that meets the circuit enhancement target requirements through large language models and combination features; Data augmentation module 504 is used to perform logic-side and / or physical-side data augmentation on the basic circuit code according to the circuit augmentation target requirements, and then perform physical implementation and index extraction in sequence to obtain enhanced EMIR index data; The data output module 505 is used to return to the code acquisition module 504 for iterative enhancement if the enhanced EMIR index data does not meet the circuit enhancement target requirements; otherwise, the enhanced EMIR index data is output as the final enhanced EMIR data to analyze and optimize the target EMIR function points.
[0051] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.
[0052] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0053] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.
[0054] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A multidimensional circuit data augmentation method for EMIR analysis, characterized in that, The method includes: S1. Determine the circuit enhancement target requirements for the target EMIR function points; S2. Based on the circuit enhancement target requirements, select corresponding circuit structure features from the pre-built circuit feature library and combine them to obtain combined features that meet the circuit enhancement target requirements; S3. Obtain the basic circuit code that meets the circuit enhancement target requirements through the large language model and the combined features; S4. After performing logic-side and / or physical-side data enhancement on the basic circuit code according to the circuit enhancement target requirements, perform physical implementation and index extraction in sequence to obtain enhanced EMIR index data. S5. If the enhanced EMIR index data does not meet the circuit enhancement target requirements, return to S3 for iterative enhancement; otherwise, output the enhanced EMIR index data as the final enhanced EMIR data to analyze and optimize the target EMIR function points.
2. The multidimensional circuit data augmentation method for EMIR analysis according to claim 1, characterized in that, S3 includes: The combined features are converted into model prompt words and input into the large language model to obtain the initial circuit code; The initial circuit code is verified for execution logic and syntax, and invalid code is filtered out to obtain the filtered circuit code. When the filtered circuit code does not meet the structural complexity condition, the model prompt words are adjusted and the filtered circuit code is regenerated until the filtered circuit code meets the structural complexity condition, thus obtaining the basic circuit code.
3. The multidimensional circuit data augmentation method for EMIR analysis according to claim 1, characterized in that, The process of performing logic-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: The architecture of the basic circuit code is converted into a parallel architecture to obtain the parallel architecture circuit code; Redundant logic is introduced into the non-critical paths, redundant signal paths, and internal control paths of the basic circuit code to obtain redundant circuit code. Modify the clock gating unit of the control circuit switch control logic in the basic circuit code to obtain circuit code with enhanced control logic; The parallel architecture circuit code, the redundant circuit code, and the control logic enhancement circuit code are physically implemented to obtain the enhanced EMIR index data.
4. The multidimensional circuit data augmentation method for EMIR analysis according to claim 1, characterized in that, The process of performing physical-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: Dynamic physical timing constraints are applied to the design constraint file corresponding to the basic circuit code to obtain constraint parameters; Based on the process library file corresponding to the basic circuit code, cell layout hotspot enhancement is performed to obtain the enhanced layout. Parametric power network planning is performed based on the process library file corresponding to the basic circuit code to obtain the planned power network. The enhanced EMIR index data is obtained by physically implementing the system based on the constraint parameters, the enhanced layout, and the planned power network.
5. The multidimensional circuit data augmentation method for EMIR analysis according to claim 1, characterized in that, The process of performing logic-side and physical-side data augmentation on the basic circuit code according to the circuit enhancement target requirements includes: The architecture of the basic circuit code is converted into a parallel architecture to obtain the parallel architecture circuit code; Redundant logic is introduced into the non-critical paths, redundant signal paths, and internal control paths of the basic circuit code to obtain redundant circuit code. Modify the clock gating unit of the control circuit switch control logic in the basic circuit code to obtain circuit code with enhanced control logic; Dynamic physical timing constraints are applied to the design constraint file corresponding to the basic circuit code to obtain constraint parameters; Based on the process library file corresponding to the basic circuit code, cell layout hotspot enhancement is performed to obtain the enhanced layout. Parametric power network planning is performed based on the process library file corresponding to the basic circuit code to obtain the planned power network. The parallel architecture circuit code, the redundant circuit code, the control logic enhancement circuit code, the constraint parameters, the enhanced layout, and the planned power network are physically implemented to obtain the enhanced EMIR index data.
6. The multidimensional circuit data augmentation method for EMIR analysis according to claim 4, characterized in that, The step of enhancing cell placement hotspots based on the process library file corresponding to the basic circuit code to obtain the enhanced layout includes: By analyzing the process library file provided by the user, the high-power cells in the process library file are obtained; The high-power unit is locked in a preset constraint region to obtain the enhanced layout.
7. The multidimensional circuit data augmentation method for EMIR analysis according to claim 4, characterized in that, The step of performing parametric power network planning based on the process library file corresponding to the basic circuit code to obtain the planned power network includes: The PDN variable space is constructed based on the process library file provided by the user; wherein, the parameters of the PDN variable space include: the metal width of the power strip, the center-to-center spacing of adjacent power strips, the metal layers used, the density of interlayer vias, and the decoupling capacitor fill ratio; The density and connection method of the power grid in the PDN variable space are adjusted according to the metal width of the power strip, the center-to-center spacing of adjacent power strips, the metal layers used, the density of interlayer vias and the decoupling capacitor filling ratio to obtain power networks with different impedances. The planned power network is obtained based on the power networks with different impedances.
8. A multidimensional circuit data enhancement device for EMIR analysis, characterized in that, The device includes: The requirements determination module is used to determine the circuit enhancement target requirements for the target EMIR function points. The feature combination module is used to select and combine corresponding circuit structure features from a pre-built circuit feature library according to the circuit enhancement target requirements, so as to obtain combined features that meet the circuit enhancement target requirements. The code acquisition module is used to obtain the basic circuit code that meets the circuit enhancement target requirements through the large language model and the combined features; The data augmentation module is used to perform logic-side and / or physical-side data augmentation on the basic circuit code according to the circuit augmentation target requirements, and then perform physical implementation and index extraction in sequence to obtain enhanced EMIR index data. The data output module is used to return to the code acquisition module for iterative enhancement if the enhanced EMIR index data does not meet the circuit enhancement target requirements; otherwise, the enhanced EMIR index data is output as the final enhanced EMIR data to analyze and optimize the target EMIR function points.