Ultra-low power consumption intelligent electric arc micro circuit breaker system

Abstract

The invention discloses an ultra-low power consumption intelligent electric arc micro circuit breaker system which comprises a master control MCU, a sampling circuit, a bias differential input circuit, a band-pass filter circuit, a comparison circuit, a JK trigger group, a counter start enabling / zero clearing circuit and an interrupt generation unit. The sampling circuit is respectively connected with a current transformer and the bias differential input circuit, the bias differential input circuit is respectively connected with the master control MCU and the band-pass filter circuit, and the band-pass filter circuit is respectively connected with the comparison circuit and the master control MCU. The comparison circuit is respectively connected with the counter start enabling / zero clearing circuit and the JK trigger group, the JK trigger group is connected with the interrupt generation unit, and the interrupt generation unit is connected with the main control MCU. According to the invention, the technical problem of how to realize effective identification, accurate positioning and wireless remote reporting of a fault arc in an ultra-low power consumption operation state is solved.

Description

Technical Field

[0001] This invention relates to the field of arc micro-interruption technology, and in particular to an ultra-low power intelligent arc micro-interruption system. Background Technology

[0002] Electrical arc faults are a major fire hazard. Statistics show that fires caused by faults account for over 70% of all electrical fires. Fault arcs typically originate from aging insulation and loose connections, and their current waveforms exhibit high-frequency oscillations, with typical characteristic signal frequencies ranging from 1MHz to 10MHz. Currently, traditional miniature circuit breakers or some intelligent miniature circuit breakers commonly installed on the load side of user meters primarily function only for overload, short-circuit, and leakage protection, failing to effectively detect fault arcs. This constitutes a significant loophole in the electrical safety protection system.

[0003] Patent document CN202223365398.8 discloses an arc fault protection device, comprising: a miniature circuit breaker disposed at the power input terminal; a current sampling unit for acquiring load-side current signals; a signal filter for filtering the current signals acquired by the current sampling unit; and a drive control circuit for judging arc faults based on high-frequency components in the filtered current signals and controlling the miniature circuit breaker according to the judgment result; a low-pass filter for removing high-frequency interference signals is disposed in the line between the miniature circuit breaker and the sampling point of the current sampling unit, wherein the upper limit of the passband of the low-pass filter is less than the lowest frequency value of the high-frequency components used for arc fault judgment. While some arc fault detection methods exist in the current technology, they generally suffer from the following prominent drawbacks: First, high power consumption. Most existing arc fault identification technologies rely on the main control unit continuously operating at high speed to complete high-frequency signal sampling and millisecond-level fault judgment. This continuous operation mode leads to a significant increase in power consumption. Since the micro-circuit interrupter (MIC) is installed on the load side of the user's meter, the power consumption is borne by the user, making the high power consumption unacceptable and hindering the widespread adoption of the technology. Second, reliability and cost issues. Existing solutions often use software algorithms directly executed by the MCU for identification. The circuitry is typically limited to simple sampling, filtering, and amplification conditioning circuits. This method is susceptible to transient interference signals, leading to misjudgments. Furthermore, the system lacks continuous characteristic waveform counting and multiple anti-jitter judgment mechanisms implemented by pure hardware circuits, resulting in lower reliability. Simultaneously, high-speed processing requires a high-performance MCU, increasing system cost. Thirdly, the communication reporting scheme is unreasonable. If fault information needs to be reported to the monitoring master station, the existing scheme has two unreasonable paths: one is to use long-distance wireless communication modules such as 4G, which further exacerbates power consumption and cost issues; the other is to have the micro-circuit communicate with the meter via RS485, and then upload the data via power line carrier. However, the stability and reliability of the meter are crucial as it is a billing device. Adding communication functionality with the micro-circuit requires complex development and replacement, which is difficult, costly, and may introduce instability risks from external devices. To solve these technical problems, an ultra-low power intelligent arc micro-circuit system is urgently needed. Summary of the Invention

[0004] The main objective of this invention is to propose an ultra-low power intelligent arc micro-disruptor system, which aims to solve the technical problem of how to effectively identify, accurately locate, and wirelessly report faulty arcs under ultra-low power operation.

[0005] To achieve the above objectives, the present invention provides an ultra-low power intelligent arc micro-interrupt system, wherein the ultra-low power intelligent arc micro-interrupt system comprises:

[0006] The main control MCU, sampling circuit, bias differential input circuit, bandpass filter circuit, comparator circuit, JK flip-flop group, counter start enable / reset circuit and interrupt generation unit;

[0007] The sampling circuit is connected to the current transformer and the bias differential input circuit, respectively. The bias differential input circuit is connected to the main control MCU and the bandpass filter circuit, respectively. The bandpass filter circuit is connected to the comparator circuit and the main control MCU, respectively. The comparator circuit is connected to the counter start enable / reset circuit and the JK flip-flop group, respectively. The JK flip-flop group is connected to the interrupt generation unit, and the interrupt generation unit is connected to the main control MCU.

[0008] In one preferred embodiment, the sampling circuit includes a sampling resistor R1, one end of which is connected to a reference voltage port, a current transformer, and a bias differential input circuit, and the other end of which is connected to the bias differential input circuit and the current transformer.

[0009] In one preferred embodiment, the bias differential input circuit includes an operational amplifier OP1, resistor R2, resistor R3, and resistor R4;

[0010] The inverting input terminal of the operational amplifier OP1 is connected to resistors R2 and R4 respectively, and the other end of resistor R2 is connected to the sampling circuit. The non-inverting input terminal of the operational amplifier OP1 is connected to resistor R3, and the other end of resistor R3 is connected to the sampling circuit. The output terminal of the operational amplifier OP1 is connected to the other end of resistor R4, the main control MCU, and the bias differential input circuit respectively. The positive power supply terminal of the operational amplifier OP1 is connected to the power supply terminal, and the negative power supply terminal of the operational amplifier OP1 is grounded.

[0011] In one preferred embodiment, the bandpass filter circuit includes an operational amplifier OP2, a resistor R5, a capacitor C1, a capacitor C2, and a resistor R6.

[0012] The inverting input terminal of the operational amplifier OP2 is connected to resistor R6 and capacitor C2, respectively. The other end of capacitor C2 is connected to resistor R5 and capacitor C1, respectively. The other end of resistor R5 is connected to the bias differential input circuit. The non-inverting input terminal of the operational amplifier OP2 is connected to the reference voltage port. The output terminal of the operational amplifier OP2 is connected to resistor R6, the main control MCU, and the comparator circuit, respectively. The positive power supply terminal of the operational amplifier OP2 is connected to the power supply terminal. The negative power supply terminal of the operational amplifier OP2 and the other end of capacitor C1 are grounded.

[0013] In one preferred embodiment, the comparison circuit includes a comparator U1 and a resistor R7;

[0014] The non-inverting input of the comparator U1 is connected to the bias differential input circuit, the inverting input of the comparator U1 is connected to the reference voltage port, the output of the comparator U1 is connected to the counter start enable / reset circuit, the JK flip-flop group and the resistor R7 respectively, the other end of the resistor R7 and the positive power supply terminal of the comparator U1 are connected to the power supply terminal, and the negative power supply terminal of the comparator U1 is grounded.

[0015] In one preferred embodiment, the JK trigger group includes several counters connected in series.

[0016] In one preferred embodiment, the JK trigger group comprises four counters connected in series.

[0017] In one preferred embodiment, the counter start-up enable / reset circuit includes a comparator U2, a diode D1, a resistor R8, a capacitor C3, and a resistor R9;

[0018] The non-inverting input of comparator U2 is connected to resistor R8, capacitor C3 and the cathode of diode D1, respectively. The anode of diode D1 is connected to the comparator circuit and the JK flip-flop group. The inverting input of comparator U2 is connected to the reference voltage port. The output of comparator U2 is connected to resistor R9 and the JK flip-flop group, respectively. The positive power supply terminal of comparator U2 and the other end of resistor R9 are connected to the power supply terminal. The negative power supply terminal of comparator U2 is grounded.

[0019] In one preferred embodiment, the interrupt generation unit includes a debouncing NAND gate U7; the input of the debouncing NAND gate U7 is connected to a JK flip-flop group, and the output of the debouncing NAND gate U7 is connected to the interrupt pin of the main control MCU.

[0020] In one preferred embodiment, the ultra-low power intelligent arc micro-break system further includes a micro-break body, which is connected to a current transformer.

[0021] In the above technical solution of the present invention, the ultra-low power intelligent arc fault micro-interrupt system includes: a main control MCU, a sampling circuit, a bias differential input circuit, a bandpass filter circuit, a comparator circuit, a JK flip-flop group, a counter start enable / reset circuit, and an interrupt generation unit. The sampling circuit is connected to a current transformer and the bias differential input circuit, the bias differential input circuit is connected to the main control MCU and the bandpass filter circuit, the bandpass filter circuit is connected to the comparator circuit and the main control MCU, the comparator circuit is connected to the counter start enable / reset circuit and the JK flip-flop group, the JK flip-flop group is connected to the interrupt generation unit, and the interrupt generation unit is connected to the main control MCU. The present invention solves the technical problem of how to effectively identify, accurately locate, and wirelessly remotely report fault arcs under ultra-low power operation. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0023] Figure 1 This is a first schematic diagram of an ultra-low power intelligent arc micro-break system according to an embodiment of the present invention;

[0024] Figure 2 This is a first schematic diagram of an ultra-low power intelligent arc micro-break system according to an embodiment of the present invention;

[0025] Figure 3 The waveforms and timing diagrams of VF at each test point in the circuit of this embodiment are shown.

[0026] The realization of the objective, functional characteristics and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] The technical solutions of the various embodiments of the present invention can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0029] See Figures 1-2 According to one aspect of the present invention, the present invention provides an ultra-low power intelligent arc micro-interrupt system, wherein the ultra-low power intelligent arc micro-interrupt system comprises:

[0030] The main control MCU, sampling circuit, bias differential input circuit, bandpass filter circuit, comparator circuit, JK flip-flop group, counter start enable / reset circuit and interrupt generation unit;

[0031] The sampling circuit is connected to the current transformer and the bias differential input circuit, respectively. The bias differential input circuit is connected to the main control MCU and the bandpass filter circuit, respectively. The bandpass filter circuit is connected to the comparator circuit and the main control MCU, respectively. The comparator circuit is connected to the counter start enable / reset circuit and the JK flip-flop group, respectively. The JK flip-flop group is connected to the interrupt generation unit, and the interrupt generation unit is connected to the main control MCU.

[0032] Specifically, in this embodiment, the sampling circuit includes a sampling resistor R1. One end of the sampling resistor R1 is connected to the reference voltage port, the current transformer, and the bias differential input circuit, respectively. The other end of the sampling resistor R1 is connected to the bias differential input circuit and the current transformer, respectively. The sampling resistor R1 is a high-precision sampling resistor for current signal input.

[0033] Specifically, in this embodiment, the bias differential input circuit includes an operational amplifier OP1, resistors R2, R3, and R4; the inverting input terminal of the operational amplifier OP1 is connected to resistors R2 and R4 respectively, the other end of resistor R2 is connected to the sampling circuit, the non-inverting input terminal of the operational amplifier OP1 is connected to resistor R3, the other end of resistor R3 is connected to the sampling circuit, the output terminal of the operational amplifier OP1 is connected to the other end of resistor R4, the main control MCU, and the bias differential input circuit respectively, the positive power supply terminal of the operational amplifier OP1 is connected to the power supply terminal, and the negative power supply terminal of the operational amplifier OP1 is grounded.

[0034] Specifically, in this embodiment, the bandpass filter circuit includes an operational amplifier OP2, a resistor R5, a capacitor C1, a capacitor C2, and a resistor R6. The inverting input terminal of the operational amplifier OP2 is connected to the resistor R6 and the capacitor C2, respectively. The other end of the capacitor C2 is connected to the resistor R5 and the capacitor C1, respectively. The other end of the resistor R5 is connected to the bias differential input circuit. The non-inverting input terminal of the operational amplifier OP2 is connected to the reference voltage port. The output terminal of the operational amplifier OP2 is connected to the resistor R6, the main control MCU, and the comparator circuit, respectively. The positive power supply terminal of the operational amplifier OP2 is connected to the power supply terminal, and the negative power supply terminal of the operational amplifier OP2 and the other end of the capacitor C1 are grounded.

[0035] Specifically, in this embodiment, the comparison circuit includes a comparator U1 and a resistor R7; the non-inverting input of the comparator U1 is connected to the bias differential input circuit, the inverting input of the comparator U1 is connected to the reference voltage port, the output of the comparator U1 is connected to the counter start enable / reset circuit, the JK flip-flop group and the resistor R7 respectively, the other end of the resistor R7 and the positive power supply terminal of the comparator U1 are connected to the power supply terminal, and the negative power supply terminal of the comparator U1 is grounded.

[0036] Specifically, in this embodiment, the JK trigger group includes several counters connected in series. In this invention, the JK trigger group includes four counters connected in series. This invention does not impose specific limitations and can be set as needed. The JK trigger group includes feature signal counters U3, U4, U5, and U6. The output of comparator U1 is connected to the pulse input of feature signal counter U3. The output of feature signal counter U3 is connected to the pulse input of feature signal counter U4, and so on up to the output of feature signal counter U6. Subsequently, the outputs of feature signal counter U6 and feature signal counter U5 are simultaneously connected to the input of debouncing NAND gate U7. The output of NAND gate U7 is connected to the interrupt pin of the main control MCU. The output of operational amplifier OP1 is connected to the main control MCU to collect the load current during normal operation. The output of operational amplifier OP2 is connected to the main control MCU to collect the arc fault feature signal.

[0037] Specifically, in this embodiment, the counter start enable / reset circuit includes a comparator U2, a diode D1, a resistor R8, a capacitor C3, and a resistor R9. The non-inverting input of the comparator U2 is connected to the cathodes of the resistor R8, the capacitor C3, and the diode D1, respectively. The anode of the diode D1 is connected to the comparator circuit and the JK flip-flop group. The inverting input of the comparator U2 is connected to the reference voltage port. The output of the comparator U2 is connected to the resistor R9 and the JK flip-flop group, respectively. The positive power supply terminal of the comparator U2 and the other end of the resistor R9 are connected to the power supply terminal. The negative power supply terminal of the comparator U2 is grounded. The counter start enable / reset circuit controls the counting and resetting of the JK flip-flop group. The resistor R7, the diode D1, and the capacitor C3 form a charge-hold circuit, and the capacitor C3 and the resistor R8 form a fast discharge circuit. The output of the comparator U2 is connected to the P (preset) terminal and the C (reset) terminal of the feature signal counters U3, U4, U5, and U6.

[0038] Specifically, in this embodiment, the interrupt generation unit includes a debouncing NAND gate U7; the input of the debouncing NAND gate U7 is connected to a JK flip-flop group, and the output of the debouncing NAND gate U7 is connected to the interrupt pin of the main control MCU.

[0039] Specifically, in this embodiment, the ultra-low power intelligent arc micro-break system further includes a micro-break body, which is connected to a current transformer.

[0040] Specifically, in this embodiment, when the system is powered on, the main control MCU goes into sleep mode, and the pure hardware circuit samples and monitors in real time, receiving characteristic signals from 1MHz to 10MHz. If no 1MHz-10MHz characteristic signal is received, the characteristic signal counter is reset. If a 1MHz-10MHz characteristic signal is received, the characteristic signal counter is enabled and starts counting. It is determined whether a reset signal is received during the counting process. If not, the 1MHz-10MHz characteristic signal is detected again. If a reset signal is received, 12 or more consecutive characteristic signals are detected. If no signal is detected, the 1MHz-10MHz characteristic signal is detected again. Otherwise, an arc fault is identified, a wake-up interrupt signal is generated, the main control MCU starts load current, arc characteristic current, phase voltage zero-crossing detection, and input / output terminal temperature sampling to determine the type and location of the arc fault, actively report the fault, and the main control MCU enters sleep mode.

[0041] Specifically, in this embodiment, the ultra-low power intelligent arc micro-circuit system further includes a phase voltage zero-crossing detection circuit, an incoming and outgoing line terminal temperature detection circuit, a Bluetooth module, and a power module. The phase voltage zero-crossing detection circuit, the incoming and outgoing line terminal temperature detection circuit, the Bluetooth module, and the power module are all connected to the main control MCU.

[0042] Specifically, in this embodiment, the ultra-low power intelligent arc micro-break system is connected to the Bluetooth module and / or power line carrier module at the meter end, and the meter end is connected to the power line carrier module of the concentrator.

[0043] Specifically, in this embodiment, the system of the present invention can identify arc faults by self-starting detection and counting of characteristic signals through pure hardware circuitry in the ultra-low power operation state of MCU sleep, and autonomously interrupt and wake up the main control MCU to further sample characteristic signals through ADC. Based on the amplitude of arc characteristic signals, single-phase or multi-phase faults, and comparison with experience database, the system can determine the type of arc fault and determine the location of the fault by comparing the temperature changes of the incoming and outgoing line terminals caused by the arc fault. The system also has line voltage and current monitoring, overload, short circuit, and terminal over-temperature protection functions. The system actively reports faults through low-power wireless (Bluetooth) instead of high-power 4G modules. The Bluetooth module in the system communicates directly with the uplink Bluetooth + power line carrier (meter end) dual-mode module and power line carrier module (concentrator) and uploads the data to the communication terminal and main station without interacting with the meter, reducing communication layers and avoiding impact on the meter.

[0044] Specifically, in this embodiment, the present invention identifies arc signals as passing through a bias differential input circuit, a bandpass filter circuit, a comparator circuit, and a JK flip-flop group to detect multiple (e.g., 12 or more) consecutive characteristic signals within a specific bandwidth range (e.g., 1MHz~10MHz) within a short period to identify arc faults. If a characteristic signal is sampled, counting begins from the JK flip-flop group. If no consecutive characteristic signal is detected, the counter is enabled and reset to the default zero state, and the JK flip-flop group is cleared. This indicates an intermittent interference signal, which will not trigger an interrupt to wake up the main control MCU, thus avoiding frequent wake-ups that generate significant power consumption. The characteristic signal counting will resume only when a characteristic signal is sampled again. After the JK flip-flop group detects multiple (e.g., 12 or more) consecutive characteristic signals within a specific bandwidth range (e.g., 1MHz~10MHz) within a short period to identify arc faults, an interrupt signal is generated by a debouncing NAND gate to autonomously wake up the main control MCU. The MCU can automatically switch from a 1mA-level ultra-low power sleep state to a 30mA high-speed operating state within a microsecond time. After the analysis is completed, it will return to the sleep state.

[0045] Specifically, in this embodiment, see Figure 3 The diagram shows the waveforms and timing of the VF signals at various test points in the key circuit. VF1: Output of the debouncing NAND gate U7, 2V per Y-axis division; VF2: Output of the 4th characteristic signal counter U6, 5V per Y-axis division; VF3: Output of the 3rd characteristic signal counter U5, 10V per Y-axis division; VF4: Output pulse signal of comparator U1, 2V per Y-axis division; VF5: Signal after comparator U2, high and low levels control the start and reset of the JK flip-flop group respectively, 2V per Y-axis division; VF6: Signal after operational amplifier OP2, 5V per Y-axis division.

[0046] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. An ultra-low power intelligent arc micro-circuit system, characterized in that, include: The main control MCU, sampling circuit, bias differential input circuit, bandpass filter circuit, comparator circuit, JK flip-flop group, counter start enable / reset circuit and interrupt generation unit; The sampling circuit is connected to the current transformer and the bias differential input circuit, respectively. The bias differential input circuit is connected to the main control MCU and the bandpass filter circuit, respectively. The bandpass filter circuit is connected to the comparator circuit and the main control MCU, respectively. The comparator circuit is connected to the counter start enable / reset circuit and the JK flip-flop group, respectively. The JK flip-flop group is connected to the interrupt generation unit, and the interrupt generation unit is connected to the main control MCU.

2. The ultra-low power intelligent arc micro-circuit system according to claim 1, characterized in that, The sampling circuit includes a sampling resistor R1. One end of the sampling resistor R1 is connected to the reference voltage port, the current transformer, and the bias differential input circuit, respectively. The other end of the sampling resistor R1 is connected to the bias differential input circuit and the current transformer, respectively.

3. The ultra-low power intelligent arc micro-circuit system according to any one of claims 1-2, characterized in that, The bias differential input circuit includes operational amplifier OP1, resistor R2, resistor R3 and resistor R4; The inverting input terminal of the operational amplifier OP1 is connected to resistors R2 and R4 respectively, and the other end of resistor R2 is connected to the sampling circuit. The non-inverting input terminal of the operational amplifier OP1 is connected to resistor R3, and the other end of resistor R3 is connected to the sampling circuit. The output terminal of the operational amplifier OP1 is connected to the other end of resistor R4, the main control MCU, and the bias differential input circuit respectively. The positive power supply terminal of the operational amplifier OP1 is connected to the power supply terminal, and the negative power supply terminal of the operational amplifier OP1 is grounded.

4. The ultra-low power intelligent arc micro-circuit system according to any one of claims 1-2, characterized in that, The bandpass filter circuit includes an operational amplifier OP2, a resistor R5, a capacitor C1, a capacitor C2, and a resistor R6; The inverting input terminal of the operational amplifier OP2 is connected to resistor R6 and capacitor C2, respectively. The other end of capacitor C2 is connected to resistor R5 and capacitor C1, respectively. The other end of resistor R5 is connected to the bias differential input circuit. The non-inverting input terminal of the operational amplifier OP2 is connected to the reference voltage port. The output terminal of the operational amplifier OP2 is connected to resistor R6, the main control MCU, and the comparator circuit, respectively. The positive power supply terminal of the operational amplifier OP2 is connected to the power supply terminal. The negative power supply terminal of the operational amplifier OP2 and the other end of capacitor C1 are grounded.

5. The ultra-low power intelligent arc micro-circuit system according to any one of claims 1-2, characterized in that, The comparison circuit includes a comparator U1 and a resistor R7; The non-inverting input of the comparator U1 is connected to the bias differential input circuit, the inverting input of the comparator U1 is connected to the reference voltage port, the output of the comparator U1 is connected to the counter start enable / reset circuit, the JK flip-flop group and the resistor R7 respectively, the other end of the resistor R7 and the positive power supply terminal of the comparator U1 are connected to the power supply terminal, and the negative power supply terminal of the comparator U1 is grounded.

6. The ultra-low power intelligent arc micro-circuit system according to any one of claims 1-2, characterized in that, The JK trigger group includes several counters connected in series.

7. The ultra-low power intelligent arc micro-circuit system according to claim 5, characterized in that, The JK trigger group includes four counters connected in series.

8. The ultra-low power intelligent arc micro-circuit system according to any one of claims 1-2, characterized in that, The counter start enable / reset circuit includes comparator U2, diode D1, resistor R8, capacitor C3 and resistor R9; The non-inverting input of comparator U2 is connected to resistor R8, capacitor C3 and the cathode of diode D1, respectively. The anode of diode D1 is connected to the comparator circuit and the JK flip-flop group. The inverting input of comparator U2 is connected to the reference voltage port. The output of comparator U2 is connected to resistor R9 and the JK flip-flop group, respectively. The positive power supply terminal of comparator U2 and the other end of resistor R9 are connected to the power supply terminal. The negative power supply terminal of comparator U2 is grounded.

9. The ultra-low power intelligent arc micro-circuit system according to any one of claims 1-2, characterized in that, The interrupt generation unit includes a debouncing NAND gate U7; the input of the debouncing NAND gate U7 is connected to a JK flip-flop group, and the output of the debouncing NAND gate U7 is connected to the interrupt pin of the main control MCU.

10. The ultra-low power intelligent arc micro-break system according to any one of claims 1-2, characterized in that, The ultra-low power intelligent arc micro-break system also includes a micro-break body, which is connected to a current transformer.

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