Bisynchronous coordinate system phase-locked loop optimization strategy

Abstract

The invention discloses a dual-synchronous coordinate system phase-locked loop optimization strategy which comprises a Clarke transformation unit, a Park transformation unit, an iPark transformation unit, a positive sequence decoupling network, a negative sequence decoupling network, a low-pass filter, a PI regulator and a frequency integration unit. When the amplitude of one-phase or two-phase voltage is zero, one-phase voltage with the amplitude not zero is selected, and a single-phase phase-locked loop lock is adopted for phase locking; and when the amplitudes of the three-phase voltages are not zero, Clarke conversion is carried out on the three-phase voltages, and the frequency is assigned to an integral quantity of a PI regulator of the three-phase phase-locked loop, so that the phase-locked loop of the double-synchronous coordinate system jumps out of a pseudo-steady state. Different coping strategies are determined to be adopted according to different voltage conditions, and the problem that the phase-locked loop of the double-synchronous coordinate system enters a pseudo-steady state is effectively prevented.

Description

Technical Field

[0001] This invention relates to a phase-locked loop (PLL) control technology, and more particularly to a dual-synchronous coordinate system PLL optimization strategy. Background Technology

[0002] Many bidirectional DC power sources require connection to the power grid via their internal power distribution cells (PFCs). These DC power sources need to acquire the fundamental voltage signal from the power grid so that the AC current of the PFC can follow the frequency and phase of the grid voltage, achieving synchronization with the grid.

[0003] Currently, phase-locked loops (PLLs) are a crucial technology for controlling power grid balancing (PFC) to achieve grid synchronization, with the Synchronous Reference Frame PLL (SRF-PLL) being the most widely used. This PLL has a simple structure and can quickly and accurately obtain the phase angle and frequency of the grid voltage under ideal grid conditions. However, when the grid voltage is unbalanced, the phase-locking capability of the SRF-PLL is severely insufficient. To address these shortcomings, power system experts proposed the Dual Synchronous Reference Frame PLL (DSFR-PLL) with positive and negative sequence decoupling, effectively solving the phase-locking problem under unbalanced grid voltage conditions.

[0004] Existing technology:

[0005] The dual-synchronous coordinate system phase-locked loop can ensure that the phase-locked output frequency and phase are synchronized with the fundamental components of the three-phase voltage when the three-phase voltage is unbalanced. The phase-locked loop contains two rotating coordinate systems. +ω and +θ are obtained through positive sequence rotating coordinate transformation, as well as the rotating positive sequence voltage Udqp. -ω and -θ are obtained through negative sequence rotating coordinate transformation, as well as the rotating negative sequence voltage Udqn.

[0006] The main drawbacks of existing technologies are:

[0007] 1) When one or two phases of the grid voltage amplitude are zero, the grid voltage has no positive or negative sequence components, and the positive and negative sequences cancel each other out. If a dual-synchronous coordinate system phase-locked loop is started at this time, it may enter a pseudo-steady state, and the output frequency will be neither positive nor negative sequence but zero sequence.

[0008] 2) If the grid voltage amplitude increases slowly from zero, the positive and negative sequences will be coupled together, which will also cause the phase-locked loop to enter a pseudo-steady state and the output frequency to be zero.

[0009] In view of this, the present invention is hereby proposed. Summary of the Invention

[0010] The purpose of this invention is to provide a dual-synchronous coordinate system phase-locked loop optimization strategy to solve the aforementioned technical problems in the prior art.

[0011] The objective of this invention is achieved through the following technical solution:

[0012] The dual-synchronous coordinate system phase-locked loop optimization strategy of the present invention includes a Clarke transform unit, a Park transform unit, an iPark transform unit, a positive-sequence decoupling network, a negative-sequence decoupling network, a low-pass filter, a PI regulator, and a frequency integration unit.

[0013] The optimization strategy includes the following steps:

[0014] When one or two phase voltage amplitudes are zero, the phase voltage with a non-zero amplitude is selected and locked using a single-phase phase-locked loop. After the phase-locked loop is completed, the frequency of the single-phase phase-locked loop is assigned to the integral of the PI regulator of the three-phase phase-locked loop, so that the dual synchronous coordinate system phase-locked loop jumps out of the pseudo steady state.

[0015] When the amplitudes of the three-phase voltages are not zero, the three-phase voltages undergo Clarke transformation to obtain the α-phase voltage and β-phase voltage. The α-phase voltage is divided by the β-phase voltage, and the arctangent is taken to obtain the grid voltage angle. The grid frequency is obtained by differentiating the angle. The frequency is assigned to the integral of the PI regulator of the three-phase phase-locked loop, so that the dual synchronous coordinate system phase-locked loop jumps out of the pseudo-steady state.

[0016] Compared with existing technologies, the dual-synchronous coordinate system phase-locked loop optimization strategy provided by this invention solves the problem of the dual-synchronous decoupled coordinate system phase-locked loop entering a pseudo-steady state during startup. Different strategies are adopted based on different voltage conditions, effectively preventing the dual-synchronous coordinate system phase-locked loop from entering a pseudo-steady state. Attached Figure Description

[0017] Figure 1 This is a dual-synchronous coordinate system phase-locked loop structure provided in an embodiment of the present invention;

[0018] Figure 2 The flowchart for optimizing the dual-synchronous coordinate system phase-locked loop is provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0020] First, the following explanations are provided for the terms that may be used in this article:

[0021] The terms “including,” “contains,” “comprising,” “having,” or other similar semantic descriptions shall be interpreted as non-exclusive inclusion.

[0022] The contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Where the manufacturers of the reagents or instruments used in the embodiments of this invention are not specified, they are all conventional products that can be purchased commercially.

[0023] The dual-synchronous coordinate system phase-locked loop optimization strategy of the present invention includes a Clarke transform unit, a Park transform unit, an iPark transform unit, a positive-sequence decoupling network, a negative-sequence decoupling network, a low-pass filter, a PI regulator, and a frequency integration unit.

[0024] The optimization strategy includes the following steps:

[0025] When one or two phase voltage amplitudes are zero, the phase voltage with a non-zero amplitude is selected and locked using a single-phase phase-locked loop. After the phase-locked loop is completed, the frequency of the single-phase phase-locked loop is assigned to the integral of the PI regulator of the three-phase phase-locked loop, so that the dual synchronous coordinate system phase-locked loop jumps out of the pseudo steady state.

[0026] When the amplitudes of the three-phase voltages are not zero, the three-phase voltages undergo Clarke transformation to obtain the α-phase voltage and β-phase voltage. The α-phase voltage is divided by the β-phase voltage, and the arctangent is taken to obtain the grid voltage angle. The grid frequency is obtained by differentiating the angle. The frequency is assigned to the integral of the PI regulator of the three-phase phase-locked loop, so that the dual synchronous coordinate system phase-locked loop jumps out of the pseudo-steady state.

[0027] The integral value of the PI regulator refers to the output frequency of the phase-locked loop.

[0028] In summary, the dual-synchronous coordinate system phase-locked loop optimization strategy of this invention solves the problem of the dual-synchronous decoupled coordinate system phase-locked loop entering a pseudo-steady state during startup, and determines different response strategies according to different voltage conditions. This effectively prevents the dual-synchronous coordinate system phase-locked loop from entering a pseudo-steady state.

[0029] To more clearly demonstrate the technical solution and its effects provided by the present invention, the embodiments of the present invention will be described in detail below with reference to specific examples.

[0030] Example 1

[0031] like Figure 1 As shown:

[0032] This is a block diagram of a phase-locked loop in a dual-synchronous coordinate system. The diagram includes Clarke transform, Park transform, iPark transform, positive-sequence decoupling network, negative-sequence decoupling network, low-pass filter, PI regulator, frequency integral, etc.

[0033] Figure 2The flowchart shows the optimization strategy for the dual-synchronous coordinate system phase-locked loop.

[0034] When one or two phase voltage amplitudes are zero, a single-phase phase-locked loop (PLL) is used to lock the voltage of the phase with a non-zero amplitude. After the PLL is completed, the frequency of the single-phase PLL is assigned to the integral of the PI regulator of the three-phase PLL (for the PLL output frequency), causing the dual-synchronous coordinate system PLL to exit the pseudo-steady state. When the amplitudes of the three phase voltages are not zero, the three phase voltages undergo Clarke transformation to obtain the α-phase voltage and β-phase voltage. The α-phase voltage is divided by the β-phase voltage, and the arctangent is taken to obtain the grid voltage angle. The derivative of the angle is used to obtain the grid frequency, which is assigned to the integral of the PI regulator of the three-phase PLL (for the PLL output frequency), causing the dual-synchronous coordinate system PLL to exit the pseudo-steady state.

[0035] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A dual-synchronous coordinate system phase-locked loop optimization strategy, characterized in that, This includes Clarke transform unit, Park transform unit, iPark transform unit, positive-sequence decoupling network, negative-sequence decoupling network, low-pass filter, PI regulator, and frequency integral unit; The optimization strategy includes the following steps: When one or two phase voltage amplitudes are zero, the phase voltage with a non-zero amplitude is selected and locked using a single-phase phase-locked loop. After the phase-locked loop is completed, the frequency of the single-phase phase-locked loop is assigned to the integral of the PI regulator of the three-phase phase-locked loop, so that the dual synchronous coordinate system phase-locked loop jumps out of the pseudo steady state. When the amplitudes of the three-phase voltages are not zero, the three-phase voltages undergo Clarke transformation to obtain the α-phase voltage and β-phase voltage. The α-phase voltage is divided by the β-phase voltage, and the arctangent is taken to obtain the grid voltage angle. The grid frequency is obtained by differentiating the angle. The frequency is assigned to the integral of the PI regulator of the three-phase phase-locked loop, so that the dual synchronous coordinate system phase-locked loop jumps out of the pseudo-steady state.

2. The dual-synchronous coordinate system phase-locked loop optimization strategy according to claim 1, characterized in that, The integral value of the PI regulator refers to the output frequency of the phase-locked loop.

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