Calibration and data synchronization method for multiple AD9361 interfaces

Abstract

The invention particularly relates to a calibration and data synchronization method for multiple AD9361 interfaces, which comprises the following steps: acquiring a digital interface propagation delay difference between a master chip and a slave chip, and quantifying the digital interface propagation delay difference into an integer delay difference value; in a receiving link verification state, performing multi-chip cooperative selection of a first receiving interface delay parameter in combination with the delay difference, and writing the first receiving interface delay parameter into the chip; under the condition that the parameter is kept unchanged, scanning the FPGA side IDELAY line by line) to obtain a second receiving interface delay parameter, and configuring the FPGA; in a transmitting link verification state, cooperatively determining a delay parameter of a first transmitting interface and writing the delay parameter into a chip, and scanning a delay parameter from an ODELAY on an FPGA side to a second transmitting interface line by line if necessary; and after the configuration is completed, executing cross-chip synchronism verification and outputting a result. Through staged calibration on the chip side and the FPGA side and introduction of time delay difference for collaborative alignment, the success rate and stability of time sequence training of multiple interfaces are improved, the inconsistency of arrival time between channels and the error code risk are reduced, and reliable synchronization of multi-chip baseband data is realized.

Description

Technical Field

[0001] This invention relates to the field of chip data synchronization technology, specifically to a method for interface calibration and data synchronization of multiple AD9361 chips. Background Technology

[0002] The AD9361 is an integrated transceiver with a zero-IF architecture, featuring flexible operating frequencies and baseband data synchronization capabilities, making it suitable for Multiple-Input Multiple-Output (MIMO) systems. In MIMO applications, due to the AD9361 chip itself and the FPGA baseband processor, parallel data, clock, and other digital interface signals exhibit certain delay differences along different paths.

[0003] In existing technologies, the digital interface calibration mechanism of the AD9361 can only adjust the delay of the entire group of data lines by an equal amount, and cannot compensate for the delay differences between different data lines within the same group. When the interface data line rate is high, this difference will further compress the effective stable period of the data, increasing the risk of timing calibration failure.

[0004] Furthermore, in systems containing multiple AD9361 chips, the trace lengths from each chip to the FPGA are often not exactly equal. If each AD9361 still uses its own locally optimal delay parameters during timing training, inconsistent delay configurations will cause baseband data misalignment across chips, leading to data asynchrony issues among multiple chips.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] This invention provides a method for calibrating and synchronizing interfaces of multiple AD9361 chips, a computer-readable storage medium, and a computer program product, which can effectively overcome the defects existing in the prior art.

[0007] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0008] According to a first aspect of the present invention, a method for calibrating and synchronizing multiple AD9361 interfaces is provided, the method comprising: Obtain the digital interface delay difference between the master chip and the slave chip in a multi-chip RF transceiver system; wherein the number of master chips is less than the number of slave chips. When multiple RF transceiver chips are in the receive link verification state, based on the receive interface test path and the digital interface delay difference, joint receive timing adjustment is performed on the RF transceiver chip and the FPGA chip to obtain the first receive interface delay parameter of the RF transceiver chip and the second receive interface delay parameter of the FPGA chip. The receiving interfaces of the RF transceiver chip and the FPGA chip are configured using the first receiving interface delay parameter and the second receiving interface delay parameter, respectively. When the RF transceiver chip that has completed the receiving interface configuration is in the transmitting link verification state, based on the transmitting interface test path, the digital interface delay difference and the first receiving interface delay parameters, the RF transceiver chip and the FPGA chip are jointly adjusted for transmitting timing to obtain the first transmitting interface delay parameters of the RF transceiver chip and the second transmitting interface delay parameters of the FPGA chip. The transmission interfaces of the RF transceiver chip and the FPGA chip are configured using the first transmission interface delay parameter and the second transmission interface delay parameter, respectively. Perform cross-chip data synchronization verification on the RF transceiver chip and FPGA chip after the transmit interface configuration is completed; when the data synchronization verification is successful, it is determined that the data synchronization of multiple RF transceiver chips is successful.

[0009] In some exemplary embodiments, obtaining the digital interface delay difference between the master chip and the slave chip in a multi-chip radio frequency transceiver system includes: Based on the digital interface trace lengths of multiple RF transceiver chips and the signal propagation speed, determine the corresponding interface propagation delay for each RF transceiver chip. Obtain the delay difference between the propagation delay from the chip's interface and the propagation delay from the main chip's interface; The delay difference is obtained by rounding the delay difference using a preset rounding algorithm.

[0010] In some exemplary embodiments, the step of performing joint receive timing adjustment on the RF transceiver chip and the FPGA chip based on the receive interface test path and the digital interface delay difference to obtain the first receive interface delay parameter of the RF transceiver chip and the second receive interface delay parameter of the FPGA chip includes: Based on the test path of the receiving interface and the delay difference of the digital interface, collaborative receiving timing adjustment is performed on multiple RF transceiver chips to obtain the first receiving interface delay parameters corresponding to each RF transceiver chip. Following the test path of the receiving interface, the receiving timing of the FPGA chip is adjusted based on the delay parameters of the first receiving interface to obtain the delay parameters of the second receiving interface of the FPGA chip.

[0011] In some exemplary embodiments, the step of performing coordinated reception timing adjustment on multiple RF transceiver chips based on the receiver interface test path and the digital interface delay difference to obtain the first receiver interface delay parameter corresponding to each RF transceiver chip includes: The data reception delay level and clock reception delay level of each RF transceiver chip are combined and iterated to obtain multiple combinations of reception delay parameters. For multiple combinations of transmission delay parameters, the FPGA chip is used to perform detection and judgment on the test data received through the test path of the receiving interface to obtain the first judgment result; Based on the first determination result, generate timing detection results for the combination of receive delay parameters for each RF transceiver chip; Delay compensation is performed on the timing detection results of the combination of received delay parameters based on the delay difference of the digital interface; The combination of receive delay parameters that simultaneously passes the timing detection of the receive interfaces of all RF transceiver chips in the timing detection results of the compensated receive delay parameter combination is determined as the first receive interface delay parameter. The first receive interface delay parameter is written into the receive interface delay adjustment register of the corresponding RF transceiver chip, and the receive interface delay adjustment register is updated.

[0012] In some exemplary embodiments, the step of performing receive timing adjustment on the FPGA chip based on the first receive interface delay parameter according to the receive interface test path to obtain the second receive interface delay parameter of the FPGA chip includes: Configure the RF transceiver chip using any combination of receive delay parameters in the first receive interface delay parameters, and continuously send a preset pseudo-random test sequence to the FPGA chip based on the receive interface test path. Based on the preset pseudo-random test sequence received by the FPGA chip, the input delay unit corresponding to the receiving interface in the FPGA chip is tested line by line to obtain the range of delay levels that pass the test. Select the target delay level within the delay level range to obtain the delay parameters of the second receiving interface.

[0013] In some exemplary embodiments, the step of performing joint transmission timing adjustment on the RF transceiver chip and the FPGA chip based on the transmit interface test path, digital interface delay difference, and first receive interface delay parameters to obtain the first transmit interface delay parameters of the RF transceiver chip and the second transmit interface delay parameters of the FPGA chip includes: Based on the test path of the transmitting interface, the delay difference of the digital interface, and the delay parameters of the first receiving interface, collaborative transmission timing adjustment is performed on multiple RF transceiver chips to obtain the delay parameters of the first transmitting interface corresponding to each RF transceiver chip. Following the test path of the transmission interface, the transmission timing of the FPGA chip is adjusted based on the delay parameters of the first transmission interface to obtain the delay parameters of the second transmission interface of the FPGA chip.

[0014] In some exemplary embodiments, the step of performing coordinated transmission timing adjustment on multiple RF transceiver chips based on the transmit interface test path, digital interface delay difference, and first receive interface delay parameters to obtain the first transmit interface delay parameters corresponding to each RF transceiver chip includes: The transmit data delay level and transmit clock delay level of each RF transceiver chip are combined and traversed to obtain multiple transmit delay parameter combinations; For multiple combinations of transmission delay parameters, the FPGA chip is used to perform detection and judgment on the test data received through the transmission interface test path to obtain a second judgment result; Based on the second determination result, the timing detection results of the transmission delay parameter combination corresponding to each RF transceiver chip are generated; When it is determined from the timing detection results of the transmission delay parameter combination that any RF transceiver chip has failed the timing detection, another receiving delay parameter combination is selected from the first receiving interface delay parameters to adjust the receiving timing of the FPGA chip. When it is determined that all RF transceiver chips have passed the timing test based on the timing test results of the transmission delay parameter combination, delay compensation is performed on the timing results of the transmission delay parameter combination of each RF transceiver chip based on the digital interface delay difference. The transmission delay parameter combination that passes the timing detection of all RF transceiver chip transmission interfaces simultaneously and whose consecutive number of passes reaches a preset threshold is determined as the first transmission interface delay parameter. The first transmission interface delay parameter is written into the transmission interface delay adjustment register of the corresponding RF transceiver chip, and the transmission interface delay adjustment register is updated.

[0015] In some exemplary embodiments, the step of adjusting the transmission timing of the FPGA chip based on the first transmission interface delay parameter according to the transmission interface test path to obtain the second transmission interface delay parameter of the FPGA chip includes: Configure the RF transceiver chip using the delay parameters of the first transmitting interface; Based on the test path of the transmission interface, the radio frequency transceiver chip continuously sends a preset pseudo-random test sequence to the FPGA chip. Based on the preset pseudo-random test sequence received by the FPGA chip, the output delay unit corresponding to the transmitting interface in the FPGA chip is tested line by line to obtain the range of delay levels that pass the test. Select the target delay level within the delay level range to obtain the delay parameters for the second sending interface.

[0016] In some exemplary embodiments, the cross-chip data synchronization verification of the RF transceiver chip and FPGA chip after the transmission link configuration is completed includes: The RF transceiver chip that has completed the transmission link configuration is in a preset transmission mode and obtains a valid indication signal of the associated clock domain. When the valid indication signal and the processing clock meet the preset phase correspondence, the RF transceiver chip is controlled to enter the internal loopback state, and the FPGA chip is used to generate a data sequence for verification. When the data sequence returns to the FPGA chip via the internal loopback path, the FPGA chip performs cross-clock domain buffering on the returned data sequence and performs a consistency comparison on the buffered data sequence to obtain the comparison result. When the comparison results indicate that the data sequences corresponding to multiple RF transceiver chips are consistent, the data synchronization verification result is determined to be that the data synchronization verification of multiple RF transceiver chips has passed.

[0017] According to a second aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium including a stored executable program, wherein, when the executable program is executed, it controls the device where the storage medium is located to perform the above-described method for multi-chip AD9361 interface calibration and data synchronization.

[0018] According to a third aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the above-described method for calibrating and synchronizing interfaces of multiple AD9361 chips.

[0019] According to a fourth aspect of the present invention, an electronic device is provided, comprising: Processor; and Memory for storing the executable instructions of the processor; The processor is configured to implement the above-described method for calibrating and synchronizing interfaces of multiple AD9361 chips by executing the executable instructions.

[0020] The embodiments of the present invention provide a method for interface calibration and data synchronization of multiple AD9361 chips. By performing layered training that combines coarse timing adjustment on the AD9361 chips with fine line-by-line adjustment on the FPGA, and by coordinating and selecting a unified delay parameter among multiple AD9361 chips, the method compensates for cross-chip delay deviations caused by unequal trace lengths and device differences. This improves the calibration success rate and timing margin under high-speed LVDS source synchronization interface, ensures that the frame boundaries and sampling times of multiple AD9361 chips are consistent, and supports verification of synchronization status and automatic retraining for anomalies, thus achieving stable multi-chip baseband data synchronization.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0023] Figure 1 This schematically illustrates a timing diagram of LVDS in the prior art; Figure 2 This diagram illustrates the ADI timing training flowchart in the prior art. Figure 3 This schematically illustrates a flowchart of an exemplary embodiment of the present invention for a method of calibrating and synchronizing interfaces of multiple AD9361 chips; Figure 4 This diagram illustrates the connection method between AD9361 and FPGA in the prior art. Figure 5 The diagram illustrates the receiving interface test path and the sending interface test path in an exemplary embodiment of the present invention. Figure 6 This diagram illustrates an array shifting and addition method in the prior art. Figure 7 This schematic diagram illustrates the result of selecting the receive interface delay parameter in an FPGA according to an exemplary embodiment of the present invention. Figure 8 This schematic diagram illustrates the delay compensation result corresponding to the timing coarse adjustment of the transmission interface in an exemplary embodiment of the present invention. Figure 9 This diagram illustrates the AD9361's accompanying clock and FPGA clock in the prior art. Figure 10 This diagram illustrates a data synchronization verification structure as an exemplary embodiment of the present invention. Figure 11 This schematically illustrates an interface timing training flowchart of an exemplary embodiment of the present invention; Figure 12 This diagram illustrates a temporal non-convergence result in the prior art. Figure 13 A schematic diagram illustrating the data asynchrony phenomenon in the prior art; Figure 14AThis diagram illustrates a comparison of the RX timing training results of an exemplary embodiment of the present invention without (left) and with (right) the present invention. Figure 14B This diagram illustrates a comparison of the TX time-series training results of an exemplary embodiment of the present invention without (left) and with (right) the present invention. Figure 15 This schematic diagram illustrates the selection of a receiving interface delay value according to an exemplary embodiment of the present invention. Figure 16 This diagram illustrates a schematic representation of an exemplary embodiment of the present invention for verifying data synchronization. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0025] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0026] The AD9361 is a highly integrated RF transceiver chip that supports multi-channel synchronous applications. Its high-speed digital interface can be configured for Low-Voltage Differential Signaling (LVDS) source-synchronous parallel transmission, including two 12-bit data buses, frame synchronization signals (RX / TX FRAME), and accompanying data clocks (RX DATA_CLK, TX FB_CLK). Frame synchronization indicates sampling boundaries, and the data clock is a source-synchronous clock, supporting dual-edge sampling. Figure 1The diagram shown is an LVDS timing diagram. CLK_P / CLK_N are differential clocks (P / N are inverted); FRAME_P / FRAME_N are differential frame synchronizations (used to identify data boundaries / word alignment / channel alignment); D[5:0]_P / D[5:0]_N are 6-channel differential data, each with its own P / N. The AD9361 provides internal digital programmable delay adjustment capabilities, allowing adjustment of the relative timing of the data clock and data and frame synchronization signals to obtain sufficient setup and hold margins and complete interface calibration.

[0027] In a multi-channel system composed of multiple AD9361 chips and an FPGA, in addition to calibrating the interface timing between each chip and the FPGA, it is also necessary to ensure the alignment of data frame boundaries and sampling times between the chips. Due to factors such as differences in internal device paths, unequal PCB trace lengths, and increased operating speeds, the relative delays between parallel data lines and between chips can compress the data stability window. If only chip-side delay adjustment is relied upon, training failures or inconsistencies in alignment between chips may occur, leading to problems such as cross-chip data asynchrony.

[0028] FPGAs typically handle both AD9361 control and baseband processing functions simultaneously within a system: on one hand, they manage the unified configuration of multiple AD9361s via control buses such as SPI; on the other hand, they receive and transmit baseband data and perform multi-channel synchronization processing on a high-speed parallel digital interface. To improve interface timing calibration accuracy, the FPGA I / O side usually features programmable pin delay resources such as IDELAY / ODELAY, which allow for fine-grained adjustment of parallel data lines, frame synchronization, and related clocks line by line. This compensates for offsets caused by board-level trace and device differences, thereby increasing setup and hold time margins.

[0029] In existing technologies, the following methods are typically used for inter-chip interface calibration and data synchronization: (1) Source synchronization scheme based on PCB equal-length wiring and symmetrical layout During the hardware design phase, data traces between multiple AD9361 chips and the baseband processor should be planned with equal length and symmetry to reduce inconsistencies in arrival times between channels after multi-chip baseband synchronization (MCS) is completed. As a reference platform, the AD-FMCOMMS5-EBZ integrates two AD9361 chips, with symmetrical and equal-length data traces between them. ADI provides interface timing adjustment modes such as... Figure 2 As shown, when using multiple AD9361 chips, each chip is initialized independently. After MCS, the baseband processing clock of the slave chip is in phase with the clock of the master chip. Then, the delay value obtained by the master chip during initialization is filled into the slave chip.

[0030] (2) Delay adjustment scheme based on AD9361 chip A parameter-polling calibration process is based on the collaboration of the processor (PS side) and programmable logic (PL side). This method utilizes the AD9361's self-test and loopback capabilities: In the receiving direction, by setting the AD9361 to output a preset PN (pseudo-random) code, the processor side polls and modifies the receiving interface delay parameters, and the FPGA side performs correlation detection between the received code stream and the preset code group; in the transmitting direction, by configuring the loopback path, the FPGA generates preset data, sends it to the AD9361, and receives the loopback data, the processor side polls and modifies the transmitting interface delay parameters, and the FPGA side makes a decision between the loopback data and the preset data, thereby automating the interface calibration.

[0031] (3) Delay adjustment scheme of single-chip AD9361 and FPGA The traditional manual adjustment of IDELAY / ODELAY using VIO / ILA is transformed into a programmed automatic calibration. In the receiving direction, by configuring the AD9361 output pseudo-random binary sequence (PRBS) code, the FPGA side uses PN detection to determine if the current sampling is correct. The control flow traverses the AD9361 receive interface delay register and the FPGA input delay (IDELAY), recording the passed combinations as an array of available delays, and selecting the median value from the available window as the optimal configuration. In the transmitting direction, the AD9361 transmit interface delay register and the FPGA output delay (ODELAY) are traversed, filtering out the set of available delays and selecting the center value for configuration, thereby achieving automated, mass-producible interface timing calibration on a single board.

[0032] (4) Fixed delay scheme In scenarios where device layout and wiring are fixed, interface speed is low, and the operating environment is stable, a set of fixed delay parameters can be obtained by pre-measuring offline, and these parameters can be used directly after each power-on without performing dynamic calibration.

[0033] However, the above technical solution has the following drawbacks: (1) In the PCB design stage, strictly equal-length and symmetrical routing of parallel LVDS data lines between multiple AD9361s and FPGAs can indeed reduce the arrival time difference across channels. However, this solution is highly dependent on hardware design: in order to meet the matching requirements of multiple differential pairs, clock and frame signals, a large number of serpentine traces and routing channels are often required, which leads to an increase in PCB area and number of layers, forced expansion of device layout, and a significant increase in design and manufacturing costs. Moreover, as the number of AD9361s increases, the equal-length and symmetrical constraints become exponentially more difficult, making it difficult to balance compact layout and manufacturability. In addition, strict equal-length routing mainly compensates for board-level trace differences, but still cannot cover the relative offsets introduced by internal path differences, batch differences and temperature drift. Furthermore, AD9361 itself has limited independent delay compensation capability for a single line, so in higher line rates or more severe environments, problems such as insufficient interface margin, training failure or unstable cross-chip synchronization may still occur.

[0034] (2) In a multi-AD9361 system without strict equal-length design, if a "parameter polling" calibration process based on the collaboration of the processor (PS side) and programmable logic (PL side) is used, relying solely on the delay adjustment of the digital interface inside the AD9361 to achieve baseband synchronization will result in the system only being able to operate at a lower sampling rate, limiting the functionality and application potential of the same hardware. Configuring the baseband sampling rate of the AD9361 to a lower value reduces the digital interface uptime and widens the setup and hold time windows. Only when the differences in board-level traces and device paths between the parallel digital interfaces of multiple AD9361 chips are within the adjustable range of the AD9361 can the digital interfaces function normally.

[0035] An ADI application note statistically analyzed the delay distribution of the RX_DATA and RX_FRAME signals relative to the DATA_CLK signal on 300 AD9361 chips, revealing a maximum difference of 0.9ns between different interfaces. At higher data clock frequencies, such as 240MHz with dual-edge sampling, the theoretical maximum data settling time is 2.083ns. However, the delay differences and data change times between parallel data may prevent the simultaneous sampling of all data's settling periods, leading to digital interface training failures. Only by reducing the data clock frequency can the data settling time be improved, making it easier to acquire the stable data period.

[0036] (3) In transforming the traditional "manual adjustment of IDELAY / ODELAY using VIO / ILA" into a programmed automatic calibration method, this approach combines the internal delay register of AD9361 with the IDELAY / ODELAY on the FPGA side to form a set of available delays and takes the window value to obtain a larger timing margin. This method is suitable for automatic interface calibration of a single chip. However, in a multi-chip AD9361 system, if each chip is still independently traversed and the local optimal is selected as the target, it is difficult to guarantee global consistency alignment between multiple chips. Different chips may fall on different optimal sampling points, causing cross-chip data arrival time differences and frame boundary offsets. In addition, this method has too many adjustable combinations, which prolongs the power-on calibration time and is not conducive to system applications that require fast startup or frequent restarts.

[0037] (4) The fixed delay scheme relies on a set of delay parameters measured offline and used directly after power-on. This method has stringent prerequisites. According to the chip datasheet, the optimal delay of AD9361 is not the same for various interface rates. Enabling the chip's internal FIR filter will cause clock and data delays to shift. Once there are differences between the device and the carrier board, temperature drift, voltage changes, or interface rate adjustments, the fixed delay cannot adapt, which can easily cause the sampling point to deviate from the center of the data eye, resulting in bit errors, occasional desynchronization, or direct training failure under boundary conditions.

[0038] To address the shortcomings and deficiencies of existing technologies, this example embodiment provides a method for interface calibration and data synchronization of multiple AD9361 chips. (Reference) Figure 3 As shown, it can specifically include: Step S11: Obtain the digital interface delay difference between the master chip and the slave chip in the multiple RF transceiver chips; wherein the number of master chips is less than the number of slave chips. Step S12: When multiple RF transceiver chips are in the receiving link verification state, based on the receiving interface test path and the digital interface delay difference, joint receiving timing adjustment is performed on the RF transceiver chip and the FPGA chip to obtain the first receiving interface delay parameter of the RF transceiver chip and the second receiving interface delay parameter of the FPGA chip. Step S13: Configure the receiving interfaces of the RF transceiver chip and the FPGA chip respectively using the first receiving interface delay parameter and the second receiving interface delay parameter; Step S14: When the RF transceiver chip that has completed the receiving interface configuration is in the transmitting link verification state, based on the transmitting interface test path, the digital interface delay difference and the first receiving interface delay parameters, the RF transceiver chip and the FPGA chip are jointly adjusted for transmitting timing to obtain the first transmitting interface delay parameters of the RF transceiver chip and the second transmitting interface delay parameters of the FPGA chip. Step S15: Configure the transmission interfaces of the RF transceiver chip and the FPGA chip respectively using the first transmission interface delay parameter and the second transmission interface delay parameter; Step S16: Perform cross-chip data synchronization verification on the RF transceiver chip and FPGA chip that have completed the transmit interface configuration; when the data synchronization verification is passed, it is determined that the data synchronization of multiple RF transceiver chips is successful.

[0039] Based on steps S11 to S16 above, a layered training process combining coarse timing adjustment of the AD9361 with fine line-by-line adjustment of the FPGA is implemented. By coordinating and selecting a unified delay parameter among multiple AD9361 chips, cross-chip delay deviations caused by unequal trace lengths and device differences are compensated. This improves the calibration success rate and timing margin under the high-speed LVDS source synchronization interface, ensures that the frame boundaries and sampling times of multiple AD9361 chips are consistent, and supports the verification of synchronization status and automatic retraining for anomalies, thus achieving stable multi-chip baseband data synchronization.

[0040] The following will describe in more detail the steps of a method for calibrating and synchronizing interfaces of multiple AD9361 chips in this exemplary embodiment, with reference to the accompanying drawings and embodiments.

[0041] Example connection method of multiple AD9361s to FPGA Figure 4 As shown, Figure 4 This diagram illustrates the connection architecture between multiple AD9361 chips and an FPGA. The FPGA is on the right, and multiple AD9361 chips are connected on the left. Data transmission between the FPGA and each AD9361 chip is bidirectional via an LVDS digital baseband interface (BB I / F). Each AD9361 chip internally contains two links: RX / ADC and TX / DAC, connecting to external RF devices. Data flow between the chips includes the following two types: (1) Received data flow (RX direction): After passing through external radio frequency devices, the radio frequency signal enters the receiving link of the radio frequency transceiver chip. After the receiving link completes the radio frequency to digital conversion, it forms baseband received data. The baseband received data is transmitted from the radio frequency transceiver chip to the FPGA through the LVDS digital baseband interface, and the FPGA performs baseband processing.

[0042] (2) Transmit data flow (TX direction): The baseband transmission data generated or processed by the FPGA is transmitted from the FPGA to the transmit link of the RF transceiver chip via the LVDS digital baseband interface. After the transmit link completes the digital-to-RF conversion, it is output through the external RF circuit.

[0043] For example, in step S11, obtaining the digital interface delay difference between the master chip and the slave chip in a multi-chip RF transceiver system includes: Step S111: Determine the interface propagation delay of each RF transceiver chip based on the digital interface trace length of the multiple RF transceiver chips and the signal propagation speed. Step S112: Obtain the delay difference between the interface propagation delay of the chip and the interface propagation delay of the main chip; Step S113: The delay difference is rounded based on a preset rounding algorithm to obtain the digital interface delay difference.

[0044] The aforementioned RF transceiver chips are used to characterize RF transceiver integrated circuit chips with configurable high-speed digital interface timing. For example, the AD9361.

[0045] The aforementioned master chip is used to characterize the reference chip among multiple RF transceiver chips, and the slave chips are used to characterize the remaining RF transceiver chips other than the master chip. The master chip is randomly selected from the multiple RF transceiver chips. For example, the master chip is one RF transceiver chip randomly selected from the multiple RF transceiver chips. Optionally, when there are only two RF transceiver chips, the master chip is one of them.

[0046] Specifically, based on the trace length of the digital interface of m AD9361 chips on the PCB board. Calculate the interface propagation delay for each RF transceiver chip. The speed at which the signal propagates on the PCB board is... Where C is the speed of light. Indicates the dielectric constant of the surrounding environment. Interface propagation delay. One AD9361 chip is randomly selected from m AD9361 chips as the master chip. Using the master chip as a reference, the delay difference between the slave chip and the master chip is calculated. ,in, For the delay of the k-th slave chip, This is the delay of the main chip.

[0047] Using the AD9361's adjustment accuracy of 0.3ns / LSB as a unit, the integer delay difference between the slave chip and the master chip is calculated using a rounding method. This is then embedded in the program. For the same PCB model, the delay difference only needs to be calculated once, without needing to be recalculated.

[0048] For example, in step S12, the joint receiving timing adjustment of the RF transceiver chip and the FPGA chip based on the receiving interface test path and the digital interface delay difference, to obtain the first receiving interface delay parameter of the RF transceiver chip and the second receiving interface delay parameter of the FPGA chip, includes: Step S121: Based on the test path of the receiving interface and the delay difference of the digital interface, perform coordinated receiving timing adjustment on multiple RF transceiver chips to obtain the first receiving interface delay parameters corresponding to each RF transceiver chip. Step S122: According to the test path of the receiving interface, the receiving timing of the FPGA chip is adjusted based on the first receiving interface delay parameter to obtain the second receiving interface delay parameter of the FPGA chip.

[0049] Specifically, the system initialization begins. This involves powering on and resetting multiple AD9361 chips, performing SPI self-tests, frequency planning, and loading FIR coefficients. The IDELAY / ODELAY delays on the FPGA side are adjusted to the median value to reserve space for subsequent line-by-line positive and negative delay adjustments. During initialization, interface training-related functions are disabled to prevent training failures from affecting initialization. The FPGA has IDELAY and ODELAY delay adjustment modules with a certain adjustable range. For example, the tap value can be adjusted from 0 to 31. In this case, the FPGA-side IDELAY / ODELAY delay is adjusted to the median value of 15, allowing for positive and negative adjustments during subsequent timing fine-tuning. The tap value refers to the delay level number. IDELAY and ODELAY have a default tap value of 0. If this value is kept zero during initialization, subsequent fine-tuning will only increase the delay of that line, making it difficult to find the data center.

[0050] Then, baseband clock synchronization is performed on multiple AD9361 chips. After the AD9361 completes initialization and enters a controllable state, the FPGA distributes a synchronization pulse to ensure that the baseband clocks of each chip are running in the same phase, creating the initial conditions for subsequent cross-chip alignment.

[0051] Next, based on the receiving interface test path, and using the digital interface delay difference between the master chip and the slave chip as the basis for collaborative alignment, the timing of the receiving digital interface of multiple AD9361 chips is coordinated and adjusted. The receiving interface delay configuration that meets the receiving link verification requirements is determined among multiple AD9361 chips, and the receiving interface delay configuration is determined as the first receiving interface delay parameter corresponding to each AD9361. Finally, with the first receiving interface delay parameter configuration completed, the timing of the FPGA chip-side receiving link is adjusted according to the receiving interface test path to obtain an FPGA-side receiving timing configuration that matches the receiving interfaces of multiple AD9361 chips, and the FPGA-side receiving timing configuration is determined as the second receiving interface delay parameter.

[0052] For example, in step S121, the collaborative reception timing adjustment of multiple RF transceiver chips based on the receiver interface test path and the digital interface delay difference to obtain the first receiver interface delay parameter corresponding to each RF transceiver chip includes: Step S1211: Combine and traverse the receive data delay level and receive clock delay level of each RF transceiver chip to obtain multiple receive delay parameter combinations. Step S1212: For multiple combinations of transmission delay parameters, the FPGA chip is used to perform detection and judgment on the test data received through the test path of the receiving interface to obtain the first judgment result. Step S1213: Generate timing detection results of the combination of receiving delay parameters for each RF transceiver chip based on the first determination result; Step S1214: Perform delay compensation on the timing detection result of the combined receiving delay parameters based on the digital interface delay difference; Step S1215: Determine the combination of receiving delay parameters that simultaneously passes the timing detection of the receiving interfaces of all RF transceiver chips in the timing detection results of the compensated receiving delay parameter combination as the first receiving interface delay parameter, and write the first receiving interface delay parameter into the receiving interface delay adjustment register of the corresponding RF transceiver chip, and update the receiving interface delay adjustment register.

[0053] The above receiving interface test path is as follows: Figure 5 In path ①, the AD9361 outputs the PRBS sequence at the digital interface, and the FPGA implements a matched PN detector to quantify whether the sampled data is within the valid region of the data eye under the set of delay parameters.

[0054] Specifically, coarse timing tuning is performed on the receiving interface. The AD9361 contains two registers for adjusting the delay of the received data group and clock, respectively, each with 16 adjustable levels. A typical step value is 0.3ns / LSB, and the adjustable range is 4.8ns. The AD9361 is controlled via the SPI protocol to be in receive link verification mode. Based on the receive interface test path, all combinations of data delay and clock delay are traversed. The result of the PN detector on the FPGA side is recorded as 1, and a failed result is recorded as 0. All results are stored in a 16*16 matrix, generating the timing test results for the receive delay parameter combinations corresponding to each RF transceiver chip, recorded as follows: , where the matrix The horizontal axis represents the clock delay level, the vertical axis represents the data delay level, and k represents the chip serial number.

[0055] Delay compensation is performed on the timing detection results of the combined receiving delay parameters based on the digital interface delay difference to compensate for the delay difference between the receiving interfaces of different chips. An array is generated after compensating for the chip delay difference using a shift-addition method. . Given a 16-row, 16-column array, where rows represent clock delay levels and columns represent data reception delay levels. Iterate through the array. Coordinates with median value m And set the clock delay level and data delay level of m AD9361 chips. They are stored separately in their respective chips. Select... After obtaining the coordinates, the value written to the delay register of the AD9361 is the value before the shift and addition. The coordinates of all values ​​m in the array are denoted as m. , coordinate The corresponding combination of delay parameters is determined as the first receiving delay parameter.

[0056] The initialization pointer P points to the first set of receive delay parameters in the first receive delay parameters, and the clock delay level and data delay level are read and written to the delay adjustment register of m AD9361 chips via the SPI protocol. The common pass area usually has more than one point (e.g., j=7 and j=8 are both acceptable). Therefore, all points satisfying... The coordinates are recorded to form the delay parameters of the first receiving interface. P points to the first group of candidates and writes it first. If the subsequent (TX coarse adjustment / final synchronization verification) fails, P++ is performed, and the next group of candidates is tried again.

[0057] Further, refer to the array shifting and addition method. Figure 6 As shown, if when i=1, the second and third AD9361 chips... The values ​​are -1 and 1 respectively. The array is shifted one position to the right and one position to the left respectively, and the corresponding values ​​are added together to get the result. .

[0058] For example, in step S122, the step of adjusting the receiving timing of the FPGA chip based on the first receiving interface delay parameter according to the receiving interface test path to obtain the second receiving interface delay parameter of the FPGA chip includes: Step S1221: Configure the RF transceiver chip using any combination of receiving delay parameters in the first receiving interface delay parameters, and continuously send a preset pseudo-random test sequence to the FPGA chip based on the receiving interface test path. Step S1223: Based on the preset pseudo-random test sequence received by the FPGA chip, perform line-by-line delay detection on the input delay unit in the FPGA chip corresponding to the receiving interface to obtain the range of delay levels that pass the detection. Step S1223: Select the target delay level within the delay level range to obtain the delay parameters of the second receiving interface.

[0059] Specifically, the AD9361 is controlled via the SPI protocol to be in interface link verification mode, receiving the interface test path. The AD9361 outputs a PRBS sequence at the digital interface, and the FPGA detects the received PRBS sequence. The delay level of the IDELAY in the FPGA corresponding to the receiving digital interface of m AD9361s is adjusted line by line from small to large. The delay level passing through the detector is recorded, and the median value, i.e., the target delay level, is selected and written to the FPGA IDELAY.

[0060] For example, taking the data transmission line lane b corresponding to the AD9361 chip k as an example. First, set the IDELAY corresponding to lane b to tap=0, and wait for several receiving clock cycles to stabilize (tens to hundreds of cycles are sufficient). Then, run the PN detector to detect a statistical window (e.g., detect N PRBS blocks / or accumulate a certain number of word errors). If the error rate is 0 or lower than the threshold, record it as 0 (PASS); otherwise, record it as # (FAIL). Then, sequentially set the tap to the maximum value. After scanning, obtain the PASS interval of lane b, take the median tap of the PASS interval, which is the target delay level, write it back and lock it. The delay value corresponding to the target delay level is the delay parameter of the second receiving interface. Regarding the tap value, a loading mode is used. During preparation, it is loaded to the median value; in the line-by-line scanning step, the tap is loaded to the minimum value to determine whether the PN detector passes; then, it is sequentially loaded from the minimum tap value to the maximum value, thus forming an interval; finally, the tap value is loaded to the median value of the passed interval.

[0061] The result of selecting the delay parameter for the IDELAY receiver interface in the FPGA is as follows: Figure 7 As shown in the image. Figure 7 In the text, "#" indicates that the timing training failed, "o" indicates that it passed, and "O" indicates the median value of the final selected delay level.

[0062] For example, in step 14, the joint transmission timing adjustment of the RF transceiver chip and the FPGA chip based on the transmit interface test path, the digital interface delay difference, and the first receive interface delay parameters, to obtain the first transmit interface delay parameters of the RF transceiver chip and the second transmit interface delay parameters of the FPGA chip, includes: Step 141: Based on the test path of the transmitting interface, the delay difference of the digital interface and the delay parameters of the first receiving interface, perform coordinated transmission timing adjustment on multiple RF transceiver chips to obtain the first transmission interface delay parameters corresponding to each RF transceiver chip. Step 142: Following the test path of the transmission interface, perform transmission timing adjustment on the FPGA chip based on the first transmission interface delay parameter to obtain the second transmission interface delay parameter of the FPGA chip.

[0063] For example, in step S141, the collaborative transmission timing adjustment of multiple RF transceiver chips based on the transmit interface test path, digital interface delay difference, and first receive interface delay parameters to obtain the first transmit interface delay parameters corresponding to each RF transceiver chip includes: Step S1411: Combine and traverse the data transmission delay level and clock transmission delay level of each RF transceiver chip to obtain multiple combinations of transmission delay parameters. Step S1412: For multiple combinations of transmission delay parameters, the FPGA chip is used to perform detection and judgment on the test data received through the transmission interface test path to obtain a second judgment result. Step S1413: Generate timing detection results of transmission delay parameter combinations for each RF transceiver chip based on the second determination result; Step S1414: When it is determined from the timing detection result of the transmission delay parameter combination that any radio frequency transceiver chip has failed the timing detection, another receiving delay parameter combination is selected from the first receiving interface delay parameters to adjust the receiving timing of the FPGA chip. Step S1415: When it is determined that all RF transceiver chips have passed the timing test based on the timing test results of the transmission delay parameter combination, delay compensation is performed on the timing results of the transmission delay parameter combination of each RF transceiver chip based on the digital interface delay difference. Step S1416: The transmission delay parameter combination that passes the timing detection of all RF transceiver chip transmission interfaces simultaneously and whose consecutive number of passes reaches a preset threshold is determined as the first transmission interface delay parameter. The first transmission interface delay parameter is written into the transmission interface delay adjustment register of the corresponding RF transceiver chip, and the transmission interface delay adjustment register is updated.

[0064] Specifically, the test path for the above sending interface is as follows: Figure 5 In path ②, the FPGA generates the PRBS sequence; the PRBS is then fed from the FPGA to the AD9361's TX digital interface. Since the AD9361 does not have an internal PN detector, a matching PN detector needs to be implemented on the FPGA to quantify whether the data is within the valid region of the data eye under the given delay parameters. The AD9361 internally performs digital loopback on the received data; the loopback data is then output from the AD9361's RX digital interface to the FPGA; the FPGA uses a PRBS Monitor (PN detector) for verification.

[0065] Specifically, coarse timing adjustments are performed on the transmit interface. The AD9361 is controlled via the SPI protocol to be in transmit link verification mode, and the registers within the AD9361 used to adjust transmit data groups and clock delays are adjusted. All combinations of data delay levels and clock delay levels are iterated through. The result of the PN detector on the FPGA side is 1, and a result of 0 indicates failure. All results are stored in a 16*16 matrix to generate the timing detection results for the transmit delay parameter combinations corresponding to each RF transceiver chip, denoted as... When based on If it is determined that any RF transceiver chip fails the timing test, another receiving delay combination is selected from the first receiving interface delay parameters to adjust the receiving timing of the FPGA chip. After the second receiving interface parameters are determined, the transmitting interface is then coarsely adjusted for timing.

[0066] Delay compensation is performed on the timing detection results of the combined transmission delay parameters based on the digital interface delay difference to compensate for the delay difference between the transmission interfaces of the chips. An array is generated after compensating for the chip delay difference using a shift-addition method. . Given a 16-row, 16-column array, where rows represent clock delay levels and columns represent data transmission delay levels. Iterate through arrays with the same clock delay... Let m be the initial coordinates and the number of consecutive values ​​of m. This can be obtained using a sorting method. and ,in, The coordinates are the coordinates corresponding to the delay combination with the minimum delay and the maximum number of consecutive passes. for The corresponding number of consecutive passes, i.e., the number of consecutive passes of m, will be the delay level coordinates. The corresponding delay value is written into the TX delay register of AD9361.

[0067] refer to Figure 8 As shown. Figure 8 This is the delay compensation result corresponding to the coarse timing adjustment of the sending interface. The delay result is selected using coordinates. for This result represents the value that can be passed through continuous values ​​with the least delay. The value is 3, therefore the delay level coordinates are... The delay level is shown in the red box in the figure.

[0068] Furthermore, depending on the BANK where the sending interface is located, it can be divided into HP BANK and HR BANK. The two IOBs have structural differences. HR BANK does not have an ODELAY module with adjustable delay on the output. This structure is directly used for subsequent synchronization verification. HP BANK has an ODELAY module with adjustable delay on the output. This structure allows for fine adjustment of the subsequent sending timing.

[0069] For example, in step S142, the step of adjusting the transmission timing of the FPGA chip based on the first transmission interface delay parameter according to the transmission interface test path to obtain the second transmission interface delay parameter of the FPGA chip includes: Step S1421: Configure the RF transceiver chip using the delay parameters of the first transmitting interface; Step S1422: Based on the test path of the transmission interface, the preset pseudo-random test sequence is continuously sent to the FPGA chip using the radio frequency transceiver chip; Step S1423: Based on the preset pseudo-random test sequence received by the FPGA chip, perform line-by-line delay detection on the output delay unit corresponding to the sending interface in the FPGA chip to obtain the range of delay levels that pass the detection. Step S1424: Select the target delay level within the delay level range to obtain the delay parameters of the second sending interface.

[0070] Specifically, the AD9361 is controlled to be in transmit link verification state via the SPI protocol. Based on the transmit interface test path, the AD9361 outputs a PRBS sequence at the digital interface, and the FPGA detects the received PRBS code. The delay level of the ODELAY corresponding to the receive digital interface of m AD9361 chips in the FPGA is adjusted line by line from small to large. The delay level passing through the detector is recorded, and the median value, i.e., the target delay level, is selected. The delay value corresponding to the target delay level is written into the FPGA ODELAY.

[0071] For example, in step S16, the cross-chip data synchronization verification of the RF transceiver chip and FPGA chip after the transmission link configuration is completed includes: Step S161: Control the RF transceiver chip that has completed the transmission link configuration to be in the preset transceiver mode and obtain the valid indication signal of the associated clock domain. Step S162: When the valid indication signal and the processing clock meet the preset phase correspondence, control the RF transceiver chip to enter the internal loopback state, and use the FPGA chip to generate a data sequence for verification. Step S163: When the data sequence returns to the FPGA chip via the internal loopback path, the FPGA chip is used to cache the returned data sequence across clock domains, and a consistency comparison is performed on the cached data sequence to obtain the comparison result. Step S164: When the comparison result indicates that the data sequences corresponding to the multiple RF transceiver chips are consistent, the data synchronization verification result is determined to be that the data synchronization verification of the multiple RF transceiver chips has passed.

[0072] Specifically, when the AD9361 is in 2T2R mode, the timing is as follows: Figure 9 As shown, the data and valid signals are in the AD9361_CLK clock domain and change every 4 clock cycles. The FPGA's internal signal processing clock, FPGA_CLK, has a period four times that of AD9361_CLK, and their phase relationship changes randomly each time power is applied, causing... Figure 9 The uncertainty of FIFO data delay is addressed by adjusting the FPGA_CLK phase upon each power-on to maintain a fixed relationship with the valid signal, thereby stabilizing the FIFO delay.

[0073] By setting m AD9361 chips to internal loopback mode via the SPI bus, the data synchronization verification structure in the FPGA is as follows: Figure 10 As shown, the Incrementer module generates incremental data for verifying synchronization. An asynchronous FIFO is used for cross-clock domain communication between the AD9361's accompanying clock and the FPGA signal processing clock, transmitting the incremental data to m AD9361 chips. The received data, looped back from the AD9361, is transmitted to the Monitor module via the asynchronous FIFO to compare the data synchronization between the m AD9361 chips. If synchronized, it outputs 1, indicating system interface calibration and data synchronization are complete; if not synchronized, it jumps to multi-chip baseband clock synchronization for adjustment. After completion, it switches back to normal operating mode and can re-call the data synchronization verification as needed after prolonged system operation to determine if the chips are synchronized.

[0074] The method provided in the embodiments of the present invention, with reference to Figure 11 As shown. Figure 11 This is an overall flowchart of an embodiment of the present invention. Figure 11 The document demonstrates the complete closed-loop steps for interface calibration and synchronous verification of multiple AD9361 chips with an FPGA. The process is as follows: First, preliminary preparations are performed. This includes obtaining the digital interface delay difference, system initialization, and baseband clock synchronization.

[0075] Then, timing adjustments are performed on the receiving interface. Coarse timing adjustments are made to the receiving interface based on the receiving interface test path, and the results are compensated using the digital interface delay difference to obtain the first receiving interface delay parameters for each RF transceiver chip. Following the receiving interface test path, fine timing adjustments are performed on the FPGA chip based on the first receiving interface delay parameters to obtain the second receiving interface delay parameters for the FPGA chip.

[0076] Next, timing adjustments are performed on the transmitting interface. Based on the transmitting interface test path, coarse timing adjustments are made to the transmitting interface, and the success of the training is determined. If not, a new receiving improvement timing value is selected, and the process returns to fine-tuning of the receiving interface for further iteration. If successful, the digital interface delay difference is used to compensate for the coarse timing adjustment results, obtaining the first transmitting interface delay parameters for each RF transceiver chip. For the FPGA, it is determined whether ODELAY is present. If so, fine-tuning of the FPGA chip's timing is performed based on the first transmitting interface delay parameters, following the receiving interface test path, to obtain the second transmitting interface delay parameters for the FPGA chip. If not, this step is skipped, and data synchronization is directly verified.

[0077] Finally, a synchronization verification is performed. If the comparison results indicate that the data sequences corresponding to the multiple RF transceiver chips are consistent, the data synchronization verification result is considered successful. If the synchronization verification fails, the iteration continues from baseband clock synchronization.

[0078] Simulation experiments were conducted using the method provided in the embodiments of the present invention. The carrier used in this invention is an architecture design of a single ZYNQ7100 chip and seven AD9361 chips. In this design, the digital interfaces of the six AD9361 chips requiring baseband synchronization and the baseband processor are not designed with equal length.

[0079] Prior to this invention, a delay adjustment scheme based on the AD9361 chip was used, which limited the digital interface clock to 40MHz. When operating at higher frequencies, such as 240MHz, the digital interface timing training failed to converge, resulting in bit errors. (Refer to...) Figure 12 As shown, the presence of numerous abnormal spikes indicates that there are occasional errors in the sampling link.

[0080] A delay adjustment scheme using a single AD9361 chip and an FPGA is employed. When selecting the delay for the digital interface between multiple AD9361 chips and the baseband processor, the local delay of each chip is used as the basis. Occasionally, inappropriate delay selection occurs, leading to cross-chip data asynchrony. For example... Figure 13 As shown. Figure 13This diagram illustrates a data asynchrony between two AD9361 chips. `adc_dat_i0` and `adc_dat_q0` represent the data received by the first AD9361 chip, `adc_dat_i1` and `adc_dat_q1` represent the data received by the second AD9361 chip, and the `adc_valid_i0` and `adc_valid_q0` signals indicate the start of data transmission. Figure 13 As shown, the second AD9361 uses itself as a reference to select the delay level, causing the sampling point to fall into the next data. The parsed data of the second AD9361 is one clock cycle slower than that of the first AD9361, resulting in data asynchrony.

[0081] refer to Figure 14A and Figure 14B As shown. Figure 14A and Figure 14B The timing training results of a single AD9361 chip without and with this invention are given respectively. The horizontal axis represents the clock delay level, and the vertical axis represents the data delay level. "o" indicates that timing training was successful under the current delay, and "#" indicates that timing training was unsuccessful under the current delay. Figure 14A In the diagram, the left image shows the RX timing training results without using this invention, and the right image shows the RX timing training results with using this invention. The RX timing data is improved from 51 points to 94 points. Figure 14B In the diagram, the left image shows the TX timing training results without using this invention, and the right image shows the TX timing training results with this invention. The number of passable TX timing training points increased from zero to 62, and the timing adjustment accuracy improved from 0.3ns to 78ps. The parameters used were: AD9361 configured in a two-transmit, two-receive mode, sampling rate of 60MHz, LVDS accompanying clock frequency of 240MHz, and FIR enabled.

[0082] refer to Figure 15 As shown. Figure 15 The timing detection results are the combined parameters of the compensated receive delay. In the current carrier, there are 6 AD9361 chips requiring baseband synchronization, therefore m is 6. The delay differences between the slave chip and the master chip are 1, 3, 1, 0, and -1, respectively. Figure 15 The display shows a total of 19 available receive delay levels ( ).

[0083] refer to Figure 16 As shown. Figure 16To apply the synchronization verification results of this invention, when the AD9361 is adjusted to internal loopback mode, the Incrementer module generates incremental data to verify synchronization. After passing through the FPGA's internal data path and data interface, the Monitor module compares the sampled data. If multiple data streams are the same, the Sync_Succ signal is pulled high to indicate that the data are different; if the data are unequal, the Sync_Succ signal is pulled high.

[0084] As described above, compared to the AD9361 chip-based delay adjustment scheme, this invention introduces FPGA IDELAY / ODELAY line-by-line scanning and takes the median value of the passed interval to center the sampling point, significantly improving the setup / hold margin at high line rates and reducing the probability of bit errors. When using a Xilinx 7 series FPGA, the timing adjustment accuracy is improved from 0.3 ns to 78 ps, and the resolution is improved by approximately 3.8 times. Using the AD9361 chip-based delay adjustment scheme, the digital interface can only operate at a lower clock frequency. With this invention, the digital interface can operate at full speed of 245.76MHz, with a setup / hold margin of approximately 0.6 ns.

[0085] While the single-chip AD9361 and FPGA joint traversal delay scheme introduces FPGA delay and can take the center value, it generally still completes calibration by obtaining the optimal window independently for each chip, lacking cross-chip consistency constraints. This invention further proposes a multi-chip collaborative delay selection strategy: each chip is aligned and intersected according to the master-slave delay difference through the matrix, and a unified delay parameter that satisfies the simultaneous passage of multiple chips is selected, ensuring frame-level alignment of multiple chips on the FPGA side; simultaneously, this invention incorporates the PCB trace length difference as a selection constraint into the joint screening process, so that even if the board length cannot be strictly equal, the algorithm can still place multiple chips within the same sampling window; in terms of interface calibration efficiency, this scheme requires running... This process involves multiple adjustments to select the optimal timing sequence. However, using the hierarchical adjustment method described in this invention requires running... The adjustment is performed once, where k is the number of rollbacks. When k=1, only 960 runs are required, which significantly improves the running efficiency.

[0086] The data synchronization verification module of this invention can verify the cross-chip data alignment status of multiple AD9361 chips after interface delay calibration. This module can verify whether the calibration results truly achieve cross-chip alignment during system initialization, and can also trigger online re-checks as needed after long-term device operation or configuration switching. Once asynchrony is detected, it can revert to the synchronization calibration process for retraining, achieving timely detection and automatic recovery of synchronization mismatch, significantly improving the long-term synchronization reliability of multi-AD9361 systems under complex operating conditions.

[0087] The beneficial effects of this invention are as follows: (1) Layered joint calibration mechanism: This scheme proposes a digital interface calibration process for multiple AD9361 chips and FPGA. The AD9361 side completes the coarse timing adjustment of the interface, and the FPGA side uses the programmable pin delay resources to complete the fine adjustment of the parallel bus line by line and the centering of the sampling point, thereby improving the training success rate and timing margin of the LVDS source synchronization interface.

[0088] (2) Multi-chip collaborative delay selection strategy: In view of the unequal length of the traces from multiple AD9361 chips to the FPGA and the internal differences of the devices, a "delay pass-through matrix" for each AD9361 chip is established. The matrices are aligned and superimposed according to the board-level propagation delay difference between the master and slave chips. The delay combination that satisfies multiple chips is selected to avoid the inconsistency between the cross-chip frame boundary and the sampling time caused by the independent selection of points by each chip.

[0089] (3) Cross-chip synchronization verification: Design a data synchronization verification structure. Under the condition of multiple AD9361 internal loopback, the FPGA generates verifiable incremental data, which is sent to each chip across the clock domain via asynchronous FIFO and read back for comparison to determine whether the data of multiple chips are consistent. When the synchronization is detected, it triggers a rollback to the synchronization calibration process for retraining, so as to realize the verifiability and recoverability of the synchronization state.

[0090] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may, for example, be executed synchronously or asynchronously in multiple modules.

[0091] It should be noted that although several modules or units of the device for performing actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0092] It should be noted that the storage medium shown in the embodiments of the present invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, wherein computer-readable program code is carried. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any storage medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the storage medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0093] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0094] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0095] It should be noted that, as another aspect, this application also provides a storage medium, which may be included in an electronic device or may exist independently without being assembled into the electronic device. The aforementioned storage medium carries one or more programs, which, when executed by an electronic device, cause the electronic device to perform the methods described in the following embodiments. For example, the electronic device may perform... Figure 1 The steps of the method shown.

[0096] In one embodiment, this application provides a computer program product including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0097] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0098] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0099] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for interface calibration and data synchronization of multiple AD9361 chips, characterized in that, The method includes: Obtain the digital interface delay difference between the master chip and the slave chip in a multi-chip RF transceiver system; wherein the number of master chips is less than the number of slave chips. When multiple RF transceiver chips are in the receive link verification state, based on the receive interface test path and the digital interface delay difference, joint receive timing adjustment is performed on the RF transceiver chip and the FPGA chip to obtain the first receive interface delay parameter of the RF transceiver chip and the second receive interface delay parameter of the FPGA chip. The receiving interfaces of the RF transceiver chip and the FPGA chip are configured using the first receiving interface delay parameter and the second receiving interface delay parameter, respectively. When the RF transceiver chip that has completed the receiving interface configuration is in the transmitting link verification state, based on the transmitting interface test path, the digital interface delay difference and the first receiving interface delay parameters, the RF transceiver chip and the FPGA chip are jointly adjusted for transmitting timing to obtain the first transmitting interface delay parameters of the RF transceiver chip and the second transmitting interface delay parameters of the FPGA chip. The transmission interfaces of the RF transceiver chip and the FPGA chip are configured using the first transmission interface delay parameter and the second transmission interface delay parameter, respectively. Perform cross-chip data synchronization verification on the RF transceiver chip and FPGA chip after the transmit interface configuration is completed; when the data synchronization verification is successful, it is determined that the data synchronization of multiple RF transceiver chips is successful.

2. The method according to claim 1, characterized in that, The process of obtaining the digital interface delay difference between the master chip and the slave chip in a multi-chip RF transceiver system includes: Based on the digital interface trace lengths of multiple RF transceiver chips and the signal propagation speed, determine the corresponding interface propagation delay for each RF transceiver chip. Obtain the delay difference between the propagation delay from the chip's interface and the propagation delay from the main chip's interface; The delay difference is obtained by rounding the delay difference using a preset rounding algorithm.

3. The method according to claim 1, characterized in that, The method involves performing joint receiving timing adjustment on the RF transceiver chip and the FPGA chip based on the receiving interface test path and the digital interface delay difference, to obtain the first receiving interface delay parameters of the RF transceiver chip and the second receiving interface delay parameters of the FPGA chip, including: Based on the test path of the receiving interface and the delay difference of the digital interface, collaborative receiving timing adjustment is performed on multiple RF transceiver chips to obtain the first receiving interface delay parameters corresponding to each RF transceiver chip. Following the test path of the receiving interface, the receiving timing of the FPGA chip is adjusted based on the delay parameters of the first receiving interface to obtain the delay parameters of the second receiving interface of the FPGA chip.

4. The method according to claim 3, characterized in that, The method involves performing coordinated reception timing adjustment on multiple RF transceiver chips based on the receiver interface test path and the digital interface delay difference to obtain the first receiver interface delay parameters corresponding to each RF transceiver chip, including: The data reception delay level and clock reception delay level of each RF transceiver chip are combined and iterated to obtain multiple combinations of reception delay parameters. For multiple combinations of transmission delay parameters, the FPGA chip is used to perform detection and judgment on the test data received through the test path of the receiving interface to obtain the first judgment result; Based on the first determination result, generate timing detection results for the combination of receive delay parameters for each RF transceiver chip; Delay compensation is performed on the timing detection results of the combination of received delay parameters based on the delay difference of the digital interface; The combination of receive delay parameters that simultaneously passes the timing detection of the receive interfaces of all RF transceiver chips in the timing detection results of the compensated receive delay parameter combination is determined as the first receive interface delay parameter. The first receive interface delay parameter is written into the receive interface delay adjustment register of the corresponding RF transceiver chip, and the receive interface delay adjustment register is updated.

5. The method according to claim 4, characterized in that, The step of adjusting the receiving timing of the FPGA chip according to the receiving interface test path and based on the first receiving interface delay parameter to obtain the second receiving interface delay parameter of the FPGA chip includes: Configure the RF transceiver chip using any combination of receive delay parameters in the first receive interface delay parameters, and continuously send a preset pseudo-random test sequence to the FPGA chip based on the receive interface test path. Based on the preset pseudo-random test sequence received by the FPGA chip, the input delay unit corresponding to the receiving interface in the FPGA chip is tested line by line to obtain the range of delay levels that pass the test. Select the target delay level within the delay level range to obtain the delay parameters of the second receiving interface.

6. The method according to claim 1, characterized in that, The method involves performing joint transmission timing adjustment on the RF transceiver chip and the FPGA chip based on the transmit interface test path, digital interface delay difference, and first receive interface delay parameters, to obtain the first transmit interface delay parameters of the RF transceiver chip and the second transmit interface delay parameters of the FPGA chip, including: Based on the test path of the transmitting interface, the delay difference of the digital interface, and the delay parameters of the first receiving interface, collaborative transmission timing adjustment is performed on multiple RF transceiver chips to obtain the delay parameters of the first transmitting interface corresponding to each RF transceiver chip. Following the test path of the transmission interface, the transmission timing of the FPGA chip is adjusted based on the delay parameters of the first transmission interface to obtain the delay parameters of the second transmission interface of the FPGA chip.

7. The method according to claim 6, characterized in that, The method involves performing coordinated transmission timing adjustment on multiple RF transceiver chips based on the transmit interface test path, digital interface delay difference, and first receive interface delay parameters to obtain the first transmit interface delay parameters corresponding to each RF transceiver chip, including: The transmit data delay level and transmit clock delay level of each RF transceiver chip are combined and traversed to obtain multiple transmit delay parameter combinations; For multiple combinations of transmission delay parameters, the FPGA chip is used to perform detection and judgment on the test data received through the transmission interface test path to obtain a second judgment result; Based on the second determination result, the timing detection results of the transmission delay parameter combination corresponding to each RF transceiver chip are generated; When it is determined from the timing detection results of the transmission delay parameter combination that any RF transceiver chip has failed the timing detection, another receiving delay parameter combination is selected from the first receiving interface delay parameters to adjust the receiving timing of the FPGA chip. When it is determined that all RF transceiver chips have passed the timing test based on the timing test results of the transmission delay parameter combination, delay compensation is performed on the timing results of the transmission delay parameter combination of each RF transceiver chip based on the digital interface delay difference. The transmission delay parameter combination that passes the timing detection of all RF transceiver chip transmission interfaces simultaneously and whose consecutive number of passes reaches a preset threshold is determined as the first transmission interface delay parameter. The first transmission interface delay parameter is written into the transmission interface delay adjustment register of the corresponding RF transceiver chip, and the transmission interface delay adjustment register is updated.

8. The method according to claim 7, characterized in that, The step of adjusting the transmission timing of the FPGA chip according to the transmission interface test path and based on the first transmission interface delay parameter to obtain the second transmission interface delay parameter of the FPGA chip includes: Configure the RF transceiver chip using the delay parameters of the first transmitting interface; Based on the test path of the transmission interface, the radio frequency transceiver chip continuously sends a preset pseudo-random test sequence to the FPGA chip. Based on the preset pseudo-random test sequence received by the FPGA chip, the output delay unit corresponding to the transmitting interface in the FPGA chip is tested line by line to obtain the range of delay levels that pass the test. Select the target delay level within the delay level range to obtain the delay parameters for the second sending interface.

9. The method according to claim 1, characterized in that, The cross-chip data synchronization verification of the RF transceiver chip and FPGA chip after the transmission link configuration is completed includes: The RF transceiver chip that has completed the transmission link configuration is in a preset transmission mode and obtains a valid indication signal of the associated clock domain. When the valid indication signal and the processing clock meet the preset phase correspondence, the RF transceiver chip is controlled to enter the internal loopback state, and the FPGA chip is used to generate a data sequence for verification. When the data sequence returns to the FPGA chip via the internal loopback path, the FPGA chip performs cross-clock domain buffering on the returned data sequence and performs a consistency comparison on the buffered data sequence to obtain the comparison result. When the comparison results indicate that the data sequences corresponding to multiple RF transceiver chips are consistent, the data synchronization verification result is determined to be that the data synchronization verification of multiple RF transceiver chips has passed.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored executable program, wherein, when the executable program is executed, it controls the device on which the storage medium is located to perform the method according to any one of claims 1 to 9.

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