Equalizer based on nonvolatile memory, SerDes and electronic system

Abstract

The invention discloses an equalizer based on a nonvolatile memory, SerDes and an electronic system, and relates to the technical field of digital baseband transmission, and the equalizer comprises a continuous time linear equalizer CTLE, a decision feedback equalizer DFE and a transimpedance amplifier TIA; the output end of the CTLE is connected with the input end of the TIA, the feedback end of the DFE is connected with the input end of the TIA, and the output end of the TIA is connected with the input end of the DFE; the CTLE comprises a zero-pole adjusting module, and the zero-pole adjusting module adopts an NVM as a zero-pole adjusting resistor. The DFE comprises a feedback weight adjustment module, and the feedback weight adjustment module adopts an NVM as a feedback weight storage device; and the TIA sums the output current of the CTLE and the feedback current of the DFE, converts the summed current into a voltage signal, transmits the voltage signal to the DFE, and controls the output quiescent operating point of the CTLE. According to the invention, the circuit complexity is reduced, the quiescent working point is stabilized, and the adjustment precision is improved.

Description

Technical Field

[0001] This invention relates to the field of digital baseband transmission technology, and more specifically, to an equalizer, SerDes, and electronic system based on non-volatile memory. Background Technology

[0002] With the development of digital baseband transmission systems, SerDes data transmission rates are increasing, and the attenuation of high-frequency components in the data signal is greater than that of low-frequency components, leading to misinterpretation at the receiver. One way to solve this problem is to add an equalization circuit at the receiver, but current technology has some drawbacks: High circuit complexity: It requires the use of multi-stage variable gain amplifiers (VGA) and continuous-time linear equalizers (CTLE) to achieve linear equalization, resulting in a complex circuit structure and a large layout area. The input quiescent operating point of the decision feedback equalizer (DFE) is unstable: the input quiescent operating point of the DFE fluctuates nonlinearly with changes in process, voltage, and temperature (PVT), which seriously affects the decision performance of the DFE. CTLE adjustment performance is limited: the adjustable range and linearity of CTLE are easily affected by PVT changes, and the adjustment accuracy is limited, making it difficult to adapt to the attenuation characteristics of different channels and failing to achieve the best equalization effect.

[0003] Therefore, there is an urgent need for a balancing scheme that can reduce circuit complexity, stabilize the static operating point, and improve adjustment accuracy to meet the transmission requirements of high-speed SerDes systems.

[0004] To address the above problems, this invention proposes a solution. Summary of the Invention

[0005] To overcome the aforementioned deficiencies of the prior art, the present invention aims to provide an equalizer, SerDes, and electronic system based on non-volatile memory. By incorporating NVM and TIA, the CTLE and DFE are directly cascaded to reduce circuit complexity and layout area; the output static operating point of the CTLE is controlled by TIA; and the adjustment accuracy of the CTLE is improved by utilizing the resistance continuity and programmability of NVM, thereby solving the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: An equalizer, SerDes and electronic system based on non-volatile memory, including a continuous-time linear equalizer (CTLE), a decision feedback equalizer (DFE) and a transimpedance amplifier (TIA). The output terminal of the CTLE is connected to the input terminal of the TIA, the feedback terminal of the DFE is connected to the input terminal of the TIA, and the output terminal of the TIA is connected to the input terminal of the DFE. The CTLE includes a zero-pole adjustment module, which uses a non-volatile memory (NVM) as the zero-pole adjustment resistor. The DFE includes a feedback weight adjustment module, which uses a non-volatile memory (NVM) as the feedback weight storage device. The TIA is used to sum the output current of the CTLE and the feedback current of the DFE, and convert the summed current into a voltage signal to be transmitted to the DFE, while controlling the output static operating point of the CTLE.

[0007] In a preferred embodiment, the non-volatile memory (NVM) is a resistive random access memory (RRAM), and the resistance value of the RRAM is adjusted by applying a SET pulse or a RESET pulse. When the number of SET pulses increases, the resistance value of the RRAM decreases, and when the number of RESET pulses increases, the resistance value of the RRAM increases.

[0008] In a preferred embodiment, the CTLE includes a current source module and a common-mode feedback module; the current source module includes four current sources I1, I2, I3, and I4 with the same current magnitude; the common-mode feedback module is used to detect the common-mode voltage of the CTLE output node and compare it with a reference common-mode voltage VCM, and adjust the current magnitude of the current sources I3 and I4 according to the comparison result so that the static voltage of the output node is maintained at VCM.

[0009] In a preferred embodiment, the DFE is a 3-tap feedback decision equalizer, and the feedback weight adjustment module includes six RRAM devices W1±, W2±, and W3±, which correspond to the feedback weights h1, h2, and h3 of the DFE, respectively. The DFE includes an analog switch, which is used to control the voltage drop applied across the RRAM devices so that the voltage across the RRAM devices never exceeds a threshold voltage.

[0010] In a preferred embodiment, the TIA includes an amplifier and a bridging resistor; the value of the bridging resistor is determined by the resistance range of the RRAM, the feedback weight of the DFE, and the threshold of the slicer in the DFE; the amplifier employs a two-stage amplification structure.

[0011] In a preferred embodiment, the value of the bridging resistor is determined by the resistance range of the RRAM, the feedback weight of the DFE, and the threshold of the slicer in the DFE, as follows: The decision threshold Vth, circuit power supply voltage Vsupply, and redundancy coefficient k of the decision device are determined, and the TIA output voltage constraint range is obtained as k*Vth≤|Vout|≤Vsupply / 2, where Vout is the output voltage of the TIA. Obtain the resistance range of the RRAM, and calculate the output current range of the CTLE using Ohm's law, in conjunction with the output voltage of the CTLE. Based on the number of taps of the DFE and the RRAM conductance range (conductance is the reciprocal of resistance) corresponding to the feedback weight of each tap, combined with the common-mode voltage and the output voltage of the decision device, the extreme value of the feedback current of a single tap is obtained, and finally the DFE feedback current range of all taps is obtained by summing. The summation current range of the TIA is obtained by superimposing the CTLE output current range with the DFE feedback current range. Based on the TIA output voltage constraint range and the summation current range, the value range of the bridging resistor is derived; within the value range, a standard resistance value is selected, and the resistance value of the bridging resistor is determined after circuit simulation verification.

[0012] In a preferred embodiment, the DFE adopts an unroll structure, the DFE includes multiple independent decision units, each decision unit corresponds to one of the feedback weights; the feedback weight adjustment module further includes a digital-to-analog converter (DAC) composed of NVMs, the DAC being used to convert the digital feedback weights into analog current signals.

[0013] In a preferred embodiment, the equalizer operates in half-speed mode, the DFE has 2 taps, the feedback path of the DFE omits the high-speed buffer unit, and the clock frequency of the DFE is adapted to the corresponding SerDes data rate.

[0014] A SerDes includes a receiver circuit that integrates an equalizer based on a non-volatile memory as described in any of the above embodiments.

[0015] An electronic system comprising the SerDes as described in the above embodiments.

[0016] The technical effects and advantages of this invention regarding an equalizer, SerDes, and electronic system based on non-volatile memory are as follows: 1. This invention provides a novel equalization circuit in which the CTLE and DFE are connected as a whole via TIA, eliminating the need for multi-stage adjustable gain amplifiers required in existing technologies. Furthermore, it employs NVM as the zero-pole adjustment device for the CTLE and the feedback weight storage device for the DFE, simplifying the circuit structure and significantly reducing circuit complexity and layout area. Utilizing the resistance continuity and programmability of NVM (RRAM), the zeros and poles of the CTLE can be continuously and precisely adjusted. Combined with an adaptive algorithm, it can be adjusted to the optimal equalization state according to the attenuation characteristics of different channels, effectively improving the equalizer's adaptability to different channel environments.

[0017] 2. This invention achieves direct cascading of the CTLE and DFE through TIA. By providing a fixed reference common-mode voltage VCM through TIA, the static current output by the CTLE can be effectively eliminated. At the same time, it provides the DFE's decision unit with a static operating point unaffected by PVT changes, ensuring the stability of the DFE's decision performance and avoiding signal misjudgment caused by environmental changes. The RRAM used in the CTLE has strong resistance to PVT changes. Combined with the adjustment function of the common-mode feedback module, the equalizer can maintain stable operating performance under different process, voltage, and temperature conditions, improving the anti-interference capability and reliability of the entire system. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an equalizer, SerDes, and electronic system structure based on non-volatile memory according to the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] This solution provides a novel equalization circuit. Its core idea is to sum the output current of the CTLE and the feedback current of the DFE, and then convert this summed current into a voltage via the TIA to provide the voltage for the DFE decision. The CTLE uses an NVM resistor as its zero-pole adjustment resistor, enabling more precise adjustment of the CTLE's zeros and poles to achieve the optimal CTLE equalization effect for the corresponding channel. Simultaneously, the output terminal uses a current source and an NVM resistor to convert the CTLE output voltage into current and transmit it to the TIA. The DFE uses an NVM resistor as its feedback weight, and the DFE feedback value is transmitted to the TIA in the form of current. In summary, the TIA's output voltage contains both the CTLE's equalization information and the DFE's feedback information, providing an effective and concise solution for SerDes equalization.

[0021] Example 1, Figure 1 A block diagram of the overall structure of an equalizer based on non-volatile memory (NVM) according to this invention is provided. The novel equalization circuit consists of three parts: CTLE, DFE, and TIA, where both CTLE and DFE have NVM. This scheme uses RRAM as the NVM, and the resistance of the RRAM can decrease with the increase of the number of SET pulses applied across it, or increase with the increase of the number of RESET pulses.

[0022] An equalizer based on non-volatile memory includes a continuous-time linear equalizer (CTLE), a decision feedback equalizer (DFE), and a transimpedance amplifier (TIA); the output of the CTLE is connected to the input of the TIA, the feedback terminal of the DFE is connected to the input of the TIA, and the output of the TIA is connected to the input of the DFE, forming a closed-loop equalization structure.

[0023] The CTLE includes a zero-pole adjustment module, which uses non-volatile memory (NVM) as the zero-pole adjustment resistor; specifically, resistive random access memory (RRAM) is selected. Since the resistance value of the RRAM can be flexibly adjusted by applying SET or RESET pulses, the resistance value of the RRAM decreases when the number of SET pulses increases, and increases when the number of RESET pulses increases. Utilizing the high resistance accuracy and wide resistance range of the RRAM, the zero-pole of the CTLE can achieve high-precision, wide-range adjustment, while enhancing its resistance to PVT variations, ensuring good equilibrium performance under different environments.

[0024] The CTLE also includes a current source module and a common-mode feedback module. The current source module consists of four current sources I1, I2, I3, and I4 with the same current magnitude. This structural design ensures that no current flows from the CTLE into the TIA in the static state, thus avoiding static errors.

[0025] To ensure that the current mismatch between current sources I1 and I3, and I2 and I4 is controlled within a small range, and to fix the drain voltage of I1 and I2 at the reference common-mode voltage VCM, a common-mode feedback module is set up. This module detects the common-mode voltage of CTLE output nodes A and B, compares it with VCM, and adjusts the current of current sources I3 and I4 according to the comparison result, so that the static voltage of the output node is always stable at VCM, while the differential-mode signal is converted into the output current of CTLE through the zero-pole adjustment resistor composed of RRAM.

[0026] The DFE includes a feedback weight adjustment module, which uses a non-volatile memory (NVM) as the feedback weight storage device. The DFE is a 3-tap feedback decision equalizer, and its feedback weight adjustment module includes six RRAM devices W1±, W2±, W3±, which correspond to the feedback weights h1, h2, and h3 of the DFE, respectively. Since the RRAM will lose stored information if the voltage across its terminals exceeds the threshold voltage, an analog switch is set in the DFE to control the voltage drop applied across the RRAM device. This ensures that the voltage across the RRAM device is within the range of VCM±Vt, and does not exceed its threshold voltage Vt, regardless of whether the transmitted data is 0 or 1, thus guaranteeing the stable storage of feedback weight information.

[0027] TIA is used to sum the output current of the CTLE and the feedback current of the DFE, and convert the summed current into a voltage signal to be transmitted to the DFE, while controlling the output static operating point of the CTLE.

[0028] The core function of the TIA is to sum the output current of the CTLE and the feedback current of the DFE, and convert the summed current into a voltage signal, which is then transmitted to the DFE's decision unit (slicer). Simultaneously, it controls the CTLE's output quiescent operating point. The TIA consists of an amplifier and a bridging resistor. The value of the bridging resistor needs to be determined based on the RRAM's resistance range, the DFE's feedback weight, and the slicer's threshold value to ensure the rationality of the current-to-voltage conversion coefficient. The specific process is as follows: The decision threshold Vth, circuit power supply voltage Vsupply, and redundancy coefficient k of the decision device are determined, and the TIA output voltage constraint range is obtained as k*Vth≤|Vout|≤Vsupply / 2, where Vout is the output voltage of the TIA. Obtain the resistance range of the RRAM, and calculate the output current range of the CTLE using Ohm's law, in conjunction with the output voltage of the CTLE. Based on the number of taps of the DFE and the RRAM conductance range (conductance is the reciprocal of resistance) corresponding to the feedback weight of each tap, combined with the common-mode voltage and the output voltage of the decision device, the extreme value of the feedback current of a single tap is obtained, and finally the DFE feedback current range of all taps is obtained by summing. The summation current range of the TIA is obtained by superimposing the CTLE output current range with the DFE feedback current range. Based on the TIA output voltage constraint range and the summation current range, the value range of the bridging resistor is derived; within the value range, a standard resistance value is selected, and the resistance value of the bridging resistor is determined after circuit simulation verification.

[0029] The amplifier employs a two-stage amplification structure to ensure signal amplification and transmission stability. Furthermore, the TIA can also be configured with an open-loop structure combined with an automatic gain control (AGC) module, making it suitable for specific applications such as optical communication.

[0030] The present invention also provides a SerDes whose receiver circuit integrates the above-mentioned equalizer based on non-volatile memory, which can effectively compensate for signal attenuation during high-speed data transmission and improve the accuracy of data reception.

[0031] The present invention further provides an electronic system including the above-mentioned SerDes, which can be widely used in electronic devices that require high-speed data transmission, such as servers, communication equipment, and storage devices, to ensure the stable operation of the electronic system.

[0032] Example 2 presents an Unroll structure equalizer according to the present invention.

[0033] The optimization for "ultra-high-speed SerDes scenarios" is based on the adoption of an Unroll architecture DFE. By optimizing the Slicer structure and introducing NVM as a DAC, the equalizer response speed is improved.

[0034] Slicer structure optimization: Abandoning the traditional "time-division multiplexing" single slicer design in DFE, an unrolled structure is adopted, which configures an independent decision logic unit for each tap (h1, h2, h3) of DFE, avoiding signal delay caused by time-division processing and improving decision speed; DAC Implementation: Based on the traditional unroll structure, an NVM (such as RRAM) is used to replace the resistor network or capacitor array of the traditional DAC, serving as the core for converting digital feedback weights to analog current signals. The continuously adjustable resistance of the NVM can accurately match the feedback weight requirements of each tap of the DFE, solving the problems of low adjustment accuracy and high susceptibility to PVT in traditional DACs.

[0035] The digital feedback weights (h1, h2, h3) of the DFE are converted into analog current signals by the DAC composed of NVM, and are fed into the TIA along with the output current of the CTLE. The TIA converts the summed current into a voltage signal and transmits it to the independent slicers of the Unroll structure for parallel decision-making. The decision results are then updated through the feedback path to update the weight configuration of the NVM, forming a closed-loop equalization.

[0036] Applicable scenarios: Ultra-high-speed SerDes (such as 200Gbps and above) and high-frequency transmission scenarios that are sensitive to signal delay.

[0037] Example 3 presents an open-loop TIA+AGC structure equalizer according to the present invention.

[0038] Customized for the "optical communication field", the core is to optimize the internal architecture of TIA, and replace the closed-loop two-stage amplification structure with "open-loop TIA + automatic gain control (AGC)" to adapt to the special needs of optical signal transmission.

[0039] TIA architecture adjustment: adopt an open-loop structure design to remove the negative feedback link of the traditional closed-loop TIA, so as to obtain wider bandwidth and faster response speed to meet the requirements of high-speed optical signal transmission. Added AGC module: An automatic gain control (AGC) module is connected in series at the output of the open-loop TIA. The AGC detects the output voltage amplitude of the TIA in real time and adjusts the gain coefficient of the open-loop TIA through feedback to make up for the defect that the gain of the open-loop structure is greatly affected by PVT, and ensure that the output voltage is stable within the decision threshold range of the slicer.

[0040] The output current of CTLE and the feedback current of DFE converge into the open-loop TIA, and after current-to-voltage conversion, it is transmitted to the AGC module. AGC dynamically adjusts the TIA gain according to the output amplitude, so that the stabilized voltage signal is input to DFE for decision-making. At the same time, TIA still maintains the function of providing a fixed VCM voltage to ensure that the static operating point of CTLE output is not affected by PVT changes.

[0041] The CTLE still uses NVM as the zero-pole adjustment device, and the DFE still uses NVM as the feedback weight storage device. The connection relationship between TIA and CTLE and DFE remains unchanged.

[0042] Applicable scenarios: optical communication systems (such as fiber optic transmission and optical module interfaces), and scenarios with large signal attenuation fluctuations and extremely high bandwidth requirements.

[0043] Example 4 presents a half-speed structure equalizer according to the present invention.

[0044] The optimization for "medium-low speed, low power consumption scenarios" is to reduce the operating speed of the equalizer to half of its full speed, thereby reducing power consumption and cost by simplifying the DFE structure.

[0045] Rate adaptation: The equalizer's sampling clock frequency is reduced to half the SerDes data rate, and the signal is processed using a "parallel sampling" method (such as parallel equalization in groups of two bits), which reduces the device switching speed requirements while ensuring the transmission rate requirements. Tap number adjustment: Based on the channel attenuation characteristics of the half-speed scenario, the number of taps of the DFE can be simplified from 3 taps to 2 taps (h1, h2), reducing the number of NVM devices and the complexity of the feedback link. Feedback path simplification: The circuit unit used for high-speed buffering in the full-speed structure is removed, and the feedback current is directly fed into the TIA through the simplified path, reducing circuit power consumption; Clock synchronization optimization: Adjust the clock and signal synchronization logic of DFE to ensure that the feedback current can be accurately summed with the output current of CTLE under half-speed clock.

[0046] After CTLE adjusts the zeros and poles through NVM, it converts the output voltage into current and transmits it to TIA; DFE outputs feedback current through simplified NVM weight modules (such as W1±, W2±), sums it with CTLE current in TIA and converts it into voltage; Slicer completes signal decision under half-speed clock control, and the decision result is fed back to DFE to update NVM weights.

[0047] The overall architecture of CTLE and DFE cascading through TIA remains unchanged, the application logic of NVM in CTLE and DFE remains unchanged, and the function of TIA stabilizing the static operating point remains unchanged.

[0048] Applicable scenarios: Low-to-medium speed SerDes (e.g., 50Gbps and below), portable electronic devices (e.g., mobile phones, tablets), and IoT devices that are sensitive to power consumption and cost.

[0049] This invention provides a novel equalization circuit in which the CTLE and DFE are connected as a whole via TIA, eliminating the need for multi-stage adjustable gain amplifiers. Furthermore, it utilizes NVM as a zero-pole adjustment device and DFE weight storage device, reducing circuit complexity and layout area. The NVM, as a zero-pole adjustment device, allows for continuous change of the CTLE's zeros and poles, achieving optimal equalization in conjunction with an adaptive algorithm. The presence of TIA allows the CTLE's output static operating point to be controlled regardless of PVT changes, or to any voltage value desired by the designer.

[0050] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0051] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0052] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0053] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0054] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0055] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An equalizer based on non-volatile memory, characterized in that, This includes continuous-time linear equalizers (CTLE), decision feedback equalizers (DFE), and transimpedance amplifiers (TIA). The output terminal of the CTLE is connected to the input terminal of the TIA, the feedback terminal of the DFE is connected to the input terminal of the TIA, and the output terminal of the TIA is connected to the input terminal of the DFE. The CTLE includes a zero-pole adjustment module, which uses a non-volatile memory (NVM) as the zero-pole adjustment resistor. The DFE includes a feedback weight adjustment module, which uses a non-volatile memory (NVM) as the feedback weight storage device. The TIA is used to sum the output current of the CTLE and the feedback current of the DFE, and convert the summed current into a voltage signal to be transmitted to the DFE, while controlling the output static operating point of the CTLE.

2. The equalizer based on non-volatile memory according to claim 1, characterized in that, The non-volatile memory (NVM) is a resistive random access memory (RRAM). The resistance value of the RRAM is adjusted by applying SET pulses or RESET pulses. When the number of SET pulses increases, the resistance value of the RRAM decreases, and when the number of RESET pulses increases, the resistance value of the RRAM increases.

3. An equalizer based on non-volatile memory according to claim 2, characterized in that, The CTLE includes a current source module and a common-mode feedback module. The current source module includes four current sources I1, I2, I3, and I4 with the same current magnitude. The common-mode feedback module is used to detect the common-mode voltage of the CTLE output node and compare it with the reference common-mode voltage VCM. Based on the comparison result, the current magnitudes of the current sources I3 and I4 are adjusted so that the static voltage of the output node is maintained at VCM.

4. An equalizer based on non-volatile memory according to claim 3, characterized in that, The DFE is a 3-tap feedback decision equalizer. The feedback weight adjustment module includes six RRAM devices W1±, W2±, and W3±, which correspond to the feedback weights h1, h2, and h3 of the DFE, respectively. The DFE includes an analog switch, which is used to control the voltage drop applied across the RRAM devices so that the voltage across the RRAM devices never exceeds the threshold voltage.

5. An equalizer based on non-volatile memory according to claim 4, characterized in that, The TIA includes an amplifier and a bridging resistor; the value of the bridging resistor is determined by the resistance range of the RRAM, the feedback weight of the DFE, and the threshold of the slicer in the DFE; the amplifier adopts a two-stage amplification structure.

6. An equalizer based on non-volatile memory according to claim 5, characterized in that, The value of the bridging resistor is determined by the resistance range of the RRAM, the feedback weight of the DFE, and the threshold of the slicer in the DFE. The process is as follows: The decision threshold Vth, circuit power supply voltage Vsupply, and redundancy coefficient k of the decision device are determined, and the TIA output voltage constraint range is obtained as k*Vth≤|Vout|≤Vsupply / 2, where Vout is the output voltage of the TIA. Obtain the resistance range of the RRAM, and calculate the output current range of the CTLE using Ohm's law, in conjunction with the output voltage of the CTLE. Based on the number of taps of the DFE and the RRAM conductance range (conductance is the reciprocal of resistance) corresponding to the feedback weight of each tap, combined with the common-mode voltage and the output voltage of the decision device, the extreme value of the feedback current of a single tap is obtained, and finally the DFE feedback current range of all taps is obtained by summing. The summation current range of the TIA is obtained by superimposing the CTLE output current range with the DFE feedback current range. Based on the TIA output voltage constraint range and the summation current range, the value range of the bridging resistor is derived. A standard resistance value is selected within the specified range, and the resistance value of the bridging resistor is determined after circuit simulation verification.

7. An equalizer based on non-volatile memory according to claim 6, characterized in that, The DFE adopts an unroll structure and includes multiple independent decision units, each of which corresponds to a feedback weight. The feedback weight adjustment module also includes a digital-to-analog converter (DAC) composed of NVMs, which is used to convert the digital feedback weight into an analog current signal.

8. An equalizer based on non-volatile memory according to claim 7, characterized in that, The equalizer operates in half-speed mode, the DFE has 2 taps, the DFE's feedback path omits the high-speed buffer unit, and the DFE's clock frequency is adapted to the corresponding SerDes data rate.

9. A SerDes, characterized in that, It includes a receiver circuit, which integrates an equalizer based on a non-volatile memory as described in any one of claims 1-8.

10. An electronic system, characterized in that, Including SerDes as described in claim 9.

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