Semiconductor device for improving self-protection capability of LDMOS and manufacturing method thereof

Abstract

The invention provides a semiconductor device for improving the self-protection capability of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) and a manufacturing method thereof. The device comprises a semiconductor substrate and an epitaxial layer located on the semiconductor substrate, and a first conductive type buried layer and a second conductive type buried layer located on the first conductive type buried layer are arranged in the epitaxial layer. The key point is that the second conductive type body region on the surface of the device extends deeply in the vertical direction and is in direct contact with the second conductive type buried layer below the second conductive type body region. According to the structure, a longitudinal low-impedance discharge channel is constructed between a body region and a deep buried layer, triggering of a parasitic transverse bipolar junction transistor is effectively restrained, and thermal breakdown caused by local current concentration is avoided. Experiments show that the structure significantly improves the secondary breakdown current of the device, greatly enhances the antistatic self-protection capability of the LDMOS, has good compatibility of the manufacturing process, and does not need to add an additional photomask.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method that improves the self-protection capability of LDMOS. Background Technology

[0002] With the miniaturization of semiconductor process technology and the widespread application of integrated circuits, electrostatic discharge (ESD) has become one of the main causes of excessive voltage stress damage to electronic components or integrated circuit systems. Preventing ESD damage is a primary challenge to address in the design and manufacturing of integrated circuits.

[0003] In advanced process technologies such as 90nm BCD (Bipolar-CMOS-DMOS), LDMOS devices typically require high self-protection capabilities. This is because LDMOS devices are often used in high-voltage drive applications, and their structure is inherently susceptible to electrostatic discharge (ESD). In a typical device structure, a first conductivity type buried layer (e.g., N-type buried layer, NBL) is placed above the substrate. After epitaxial layer growth, a second conductivity type buried layer (e.g., P-type buried layer, Punder / PBL) is usually formed inside the epitaxial layer and above the NBL. Furthermore, to prevent latch-up and isolate high-voltage noise, a guard ring structure is typically placed around the device. This structure usually includes a well region, a buried layer, and a heavily doped contact region (P+) on the surface.

[0004] However, existing LDMOS devices often exhibit insufficient self-protection capabilities when facing electrostatic discharge (ESD). The specific mechanism lies in the fact that the parasitic lateral bipolar junction transistors (BJTs) in the existing structure are easily triggered and turn on prematurely. Once the parasitic BJTs are turned on, current tends to concentrate in localized areas, causing the device to thermally fail at relatively low current levels.

[0005] When the self-protection capability of an LDMOS device is insufficient, additional protection circuitry must be added to the circuit design to meet product reliability standards. This inevitably increases the chip's design area, leading to a significant increase in manufacturing costs. Furthermore, it also increases the complexity of the circuit design.

[0006] In the prior art, based on actual transmission line pulse (TLP) test data, LDMOS devices using the original process structure have a low secondary breakdown current (It2, an indicator used to characterize the device's ESD resistance), for example, only about 1.15A, which limits the stability of the device in harsh environments.

[0007] Therefore, providing a semiconductor device structure that can significantly improve self-protection capabilities is of great significance for improving device stability and optimizing customer designs. Summary of the Invention

[0008] The technical problem to be solved by this invention is that the existing LDMOS device structure has insufficient self-protection capability when facing electrostatic discharge. The internal parasitic lateral bipolar junction transistor is easily triggered and turned on prematurely, causing the device to fail due to thermal breakdown at a low current. This often requires an external additional protection circuit, which increases the design area and cost.

[0009] To address the aforementioned technical problems, this invention provides a semiconductor device with improved self-protection capability of LDMOS, comprising:

[0010] Semiconductor substrate;

[0011] A buried layer having a first conductivity type is located in the semiconductor substrate;

[0012] An epitaxial layer located above the semiconductor substrate and the buried layer having a first conductivity type;

[0013] A buried layer having a second conductivity type located inside the epitaxial layer and above the buried layer having a first conductivity type;

[0014] Drift regions and well regions located in the epitaxial layer;

[0015] A gate structure located on the surface of the epitaxial layer; a body region having a second conductivity type located in the epitaxial layer;

[0016] The source and drain regions are located in the epitaxial layer;

[0017] The body region having the second conductivity type extends vertically into depth and contacts the buried layer having the second conductivity type located below it.

[0018] Preferably, the first conductivity type is N-type and the second conductivity type is P-type.

[0019] Preferably, the semiconductor substrate is a P-type single-crystal silicon substrate, the epitaxial layer is a P-type epitaxial silicon layer, the buried layer with a first conductivity type is an N-type buried layer, and the buried layer with a second conductivity type is a P-type buried layer.

[0020] Preferably, the drift region has a first conductivity type, and the well region includes a well region having a first conductivity type and a well region having a second conductivity type.

[0021] Preferably, the semiconductor device further includes: an isolation ring structure located around the semiconductor device; the isolation ring structure includes a buried layer of a second conductivity type at the bottom and a well region of a second conductivity type above the buried layer of the second conductivity type; the well region of the second conductivity type is isolated from an adjacent well region of a first conductivity type by a shallow trench isolation structure, and the surface of the well region of the second conductivity type is provided with a heavily doped region of the second conductivity type.

[0022] The present invention also provides a method for manufacturing a semiconductor device with improved self-protection capability of LDMOS, comprising:

[0023] Step 1: Provide a semiconductor substrate and form a buried layer having a first conductivity type in the semiconductor substrate;

[0024] Step 2: Grow an epitaxial layer on the semiconductor substrate and the buried layer having the first conductivity type;

[0025] Step 3: Form an isolation structure in the epitaxial layer to define the active region;

[0026] Step 4: Ion implantation is performed in the epitaxial layer to form a buried layer with a second conductivity type on the buried layer with a first conductivity type, and a drift region and a well region are formed in the epitaxial layer;

[0027] Step 5: Form a gate structure on the surface of the epitaxial layer;

[0028] Step 6: Implant ions that evolve into a body region having a second conductivity type into the epitaxial layer, and extend the body region having the second conductivity type to a depth in the vertical direction to contact the buried layer having the second conductivity type;

[0029] Step 7: Form the source and drain regions.

[0030] Preferably, in step one, the first conductivity type is N-type and the second conductivity type is P-type.

[0031] Preferably, in step one, the semiconductor substrate is a P-type single-crystal silicon substrate, and the buried layer having a first conductivity type is formed by ion implantation and push-junction processes.

[0032] Preferably, in step three, the isolation structure is formed by photolithography and shallow trench isolation.

[0033] Preferably, in step four, forming a buried layer with a second conductivity type includes: implanting P-type ions deep into the epitaxial layer using a high-energy ion implantation process, so that they are located above the buried layer with a first conductivity type.

[0034] Preferably, step four further includes the step of forming a well region and a buried layer in an isolation ring structure located at the edge of the device, the isolation ring structure including a buried layer having a second conductivity type and a well region having a second conductivity type located thereon.

[0035] Preferably, in step five, forming the gate structure includes defining the gate polysilicon and the stepped oxide layer through thin film deposition, photolithography and etching processes.

[0036] Preferably, in step six, the contact between the body region having the second conductivity type and the buried layer having the second conductivity type is used to form a longitudinal current discharge channel to suppress the triggering of the lateral parasitic bipolar junction transistor.

[0037] Preferably, step seven includes: forming an N-type lightly doped drain; performing N-type heavy doping implantation and P-type heavy doping implantation to form a contact region between the source region and the drain region; wherein, during the P-type heavy doping implantation, a P-type heavy doped region is simultaneously formed on the surface of the well region having the second conductivity type in the isolation ring structure.

[0038] As described above, the semiconductor device and its manufacturing method for improving the self-protection capability of LDMOS of the present invention have the following beneficial effects:

[0039] This invention creates a vertical, low-impedance discharge channel within the device by deepening the body region (Pbody) with a second conductivity type, making it contact the underlying buried layer (Punder) with the same second conductivity type. This structure effectively suppresses the triggering of parasitic lateral bipolar junction transistors (BJTs) within the LDMOS, thus preventing device failure due to localized current concentration under ESD impacts. Actual test data shows that the failure current (It2) is significantly improved using the device structure of this invention, indicating a significant improvement in the self-protection capability of the LDMOS device. Attached Figure Description

[0040] Figure 1 The diagram shows a manufacturing process flow of a semiconductor device for improving the self-protection capability of LDMOS according to the present invention.

[0041] Figure 2 The diagram shows a cross-sectional view of the device structure obtained in step one of the manufacturing processes of a semiconductor device with improved LDMOS self-protection capability according to the present invention.

[0042] Figure 3 The diagram shows a cross-sectional view of the device structure obtained in step two of the manufacturing process of a semiconductor device with improved LDMOS self-protection capability according to the present invention.

[0043] Figure 4The diagram shows a cross-sectional view of the semiconductor device structure obtained in step three of the manufacturing process of an improved LDMOS self-protection capability according to the present invention.

[0044] Figure 5 The diagram shows a cross-sectional view of the device structure obtained in step four of the manufacturing process of a semiconductor device with improved LDMOS self-protection capability according to the present invention.

[0045] Figure 6 The diagram shows a cross-sectional view of the device structure obtained in step five of the manufacturing process of a semiconductor device with improved LDMOS self-protection capability according to the present invention.

[0046] Figure 7 The diagram shows a cross-sectional view of the device structure obtained in step six of the manufacturing process of a semiconductor device with improved LDMOS self-protection capability according to the present invention.

[0047] Figure 8 The diagram shows a cross-sectional view of the device structure obtained in step seven of the manufacturing process of a semiconductor device with improved LDMOS self-protection capability according to the present invention.

[0048] Figure 9 The diagram shows a cross-sectional view of the device structure obtained in step eight of the manufacturing process of a semiconductor device with improved LDMOS self-protection capability according to the present invention.

[0049] Figure 10 The diagram shows a comparison of test data on the self-protection capability of a semiconductor device with improved LDMOS self-protection capability according to the present invention and that of the prior art. Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] This invention provides a semiconductor device and its manufacturing method for improving the self-protection capability of LDMOS. The following will be described in conjunction with the appendix. Figure 1 To be continued Figure 10 The technical solution of the present invention will be described in detail below. Figure 1 This is a schematic diagram of the process of the method of the present invention. Figures 2 to 9 This is a schematic cross-sectional view of the device structure corresponding to each step of the manufacturing process of this invention. Figure 10 This is a comparison chart of TLP test data between the LDMOS device of this embodiment and the device of the comparative example.

[0052] This invention provides a semiconductor device that improves the self-protection capability of LDMOS, such as... Figure 9 As shown, the device includes a semiconductor substrate 101.

[0053] In some embodiments, the semiconductor substrate 101 is a P-type single-crystal silicon substrate. Besides single-crystal silicon, to adapt to different device performance requirements and integrated circuit process environments, the semiconductor substrate 101 may also contain other suitable elemental semiconductors, such as diamond or germanium; it may also contain suitable compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), arsenic carbide (AsC), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), or combinations thereof; it may also contain suitable alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium arsenide phosphide (GaInAsP), or combinations thereof. Furthermore, the semiconductor substrate 101 may also be a semiconductor-on-insulator (SOI) structure. The semiconductor-on-insulator substrate 101 can be fabricated using oxygen implantation isolation (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements, the semiconductor substrate 101 may have different crystal orientations, such as (100), (110) or (111) crystal planes.

[0054] The semiconductor device that improves the self-protection capability of LDMOS includes a buried layer with a first conductivity type located in the semiconductor substrate 101.

[0055] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. Alternatively, the first conductivity type is P-type and the second conductivity type is N-type. This means that the device structure provided by the present invention is also applicable to complementary type devices (such as P-channel LDMOS). In this case, the aforementioned material and doping polarities will be reversed accordingly. For example, the semiconductor substrate 101 can be N-type single-crystal silicon; the buried layer with the first conductivity type becomes a P-type buried layer; the buried layer with the second conductivity type becomes an N-type buried layer; the drift region becomes a P-type drift region; and the body region becomes an N-type body region. Correspondingly, impurities used to form the N-type region (such as phosphorus, arsenic, and antimony) will be replaced with impurities used to form the P-type region (such as boron, boron difluoride, and indium), and vice versa. For ease of description, the following description mainly uses N-type as the first conductivity type and P-type as the second conductivity type (i.e., N-channel LDMOS) as an example.

[0056] In some embodiments, the buried layer having a first conductivity type is an N-type buried layer 103. For example... Figure 9As shown, the N-type buried layer 103 is located above the semiconductor substrate 101, but its position is relatively deep in the final structure of the device. The N-type buried layer 103 is typically used to isolate the device from the substrate in the vertical direction, reduce substrate noise interference, and suppress the gain of parasitic PNP transistors.

[0057] The semiconductor device that improves the self-protection capability of LDMOS includes an epitaxial layer 104 located on a semiconductor substrate 101 and a buried layer having a first conductivity type.

[0058] In some embodiments, the epitaxial layer 104 is a P-type epitaxial silicon layer. The epitaxial layer 104 provides the main fabrication environment for the active region of the device. Its doping concentration and thickness are key parameters that determine the breakdown voltage of the LDMOS. Epitaxial growth can be accomplished by methods such as chemical vapor deposition (CVD).

[0059] The semiconductor device that improves the self-protection capability of LDMOS includes a buried layer of a second conductivity type located inside the epitaxial layer 104 and above a buried layer of a first conductivity type.

[0060] In some embodiments, the buried layer having a second conductivity type is a P-type buried layer 109. For example... Figure 9 As shown, the P-type buried layer 109 is located above the N-type buried layer 103 and deep within the epitaxial layer 104. As part of the RESURF (Reduced Surface Electric Field) technique, the P-type buried layer 109 helps deplete the drift region, thereby allowing for higher doping concentrations to reduce on-resistance while maintaining high breakdown voltage.

[0061] Semiconductor devices that improve the self-protection capability of LDMOS include drift regions and well regions located in the epitaxial layer 104.

[0062] In some embodiments, the drift region has a first conductivity type, and the well region includes a well region having a first conductivity type and a well region having a second conductivity type. For example... Figure 9 As shown, the drift region is an N-type drift region 108, which extends laterally to withstand high voltages. The well regions include N-type wells 106 and P-type wells 107 located at the device edges or in the isolation regions. These regions define the device's boundaries and isolation characteristics.

[0063] Semiconductor devices that improve the self-protection capability of LDMOS include gate structures located on the surface of epitaxial layer 104. For example... Figure 9 As shown, the gate structure includes a stepped oxide layer 114 (HVOX) and a gate conductive layer 115. The stepped oxide layer 114 is thicker above the drift region to withstand high voltage and thinner above the channel region to control device turn-on. The gate conductive layer 115 can be polysilicon, metal silicide, or a metal material.

[0064] Semiconductor devices that improve the self-protection capability of LDMOS include a body region with a second conductivity type located in the epitaxial layer 104.

[0065] Semiconductor devices that improve the self-protection capability of LDMOS include the source and drain regions located in the epitaxial layer 104.

[0066] The body region having the second conductivity type extends vertically into depth and contacts the buried layer having the second conductivity type located below it.

[0067] In some embodiments, the body region having a second conductivity type is a P-type body region 116. The buried layer having the second conductivity type is connected to the body region having the second conductivity type to form a longitudinal discharge channel. For example... Figure 7 and Figure 9 As shown, the P-type body region 116 (Pbody) differs from the conventional bowl-shaped floating structure in that its bottom is designed to be deep enough to physically contact the underlying P-type buried layer 109 (Punder). This deep contact structure establishes a hole discharge path from the body contact region on the device surface to the deep substrate. In an electrostatic discharge (ESD) event, the large amount of hole current generated can rapidly flow directly through the P-type body region 116 into the P-type buried layer 109 and eventually dissipate to the substrate without excessive accumulation within the P-type body region 116, which would lead to a potential increase. This effectively suppresses the forward bias of the emitter junction of the parasitic lateral NPN bipolar junction transistor (BJT), thereby preventing the BJT from being triggered.

[0068] To verify the technical effectiveness of this embodiment, a transmission line pulse (TLP) test was performed on the LDMOS device using this structure. Figure 10 As shown, Figure 10 This displays comparative data on the self-protection capabilities of LDMOS transistors. The horizontal axis represents the test voltage, and the vertical axis represents the test current. From... Figure 10 It is clear from the data that the original device failed at a current of approximately 1.15 A; while the curve for the device of this invention extends to a higher current range, failing only at a test current of approximately 7.43 A. Specifically, the data shows that It2 (failure current, characterizing self-protection capability) increased from 1.1586 A to 7.432535 ​​A, an improvement of 541.51%. This result fully demonstrates that the contact design between the Pbody and Punder significantly improves the electrostatic discharge (ESD) protection capability of the LDMOS.

[0069] In some embodiments, the semiconductor device for improving the self-protection capability of LDMOS further includes an isolation ring structure located around the periphery of the semiconductor device. The isolation ring structure includes a buried layer of a second conductivity type at the bottom, and a well region of the second conductivity type above the buried layer. The well region of the second conductivity type is isolated from adjacent well regions of a first conductivity type by a shallow trench isolation structure, and the surface of the well region of the second conductivity type is provided with a heavily doped region of the second conductivity type. Figure 9 As shown on the far left and far right, the isolation ring structure consists of a bottom P-type buried isolation layer 102 / 111 (PBL), a middle P-type isolation well 112 (Pwell), and a surface P-type heavily doped region 113 (P+). The P-type isolation well 112 is separated from the internal N-type well 106 by a shallow trench isolation structure 105. This isolation ring structure surrounds the entire high-voltage device, enabling it to collect minority carriers injected into the substrate, prevent latch-up, and reduce the interference of high-voltage switching noise on adjacent circuits.

[0070] This invention also provides a method for manufacturing a semiconductor device that improves the self-protection capability of LDMOS. For example... Figure 1 As shown, the method includes:

[0071] Step 1: Provide a semiconductor substrate and form a buried layer with a first conductivity type in the semiconductor substrate.

[0072] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. Similarly, the first conductivity type can also be P-type and the second conductivity type can also be N-type, to meet the manufacturing requirements of P-channel devices.

[0073] In some embodiments, in step one, the semiconductor substrate is a P-type single-crystal silicon substrate 101. For example... Figure 2 As shown, a P-type single-crystal silicon substrate 101 is provided. A sacrificial oxide layer (not shown) is typically grown prior to the implantation process to protect the surface.

[0074] In some embodiments, in step one, the buried layer having a first conductivity type is formed by an ion implantation process and a push-bond process. For example... Figure 2 As shown, N-type impurities such as antimony (Sb) or arsenic (As) are implanted into the defined regions via photolithography to form an N-type buried layer region 103 (NBL). Simultaneously, P-type impurities such as boron (B) can be implanted into the device edge regions to form a P-type buried layer region 102 (PBL), serving as the basis for subsequent isolation rings. After implantation, high-temperature annealing is performed to promote impurity diffusion and activation.

[0075] Step 2: Grow an epitaxial layer on a semiconductor substrate and a buried layer having a first conductivity type. For example... Figure 3As shown, in the epitaxial reaction chamber, a P-type epitaxial silicon layer 104 (P-EPI) is grown using a semiconductor substrate 101 as a seed crystal. The epitaxial layer 104 covers the N-type buried layer 103 and the P-type buried layer region 102.

[0076] Step 3: Form an isolation structure in the epitaxial layer to define the active region.

[0077] In some embodiments, in step three, the isolation structure is formed by photolithography and shallow trench isolation processes. For example... Figure 4 As shown, a shallow trench isolation structure 105 (STI) is formed on the surface of the epitaxial layer 104. This typically involves hard mask deposition, trench etching, oxide filling, and chemical mechanical polishing (CMP). The shallow trench isolation structure 105 is used to define the active region and isolate well regions at different potentials.

[0078] Step 4: Ion implantation is performed in the epitaxial layer to form a buried layer with a second conductivity type on top of the buried layer with a first conductivity type, and a drift region and a well region are formed in the epitaxial layer.

[0079] In some embodiments, step four, forming a buried layer with a second conductivity type includes: implanting P-type ions into the depth of the epitaxial layer using a high-energy ion implantation process, so that they are located above the buried layer with a first conductivity type.

[0080] In some embodiments, step four further includes the step of forming a well region and a buried layer in an isolation ring structure located at the edge of the device, the isolation ring structure including a buried layer having a second conductivity type and a well region having a second conductivity type located thereon. Figure 5 As shown, using different photomasks and injection energies, the following are sequentially formed: a P-type buried layer 109 located deep above the N-type buried layer 103; an N-type drift region 108 located on the surface of the epitaxial layer; and various well regions, including an N-type well 106 and P-type wells 107 / 112. Specifically, in the edge region, P-type isolation buried layers 111 / 102 and P-type isolation wells 112 are formed through multiple injections, which together constitute the longitudinal barrier of the isolation ring. The concentration and distribution of the N-type drift region 108 are optimized to meet RESURF conditions.

[0081] Step 5: Form a gate structure on the surface of the epitaxial layer.

[0082] In some embodiments, step five, forming the gate structure includes: defining the gate polysilicon and the stepped oxide layer through thin film deposition, photolithography, and etching processes. For example... Figure 6 As shown, a stepped oxide layer 114 (HVOX) is first formed by thermal growth or deposition, which has thick oxide regions and thin oxide regions. Subsequently, a polysilicon layer is deposited, and after doping and patterning etching, a gate conductive layer 115 is formed.

[0083] Step 6: Implant ions that evolve into a volume region with a second conductivity type into the epitaxial layer, and extend the volume region with the second conductivity type to a depth in the vertical direction to contact the buried layer with the second conductivity type.

[0084] In some embodiments, in step six, the contact between the body region having a second conductivity type and the buried layer having a second conductivity type is used to form a longitudinal current discharge channel to suppress the triggering of lateral parasitic bipolar junction transistors. For example... Figure 7 As shown, implantation is performed on the P-type body region 116. By employing high-energy implantation or extending the subsequent thermal process, the vertical junction depth of the P-type body region 116 is controlled, allowing it to penetrate downwards through the N-type drift region 108 (if overlap exists) or extend directly until it contacts the P-type buried layer 109 formed in step four. This process design significantly improves the device's self-protection capability without requiring additional masks.

[0085] Step 7: Form the source and drain regions.

[0086] In some embodiments, step seven includes: forming an N-type lightly doped drain; performing N-type heavy doping implantation and P-type heavy doping implantation to form a contact region between the source region and the drain region; wherein, during P-type heavy doping implantation, a P-type heavy doped region is simultaneously formed on the surface of the well region of the isolation ring structure having a second conductivity type. Figure 8 As shown, an N-type lightly doped drain 117 (NLDD) is first formed. After forming sidewalls (not shown), N-type heavy doping implantation is performed to form source / drain 118 (N+). Subsequently, P-type heavy doping implantation is performed to form body contact region 119 (P+). The key is that during P+ implantation, a window in the edge isolation ring region is simultaneously opened, thereby forming a P-type heavy doped region 113 on the surface of the P-type isolation well 112, completing the electrode contact fabrication of the isolation ring.

[0087] In some embodiments, after step seven, the method further includes: step eight, defining a silicide barrier layer and contact holes on the surface of the epitaxial layer, and forming an electrical interconnect structure through a metal deposition process. For example... Figure 9 As shown, a silicide barrier layer 120 (SAB) is first formed on the device surface. The material may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and is formed via plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). The silicide barrier layer 120 is patterned to cover drift regions on the surface where silicide formation is not desired. Subsequently, a self-aligned metal silicide process is performed to deposit a refractory metal (such as nickel, cobalt, titanium, platinum, erbium, palladium, or a combination thereof), followed by annealing to form a low-resistivity metal silicide layer on the exposed silicon surface.

[0088] After silicide formation, an interlayer dielectric (ILD) is deposited. The material can include borosilicate glass (BPSG), phosphosilicate glass (PSG), fluorinated silicon glass (FSG), undoped silicate glass (USG), oxides formed from tetraethyl orthosilicate (TEOS), low-k dielectrics, or combinations thereof. The interlayer dielectric is deposited using processes such as spin coating, CVD, and HDP-CVD, and planarized using chemical mechanical planarization (CMP). Contact holes are formed in the interlayer dielectric using photolithography and anisotropic dry etching.

[0089] To form electrical connections, a barrier layer and / or a pad layer are deposited within the contact holes. Materials may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. Subsequently, conductive material is filled into the contact holes to form contact plugs 121. Conductive materials may include tungsten (W), aluminum (Al), copper (Cu), or alloys thereof. Finally, a metal interconnect structure is formed over the interlayer dielectric layer, typically involving the deposition of metal layers (such as aluminum-copper alloys), photolithography, and etching, or a damascene process to form copper interconnects, electrically connecting the source 118, drain 118, gate 115, and isolation rings, ultimately completing the fabrication of the semiconductor device.

[0090] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device for improving the self-protection capability of LDMOS, comprising: Semiconductor substrate; A buried layer having a first conductivity type is located in the semiconductor substrate; An epitaxial layer located above the semiconductor substrate and the buried layer having a first conductivity type; A buried layer having a second conductivity type located inside the epitaxial layer and above the buried layer having a first conductivity type; Drift regions and well regions located in the epitaxial layer; Gate structure located on the surface of the epitaxial layer; The body region having a second conductivity type is located in the epitaxial layer; The source and drain regions are located in the epitaxial layer; Its features are, The body region having the second conductivity type extends vertically into depth and contacts the buried layer having the second conductivity type located below it.

2. The semiconductor device for improving the self-protection capability of LDMOS according to claim 1, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type.

3. The semiconductor device for improving the self-protection capability of LDMOS according to claim 2, characterized in that: The semiconductor substrate is a P-type single-crystal silicon substrate, the epitaxial layer is a P-type epitaxial silicon layer, the buried layer with a first conductivity type is an N-type buried layer, and the buried layer with a second conductivity type is a P-type buried layer.

4. The semiconductor device for improving the self-protection capability of LDMOS according to claim 1, characterized in that: The drift region has a first conductivity type, and the well region includes a well region having a first conductivity type and a well region having a second conductivity type.

5. The semiconductor device for improving the self-protection capability of LDMOS according to claim 1, characterized in that: Also includes: An isolation ring structure is located around the semiconductor device; the isolation ring structure includes a buried layer of a second conductivity type at the bottom and a well region of a second conductivity type above the buried layer of the second conductivity type; the well region of the second conductivity type is isolated from an adjacent well region of a first conductivity type by a shallow trench isolation structure, and the surface of the well region of the second conductivity type is provided with a heavily doped region of the second conductivity type.

6. A method for manufacturing a semiconductor device with improved self-protection capability of LDMOS, comprising: Step 1: Provide a semiconductor substrate and form a buried layer having a first conductivity type in the semiconductor substrate; Step 2: Grow an epitaxial layer on the semiconductor substrate and the buried layer having the first conductivity type; Step 3: Form an isolation structure in the epitaxial layer to define the active region; Step 4: Ion implantation is performed in the epitaxial layer to form a buried layer with a second conductivity type on the buried layer with a first conductivity type, and a drift region and a well region are formed in the epitaxial layer; Step 5: Form a gate structure on the surface of the epitaxial layer; Step 6: Implant ions that evolve into a body region having a second conductivity type into the epitaxial layer, and extend the body region having the second conductivity type to a depth in the vertical direction to contact the buried layer having the second conductivity type; Step 7: Form the source and drain regions.

7. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 6, characterized in that: In step one, the first conductivity type is N-type, and the second conductivity type is P-type.

8. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 7, characterized in that: In step one, the semiconductor substrate is a P-type single-crystal silicon substrate.

9. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 7, characterized in that: In step one, the buried layer having the first conductivity type is formed by ion implantation and push-bonding processes.

10. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 6, characterized in that: In step three, the isolation structure is formed by photolithography and shallow trench isolation processes.

11. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 7, characterized in that: In step four, forming a buried layer with a second conductivity type includes: implanting P-type ions deep into the epitaxial layer using a high-energy ion implantation process, so that they are located above the buried layer with a first conductivity type.

12. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 6, characterized in that: Step four also includes the step of forming a well region and a buried layer in an isolation ring structure located at the edge of the device, the isolation ring structure including a buried layer having a second conductivity type and a well region having a second conductivity type located thereon.

13. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 6, characterized in that: In step five, forming the gate structure includes defining the gate polysilicon and the stepped oxide layer through thin film deposition, photolithography and etching processes.

14. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 6, characterized in that: In step six, the contact between the body region having the second conductivity type and the buried layer having the second conductivity type is used to form a longitudinal current discharge channel to suppress the triggering of the lateral parasitic bipolar junction transistor.

15. The method for manufacturing a semiconductor device with improved self-protection capability of LDMOS according to claim 7, characterized in that: Step seven includes: forming an N-type lightly doped drain; performing N-type heavy doping implantation and P-type heavy doping implantation to form a contact region between the source region and the drain region; wherein, during the P-type heavy doping implantation, a P-type heavy doped region is simultaneously formed on the surface of the well region having the second conductivity type in the isolation ring structure.

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