Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, and relates to the technical field of display, which can avoid the problem of light and dark lines of the display panel. The multiplexing unit of the display panel comprises a first multiplexing unit and a second multiplexing unit. The first multiplexing unit comprises a first type of transistor and a first multiplexing connection line. One data signal line is connected with one first type of transistor, and a first number of first type of transistors are connected with one first multiplexing connection line. The second multiplexing unit comprises a second type of transistor and a second multiplexing connection line. One data signal line is connected with one second type of transistor, and a second number of second type of transistors are connected with one second multiplexing connection line. The second number is less than the first number. The compensation unit is located in the first peripheral area. One compensation unit is connected with one second multiplexing connection line. The compensation unit makes the load connected with the second multiplexing unit same as the load connected with the first multiplexing unit.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the rapid development of modern electronic information technology, the display industry is also constantly progressing, and display devices are being used in a wider range of fields.

[0003] For example, OLED (Organic Light-Emitting Diode) display devices have gradually gained an important position in the market due to their advantages such as thinness, high brightness, low power consumption, good flexibility, and fast response. OLED display devices have allowed more users to enjoy a wonderful visual experience. Summary of the Invention

[0004] The purpose of some embodiments of this disclosure is to provide a display panel and display device for avoiding the problem of bright and dark lines on the display panel.

[0005] On one hand, a display panel is provided, comprising a display area and a first peripheral area located on one side of the display area along a first direction, the first peripheral area being used for connection with a driver chip; the display panel includes a substrate, and multiple data signal lines, multiple multiplexing units, and at least one compensation unit disposed on the substrate; the multiple data signal lines are located in the display area and extend along the first direction; the multiple multiplexing units are located in the first peripheral area and arranged along a second direction, the second direction being perpendicular to the first direction; the multiple multiplexing units include multiple first multiplexing units and at least one second multiplexing unit located on at least one side of the multiple first multiplexing units along the second direction, the first multiplexing unit including multiple A first type of transistor and at least one first multiplexed connection line, a data signal line and a first type of transistor are connected, a first number of first type of transistors and a first multiplexed connection line are connected; a second multiplexed unit includes a plurality of second type transistors and at least one second multiplexed connection line, a data signal line and a second type of transistor are connected, a second number of second type transistors and a second multiplexed connection line are connected; the second number is less than the first number; at least one compensation unit is located in a first peripheral area, a compensation unit and a second multiplexed connection line are connected, and the compensation unit is configured to make the load connected to the second multiplexed unit the same as the load connected to the first multiplexed unit.

[0006] Some embodiments of this disclosure utilize the ample space in the first peripheral area to set at least one compensation unit, and each compensation unit is connected to a second multiplexing connection line to increase the load connected to each second multiplexing connection line of the outermost second multiplexing unit in the multiplexing structure. This makes the load connected to each second multiplexing connection line of the second multiplexing unit approximately the same as the load connected to the first multiplexing connection line of the first multiplexing unit, thereby making the load connected to the second multiplexing unit the same or approximately the same as the load connected to the first multiplexing unit, and avoiding the problem of bright and dark lines on the display panel.

[0007] In some embodiments, the compensation unit includes at least one compensation capacitor, which includes a first plate and a second plate, the first plate and the second plate being connected by a multiplexed connection line, and the second plate being used to receive DC signals.

[0008] In some embodiments, the display panel includes a first power signal line located in a first peripheral area, and the second plate of a compensation capacitor is connected to the first power signal line.

[0009] In some embodiments, the display panel includes an active layer, a first gate conductive layer, and a source-drain conductive layer. The active layer is disposed on one side of the substrate along its own thickness direction. The active layer includes a plurality of active patterns arranged along a second direction, which are used to form the first and second electrodes of each transistor in a plurality of multiplexing units. The first gate conductive layer is disposed on the side of the active layer away from the substrate. The first gate conductive layer includes a first electrode of a compensation capacitor. The source-drain conductive layer is disposed on the side of the first gate conductive layer away from the substrate. The source-drain conductive layer includes at least one second multiplexing connection line extending along the second direction. The second multiplexing connection line is connected to the active pattern of a corresponding second type of transistor and also connected to the first electrode of a corresponding compensation capacitor.

[0010] In some embodiments, the first power signal line is disposed on the source / drain conductive layer; the display panel further includes a second gate conductive layer disposed between the active layer and the first gate conductive layer; the second electrode of the compensation capacitor includes a first sub-plate disposed on the second gate conductive layer; the orthographic projection of the first sub-plate on the substrate overlaps with the orthographic projection of the first electrode on the substrate; the first sub-plate is connected to the first power signal line; and / or, the display panel further includes a third gate conductive layer disposed between the first gate conductive layer and the source / drain conductive layer; the second electrode of the compensation capacitor includes a second sub-plate disposed on the third gate conductive layer; the orthographic projection of the second sub-plate on the substrate overlaps with the orthographic projection of the first electrode on the substrate; the second sub-plate is connected to the first power signal line.

[0011] In some embodiments, the second multiplexing unit includes multiple second multiplexing connection lines, and the display panel includes multiple compensation units; one second multiplexing connection line is connected to the first plate of at least one compensation capacitor in a compensation unit; the second plate of the compensation capacitor includes a first sub-plate, and the first sub-plates of the multiple compensation capacitors of the multiple compensation units are integrally disposed; the second plate of the compensation capacitor includes a second sub-plate, and the second sub-plates of the multiple compensation capacitors of the multiple compensation units are integrally disposed.

[0012] In some embodiments, the first power signal line is disposed on the source-drain conductive layer; the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the first power signal line on the substrate; the portion of the first power signal line that overlaps with the first electrode plate forms the second electrode plate of the compensation capacitor.

[0013] In some embodiments, the orthographic projection of at least one compensation unit on the substrate overlaps with the orthographic projection of the first power signal line on the substrate.

[0014] In some embodiments, the second multiplexing unit further includes at least one third type transistor located on the side of the plurality of second type transistors away from the first multiplexing unit, and the third type transistor is configured to: not be connected to the data signal line; a second multiplexing connection line is also connected to a third number of third type transistors, the first number being equal to the sum of the second number and the third number.

[0015] In some embodiments, the orthographic projection of the first power signal line on the substrate is located on the side of the orthographic projection of the plurality of multiplexing units on the substrate that is closer to the display area; the first power signal line extends along a second direction; and the first plate of a compensation capacitor is connected via a first adapter wire and a third type of transistor.

[0016] In some embodiments, the orthographic projection of the first power signal line on the substrate is located on the side of the orthographic projection of the plurality of multiplexing units on the substrate that is away from the display area; the first power signal line extends along a second direction; and the first plate of a compensation capacitor is connected to a corresponding second multiplexing connection line via a second adapter line.

[0017] In some embodiments, at least one compensation unit is located on the side of the plurality of second-type transistors away from the first multiplexing unit, and also on the side of at least one second multiplexing connection line close to the display area; the first plate of a compensation capacitor is connected to the corresponding second multiplexing connection line via a third adapter line.

[0018] In some embodiments, the second multiplexing unit further includes at least one third multiplexing connection line, and a first number of second-type transistors are connected to the third multiplexing connection line.

[0019] In some embodiments, the difference between the number of first-type transistors connected to the first multiplex connection line and the number of second-type transistors connected to the second multiplex connection line is greater than or equal to 2; the compensation unit includes a first compensation capacitor and a second compensation capacitor, the first plate of the first compensation capacitor and the first plate of the second compensation capacitor are connected to the same second multiplex connection line; the second plate of the first compensation capacitor and the second plate of the second compensation capacitor are used to receive DC signals.

[0020] In some embodiments, the second plate of the first compensation capacitor and the second plate of the second compensation capacitor are integrally disposed.

[0021] In some embodiments, the first multiplexing unit includes nine first-type transistors and three first multiplexing connection lines, with one first multiplexing connection line connected to three first-type transistors; the first multiplexing unit also includes three control signal lines, with the gates of the three first-type transistors connected to the same first multiplexing connection line respectively connected to the three control signal lines; and three data signal lines connected to three columns of sub-pixels of the same color are connected to the same first multiplexing connection line through the three first-type transistors.

[0022] In some embodiments, the second multiplexing unit includes three second multiplexing connection lines; one second multiplexing connection line is connected to one or two second type transistors.

[0023] In some embodiments, the multiple data signal lines include multiple first data signal lines and at least one second data signal line, the second data signal line being configured to be connected to a virtual sub-pixel in the display panel; the multiple second type transistors in the second multiplexing unit include at least one first transistor and at least one second transistor, a first data signal line and a first transistor are connected, and a second data signal line and a second transistor are connected.

[0024] On the other hand, a display device is provided, which includes a display panel and a driver chip as described in any of the above embodiments, wherein the driver chip is connected to a first peripheral area of ​​the display panel.

[0025] In some embodiments, the display panel includes a first multiplexing unit and a second multiplexing unit, wherein the first multiplexing connection line in the first multiplexing unit and the second multiplexing connection line in the second multiplexing unit are respectively connected to the driver chip via fan-out lines. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 This is a top view of a display panel according to some embodiments;

[0028] Figure 2 This is a partial top view of a display panel according to some embodiments;

[0029] Figure 3 This is a partial cross-sectional view of a display panel according to some embodiments;

[0030] Figure 4 A top view (a) of a multiplexing unit according to some embodiments;

[0031] Figure 5 A top view (II) of a multiplexing unit according to some embodiments;

[0032] Figure 6 This is a top view of a first multiplexing unit and a second multiplexing unit according to some embodiments;

[0033] Figure 7 A top view (a) of a second multiplexing unit according to some embodiments;

[0034] Figure 8 A top view (II) of a second multiplexing unit according to some embodiments;

[0035] Figure 9A for Figure 8 A stacked diagram of an active layer and a second gate conductive layer;

[0036] Figure 9B for Figure 8 A film diagram of a first gate conductive layer;

[0037] Figure 9C for Figure 8 A stacked diagram of a third gate conductive layer and a source / drain conductive layer;

[0038] Figure 10 A top view (iii) of a second multiplexing unit according to some embodiments;

[0039] Figure 11A top view (four) of a second multiplexing unit according to some embodiments;

[0040] Figure 12 A top view (V) of a second multiplexing unit according to some embodiments;

[0041] Figure 13 A top view (VI) of a second multiplexing unit according to some embodiments;

[0042] Figure 14 A top view (VII) of a second multiplexing unit according to some embodiments;

[0043] Figure 15 A top view (eight) of a second multiplexing unit according to some embodiments;

[0044] Figure 16 A top view (IX) of a second multiplexing unit according to some embodiments. Detailed Implementation

[0045] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0048] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0051] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0052] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0053] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0054] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] Display devices can be any device that displays either moving (e.g., video) or stationary (e.g., still images), and whether it is text or images. Display devices include, but are not limited to, televisions, mobile phones, wearable devices, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, clocks, calculators, television monitors, flat panel displays, computer monitors, in-vehicle displays (e.g., odometer displays), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0056] The display device may include a display panel 1000. With the development of display technology, there are more and more types of display panels 1000. For example, the display panel 1000 may be an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (MicroOLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a mini light-emitting diode (Mini LED) display panel, a micro light-emitting diode (Micro LED) display panel, or a liquid crystal display (LCD) display panel, etc. Some embodiments of this application are described using an OLED display panel as an example.

[0057] like Figure 1 , Figure 2 As shown, the display panel 1000 may include a display area AA and a peripheral area BB located on at least one side of the display area AA. For example, the peripheral area BB is located on all four sides of the display area AA, that is, the peripheral area BB is located on the top, bottom, left, and right sides of the display area AA, and the peripheral area BB is arranged around the display area AA. The display area AA can be used to display images and set signal lines (such as gate signal lines, data signal lines, etc.); the peripheral area BB can be used to set signal lines (such as initialization signal lines, etc.) to ensure the normal display of the display panel 1000.

[0058] like Figure 1 As shown, the display area AA of the display panel 1000 can be set with multiple sub-pixels P. The sub-pixel P is the smallest unit for displaying images on the display panel 1000. Each sub-pixel P can display a single color, such as red (R), green (G), or blue (B). Multiple sub-pixels P can be arranged in an array.

[0059] like Figure 1 As shown, each sub-pixel P may include a light-emitting device EL and a pixel driving circuit D for driving the light-emitting device EL to emit light. That is, one sub-pixel P corresponds to one light-emitting device EL and one pixel driving circuit D. Multiple sub-pixels P can be arranged and set in the display area AA according to a specified rule.

[0060] In each sub-pixel P, the light-emitting device EL is electrically connected to the corresponding pixel driving circuit D below. In response to the received scan signal and data signal (e.g., the scan signal output by the scan driving circuit and the data signal output by the data driving circuit), the pixel driving circuit D provides an electrical signal (e.g., driving voltage or driving current) to the light-emitting device EL coupled to the pixel driving circuit D to drive the light-emitting device EL to emit light, thereby enabling the display panel 1000 to display an image.

[0061] The pixel driving circuit D may include multiple transistors and at least one (e.g., one; or multiple) capacitor. For example, the pixel driving circuit D may be a structure such as "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C". Here, "T" represents a transistor, such as a thin-film transistor. The number preceding "T" indicates the number of transistors. "C" represents a capacitor, and the number preceding "C" indicates the number of capacitors.

[0062] Light-emitting devices (ELs) can include organic light-emitting diodes (OLEDs). OLEDs are a type of current-driven organic light-emitting device that emits light through the injection and recombination of charge carriers. The luminous intensity is proportional to the injected current. Under the influence of an electric field, holes generated at the anode and electrons generated at the cathode move and are injected into the hole transport layer and electron transport layer, respectively, migrating to the light-emitting layer. When the two meet in the light-emitting layer, they generate energy excitons, which excite the light-emitting molecules to ultimately produce visible light. Depending on their formulation, the light-emitting molecules produce the three primary colors of red, green, and blue (RGB), which constitute the basic colors.

[0063] OLED display panels, made from OLEDs, have advantages such as high brightness, high efficiency, wide viewing angle, self-emissive, all-solid-state, ultra-thin and ultra-lightweight, simple manufacturing process, fast response speed, full-color display capability, and good machinability. They have been increasingly widely used in display products such as mobile phones, tablets, computers, and televisions.

[0064] The light-emitting device (EL) may also include micro organic light-emitting diodes (Micro OLED), quantum dot light-emitting diodes (QLED), mini light-emitting diodes (Mini LED), micro light-emitting diodes (Micro LED), or liquid crystal displays (LCD), etc. This disclosure does not limit the scope of the device. Some embodiments of this disclosure are illustrated using OLED as an example.

[0065] In some embodiments, the multiple light-emitting devices EL of the display panel 1000 may include red light-emitting devices, green light-emitting devices and blue light-emitting devices, which can emit red light, green light and blue light respectively, so that the sub-pixel P where the light-emitting devices EL of different colors are located can display red, green and blue respectively, thereby realizing the display of color images on the display panel 1000.

[0066] In other embodiments, the multiple light-emitting devices EL of the display panel 1000 can all be light-emitting devices of the same color, for example, they can all be blue light-emitting devices that emit blue light. Then, through other film layers (such as color conversion layers), the blue light emitted by the blue light-emitting devices can be converted into light of other colors, such as red light or green light, so that the sub-pixel P where the light-emitting device EL is located can display red, green, and blue respectively, thereby realizing the display of a color image on the display panel 1000.

[0067] In some embodiments, such as Figure 3 As shown, and refer to Figure 1 The display panel 1000 may include, for example, an array substrate 100.

[0068] The array substrate 100 can be used to set the pixel driving circuit D of the sub-pixel P in the display panel 1000, and can also be used to set multiple signal lines to drive the pixel driving circuit D. That is, the array substrate 100 can include multiple pixel driving circuits D and multiple signal lines.

[0069] like Figure 3As shown, the array substrate 100 may include a substrate 100-1, which supports other structures in the display panel 1000. The substrate 100-1 can be a flexible substrate, and the material of the flexible substrate can be polyethylene terephthalate (PET), polyethylene naphthalate (PEN), ultrathin glass, or polyimide (PI), etc. The substrate 100-1 can also be a rigid substrate, and the material of the rigid substrate can be glass or PMMA (polymethyl methacrylate), etc.

[0070] like Figure 3 As shown, and refer to Figure 1 The array substrate 100 may also include a plurality of conductive layers located on one side of the substrate 100-1 along its own thickness direction. The plurality of conductive layers can be used to form a plurality of pixel driving circuits D and a plurality of signal lines. That is, the plurality of pixel driving circuits D and the plurality of signal lines are disposed on one side of the substrate 100-1.

[0071] For example, such as Figure 3 As shown, the multiple conductive layers may include, for example, an active layer 100-2, a gate conductive layer 100-4, and a source / drain conductive layer 100-6, etc., stacked together. Of course, the array substrate 100 may also include other conductive layers, which can be specifically configured according to the actual situation, and this disclosure does not limit them.

[0072] The pixel driving circuit D may include at least one transistor TFT, and multiple conductive layers on the array substrate 100 may form at least one transistor TFT. For example, as Figure 3 As shown, the transistor TFT may include an active pattern t1 disposed on the active layer 100-2 and a gate pattern t2 disposed on the gate conductive layer 100-4; the active pattern t1 may be used to form the first electrode and the second electrode of the transistor TFT; the gate pattern t2 may be used to form the gate of the transistor TFT.

[0073] Exemplarily, the array substrate 100 may further include an insulating layer located between adjacent conductive layers, the insulating layer serving to isolate the adjacent conductive layers. For example, such as Figure 3As shown, the array substrate 100 may include a gate insulating layer 100-3 located between the active layer 100-2 and the gate conductive layer 100-4, an interlayer dielectric layer 100-5 located between the gate conductive layer 100-4 and the source / drain conductive layer 100-6, a passivation layer 100-7 located on the side of the source / drain conductive layer 100-6 away from the substrate 100-1, and a planarization layer 100-8. The array substrate 100 may also include other insulating layers, which may be specifically configured according to actual conditions, and are not limited herein.

[0074] In some embodiments, such as Figure 3 As shown, the display panel 1000 may also include a light-emitting device layer 200 disposed on one side of the array substrate 100. The light-emitting device layer 200 may be specifically disposed on the side of the array substrate 100 away from the substrate 100-1.

[0075] The light-emitting device layer 200 can be used to set the light-emitting device EL of the sub-pixel P in the display panel 1000.

[0076] For example, such as Figure 3 As shown, the light-emitting device layer 200 may include a first electrode layer 200-1, a pixel defining layer 200-2, a light-emitting layer 200-3, and a second electrode layer 200-4 stacked from bottom to top. The first electrode layer 200-1 of the light-emitting device layer 200 may be an anode layer, for example, and may include at least one first electrode. The pixel defining layer 200-2 includes at least one pixel opening, and the light-emitting layer 200-3 includes at least one light-emitting portion. A pixel opening may expose a first electrode. A light-emitting portion is disposed within a pixel opening. The second electrode layer 200-4 may be a cathode layer, for example, and may be disposed as a single layer, located on the side of the light-emitting layer 200-3 and the pixel defining layer 200-2 away from the array substrate 100.

[0077] The first electrode layer 200-1 can be used to set the first electrode of the light-emitting device EL, that is, the first electrode of the first electrode layer 200-1 can be the first electrode of the light-emitting device EL; the second electrode layer 200-4 can be used to set the second electrode of the light-emitting device EL.

[0078] The first electrode layer 200-1 can be formed, for example, by a conductive material with a high work function, including indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc gallium oxide (GZO), zinc oxide (ZnO), indium oxide (In2O3), zinc aluminum oxide (AZO), and carbon nanotubes, etc.

[0079] The first electrode layer 200-1 may include only one conductive material layer or multiple conductive material layers. For example, the first electrode layer 200-1 may include three conductive material layers, which may be indium tin oxide, silver, and indium tin oxide, respectively.

[0080] The second electrode layer 200-4 can be formed of a material with high conductivity and low work function, such as an alloy of magnesium-aluminum (MgAl) and lithium-aluminum (LiAl) or a metallic element such as magnesium (Mg), aluminum (Al), lithium (Li) and silver.

[0081] The material of the light-emitting layer 200-3 may include low molecular weight organic materials or polymer materials, which are fluorescent or phosphorescent materials that can emit red, green, blue or white light under the action of an electric field.

[0082] To improve the luminous efficiency of the light-emitting device EL in the display panel 1000, the light-emitting device layer 200 may also include one or more of the following: an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0083] In some embodiments, such as Figure 3 As shown, the display panel 1000 may also include, for example, an encapsulation layer 300 disposed on the side of the light-emitting device layer 200 away from the array substrate 100.

[0084] For example, such as Figure 3 As shown, the encapsulation layer 300 may include a first encapsulation layer 300-1, a second encapsulation layer 300-2, and a third encapsulation layer 300-3 stacked along a direction away from the substrate 100-1; wherein, the first encapsulation layer 300-1 and the third encapsulation layer 300-3 may be inorganic materials and may be formed by plasma chemical vapor deposition process; the second encapsulation layer 300-2 may be organic materials and may be formed by inkjet printing process.

[0085] The encapsulation layer 300 covers the side of the light-emitting device layer 200 away from the substrate 100-1, and encapsulates the display panel 1000 to prevent moisture and oxygen from the external environment from entering the display panel 1000 and damaging the organic materials in the light-emitting device layer 200, thereby shortening the lifespan of the display panel 1000.

[0086] For example, such as Figure 1As shown, the display area AA of the display panel 1000 can be provided with multiple data signal lines Data. These multiple data signal lines Data can extend along a first direction X, which can be, for example, the column direction of a multi-subpixel array P. A column of subpixels P can be connected to one data signal line Data.

[0087] For example, such as Figure 1 As shown, the peripheral area BB of the display panel 1000 may include a first peripheral area BB1 located on one side of the display area AA in the first direction X. For example, the upper and lower sides of the display area AA are located in the first direction X, and the first peripheral area BB1 may be located on the lower side of the display area AA.

[0088] The first peripheral area BB1 of the display panel 1000 can, for example, be used to bond a driver chip IC, so that multiple data signal lines Data of the display area AA can be electrically connected to corresponding pins of the driver chip IC. The driver chip IC can send data signals to the multiple data signal lines Data respectively, thereby driving the display panel 1000 to display an image.

[0089] Driver chip ICs can be central processing units (CPUs), digital signal processors (DSPs), microcontrollers, programmable logic controllers (PLCs), etc. For example, driver chip ICs may also include memory, power modules, etc., and achieve power supply and signal input / output functions through separately configured wires and signal lines. For example, driver chip ICs may also include hardware circuits and computer-executable code. Hardware circuits may include conventional very large-scale integration circuits (VLSIs) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; hardware circuits may also include field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc.

[0090] For example, the number of driver chip ICs can be set according to the actual situation, and this disclosure does not impose any restrictions.

[0091] As the resolution of the display panel 1000 continues to increase, the number of data signal lines Data within the display area AA of the display panel 1000 also increases. This leads to an increase in the number of fan-out lines F connecting the data signal lines Data to the driver chip IC within the first peripheral area BB1 of the display panel 1000. Simultaneously, this results in an increase in the number of pins integrated within the driver chip IC that connect to the data signal lines Data. However, due to the size limitations of the driver chip IC itself, it cannot accommodate too many pins connecting to the data signal lines Data. This may cause the driver chip IC to be unable to adapt to the high-resolution display panel 1000, or the display panel 1000 to require connection to a large number of driver chip ICs, thereby increasing the manufacturing cost of the display device and increasing the size of the display device's bezel. Furthermore, having too many fan-out lines F in the first peripheral area BB1 can easily lead to short circuits between the fan-out lines F, significantly reducing product yield.

[0092] Therefore, in order to ensure that the driver chip IC can be adapted to the high-resolution display panel 1000, and to reduce the number of fan-out lines F in the first peripheral area BB1, such as Figure 1 , Figure 2 As shown, a multiplexing structure 400 can be set in the first peripheral area BB1 of the display panel 1000, and multiple data signal lines Data in the display area AA of the display panel 1000 can be connected to the driver chip IC through the multiplexing structure 400.

[0093] For example, such as Figure 1 , Figure 2 As shown, multiple data signal lines Data within the display area AA of the display panel 1000 can all be connected to the multiplexing structure 400. The multiplexing structure 400 can be connected to the driver chip IC via multiple fan-out lines F, and the number of fan-out lines F is less than the number of data signal lines Data within the display area AA. Therefore, the number of pins integrated within the driver chip IC that are connected to the data signal lines Data can be reduced, enabling the driver chip IC to adapt to the high-resolution display panel 1000; at the same time, the number of fan-out lines F in the first peripheral area BB1 of the display panel 1000 is reduced, improving the yield of the display panel 1000.

[0094] Specifically, it can be, for example Figure 1 , Figure 2 As shown, the multiplexing structure 400 may include multiple multiplexing units (MUX). The multiple multiplexing units MUX in the multiplexing structure 400 may be arranged along the boundary line between the display area AA and the first peripheral area BB1, that is, the multiple multiplexing units MUX may be arranged along the second direction Y, and each multiplexing unit MUX may extend along the second direction Y.

[0095] In this configuration, the second direction Y intersects the first direction X. For example, the second direction Y can be the row direction of an array of multiple sub-pixels P, and the second direction Y is perpendicular to the first direction X.

[0096] like Figure 4 As shown, and refer to Figure 1 A multiplexing unit (MUX) may include, for example, multiple transistor TFTs, which may be arranged sequentially along the second direction Y. The first electrode of one transistor TFT may be connected to a data signal line Data, and the second electrodes of at least two of the multiple transistor TFTs may be connected to a fan-out line F, which is connected to a driver chip IC.

[0097] For example, such as Figure 4 As shown, and refer to Figure 1 The multiple sub-pixels P of the display area AA in the display panel 1000 may include, for example, a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may emit light of different colors, for example.

[0098] For example, the first sub-pixel P1 can emit red light, the second sub-pixel P2 can emit green light, and the third sub-pixel P3 can emit blue light; or, for example, the first sub-pixel P1 can emit red light, the second sub-pixel P2 can emit blue light, and the third sub-pixel P3 can emit green light; or, for example, the first sub-pixel P1 can emit green light, the second sub-pixel P2 can emit red light, and the third sub-pixel P3 can emit blue light; or, for example, the first sub-pixel P1 can emit green light, the second sub-pixel P2 can emit blue light, and the third sub-pixel P3 can emit red light; or, for example, the first sub-pixel P1 can emit blue light, the second sub-pixel P2 can emit red light, and the third sub-pixel P3 can emit green light; or, for example, the first sub-pixel P1 can emit blue light, the second sub-pixel P2 can emit green light, and the third sub-pixel P3 can emit red light; this disclosure is not limited thereto. This disclosure uses the example of the first sub-pixel P1 emitting red light, the second sub-pixel P2 emitting green light, and the third sub-pixel P3 emitting blue light for illustration.

[0099] For example, such as Figure 4 As shown, and refer to Figure 1In the display panel 1000, the multiple sub-pixels P of the display area AA can be arranged in an array; the multiple sub-pixels P in each column can emit light of the same color, and the multiple sub-pixels P in each row can be arranged in a cyclical manner as first sub-pixel P1, second sub-pixel P2, third sub-pixel P3, first sub-pixel P1, second sub-pixel P2, third sub-pixel P3, etc. That is, in the display area AA of the display panel 1000, the sub-pixels P in the first column can all be the first sub-pixel P1, the sub-pixels P in the second column can all be the second sub-pixel P2, the sub-pixels P in the third column can all be the third sub-pixel P3, the sub-pixels P in the fourth column can all be the first sub-pixel P1, the sub-pixels P in the fifth column can all be the second sub-pixel P2, the sub-pixels P in the sixth column can all be the third sub-pixel P3, and so on.

[0100] It should be noted that the arrangement of the multiple sub-pixels P of the display area AA in the display panel 1000 is not limited to the above arrangement method, and can be specifically set according to the specific application. For example, in some other embodiments, the multiple sub-pixels P of the display area AA in the display panel 1000 are not arranged in an array, but are arranged irregularly according to the specific space of the display area AA of the display panel 1000. For example, the first sub-pixel P1 and the second sub-pixel P2 can be arranged around the third sub-pixel P3, etc. This disclosure does not limit this.

[0101] This disclosure describes an arrangement in the display area AA of the display panel 1000 where the subpixels P in the first column are all first subpixels P1, the subpixels P in the second column are all second subpixels P2, the subpixels P in the third column are all third subpixels P3, the subpixels P in the fourth column are all first subpixels P1, the subpixels P in the fifth column are all second subpixels P2, and the subpixels P in the sixth column are all third subpixels P3, etc.

[0102] In some embodiments, such as Figure 4 As shown, and refer to Figure 1 In the display area AA of the display panel 1000, a column of sub-pixels P can be connected to a data signal line Data. The nine data signal lines Data connected to the nine adjacent columns of sub-pixels P can be connected to the driver chip IC through a multiplexing unit MUX.

[0103] Specifically, such as Figure 4 As shown, a multiplexing unit MUX may include, for example, nine transistors TFT, which may be the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9.

[0104] like Figure 4As shown, the nine data signal lines Data may include the first data signal line D1 connected to the sub-pixel P in the first column, the second data signal line D2 connected to the sub-pixel P in the second column, the third data signal line D3 connected to the sub-pixel P in the third column, the fourth data signal line D4 connected to the sub-pixel P in the fourth column, the fifth data signal line D5 connected to the sub-pixel P in the fifth column, the sixth data signal line D6 connected to the sub-pixel P in the sixth column, the seventh data signal line D7 connected to the sub-pixel P in the seventh column, the eighth data signal line D8 connected to the sub-pixel P in the eighth column, and the ninth data signal line D9 connected to the sub-pixel P in the ninth column.

[0105] like Figure 4 As shown, the first electrode of the nine transistor TFTs (transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, and transistor T9) can be connected to the nine data signal lines Data (data signal line D1, data signal line D2, data signal line D3, data signal line D4, data signal line D5, data signal line D6, data signal line D7, data signal line D8, and data signal line D9) respectively.

[0106] A multiplexing unit (MUX) can be connected to a driver chip IC, for example, via one or more fan-out lines F. In some embodiments, such as... Figure 4 As shown, and refer to Figure 1 A multiplexing unit (MUX) can be connected to a driver chip IC, for example, through three fan-out lines F.

[0107] For example, the first terminal of the first transistor T1 can be connected to the first data signal line D1, the first terminal of the fourth transistor T4 can be connected to the fourth data signal line D4, and the first terminal of the seventh transistor T7 can be connected to the seventh data signal line D7; the second terminals of the first transistor T1, the fourth transistor T4, and the seventh transistor T7 are connected and connected to a fan-out line F. Among these, multiple sub-pixels P in the first column of sub-pixels P connected to the first data signal line D1, the fourth column of sub-pixels P connected to the fourth data signal line D4, and the seventh column of sub-pixels P connected to the seventh data signal line D7 can all be the first sub-pixel P1.

[0108] For example, the first terminal of the second transistor T2 can be connected to the second data signal line D2, the first terminal of the fifth transistor T5 can be connected to the fifth data signal line D5, and the first terminal of the eighth transistor T8 can be connected to the eighth data signal line D8; the second terminals of the second transistor T2, the fifth transistor T5, and the eighth transistor T8 are connected and connected to a fan-out line F. Multiple sub-pixels P in the second column (connected to the second data signal line D2), the fifth column (connected to the fifth data signal line D5), and the eighth column (connected to the eighth data signal line D8) can all be the second sub-pixel P2.

[0109] For example, the first terminal of the third transistor T3 can be connected to the third data signal line D3, the first terminal of the sixth transistor T6 can be connected to the sixth data signal line D6, and the first terminal of the ninth transistor T9 can be connected to the ninth data signal line D9; the second terminals of the third transistor T3, the sixth transistor T6, and the ninth transistor T9 are connected and connected to a fan-out line F. Multiple sub-pixels P in the third column (connected to the third data signal line D3), the sixth column (connected to the sixth data signal line D6), and the ninth column (connected to the ninth data signal line D9) can all be the third sub-pixel P3.

[0110] In other embodiments, three data signal lines Data connected to three consecutively adjacent sub-pixels P can be connected to the driver chip IC through a multiplexing unit MUX. In this case, the multiplexing unit MUX may include, for example, three transistor TFTs. In still other embodiments, six data signal lines Data connected to six consecutively adjacent sub-pixels P can be connected to the driver chip IC through a multiplexing unit MUX. In this case, the multiplexing unit MUX may include, for example, six transistor TFTs. This disclosure does not limit the number of data signal lines Data connected to a multiplexing unit MUX.

[0111] In some embodiments, such as Figure 4 As shown, a multiplexing unit MUX may also include at least one control signal line K. That is, a multiplexing unit MUX may include one control signal line K, or a multiplexing unit MUX may include multiple control signal lines K. This disclosure uses a multiplexing unit MUX including three control signal lines K as an example for illustration.

[0112] For example, such as Figure 4As shown, a multiplexing unit (MUX) may include, for example, three control signal lines K, which may extend along a second direction Y. The three control signal lines K may be a first control signal line K1, a second control signal line K2, and a third control signal line K3. The gates of the first transistor T1, the second transistor T2, and the third transistor T3 may be connected to the first control signal line K1, which controls the on / off state of these transistors. The gates of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be connected to the second control signal line K2, which controls their on / off state. The gates of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be connected to the third control signal line K3, which controls their on / off state.

[0113] like Figure 4 As shown, and refer to Figure 1 , Figure 2 One multiplexing unit MUX can be connected to nine data signal lines Data; therefore, when the number of data signal lines Data in the display area AA is a multiple of nine, all the transistor TFTs of the multiplexing unit MUX in the multiplexing structure 400 can be connected to one data signal line Data.

[0114] However, as Figure 5 As shown, and refer to Figure 1 , Figure 2 When the number of data signal lines Data located in the display area AA is not a multiple of nine, a multiplexing unit MUX at the edge of the multiplexing structure 400 will be connected to fewer than nine data signal lines Data, resulting in some transistors TFT in the multiplexing unit MUX not being connected to the data signal lines Data.

[0115] For example, such as Figure 5 As shown, and refer to Figure 1 , Figure 2When the rightmost six data signal lines Data in the display area AA are not connected to the multiplexing unit MUX, only six transistor TFTs in the rightmost multiplexing unit MUX of the multiplexing structure 400 can be connected to the six data signal lines Data respectively. The remaining three transistor TFTs (e.g., the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9) cannot be connected to the data signal lines Data. This will cause the rightmost multiplexing unit MUX to be connected to a different load than the multiplexing unit MUX that normally connects to nine data signal lines Data. When the voltage signal input from the driver chip IC to the multiplexing unit MUX alternates between high and low voltage, the voltage difference between the multiplexing units MUX with different connected loads will be too large, causing crosstalk coupling between the write voltages transmitted to the data signal lines Data, thus causing bright and dark lines on the display panel 1000.

[0116] Based on this, in some embodiments, a display panel 1000 is provided, such as... Figure 6 , Figure 7 , Figure 8 As shown, and refer to Figure 1 , Figure 2 , Figure 4 , Figure 5The display panel 1000 includes a display area AA and a first peripheral area BB1 located on one side of the display area AA along a first direction X. The first peripheral area BB1 is used to connect to a driver chip IC. The display panel 1000 includes a substrate 100-1, and multiple data signal lines Data, multiple multiplexing units MUX, and at least one compensation unit 500 disposed on the substrate 100-1. The multiple data signal lines Data are located in the display area AA and extend along the first direction X. The multiple multiplexing units MUX are located in the first peripheral area BB1 and arranged along a second direction Y, the second direction Y being perpendicular to the first direction X. The multiple multiplexing units MUX include multiple first multiplexing units MUX1 and at least one second multiplexing unit MUX2 located on at least one side of the multiple first multiplexing units MUX1 along the second direction Y. The first multiplexing unit MUX1 includes multiple first multiplexing units MUX1. A first multiplexer TFT1 is connected to at least one first multiplexed connection line L1, a data signal line Data is connected to a first multiplexer TFT1, and a first number of first multiplexer TFT1s are connected to a first multiplexed connection line L1; a second multiplexer MUX2 includes multiple second multiplexer TFT2s and at least one second multiplexed connection line L2, a data signal line Data is connected to a second multiplexer TFT2, and a second number of second multiplexer TFT2s are connected to a second multiplexed connection line L2; the second number is less than the first number; at least one compensation unit 500 is located in a first peripheral region BB1, and one compensation unit 500 is connected to a second multiplexed connection line L2. The compensation unit 500 is configured to make the load connected to the second multiplexer MUX2 the same as or substantially the same as the load connected to the first multiplexer MUX1.

[0117] For example, multiple multiplexing units (MUX) may include multiple first multiplexing units (MUX1). Figure 6 As shown, and refer to Figure 4 The first multiplexing unit MUX1 may include a plurality of first type transistors TFT1 and at least one first multiplexing connection line L1. A data signal line Data may be connected to a first type transistor TFT1, and a first number of first type transistors TFT1 may be connected to a first multiplexing connection line L1.

[0118] Specifically, such as Figure 6 As shown, and refer to Figure 1 , Figure 4The first multiplexing unit MUX1 may include, for example, nine first-type transistors TFT1 and three first multiplexing connection lines L1; one data signal line Data can be connected to one first-type transistor TFT1, that is, the first electrode of the nine first-type transistors TFT1 in the first multiplexing unit MUX1 can be connected to the nine data signal lines Data in the display area AA respectively; one first multiplexing connection line L1 can be connected to three first-type transistors TFT1, that is, the three first multiplexing connection lines L1 in the first multiplexing unit MUX1 can all be connected to the second electrode of the three first-type transistors TFT1.

[0119] For example, such as Figure 6 As shown, and refer to Figure 1 , Figure 4 The three data signal lines Data connected to the three columns of sub-pixels P of the same color can be connected to the same first multiplexed connection line L1 through three first-type transistors TFT1; the first multiplexed connection line L1 can be connected to a fan-out line F, and the fan-out line F is connected to the driver chip IC. The control signal output by the driver chip IC can be transmitted to the three data signal lines Data connected to the three columns of sub-pixels P of the same color through the fan-out line F.

[0120] like Figure 6 As shown, and refer to Figure 4 The first multiplexing unit MUX1 may further include three control signal lines K, wherein the gates of three first-type transistors TFT1 connected to the same first multiplexing connection line L1 can be respectively connected to the three control signal lines K. The three first-type transistors TFT1 connected to the same first multiplexing connection line L1 are respectively turned on or off in response to the control signals transmitted by the three control signal lines K.

[0121] This disclosure does not specifically limit the number of first-type transistors TFT1 and first multiplexing connection lines L1 in the first multiplexing unit MUX1. The number of first-type transistors TFT1 and first multiplexing connection lines L1 in the first multiplexing unit MUX1 can be specifically set according to the specific actual process.

[0122] For example, the plurality of multiplexing units MUX may further include at least one second multiplexing unit MUX2 located on at least one side of all first multiplexing units MUX1 along the second direction Y. For example, a second multiplexing unit MUX2 may be provided on each side of all first multiplexing units MUX1 along the second direction Y; or a second multiplexing unit MUX2 may be provided on one side of all first multiplexing units MUX1 along the second direction Y. The second multiplexing unit MUX2 is located at the edge of the multiplexing structure 400.

[0123] like Figure 7 , Figure 8 As shown, and refer to Figure 5 The second multiplexing unit MUX2 may include a plurality of second-type transistors TFT2 and at least one second multiplexing connection line L2. A data signal line Data may be connected to a second-type transistor TFT2. A second number of second-type transistors TFT2 may be connected to a second multiplexing connection line L2; wherein the second number is less than the first number.

[0124] Specifically, such as Figure 7 , Figure 8 As shown, and refer to Figure 1 , Figure 5 The second multiplexing unit MUX2 may include six second-type transistors TFT2 and three second multiplexing connection lines L2. One data signal line Data can be connected to one second-type transistor TFT2. That is, the first electrode of the six second-type transistors TFT2 in the second multiplexing unit MUX2 can be connected to the six data signal lines Data in the display area AA respectively. One second multiplexing connection line L2 can be connected to two second-type transistors TFT2. That is, all three second multiplexing connection lines L2 in the second multiplexing unit MUX2 can be connected to the second electrode of two second-type transistors TFT2.

[0125] In some embodiments, the second multiplexing unit MUX2 may include seven second-type transistors TFT2 and two second multiplexing connection lines L2, each of which can be connected to the second terminal of two second-type transistors TFT2. In still other embodiments, the second multiplexing unit MUX2 may further include three second-type transistors TFT2 and three second multiplexing connection lines L2, each of which can be connected to the second terminal of one second-type transistor TFT2.

[0126] This disclosure does not specifically limit the number of second-type transistors TFT2 and the number of second multiplexing connection lines L2 in the second multiplexing unit MUX2, as long as the number of second-type transistors TFT2 connected on the second multiplexing connection line L2 in the second multiplexing unit MUX2 is less than the number of first-type transistors TFT1 connected on the first multiplexing connection line L1.

[0127] For example, such as Figure 7 , Figure 8 As shown, and refer to Figure 1 , Figure 5Multiple data signal lines (Data) connected to multiple second-type transistors (TFTs) connected to the same second multiplexed connection line L2 are all connected to sub-pixels P of the same color. A second multiplexed connection line L2 can be connected to a fan-out line F, which is connected to the driver chip IC. The control signal output by the driver chip IC can be transmitted via the fan-out line F to the data signal line (Data) connected to the corresponding column's sub-pixels P of the same color.

[0128] like Figure 7 , Figure 8 As shown, and refer to Figure 5 The second multiplexing unit MUX2 may further include three control signal lines K, wherein the gates of two second-type transistors TFT2 connected to the same second multiplexing connection line L2 may be connected to two of the control signal lines K respectively. The plurality of second-type transistors TFT2 connected to the same second multiplexing connection line L2 are turned on or off in response to the control signal transmitted through their respective connected control signal lines K.

[0129] It is understandable that when there is only one second-type transistor TFT2 connected on a second multiplexed connection line L2, the gate of the second-type transistor TFT2 can be connected to one of the control signal lines K.

[0130] It should be noted that, referring to Figure 2 , Figure 6 The multiplexing structure 400 may include three control signal lines K, which extend along the second direction Y. The three control signal lines K can be used as three control signal lines K in the first multiplexing unit MUX1, and also as three control signal lines K in the second multiplexing unit MUX2.

[0131] In some embodiments, such as Figure 7 , Figure 8 As shown, and refer to Figure 1 , Figure 2 The display panel 1000 may also include at least one compensation unit 500 located in the first peripheral area BB1; the number of compensation units 500 may be the same as the number of second multiplexed connection lines L2, and one compensation unit 500 may be connected to one second multiplexed connection line L2.

[0132] The compensation unit 500 can be configured to make the load connected to the second multiplexing unit MUX2 the same as or substantially the same as the load connected to the first multiplexing unit MUX1.

[0133] In some embodiments of this disclosure, at least one compensation unit 500 is provided in the sufficient space of the first peripheral area BB1, and each compensation unit 500 is connected to a second multiplexing connection line L2 to increase the load connected to each second multiplexing connection line L2 of the outermost second multiplexing unit MUX2 in the multiplexing structure 400. This makes the load connected to each second multiplexing connection line L2 of the second multiplexing unit MUX2 approximately the same as the load connected to the first multiplexing connection line L1 of the first multiplexing unit MUX1. This ensures that the load connected to the second multiplexing unit MUX2 is the same as or approximately the same as the load connected to the first multiplexing unit MUX1, thus avoiding the problem of bright and dark lines on the display panel 1000.

[0134] For example, "same or substantially the same" means that the difference between the load connected to the second multiplexing unit MUX2 and the load connected to the first multiplexing unit MUX1 is within a preset range. The preset range can be set according to the actual situation. When the difference between the load connected to the second multiplexing unit MUX2 and the load connected to the first multiplexing unit MUX1 is within the preset range, the display panel 1000 will not have a problem with bright and dark lines.

[0135] The above settings improve the display resolution and image quality of the display panel 1000, effectively reduce the number of fan-out lines F in the first peripheral area BB1, achieving a more compact circuit layout and making the display panel 1000 thinner and lighter; enhance the brightness uniformity and contrast of the display panel 1000, improve color accuracy and absoluteness, increase the viewing angle range, accelerate the signal transmission speed of the display panel 1000, optimize the charging efficiency of sub-pixels P, reduce the impact of electromagnetic interference, achieve a higher refresh rate, and reduce the power consumption of the display panel 1000; they also enhance the stability and reliability of the display panel 1000. This system improves display performance, reduces production costs, enhances dynamic response for smoother screen transitions, reduces ghosting, optimizes image detail, improves grayscale levels, enhances adaptability to ambient light, reduces noise, extends lifespan, improves heat dissipation for optimal performance at varying temperatures, increases humidity tolerance, reduces dust impact, optimizes shock resistance, improves vibration resistance, enhances anti-static properties to ensure normal operation under low voltage, and improves stability under high voltage. It also optimizes self-calibration, enhances intelligent control, reduces color deviation, improves color consistency, reduces geometric distortion, enhances image clarity, optimizes icon display, and improves video playback quality.

[0136] In some embodiments, such as Figure 7 , Figure 8 As shown, the compensation unit 500 may include at least one compensation capacitor C. For example, the compensation unit 500 may include one compensation capacitor C; or, for another example, the compensation unit 500 may include two compensation capacitors C. This disclosure does not limit the number of compensation capacitors C in the compensation unit 500.

[0137] like Figure 7 , Figure 8 As shown, the compensation capacitor C may include a first plate C-1 and a second plate C-2. The first plate C-1 of the compensation capacitor C may be connected to the second multiplexing connection line L2, and the second plate C-2 of the compensation capacitor C may be used to receive DC signals.

[0138] In some embodiments, such as Figure 7 , Figure 8 As shown, and refer to Figure 2 The display panel 1000 may include a first power signal line V1, which may be located in the first peripheral area BB1. The first power signal line V1 may transmit a high-voltage signal, such as a Vdd signal. The second plate C-2 of the compensation capacitor C may be connected to the first power signal line V1.

[0139] In some embodiments, such as Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, and refer to Figure 3 ,in, Figure 9A for Figure 8 A stacked diagram of the active layer and the second gate conductive layer; Figure 9B for Figure 8 A diagram of the first gate conductive layer in the middle; Figure 9C for Figure 8The image shows a stacked diagram of the third gate conductive layer and the source / drain conductive layer. The display panel 1000 includes an active layer 100-2, a first gate conductive layer 100-42, and a source / drain conductive layer 100-6. The active layer 100-2 is disposed on one side of the substrate 100-1 along its own thickness direction. The active layer 100-2 includes multiple active patterns t1 arranged along the second direction Y. The multiple active patterns t1 are used to form the first and second electrodes of each transistor TFT in multiple multiplexed units (MUXs). The first gate conductive layer 100-42 is disposed away from the substrate of the active layer 100-2. On one side of 100-1; the first gate conductive layer 100-42 includes the first electrode C-1 of the compensation capacitor C; the source-drain conductive layer 100-6 is disposed on the side of the first gate conductive layer 100-42 away from the substrate 100-1; the source-drain conductive layer 100-6 includes at least one second multiplexing connection line L2 extending along the second direction Y, the second multiplexing connection line L2 is connected to the active pattern t1 of the corresponding second type transistor TFT2, and is also connected to the first electrode C-1 of the corresponding compensation capacitor C.

[0140] For example, such as Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, and refer to Figure 3 The gate conductive layer 100-4 may include, for example, a first gate conductive layer 100-42, a second gate conductive layer 100-41, and a third gate conductive layer 100-43.

[0141] In some embodiments, such as Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, and refer to Figure 3 The display panel 1000 may include an active layer 100-2, a second gate conductive layer 100-41, a first gate conductive layer 100-42, a third gate conductive layer 100-43, and a source / drain conductive layer 100-6 stacked along a direction away from the substrate 100-1.

[0142] like Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, and refer to Figure 3 The active layer 100-2 may include a plurality of active patterns t1 arranged along the second direction Y. The plurality of active patterns t1 may be used to form the first and second electrodes of each transistor TFT in a plurality of multiplexed units MUX.

[0143] like Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, and refer to Figure 3 The second gate conductive layer 100-41 may include a plurality of gate patterns t2 arranged along the second direction Y. The orthographic projection of a gate pattern t2 on the substrate 100-1 overlaps with the orthographic projection of an active pattern t1 on the substrate 100-1. The plurality of gate patterns t2 can be used to form the gate of each transistor TFT in a plurality of multiplexed units MUX.

[0144] like Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, the first gate conductive layer 100-42 may include the first plate C-1 of the compensation capacitor C.

[0145] like Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, the source / drain conductive layer 100-6 may include at least one second multiplexed connection line L2 extending along the second direction Y. The second multiplexed connection line L2 may be connected to the active pattern t1 of the corresponding second type transistor TFT2, and also to the first plate C-1 of the corresponding compensation capacitor C. That is, one second multiplexed connection line L2 may be connected to a second number of active patterns t1 forming the first and second electrodes of the second type transistor TFT2, and also to the first plate C-1 of all compensation capacitors C in a compensation unit 500.

[0146] In some embodiments, such as Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9CAs shown, the first power signal line V1 is disposed on the source-drain conductive layer 100-6; the display panel 1000 also includes a second gate conductive layer 100-41, which is disposed between the active layer 100-2 and the first gate conductive layer 100-42; the second electrode C-2 of the compensation capacitor C includes a first sub-plate C-21, which is disposed on the second gate conductive layer 100-41; the orthographic projection of the first sub-plate C-21 on the substrate 100-1 overlaps with the orthographic projection of the first electrode C-1 on the substrate 100-1; the first sub-plate C-21 and the first The power signal line V1 is connected; and / or, the display panel 1000 further includes a third gate conductive layer 100-43, which is disposed between the first gate conductive layer 100-42 and the source / drain conductive layer 100-6; the second electrode C-2 of the compensation capacitor C includes a second sub-plate C-22, which is disposed between the third gate conductive layer 100-43; the orthographic projection of the second sub-plate C-22 on the substrate 100-1 overlaps with the orthographic projection of the first electrode C-1 on the substrate 100-1; the second sub-plate C-22 is connected to the first power signal line V1.

[0147] like Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, the source / drain conductive layer 100-6 may further include a first power signal line V1 extending along the second direction Y.

[0148] For example, such as Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, and refer to Figure 3 The second plate C-2 of the compensation capacitor C may include a first sub-plate C-21, which may be disposed on the second gate conductive layer 100-41. The orthographic projection of the first sub-plate C-21 on the substrate 100-1 overlaps with the orthographic projection of the first plate C-1 on the substrate 100-1. The first sub-plate C-21 may be connected to the first power signal line V1.

[0149] For example, such as Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, and refer to Figure 3The second plate C-2 of the compensation capacitor C may include a second sub-plate C-22, which may be disposed on the third gate conductive layer 100-43; the orthographic projection of the second sub-plate C-22 on the substrate 100-1 overlaps with the orthographic projection of the first plate C-1 on the substrate 100-1; the second sub-plate C-22 may be connected to the first power signal line V1.

[0150] For example, such as Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, and refer to Figure 3 The second plate C-2 of the compensation capacitor C may include a first sub-plate C-21 and a second sub-plate C-22. The first sub-plate C-21 may be disposed on the second gate conductive layer 100-41, and the second sub-plate C-22 may be disposed on the third gate conductive layer 100-43. The orthographic projections of the first sub-plate C-21 and the second sub-plate C-22 on the substrate 100-1 overlap with the orthographic projection of the first plate C-1 on the substrate 100-1. The first sub-plate C-21 and the second sub-plate C-22 may be connected to the first power signal line V1.

[0151] In some embodiments, such as Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, when the second multiplexing unit MUX2 includes multiple second multiplexing connection lines L2, the display panel 1000 may include multiple compensation units 500; one second multiplexing connection line L2 may be connected to the first plate C-1 of all compensation capacitors C in a compensation unit 500.

[0152] like Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, when the second plate C-2 of the compensation capacitor C includes the first sub-plate C-21, the first sub-plate C-21 of the multiple compensation capacitors C of the multiple compensation units 500 can be integrally arranged.

[0153] like Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C As shown, when the second plate C-2 of the compensation capacitor C includes the second sub-plate C-22, the second sub-plate C-22 of the multiple compensation capacitors C of the multiple compensation units 500 can be integrally set.

[0154] In some embodiments, such as Figure 10 As shown, and refer to Figure 3 The first power signal line V1 can be disposed on the source-drain conductive layer 100-6. The orthographic projection of the first plate C-1 of the compensation capacitor C on the substrate 100-1 can overlap with the orthographic projection of the first power signal line V1 on the substrate 100-1; the portion of the first power signal line V1 that overlaps with the first plate C-1 of the compensation capacitor C can form the second plate C-2 of the compensation capacitor C.

[0155] For example, the first electrode C-1 and the first power signal line V1 form a compensation capacitor C, and the first electrode C-1 is connected to the second multiplexing connection line L2. This can increase the load connected to each second multiplexing connection line L2 of the second multiplexing unit MUX2 at the edge of the multiplexing structure 400, so that the load connected to each second multiplexing connection line L2 of the second multiplexing unit MUX2 is approximately the same as the load connected to the first multiplexing connection line L1 of the first multiplexing unit MUX1. This makes the load connected to the second multiplexing unit MUX2 the same as or approximately the same as the load connected to the first multiplexing unit MUX1, thus avoiding the problem of bright and dark lines on the display panel 1000.

[0156] Meanwhile, by utilizing the portion of the first power signal line V1 that overlaps with the first electrode C-1 to form the second electrode C-2 of the compensation capacitor C, the manufacturing process can be simplified, and the signal lines within the display panel can be fully utilized.

[0157] In some embodiments, such as Figure 8 , Figure 10 As shown, and refer to Figure 3 At least one compensation unit 500, for example, the orthographic projection of all compensation units 500 in the display panel 1000 onto the substrate 100-1, can overlap with the orthographic projection of the first power signal line V1 onto the substrate 100-1. The wiring space of the first peripheral area BB1 of the display panel 1000 can be fully utilized to achieve the design of a narrow bezel for the display panel 1000.

[0158] In some embodiments, such as Figure 8 , Figure 10 As shown, and refer to Figure 1 , Figure 6 The second multiplexing unit MUX2 may further include at least one third type transistor TFT3, which is located on the side of the plurality of second type transistors TFT2 away from the first multiplexing unit MUX1 in the second direction Y. The third type transistor TFT3 is configured to: not be connected to the data signal line Data; and a second multiplexing connection line L2 is also connected to a third number of third type transistors TFT3, the first number being equal to the sum of the second number and the third number.

[0159] For example, the sum of the number of second-type transistors TFT2 and the number of third-type transistors TFT3 in the second multiplexing unit MUX2 can be equal to the number of first-type transistors TFT1 in the first multiplexing unit MUX1. For example, as Figure 8 , Figure 10 As shown, when the second multiplexing unit MUX2 includes six second-type transistors TFT2, the second multiplexing unit MUX2 may also include three third-type transistors TFT3.

[0160] This disclosure does not specifically limit the number of second-type transistors TFT2 and third-type transistors TFT3 in the second multiplexing unit MUX2. The sum of the number of second-type transistors TFT2 and the number of third-type transistors TFT3 in the second multiplexing unit MUX2 is equal to the number of first-type transistors TFT1 in the first multiplexing unit MUX1.

[0161] For example, such as Figure 8 , Figure 10 As shown, all third-type transistors TFT3 can be located on the side of all second-type transistors TFT2 away from the first multiplexing unit MUX1 in the second direction Y. A second multiplexing connection line L2 can also be connected to a third number of third-type transistors TFT3, the first number being equal to the sum of the second and third numbers. That is, the number of second-type transistors TFT2 and third-type transistors TFT3 connected to a second multiplexing connection line L2 is the same as the number of first-type transistors TFT1 connected to a first multiplexing connection line L1.

[0162] A first multiplexed connection line L1 can be connected to three first-class transistors TFT1. In this case, for example, as... Figure 8 , Figure 10 As shown, a second multiplexed connection line L2 can be connected to two second-type transistors TFT2 and one third-type transistor TFT3. Alternatively, a second multiplexed connection line L2 can be connected to one second-type transistor TFT2 and two third-type transistors TFT3.

[0163] Since the third-type transistor TFT3 is not connected to the data signal line Data within the display area AA, therefore, Figure 8 , Figure 10 As shown, the second multiplexing connection line L2 in the second multiplexing unit MUX2 also needs to be connected to the compensation unit 500.

[0164] In some embodiments, such as Figure 11 As shown, and refer to Figure 2 , Figure 3The first power signal line V1 can extend along the second direction Y; the orthographic projection of the first power signal line V1 on the substrate 100-1 can be located on the side of the orthographic projection of the multiple multiplexing units MUX on the substrate 100-1 that is close to the display area AA.

[0165] For example, such as Figure 11 As shown, the first plate C-1 of a compensation capacitor C can be connected to a third-type transistor TFT3 via a first adapter line Z1. The first adapter line Z1 and the first plate C-1 of the compensation capacitor C can both be disposed on the first gate conductive layer 100-42, and the first adapter line Z1 and the first plate C-1 of the compensation capacitor C can be integrally disposed.

[0166] For example, such as Figure 11 As shown, and refer to Figure 3 , Figure 9A A first adapter line Z1 can be connected to an active pattern t1 used to form the first and second electrodes of a third-class transistor TFT3.

[0167] In some embodiments, such as Figure 8 , Figure 10 As shown, and refer to Figure 2 , Figure 3 The first power signal line V1 can extend along the second direction Y; the orthographic projection of the first power signal line V1 on the substrate 100-1 can be located on the side of the orthographic projection of the multiple multiplexing units MUX on the substrate 100-1 that is away from the display area AA.

[0168] For example, such as Figure 8 , Figure 9B , Figure 10 As shown, the first plate C-1 of a compensation capacitor C can be connected via a second adapter line Z2 and a corresponding second multiplex connection line L2. The second adapter line Z2 and the first plate C-1 of the compensation capacitor C can both be disposed on the first gate conductive layer 100-42, and the second adapter line Z2 and the first plate C-1 of the compensation capacitor C can be integrally disposed.

[0169] In some embodiments, such as Figure 7 As shown, and refer to Figure 2 , Figure 6 At least one compensation unit 500 is located on the side of the plurality of second-type transistors TFT2 away from the first multiplexing unit MUX1 in the second direction Y, and is also located on the side of at least one second multiplexing connection line L2 close to the display area AA; the first plate C-1 of a compensation capacitor C is connected to the corresponding second multiplexing connection line L2 via a third adapter line Z3.

[0170] For example, such as Figure 7 As shown, and refer to Figure 6 The second multiplexing unit MUX2 may include only a plurality of second-type transistors TFT2. It is understood that the number of the plurality of second-type transistors TFT2 in the second multiplexing unit MUX2 is less than the number of the plurality of first-type transistors TFT1 in the first multiplexing unit MUX1.

[0171] like Figure 7 As shown, and refer to Figure 2 , Figure 6 , Figure 8 All compensation units 500 can be located on the side of all second-type transistors TFT2 away from the first multiplexing unit MUX1 in the second direction Y, and can also be located on the side of all second multiplexing connection lines L2 close to the display area AA; that is, all compensation units 500 can be set at the original location of the third-type transistor TFT3, which can make full use of the wiring space of the first peripheral area BB1 in the display panel 1000, so that the compensation units 500 will not occupy additional wiring space in the first peripheral area BB1, which is conducive to realizing the narrow bezel design of the display panel 1000.

[0172] For example, such as Figure 7 As shown, the first plate C-1 of a compensation capacitor C can be connected to the corresponding second multiplexing connection line L2 via a third adapter line Z3. The third adapter line Z3 and the first plate C-1 of the compensation capacitor C can both be disposed on the first gate conductive layer 100-42, and the third adapter line Z3 and the first plate C-1 of the compensation capacitor C can be integrally disposed.

[0173] In some embodiments, such as Figure 12 , Figure 13 As shown, the second multiplexing unit MUX2 may also include at least one third multiplexing connection line L3, which connects the first number of second-type transistors TFT2 and the third multiplexing connection line L3.

[0174] For example, such as Figure 12 , Figure 13 As shown, and refer to Figure 6 The second multiplexing unit MUX2 may also include seven second-type transistors TFT2, two second multiplexing connection lines L2, and one third multiplexing connection line L3; wherein, one second multiplexing connection line L2 can be connected to two second-type transistors TFT2, and one third multiplexing connection line L3 can be connected to three second-type transistors TFT2; since the number of second-type transistors TFT2 connected on the third multiplexing connection line L3 is the same as the number of first-type transistors TFT1 connected on the first multiplexing connection line L1, no load compensation is required on the third multiplexing connection line L3, that is, the third multiplexing connection line L3 does not need to be connected to the compensation unit 500.

[0175] This disclosure does not specifically limit the number of second-type transistors TFT2, the number of second multiplexing connection lines L2, and the number of third multiplexing connection lines L3 in the second multiplexing unit MUX2.

[0176] In some embodiments, the second multiplexing unit MUX2 may include three second multiplexing connection lines L2; ​​one second multiplexing connection line L2 may be connected to one or two second-type transistors TFT2. The number of second-type transistors TFT2 connected to the three second multiplexing connection lines L2 may be the same or different.

[0177] In some embodiments, when the difference between the number of first-type transistors TFT1 connected to the first multiplexed connection line L1 and the number of second-type transistors TFT2 connected to the second multiplexed connection line L2 is greater than or equal to 2, for example, as... Figure 14 As shown, and refer to Figure 6 When the first multiplexed connection line L1 is connected to three first-type transistors TFT1 and the second multiplexed connection line L2 is connected to one second-type transistor TFT2, a compensation unit 500 may include a first compensation capacitor C1 and a second compensation capacitor C2. The first plate C-1 of the first compensation capacitor C1 and the first plate C-1 of the second compensation capacitor C2 in a compensation unit 500 may be connected to the same second multiplexed connection line L2. The second plate C-2 of the first compensation capacitor C1 and the second plate C-2 of the second compensation capacitor C2 may be connected to the first power signal line V1 for receiving DC signals.

[0178] In some embodiments, such as Figure 14 As shown, the second plate C-2 of the first compensation capacitor C1 and the second plate C-2 of the second compensation capacitor C2 can be integrally formed.

[0179] For example, such as Figure 14 As shown, and refer to Figure 9A , Figure 9B , Figure 9C The second plate C-2 of the compensation capacitor C may include a first sub-plate C-21, which may be disposed on the second gate conductive layer 100-41; the first sub-plate C-21 of the first compensation capacitor C1 and the first sub-plate C-21 of the second compensation capacitor C2 may be integrally disposed.

[0180] For example, such as Figure 14 As shown, and refer to Figure 9A , Figure 9B , Figure 9CThe second plate C-2 of the compensation capacitor C may include a second sub-plate C-22, which may be disposed on the third gate conductive layer 100-43; the second sub-plate C-22 of the first compensation capacitor C1 and the second sub-plate C-22 of the second compensation capacitor C2 may be integrally disposed.

[0181] For example, such as Figure 14 As shown, and refer to Figure 9A , Figure 9B , Figure 9C In the multiple compensation units 500, the first sub-board C-21 of multiple first compensation capacitors C1 and the first sub-board C-21 of multiple second compensation capacitors C2 can be integrally set; the second sub-board C-22 of multiple first compensation capacitors C1 and the second sub-board C-22 of multiple second compensation capacitors C2 can be integrally set.

[0182] For example, such as Figure 14 As shown, the multiple first compensation capacitors C1 and multiple second compensation capacitors C2 in the multiple compensation units 500 can be disposed on the side of all the second type transistors TFT2 away from the first multiplexing unit MUX1 in the second direction Y.

[0183] For example, the orthographic projections of the plurality of first compensation capacitors C1 and the plurality of second compensation capacitors C2 in the plurality of compensation units 500 on the substrate 100-1 may overlap with the orthographic projection of the first power signal line V1 on the substrate 100-1.

[0184] For example, such as Figure 15 As shown, and refer to Figure 3 , Figure 6 When the first multiplexing connection line L1 is connected to three first-type transistors TFT1 and the second multiplexing connection line L2 is connected to one second-type transistor TFT2, a compensation unit 500 may include a compensation capacitor C. The orthographic projection of the multiple compensation capacitors C in the multiple compensation units 500 on the substrate 100-1 may overlap with the orthographic projection of the first power signal line V1 on the substrate 100-1; the multiple compensation capacitors C in the multiple compensation units 500 may also be disposed on the side of all second-type transistors TFT2 away from the first multiplexing unit MUX1 in the second direction Y.

[0185] In some embodiments, such as Figure 16 As shown, and refer to Figure 1 The multiple data signal lines Data may include multiple first data signal lines Data1 and at least one second data signal line Data2. One first data signal line Data1 may be connected to a column of sub-pixels P in the display area AA; the second data signal line Data2 may be configured to be connected to a column of virtual sub-pixels in the display panel 1000.

[0186] It is understandable that virtual subpixels are subpixels in display panel 1000 that do not display images.

[0187] like Figure 16 As shown, the multiple second-type transistors TFT2 in the second multiplexing unit MUX2 may include at least one first transistor TFT2-1 and at least one second transistor TFT2-2. A first data signal line Data1 is connected to a first transistor TFT2-1, and a second data signal line Data2 is connected to a second transistor TFT2-2.

[0188] For example, such as Figure 16 As shown, multiple data signal lines Data may include one second data signal line Data2; the multiple second-type transistors TFT2 in the second multiplexing unit MUX2 may include six first transistors TFT2-1 and one second transistor TFT2-2, one first data signal line Data1 may be connected to one first transistor TFT2-1, and one second data signal line Data2 may be connected to one second transistor TFT2-2.

[0189] like Figure 16 As shown, the second multiplexing unit MUX2 may also include two third-type transistors TFT3, which are not connected to the data signal line Data.

[0190] In some embodiments, a display device is provided, which may include a display panel 1000 as described in any of the above embodiments and a driver chip IC, wherein the driver chip IC is connected to a first peripheral area BB1 of the display panel 1000.

[0191] For example, refer to Figure 1 , Figure 6 , Figure 7 In the display panel 1000, the first multiplexing connection line L1 of the first multiplexing unit MUX1 and the second multiplexing connection line L2 of the second multiplexing unit MUX2 are respectively connected to the driver chip IC through fan-out lines F.

[0192] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0193] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: The display panel includes a display area and a first peripheral area located on one side of the display area along a first direction, the first peripheral area being used for connection with a driver chip; the display panel includes a substrate, and a component disposed on the substrate: Multiple data signal lines are located in the display area and extend along the first direction; Multiple multiplexing units are located in the first peripheral area and arranged along a second direction, the second direction being perpendicular to the first direction; the multiple multiplexing units include multiple first multiplexing units and at least one second multiplexing unit located on at least one side of the multiple first multiplexing units along the second direction, the first multiplexing unit includes multiple first type transistors and at least one first multiplexing connection line, a data signal line is connected to a first type transistor, and a first number of first type transistors are connected to a first multiplexing connection line; The second multiplexing unit includes a plurality of second-type transistors and at least one second multiplexing connection line, a data signal line is connected to a second-type transistor, and a second number of second-type transistors are connected to a second multiplexing connection line; the second number is less than the first number; At least one compensation unit is located in the first peripheral area, and one compensation unit is connected to a second multiplexing connection line. The compensation unit is configured to make the load connected to the second multiplexing unit the same as the load connected to the first multiplexing unit.

2. The display panel according to claim 1, characterized in that, The compensation unit includes at least one compensation capacitor, which includes a first plate and a second plate. The first plate is connected to the second multiplexing connection line, and the second plate is used to receive DC signals.

3. The display panel according to claim 2, characterized in that, The display panel includes a first power signal line located in the first peripheral area, and the second plate of the compensation capacitor is connected to the first power signal line.

4. The display panel according to claim 3, characterized in that, The display panel includes: An active layer is disposed on one side of the substrate along its own thickness direction; the active layer includes a plurality of active patterns arranged along the second direction, the plurality of active patterns being used to form the first and second electrodes of each transistor in the plurality of multiplexing units; A first gate conductive layer is disposed on the side of the active layer away from the substrate; the first gate conductive layer includes the first electrode of the compensation capacitor; A source-drain conductive layer is disposed on the side of the first gate conductive layer away from the substrate; the source-drain conductive layer includes at least one second multiplexed connection line extending along the second direction, the second multiplexed connection line being connected to the active pattern of the corresponding second type of transistor and also connected to the first plate of the corresponding compensation capacitor.

5. The display panel according to claim 4, characterized in that, The first power signal line is located on the source / drain conductive layer; The display panel further includes a second gate conductive layer disposed between the active layer and the first gate conductive layer; the second electrode of the compensation capacitor includes a first sub-plate disposed in the second gate conductive layer; the orthographic projection of the first sub-plate on the substrate overlaps with the orthographic projection of the first electrode on the substrate; the first sub-plate is connected to the first power signal line; and / or... The display panel further includes a third gate conductive layer, which is disposed between the first gate conductive layer and the source / drain conductive layer; the second electrode of the compensation capacitor includes a second sub-plate, which is disposed in the third gate conductive layer; the orthographic projection of the second sub-plate on the substrate overlaps with the orthographic projection of the first electrode on the substrate; the second sub-plate is connected to the first power signal line.

6. The display panel according to claim 5, characterized in that, The second multiplexing unit includes multiple second multiplexing connection lines, and the display panel includes multiple compensation units; one second multiplexing connection line is connected to the first plate of at least one compensation capacitor in one of the compensation units; The second plate of the compensation capacitor includes a first sub-plate, and the first sub-plates of the multiple compensation capacitors of the multiple compensation units are integrally disposed. The second plate of the compensation capacitor includes a second sub-plate, and the second sub-plates of the multiple compensation capacitors of the multiple compensation units are integrally arranged.

7. The display panel according to claim 4, characterized in that, The first power signal line is disposed on the source and drain conductive layer; the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the first power signal line on the substrate; the portion of the first power signal line that overlaps with the first electrode plate forms the second electrode plate of the compensation capacitor.

8. The display panel according to any one of claims 3 to 7, characterized in that, The orthographic projection of the at least one compensation unit on the substrate overlaps with the orthographic projection of the first power signal line on the substrate.

9. The display panel according to claim 8, characterized in that, The second multiplexing unit further includes at least one third type transistor, which is located on the side of the plurality of second type transistors away from the first multiplexing unit, and the third type transistor is configured not to be connected to the data signal line; A second multiplexed connection line is also connected to a third number of the third type of transistors, the first number being equal to the sum of the second number and the third number.

10. The display panel according to claim 9, characterized in that, The orthogonal projection of the first power signal line on the substrate is located on the side of the orthogonal projection of the plurality of multiplexing units on the substrate that is closer to the display area; the first power signal line extends along the second direction; The first plate of one of the compensation capacitors is connected via a first adapter wire and a third type of transistor.

11. The display panel according to claim 8, characterized in that, The orthogonal projection of the first power signal line on the substrate is located on the side of the orthogonal projection of the plurality of multiplexing units on the substrate that is away from the display area; the first power signal line extends along the second direction; The first plate of one of the compensation capacitors is connected via a second adapter wire and a corresponding second multiplex connection wire.

12. The display panel according to any one of claims 2 to 6, characterized in that, The at least one compensation unit is located on the side of the plurality of second-type transistors away from the first multiplexing unit, and is also located on the side of the at least one second multiplexing connection line close to the display area; The first plate of one of the compensation capacitors is connected via a third adapter wire and a corresponding second multiplex connection wire.

13. The display panel according to any one of claims 1 to 7, characterized in that, The second multiplexing unit further includes at least one third multiplexing connection line, and the first number of second-type transistors are connected to one of the third multiplexing connection lines.

14. The display panel according to any one of claims 1 to 7, characterized in that, The difference between the number of first-type transistors connected to the first multiplexed connection line and the number of second-type transistors connected to the second multiplexed connection line is greater than or equal to 2. The compensation unit includes a first compensation capacitor and a second compensation capacitor, wherein the first plate of the first compensation capacitor and the first plate of the second compensation capacitor are connected to the same second multiplexing connection line. The second plate of the first compensation capacitor and the second compensation capacitor are used to receive DC signals.

15. The display panel according to claim 14, characterized in that, The second plate of the first compensation capacitor and the second compensation capacitor are integrally formed.

16. The display panel according to any one of claims 1 to 7, characterized in that, The first multiplexing unit includes nine transistors of the first type and three first multiplexing connection lines, with one first multiplexing connection line connected to three transistors of the first type; The first multiplexing unit further includes three control signal lines, and the gates of three first-type transistors connected to the same first multiplexing connection line are respectively connected to the three control signal lines; The three data signal lines connected to the three columns of sub-pixels of the same color are connected to the same first multiplexed connection line via three first-type transistors.

17. The display panel according to claim 16, characterized in that, The second multiplexing unit includes three second multiplexing connection lines; one second multiplexing connection line is connected to one or two second type transistors.

18. The display panel according to any one of claims 1 to 7, characterized in that, The plurality of data signal lines include a plurality of first data signal lines and at least one second data signal line, wherein the second data signal line is configured to be connected to a virtual sub-pixel in the display panel; The plurality of second-type transistors in the second multiplexing unit include at least one first transistor and at least one second transistor, a first data signal line is connected to the first transistor, and a second data signal line is connected to the second transistor.

19. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 18; A driver chip is connected to the first peripheral area of ​​the display panel.

20. The display device according to claim 19, characterized in that, The display panel includes a first multiplexing unit and a second multiplexing unit. The first multiplexing connection line in the first multiplexing unit and the second multiplexing connection line in the second multiplexing unit are respectively connected to the driver chip through fan-out lines.

Images