Method for forming epitaxial layer
By reducing the dry etching power and extending the etching time, surface damage to silicon wafers and residual silicon-fluorine bonds are reduced, solving the problem of doped region diffusion in MOS devices caused by high-temperature baking, and improving device reliability and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICONDUCTOR MANUFACTURING (WUXI) LTD
- Filing Date
- 2026-01-28
- Publication Date
- 2026-05-19
AI Technical Summary
In the existing technology, the method of forming the epitaxial layer can easily lead to contact between the doped regions of the MOS device, especially during high-temperature heat treatment, which can cause diffusion contact between the source and drain of the MOS device and result in loss of performance.
By reducing the dry etching power in the Siconi process to 10 to 20 watts and extending the etching time, damage to the silicon wafer surface and the amount of reactive gas dissociation are reduced. Subsequently, a baking process is performed at a lower temperature to remove silicon-fluorine bonds and form an epitaxial layer.
This effectively reduces the risk of diffusion contact in the doped region of MOS devices, improves device reliability and yield, and ensures the quality of the epitaxial layer.
Smart Images
Figure CN122069948A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for forming an epitaxial layer. Background Technology
[0002] The extrinsic base (ext-base) is the part of a heterojunction bipolar transistor (HBT) device that is in direct contact with the metal electrode. It can improve the high-frequency characteristics, power, and reliability of the device by reducing resistance, optimizing current distribution, and assisting carrier transport.
[0003] Before the epitaxial growth (EPI) process on the outer base region of HBT devices, the native oxide layer on the silicon wafer is removed by high-temperature baking to ensure film quality, or by in-situ drying chemical pre-cleaning (Siconi) process (the Siconi process chamber can be mounted as a pre-processing chamber on the EPI machine). Since the Siconi process increases silicon-fluorine (Si-F) bonds on the silicon wafer surface, affecting the quality of the epitaxial layer, high-temperature baking is usually required to reduce fluorine bonds. Therefore, the native oxide layer can be removed by baking alone or by a combination of Siconi process and baking; however, neither method can avoid the high-temperature heat treatment during baking.
[0004] High-temperature heat treatment has a significant impact on impurity diffusion in heavily doped regions and lightly doped drains (LDDs). This can easily lead to source and drain diffusion contacts in short-channel metal-oxide-semiconductor field-effect transistors (MOSFETs, referred to as "MOS" in this application) formed on the same silicon wafer during the high-temperature heat treatment of the epitaxial layer of HBT devices, resulting in performance loss. Summary of the Invention
[0005] This application provides a method for forming an epitaxial layer, which can solve the problem that epitaxial layer formation methods provided in related technologies easily lead to contact between doped regions of MOS devices. The method includes: The silicon wafer is transferred to the Siconi process chamber. The silicon wafer has a first region and a second region for forming semiconductor devices. The first region is used to form HBT devices, and the second region is used to form MOS devices. An oxide layer is formed on the surface of the first region. A pretreatment process is performed to remove the oxide layer using a dry etching process, with a power of 10 to 20 watts during the dry etching process. Heat treatment is performed to remove reaction byproducts generated during the dry etching process; The silicon wafer is transferred to the epitaxial process chamber; A baking process is performed to remove silicon-fluorine bonds on the surface of the silicon wafer at a temperature of 700 to 780 degrees Celsius. An epitaxial layer is formed on the surface of the first region using an epitaxial growth process.
[0006] In some embodiments, the dry etching process lasts for more than 13 seconds.
[0007] In some embodiments, the reaction gases introduced in the dry etching process include nitrogen trifluoride and ammonia.
[0008] In some embodiments, the temperature of the Siconi process chamber during heat treatment is between 150 and 220 degrees Celsius.
[0009] In some embodiments, the MOS device includes a gate, a gate dielectric layer formed between the gate and a silicon wafer, LDD regions formed in the silicon wafers on both sides of the gate, and heavily doped regions formed in the LDD regions.
[0010] In some embodiments, sidewalls are formed around the gate and gate dielectric layer.
[0011] The technical solution of this application has at least the following advantages: By reducing the power of dry etching in the Siconi process (as low as 10 to 20 watts), damage to the wafer surface and the amount of reactant gas dissociation per unit time can be reduced, thereby reducing the residual silicon-fluorine bonds on the wafer surface. This allows subsequent baking processes to be performed at lower temperatures (700 to 780 degrees Celsius), solving the problem that high baking temperatures cause the doped regions of MOS devices on the wafer to fail due to diffusion contact, thus improving the reliability and yield of device products. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0013] Figure 1 This is a flowchart of a method for forming an epitaxial layer provided in an exemplary embodiment of this application; Figure 2 This is a cross-sectional schematic diagram of the active region of a MOS device before the Siconi process, provided by an exemplary embodiment of this application, showing the method for forming an epitaxial layer. Figures 3 to 7 This is a schematic diagram of the formation process of an epitaxial layer formation method provided in an exemplary embodiment of this application; Figure 8 This is a schematic cross-sectional view of the active region of a MOS device after baking, provided by an exemplary embodiment of this application for forming an epitaxial layer. Detailed Implementation
[0014] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0015] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0016] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0017] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0018] refer to Figure 1 It illustrates a flowchart of a method for forming an epitaxial layer provided in an exemplary embodiment of this application, such as... Figure 1 As shown, the method includes: Step S1: The silicon wafer is transferred to the Siconi process chamber. The silicon wafer has a first region and a second region for forming semiconductor devices. The first region is used to form HBT devices, and the second region is used to form MOS devices. An oxide layer is formed on the surface of the first region.
[0019] refer to Figure 2 It shows a schematic cross-sectional view of the active region of a MOS device before the Siconi process; Reference Figure 3 This shows a schematic cross-sectional view of the first region before the Siconi process. For example, as shown... Figure 2 and Figure 3 As shown: The silicon wafer 210 includes a first region 21 and a second region 22 for forming semiconductor devices. The first region 21 is used to form an HBT device, and the second region 22 is used to form a MOS device. An oxide layer 300 (including a silicon dioxide (SiO2) layer) is formed on the surface of the first region 21, which is the native oxide layer of the silicon wafer 210. The MOS device includes a gate 230, a gate dielectric layer 220 formed between the gate 230 and the silicon wafer 210, LDD regions 201 formed on both sides of the gate 230 in the silicon wafer, and heavily doped regions 202 formed in the LDD regions 201. The impurity concentration in the heavily doped regions 202 is greater than that in the LDD regions 201. When the MOS device is operating, the heavily doped regions 202 can serve as the source and drain of the device. Before the Siconi process, the shortest spacing between the two LDD regions 201 is d1.
[0020] The Siconi process is completed sequentially through the pre-cleaning operation in step S2 and the anneling operation in step S3.
[0021] Step S2 involves a pretreatment process where the oxide layer is removed using a dry etching process with a power of 10 to 20 watts.
[0022] refer to Figure 4 It shows a cross-sectional schematic diagram of the first region after preprocessing. For example, as shown... Figure 4 As shown, the oxide layer 300 can be removed by a dry etching process. After the dry etching process, reaction byproducts 301 remain on the silicon wafer 210.
[0023] The reaction gases introduced in the dry etching process include nitrogen trifluoride (NF3) and ammonia (NH3), and the reaction equation is as follows: NF3+NH3+SiO2 →(NH4)2SiF6(g)+H2O (NH4)2SiF6 is the main component of the reaction byproducts. Since the power is reduced to 10 to 20 watts during the dry etching process, the duration of the dry etching process needs to be increased to ensure that the natural oxide layer is completely removed (the duration of the dry etching process can be greater than 13 seconds).
[0024] Step S3: Perform heat treatment to remove reaction byproducts generated during the dry etching process.
[0025] In related technologies, the dry etching process in the pretreatment operation is carried out at high power. The enhanced positive ion capacity in the Siconi process chamber promotes the full dissociation of nitrogen trifluoride and ammonia, producing more highly active fluorine groups and accelerating the reaction with silicon dioxide, thereby increasing the etching ratio (ER). However, high-energy ion bombardment of the silicon wafer surface increases the surface roughness, and the excess fluorine generated by the full dissociation of nitrogen trifluoride adsorbs onto the silicon wafer surface, forming silicon-fluorine bonds that are difficult to desorb.
[0026] In this embodiment, by appropriately reducing the power (as low as 10 watts to 20 watts), the physical bombardment effect on the silicon wafer surface can be reduced, thus reducing surface damage. By extending the etching time (greater than 13 seconds), the problem of reduced etching rate caused by reduced power can be compensated, ensuring the etching amount and guaranteeing that the natural oxide layer is completely removed. At the same time, the amount of nitrogen trifluoride and ammonia dissociated per unit time is reduced, allowing fluorine groups to react completely with silicon dioxide, avoiding the adsorption of excessive residual fluorine on the surface, thereby reducing the number of silicon-fluorine bonds, reducing the difficulty of subsequent removal of silicon-fluorine bonds, and enabling subsequent baking at a lower temperature to remove residual silicon-fluorine bonds.
[0027] refer to Figure 5 It shows a cross-sectional schematic diagram after heat treatment. For example, such as... Figure 5 As shown, after the heat treatment process, the reaction byproduct 301 is removed, and silicon-fluorine bonds remain on the surface of the silicon wafer 210. The temperature of the Siconi process chamber during the heat treatment process is between 150 degrees Celsius (°C) and 220 degrees Celsius.
[0028] Step S4: Transfer the silicon wafer to the epitaxial process chamber.
[0029] After the heat treatment, the Siconi process is completed, and the silicon wafer is transferred from the Siconi process chamber to the epitaxial process chamber for epitaxial growth.
[0030] Step S5 involves baking to remove silicon-fluorine bonds on the surface of the silicon wafer at a temperature of 700 to 780 degrees Celsius.
[0031] refer to Figure 6It shows a cross-sectional view after baking; Reference Figure 8 This illustrates a schematic cross-sectional view of the active region of a MOS device after baking. For example, such as... Figure 6 As shown, after baking, the silicon-fluorine bonds remaining on the surface of silicon wafer 210 are removed. Because the power of the dry etching process in the Siconi process is reduced, the number of residual silicon-fluorine bonds on silicon wafer 210 is also reduced. Complete removal of the residual silicon-fluorine bonds on the surface of silicon wafer 210 can be achieved by baking at a lower temperature (700°C to 780°C). Simultaneously, as... Figure 8 As shown, due to the low baking temperature, the doped regions of the MOS device formed on the silicon wafer 210 will not make contact due to diffusion at higher temperatures, and the closest distance d2 of its LDD region 201 can reach a safe distance.
[0032] Step S6: An epitaxial layer is formed on the surface of the first region using an epitaxial growth process.
[0033] refer to Figure 7 This shows a schematic cross-sectional view after the epitaxial layer has been formed. For example, as shown... Figure 7 As shown, an epitaxial layer 211 can be formed on the surface of the first region 21 by an epitaxial growth process.
[0034] In summary, in this embodiment of the application, by reducing the power of dry etching (as low as 10 watts to 20 watts) in the Siconi process, damage to the silicon wafer surface and the amount of reactant gas dissociation per unit time can be reduced, thereby reducing the residual silicon-fluorine bonds on the silicon wafer surface. This allows the subsequent baking process to be carried out at a lower temperature (700 degrees Celsius to 780 degrees Celsius), solving the problem that high baking temperatures cause the doped regions of MOS devices on the silicon wafer to fail due to diffusion contact, thus improving the reliability and yield of the device products.
[0035] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for forming an epitaxial layer, characterized in that, include: The silicon wafer is transferred to the Siconi process chamber. The silicon wafer has a first region and a second region for forming semiconductor devices. The first region is used to form HBT devices, and the second region is used to form MOS devices. An oxide layer is formed on the surface of the first region. A pretreatment process is performed to remove the oxide layer using a dry etching process, with a power of 10 to 20 watts during the dry etching process. Heat treatment is performed to remove reaction byproducts generated during the dry etching process; The silicon wafer is transferred to the epitaxial process chamber; A baking process is performed to remove silicon-fluorine bonds on the surface of the silicon wafer at a temperature of 700 to 780 degrees Celsius. An epitaxial layer is formed on the surface of the first region using an epitaxial growth process.
2. The method according to claim 1, characterized in that, The dry etching process lasts for more than 13 seconds.
3. The method according to claim 2, characterized in that, In the dry etching process, the reaction gases introduced include nitrogen trifluoride and ammonia.
4. The method according to claim 3, characterized in that, The temperature in the Siconi process chamber during heat treatment is between 150 and 220 degrees Celsius.
5. The method according to any one of claims 1 to 4, characterized in that, The MOS device includes a gate, a gate dielectric layer formed between the gate and a silicon wafer, LDD regions formed in the silicon wafers on both sides of the gate, and heavily doped regions formed in the LDD regions.
6. The method according to claim 5, characterized in that, Sidewalls are formed around the gate and gate dielectric layer.