Pulse neural network acceleration device based on hafnium-based ferroelectric memristor

Abstract

The invention provides a pulse neural network acceleration device based on a hafnium-based ferroelectric memristor. The structure of the device comprises a PC, a power supply circuit, an FPGA core board, a digital-to-analog conversion unit, a coding unit, a switch unit, a memristor array, a signal amplification circuit and an LIF neuron circuit. According to the hafnium-based ferroelectric memristor array, functions needing to be achieved are selected through specific software of the PC, read-write, weight modulation and image recognition of the hafnium-based ferroelectric memristor array can be achieved, image RGB values in the PC are converted into corresponding gray values to be sent to the FPGA core board, the FPGA core board controls and selects memristors needing to be modulated through the coding unit, the digital-to-analog conversion unit and the switch unit, and therefore the memristors needing to be modulated can be modulated. Read-write, weight modulation and image recognition functions of the ferroelectric memristor are realized, and results are output through the LIF neuron circuit.

Description

Technical Field

[0001] This invention relates to the field of neural network technology, specifically to a pulse neural network acceleration device based on hafnium-based ferroelectric memristors. Background Technology

[0002] With the rapid development of artificial intelligence and machine learning technologies, spiking neural networks (SNNs), as an emerging computational model, have attracted widespread attention due to their enormous potential in information processing and learning tasks. Unlike traditional artificial neural networks, SNNs transmit information by simulating the spiking mechanism of biological neurons, resulting in higher computational efficiency and lower energy consumption. This allows SNNs to demonstrate significant advantages in specific application scenarios, such as real-time data processing, pattern recognition, and intelligent control. In SNNs, information is not only transmitted in the form of pulses, but the temporal information of these pulses also carries important semantic information. This temporal characteristic enables SNNs to process dynamic input signals more flexibly, such as video and audio data. Therefore, when processing complex temporal tasks, SNNs can more effectively mimic the function of biological nervous systems, thus providing more expressive computational capabilities.

[0003] However, despite the numerous advantages of SNNs, their implementation still faces several challenges. Hardware implementation is a crucial aspect, especially since memristors, as emerging electronic devices, can effectively simulate the characteristics of neurons and achieve efficient parallel computing. However, research on control circuits for memristors, particularly ferroelectric memristors, remains relatively limited, becoming a bottleneck restricting the development of memristor SNNs. Ferroelectric memristors have attracted increasing attention in recent years due to their excellent electrical performance and non-volatility. They can not only be used to store information but also to perform computations and processing by changing their conductance. However, ferroelectric memristors have some problems in practical applications, such as their low current and complex operation, making them inconvenient to manipulate in high-performance computing environments. This limitation restricts the potential applications of SNNs, as in many cases, efficient and precise control circuits are needed to ensure that the performance of ferroelectric memristors is fully utilized.

[0004] To overcome these challenges, developing an efficient and convenient ferroelectric memristor control circuit is crucial. Such a control circuit not only optimizes memristor operation, making it easier to integrate into a sorted neural network (SNN), but also improves the overall performance of the SNN. By precisely controlling the state of the ferroelectric memristor, more complex pulse firing patterns can be achieved, thereby enhancing the network's learning ability and adaptability. Summary of the Invention

[0005] The purpose of this invention is to provide a pulse neural network acceleration device based on hafnium-based ferroelectric memristors, so as to efficiently and accurately control hafnium-based ferroelectric memristors to achieve read / write, weight modulation, and image recognition.

[0006] This invention is implemented as follows:

[0007] This invention provides a pulsed neural network acceleration device based on a hafnium oxide-doped lanthanum ferroelectric memristor. Essentially, this device is a circuit system comprising a PC, a power supply circuit, an FPGA core board, a digital-to-analog converter (DAC), an encoding unit, a switching unit, a memristor array, a signal amplification circuit, and a LIF neuron circuit. The invention allows for the selection of desired functions via specific software on the PC, enabling array read / write, weight modulation, and image recognition. The RGB values ​​of an image from the PC are converted to corresponding grayscale values ​​and sent to the FPGA core board. The FPGA core board, through the encoding unit, DAC, and switching unit, controls the selection of the memristor to be modulated, thus achieving ferroelectric memristor read / write, weight modulation, and image recognition functions. The results are then output via the LIF neuron circuit.

[0008] A pulse neural network acceleration device based on hafnium-based ferroelectric memristors includes a PC, a power supply circuit, an FPGA core board, an encoding unit, a digital-to-analog converter (DAC) unit, a switching unit, a memristor array, a signal amplification circuit, and a LIF neuron circuit. The FPGA core board is connected to the PC and also to the encoding unit. The encoding unit is connected to both the switching unit and the DAC unit. The encoding unit receives digital signals from the FPGA core board, sends them to the switching unit to control switch selection, and encodes the signals using voltage encoding before outputting them to the DAC unit. The DAC unit is connected to the switching unit, which includes six 8-to-1 switches. Three of these 8-to-1 switches are connected to the DAC unit and the memristor array, while the other three are connected to the memristor array and the signal amplification circuit. The digital-to-analog converter (DAC) receives the voltage-encoded signal output from the encoding unit and converts it into a corresponding pulse signal, which is then output to three 8-to-1 switch units. The outputs of these three 8-to-1 switch units are connected to the row lines of the memristor array, and the inputs of the other three 8-to-1 switch units are connected to the column lines of the memristor array. The outputs of the other three 8-to-1 switch units are connected to a signal amplification circuit, which in turn is connected to the LIF neuron circuit. The switch units select the row and column lines of the memristor array and input the pulse signal output from the DAC to the corresponding row and column device. The memristor array converts the received pulse signal into a corresponding current signal and outputs it to the switch units for selective output. The signal amplification circuit converts the current signal output from the memristor array into a corresponding voltage signal, amplifies the signal, and outputs it to the LIF neuron circuit. The final result is output and sent to the FPGA core board, which then transmits the result to the PC.

[0009] The power supply circuit includes an MC34063 chip, which provides 5V and 3.3V operating voltages to the devices in the device.

[0010] The FPGA core board is the EG4S20 chip core board from Anlu Technology.

[0011] The digital-to-analog converter circuit includes an LM324PWR chip.

[0012] The encoding unit includes a TXS0108E chip.

[0013] The memristor array is a 20×20 hafnium-based ferroelectric memristor array, specifically a hafnium oxide-doped lanthanum memristor.

[0014] The eight-to-one switch unit includes a CD4051 chip.

[0015] The signal amplification circuit includes an LM324PWR chip.

[0016] The LIF neuron circuit comprises ten LIF neuron units.

[0017] Each LIF neuron unit includes a LIF neuron signal amplification circuit and a LIF neuron signal output unit.

[0018] The LIF neuron signal amplification circuit includes an LM324 comparator chip, and the LIF neuron signal output unit includes an LM339 comparator chip.

[0019] This invention proposes a pulse neural network acceleration device based on hafnium-based ferroelectric memristors, focusing primarily on the design and implementation of the memristor control circuit. By optimizing the characteristics of the ferroelectric memristor, this control circuit can significantly improve the performance of the pulse neural network and promote its application in a wider range of fields. Combining the excellent characteristics of the memristor with the flexibility of the pulse neural network, this invention not only provides a theoretical basis for the further development of related technologies but also offers an effective solution to the technical bottlenecks encountered in practical applications.

[0020] Therefore, given the shortcomings of current memristor control circuits and the challenges of hardware implementation of spiking neural networks, this invention has significant theoretical and practical implications, and is expected to bring new breakthroughs to research and application in this field. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall circuit structure of the device in this invention.

[0022] Figure 2 This is a circuit diagram of the power switch in this invention.

[0023] Figure 3 This is a circuit diagram of the 5V to 3.3V voltage conversion in this invention.

[0024] Figure 4 This is a circuit diagram of the digital-to-analog converter unit in this invention.

[0025] Figure 5 This is a circuit structure diagram of the six encoding units in this invention.

[0026] Figure 6 This is a circuit diagram of the signal amplification circuit in this invention.

[0027] Figure 7 This is a circuit diagram of the six switching units in this invention.

[0028] Figure 8 This is a schematic diagram of the amplifier circuit structure of the first, second, third, and fourth LIF neuron units in this invention.

[0029] Figure 9 This is a schematic diagram of the amplifier circuit structure of the fifth, sixth, seventh, and eighth LIF neuron units in this invention.

[0030] Figure 10 This is a schematic diagram of the amplifier circuit structure of the ninth and tenth LIF neuron units in this invention.

[0031] Figure 11 This is a diagram showing the output circuit structure of the first, second, third, and fourth LIF neuron units in this invention.

[0032] Figure 12 This is a diagram showing the output circuit structure of the fifth, sixth, seventh, and eighth LIF neuron units in this invention.

[0033] Figure 13 This is a diagram showing the output circuit structure of the ninth and tenth LIF neuron units in this invention. Detailed Implementation

[0034] This invention provides a pulsed neural network acceleration device based on hafnium-based ferroelectric memristors, also known as a ferroelectric memristor array read / write circuit. The overall framework of this circuit is as follows: Figure 1 As shown, the circuit specifically includes a PC, a power supply circuit, an FPGA core board, a digital-to-analog converter unit, an encoding unit, a switching unit, a memristor array, a signal amplification circuit, and a LIF neuron circuit.

[0035] The FPGA core board is connected to the PC, the encoding unit, and the LIF neuron circuit. The FPGA core board is used to send read / write, weight modulation, or image recognition commands under the control of the PC. The encoding unit is connected to the FPGA core board, the switching unit, and the digital-to-analog converter. The encoding unit receives the instruction digital signals sent by the FPGA core board, sends them to the switching unit to control the switching selection, and then encodes the signals using voltage encoding before outputting them to the digital-to-analog converter. The analog-to-digital converter (ADC) unit is connected to a switching unit, which includes six 8-to-1 switches. The ADC unit receives the voltage-encoded signal output from the encoding unit and converts it into a corresponding pulse signal, outputting it to three of the 8-to-1 switches. The outputs of these three 8-to-1 switches are connected to the row lines of the memristor array, and the inputs of the other three 8-to-1 switches are connected to the column lines of the memristor array. The outputs of the other three 8-to-1 switches are connected to a signal amplification circuit, which is connected to the LIF neuron circuit. The switching unit selects the row and column lines of the memristor array and inputs the pulse signal output from the ADC unit to the corresponding row and column device. The memristor array converts the received pulse signal into a corresponding current signal and outputs it to the switching unit for selective output. The signal amplification circuit converts the current signal output from the memristor array into a corresponding voltage signal, amplifies the signal, and outputs it to the LIF neuron circuit. The LIF neuron circuit finally outputs the result and sends it to the FPGA core board.

[0036] The power supply circuit includes the power switch circuit ( Figure 2 ) and step-down circuit ( Figure 3 ).like Figure 2 As shown, the power switch circuit includes a power socket DC1, a six-pin self-locking switch SW1, a second resistor R2, and a red LED1 connected in sequence. Power socket DC1 provides a 5V voltage. After the power circuit is connected and the six-pin self-locking switch SW1 is pressed, the power indicator light (red LED1) illuminates.

[0037] like Figure 3As shown, the step-down circuit converts 5V to 3.3V. The circuit includes a voltage converter chip U1 (MC34063). The 5V input is connected to the DC terminal (pin 8) of the chip via a first resistor R1 (0Ω), which helps to eliminate power surges. The DC terminal (pin 8) of the chip U1 is connected to the IPK terminal (pin 7) and the SC terminal (pin 1). The VCC terminal of the chip U1 is connected to the 5V input. Simultaneously, the VCC terminal is grounded through three parallel capacitors: C1 (680μF), C2 (100nF), and C3 (22μF). C1 is a polarized capacitor, while C2 and C3 are non-polarized capacitors. C1 stores energy, while C2 and C3 filter the signal. The GDN terminal (pin 4) of voltage converter chip U1 is grounded, and the CT terminal (pin 3) of voltage converter chip U1 is grounded through the fifth capacitor C5 (240pF). The fifth capacitor C5 is used for oscillation. The SE terminal (pin 2) of voltage converter chip U1 is connected to the output terminal (i.e., 3.3V voltage) through the first inductor L1 (220μH), which serves as an energy storage unit. The end of the first inductor L1 connected to the SE terminal of voltage converter chip U1 is grounded through the first diode D1 (SS14). The first diode D1 is a Zener diode; its anode is grounded, and its cathode is connected to one end of the first inductor L1 (i.e., the SE terminal of voltage converter chip U1). The first diode D1 serves as a freewheeling unit. The end of the first inductor L1 connected to the output terminal (i.e., 3.3V voltage) is grounded through the fourth capacitor C4 (680μF). The fourth capacitor C4 also serves as an energy storage unit.

[0038] The FB terminal (pin 5) of the voltage conversion chip U1 branches into two paths, each connected to ground. One path has a fourth resistor R4 (1kΩ), while the other path first has a third resistor R3 (1.6kΩ), then connects to ground through two parallel capacitors: the sixth capacitor C6 (22μF) and the seventh capacitor C7 (100nF). The non-grounded terminal of the parallel capacitors C6 and C7 is connected to the 3.3V output voltage. The third resistor R3 and the fourth resistor R4 are used for voltage reduction. The sixth capacitor C6 and the seventh capacitor C7 are used for filtering.

[0039] Figure 3 The formula for the step-down circuit is Uo = 1.25V(1 + R3 / R4). With an input voltage of 5V, substituting the resistance values ​​yields an output voltage of 3.3V, which is used to power the downstream chips.

[0040] Figure 4The circuit diagram of the digital-to-analog converter (DAC) unit is shown. The DAC unit converts the received digital signal into a corresponding pulse signal and outputs it to the switching unit. The DAC unit includes an operational amplifier chip U3 (LM324PWR). The INA+ terminal (pin 3) of the operational amplifier chip U3 is connected to the seventh test pin H7. The seventh test pin H7 is connected to the PWM1 signal via the eighth resistor R8 (3kΩ). Simultaneously, the seventh test pin H7 is grounded via the twenty-third capacitor C23 (22μF). The eighth resistor R8 and the twenty-third capacitor C23 form an RC filter circuit. The INA- terminal (pin 2) and OUTA terminal (pin 1) of the operational amplifier chip U3 are connected to the eighth test pin H8. The IND- terminal (pin 13) and OUTD terminal (pin 14) of the operational amplifier chip U3 are connected to the ninth test pin H9. The OUTB terminal (pin 7) and IND+ terminal (pin 12) of the operational amplifier chip U3 are connected to the tenth test pin H10. The V+ terminal (pin 4) of operational amplifier chip U3 is connected to a +5V power supply through the third inductor L3 (10μH), and the V- terminal (pin 11) of operational amplifier chip U3 is connected to a -5V power supply through the fourth inductor L4 (10μH). The end of the third inductor L3 connected to the V+ terminal is grounded through two parallel capacitors (C19 and C21), and the end of the fourth inductor L4 connected to the V- terminal is grounded through two parallel capacitors (C20 and C22). The third inductor L3, together with C19 and C21, forms an LC filter circuit, and the fourth inductor L4, together with C20 and C22, forms an LC filter circuit. The INB+ terminal (pin 5) of operational amplifier chip U3 is grounded sequentially through the ninth resistor R9 (100kΩ) and the tenth resistor R10 (200kΩ). The connection between R9 and R10 is then connected to the eighth test pin H8. The INB- terminal (pin 6) of operational amplifier chip U3 has two connections. One connection is to the 10th test pin H10 via the 11th resistor R11 (200kΩ), and the other connection is to ground via the 12th resistor R12 (100kΩ) and the 25th capacitor C25 (22μF). The connection between R12 and C25 is grounded via the 15th resistor R15 (1kΩ) and connected to a 3.3V power supply via the 16th resistor R16 (1kΩ). The INC+ terminal (pin 10) of operational amplifier chip U3 is grounded via the 13th resistor R13 (1kΩ) and connected to a -5V power supply via the 14th resistor R14 (9kΩ). A 24th capacitor C24 (22μF) is connected in parallel across the 13th resistor R13. The INC- terminal (pin 9) and the OUTC terminal (pin 8) of operational amplifier chip U3 are connected together, forming the VREAD- terminal. The operational amplifier chip U3 has a 5V power supply input at pin 4 and a -5V power supply input at pin 11. The input signal is a PWM1 signal, which is filtered by R8 and C23 before being input to pin 3. The output pin is the PWM-DAC signal at pin 14.

[0041] Figure 5 This is a circuit diagram of the six encoding units in this invention. All six encoding units have the same structure, each containing a TXS0108E chip, a 1kΩ pull-down resistor, and two 100nF filter capacitors. One end of the pull-down resistor is connected to the OE terminal of the TXS0108E chip, and the other end is grounded. One of the two filter capacitors is connected between the VCCA terminal of the TXS0108E chip and ground, and the other is connected between the VCCB terminal of the TXS0108E chip and ground. The VCCA terminal is connected to a 3.3V power supply, and the VCCB terminal is connected to a 5V power supply. The eight input pins (A1-A8) of each TXS0108E chip come from the FPGA core board pins, and the eight output pins (B1-B8) are connected to the memristor circuit switching control circuit and the analog-to-digital converter circuit.

[0042] Figure 6This is a circuit diagram of the signal amplification circuit in this invention. The signal amplification circuit is used to amplify the received pulse signal, thereby modulating the device. The signal amplification circuit includes an operational amplifier chip U23 (LM324PWR), and the 1OUT terminal (pin 1) of the operational amplifier chip U23 is connected to the twentieth test pin H20. Pin 1 of the eighteenth test pin H18 is the OUTA terminal. Its pin 2 (VIN1) is connected to the 1IN- terminal (pin 2) of the operational amplifier chip U23 via the twenty-sixth resistor R26 (100Ω). Two diodes are connected in parallel between the 1IN- terminal (pin 2) and the 1IN+ terminal (pin 3) of the operational amplifier chip U23. These two diodes are the third diode D3 (1N4148W) and the fourth diode D4 (1N4148W). The positive terminal of D4 is connected to the 1IN- terminal (pin 2) of the operational amplifier chip U23, and the negative terminal is connected to the 1IN+ terminal (pin 3) of the operational amplifier chip U23. The positive terminal of D3 is connected to the 1IN+ terminal (pin 3) of the operational amplifier chip U23, and the negative terminal is connected to the 1IN- terminal (pin 2) of the operational amplifier chip U23. The 1IN+ terminal (pin 3) of the operational amplifier chip U23 is grounded. D3 and D4 serve as protection circuitry. The 1IN- (pin 2) and 1OUT (pin 1) terminals of the operational amplifier chip U23 are connected to the two ends of the sixty-fourth capacitor C64 (47pF), respectively. The twenty-fourth resistor R24 ​​(10kΩ) and the twenty-fifth resistor R25 (10kΩ) are connected in series and then in parallel across C64. The connection terminals of R24 and R25 are grounded through the twenty-third resistor R23 (1kΩ). R23, R24, R25, and C64 serve as filters. R26 serves as a first-stage amplifier. The VDD+ (pin 4) terminal of the operational amplifier chip U23 is connected to the +5V power supply through the sixth inductor L6 (10μH). At the same time, the VDD+ (pin 4) terminal of the operational amplifier chip U23 is also grounded through two parallel capacitors: the sixty-seventh capacitor C67 (100nF) and the sixty-eighth capacitor C68 (22μF). The 2IN+ terminal (pin 5) of the operational amplifier chip U23 is grounded via the thirty-first resistor R31 (1kΩ). A thirty-second resistor R30 (1kΩ) is connected between the 1OUT terminal (pin 1) and the 2IN- terminal (pin 6) of the operational amplifier chip U23. A thirty-second resistor R32 (100kΩ) is connected between the 2IN- terminal (pin 6) and the 2OUT terminal (pin 7) of the operational amplifier chip U23. A thirty-fourth resistor R34 is connected in parallel across R32. R34 is a variable resistor with a maximum resistance of 100kΩ. The 2OUT terminal (pin 7) of the operational amplifier chip U23 is also connected to the twenty-second test pin H22.

[0043] A 28th resistor, R28, is connected between the 4OUT terminal (pin 14) and the 4IN- terminal (pin 13) of the operational amplifier chip U23. R28 is a variable resistor with a maximum resistance of 100kΩ. The 19th test pin, H19, is connected to the 4OUT terminal (pin 14) of the operational amplifier chip U23. A 29th resistor, R29 (1kΩ), is connected between the 4IN- terminal (pin 13) and the 3OUT terminal (pin 8) of the operational amplifier chip U23. The 4IN+ terminal (pin 12) of the operational amplifier chip U23 is grounded through the 27th resistor, R27 (1kΩ). The VDD- terminal (pin 11) of the operational amplifier chip U23 is connected to a -5V power supply through the 5th inductor, L5 (10μH). The VDD- terminal (pin 11) of the operational amplifier chip U23 is also grounded through two parallel capacitors: the 65th capacitor, C65 (100nF), and the 66th capacitor, C66 (22μF). The operational amplifier chip U23 has a fifth diode D5 (1N4148W) and a sixth diode D6 (1N4148W) connected between its 3IN+ (pin 10) and 3IN- (pin 9) terminals. The positive terminal of D5 is connected to pin 10, and the negative terminal is connected to pin 9. The positive terminal of D6 is connected to pin 9, and the negative terminal is connected to pin 10. Pin 10 is grounded. The thirty-third resistor R33 (100kΩ) and the thirty-fifth resistor R35 (1kΩ) are connected in series, and then in parallel with the sixth diode D6. The connection terminals of R33 and R35 are connected to pin 2 (VIN2) of the twenty-first test pin H21, and pin 1 is the OUTA terminal. A sixty-ninth capacitor C69 (47pF) is connected between the 3OUT terminal (pin 8) and the 3IN- terminal (pin 9) of the operational amplifier chip U23. A thirty-sixth resistor R36 (10K) is connected in parallel across the two ends of C69. The 3OUT terminal (pin 8) of the operational amplifier chip U23 is also connected to the twenty-third test pin H23.

[0044] The VDD+ terminal (pin 4) of the operational amplifier chip U23 is connected to the +5V input power supply, and its VDD- terminal (pin 11) is connected to the -5V input power supply. The input signal is input from OUTA, protected by diodes D3 and D4, and then input to pin 3 of the LM324PWR chip. The output pin is pin 14, VOUTB signal.

[0045] Figure 7This is a circuit diagram of six switching units. All six switching units have identical structures. The switching units are used to select rows and columns of a memristor array (20*20 memristors, specifically hafnium oxide-doped lanthanum memristors). Each switching unit is an 8-to-1 switching unit using the CD4051 chip. Each chip's power supply terminal is filtered by a 100nF capacitor. U15, U19, and U21 are for row line control. The input signal INA is taken from pin 3 of the CD4051 chip, and the row line outputs RO1 to RO20 are controlled via CTRL1, CTRL2, CTRL3, CTRL4, CTRL5, CTRL6, CTRL7, CTRL8, and CTRL9. U14, U15, and U22 are column line controls. They control the column line outputs CO1 to CO20 via CTRL10, CTRL12, CTRL13, CTRL14, CTRL15, CTRL16, CTRL17, and CTRL8, and output signal OUTA from pin 3 of their respective CD4051 chips.

[0046] LIF neuron circuits are used to generate output signals at the back end of memristor neural network layers. The LIF neuron circuit consists of ten LIF neuron units, the circuit structure of which is as follows: Figure 8-13 As shown, where Figure 8-10 This is an amplification circuit for the signal of each neuron. Figure 11-13 This is the output circuit for LIF neurons. Neuron signals exceeding the threshold voltage output a high level. Figure 8 and Figure 9 The image shows four LIF neuron signal amplification units. Figure 10 Two LIF neuron signal amplification units are shown, each with the same circuit structure. Each LIF neuron signal amplification unit includes an LM324 operational amplifier chip. Figures 8-10 U25, U26, and U27 are all LM324 comparator chips. The input to the LIF neuron signal amplification unit is the LF signal output from the memristor array, which is connected to pin 3 of the LM324 operational amplifier through a 1K ohm resistor, and the output is the LFO signal. Figure 8As shown, the VDD+ terminal (pin 4) of U25 is connected to a +5V power supply through the seventh inductor L7 (10μH), and its VDD- terminal (pin 11) is grounded. Two capacitors, C70 (22μF) and C72 (100nF), are connected in parallel between pins 4 and 11. Resistors R47 (100kΩ), R48, and capacitor C74 (47pF) are connected between the 1OUT terminal (pin 1) and the 1IN- terminal (pin 2) of U25. R47, R48, and C74 are connected in parallel, and R48 is a variable resistor with a maximum resistance of 100kΩ. The output terminal LF1 of the memristor array is connected to the 1IN+ terminal (pin 3) of U25 through resistor R61 (1kΩ). Simultaneously, the output terminal LF1 of the memristor array is also grounded through resistor R63 (100kΩ). The circuits connected to pins 1OUT (1), 1IN- (2), and 1IN+ (3) of the U25 form a LIF neuron signal amplification unit. Pin 1OUT is the output, and the maximum overall amplification factor is 100x (R48 / R61). The structures of the other nine LIF neuron signal amplification units are the same and will not be described in detail here. For more information, please refer to [link to relevant documentation]. Figures 8-10 The circuit structure diagram. Figure 11 and Figure 12 The image shows the signal output units of four LIF neurons. Figure 13 Two LIF neuron signal output units are shown, each with the same circuit structure. The LIF neuron output unit includes an LM339 comparator chip. Figures 11-13 U30, U31, and U32 are all LM339 comparator chips. The input to the LIF neuron output unit is the output signal LFO1~LFO10 of the LIF neuron amplification unit. Figure 8-10 For example, in the first LIF neuron output circuit, the input LFO1 signal is input from pin 3 of the U30 chip, pin 2 VREF is an externally adjustable threshold voltage, typically 1.65V, and the output is the LFOUT signal from pin 1. When the LFO1 signal voltage is greater than the VREF signal, the output LFOUT is high, and vice versa. Pin 4 of the U30 chip is connected to the 3.3V power supply port through an L17 inductor (10μH), and pin 11 is connected to GND. Two capacitors, C112 (22μF) and C108 (100nF), are used as energy storage and filtering capacitors at the power supply end. The structure of the other nine LIF neuron signal output units is the same, and will not be described in detail here. For more information, please refer to [link to relevant documentation]. Figures 11-13 The circuit structure diagram.

[0047] In the software design of this invention, Python 3.10 is used on a WIN10 system host to control the board for reading, writing, and identification operations via serial communication, and the results are saved to a TXT document.

[0048] The device testing procedure of this invention is as follows:

[0049] a. First, the host computer (PC) sends instructions to the FPGA core board to determine the status of the ferroelectric memristor devices through read / write pulses. This process can check whether the ferroelectric memristor has been written to, whether it is currently damaged, and whether each device is in a low-resistance or high-resistance state, etc.

[0050] b. Then the host computer of the device sends a command to update the weights of the memristor, and writes the weights trained on the computer as the conductance value of the memristor.

[0051] c. The host computer of the device encodes the neural network recognition task into pulse form to perform recognition operations on the device.

[0052] d. Finally, the host computer of the device saves the collected data to a TXT text file on the computer for further processing.

Claims

1. A pulsed neural network acceleration device based on hafnium-based ferroelectric memristors, characterized in that, It includes a PC, FPGA core board, encoding unit, digital-to-analog converter unit, switching unit, memristor array, signal amplification circuit, and LIF neuron circuit; The FPGA core board is connected to the PC, the encoding unit, and the LIF neuron circuit, respectively; the FPGA core board is used to send read / write, weight modulation, or image recognition commands under the control of the PC. The encoding unit is connected to the FPGA core board, the switching unit and the digital-to-analog converter respectively. The encoding unit is used to receive the instruction digital signal sent by the FPGA core board, send it to the switching unit to control the selection of the switch, and output the signal to the digital-to-analog converter after voltage encoding. The digital-to-analog converter (DAC) is connected to a switching unit, which includes six 8-to-1 switching units. The DAC receives the voltage encoding signal output by the encoding unit and converts it into a corresponding pulse signal, outputting it to three 8-to-1 switching units. The output terminals of these three 8-to-1 switching units are connected to the row lines of the memristor array, and the input terminals of the other three 8-to-1 switching units are connected to the column lines of the memristor array. The output terminals of the other three 8-to-1 switching units are connected to a signal amplification circuit, which is connected to a LIF neuron circuit. The switching unit is used to select the row and column lines of the memristor array and input the pulse signal output by the DAC to the corresponding row and column devices. The memristor array converts the received pulse signal into a corresponding current signal and outputs it to the switching unit for selective output. The signal amplification circuit converts the current signal output by the memristor array into a corresponding voltage signal, amplifies the signal, and outputs it to the LIF neuron circuit. The LIF neuron circuit ultimately outputs the results and sends them to the FPGA core board.

2. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 1, characterized in that, It also includes a power supply circuit, which includes an MC34063 chip to provide 5V and 3.3V operating voltages to the devices in the device.

3. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 1, characterized in that, The memristor array is a 20×20 hafnium-based ferroelectric memristor array, specifically a hafnium oxide-doped lanthanum memristor.

4. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 1, characterized in that, The digital-to-analog converter circuit includes an LM324PWR chip.

5. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 1, characterized in that, The encoding unit includes a TXS0108E chip.

6. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 1, characterized in that, The eight-to-one switch unit includes a CD4051 chip.

7. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 1, characterized in that, The signal amplification circuit includes an LM324PWR chip.

8. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 1, characterized in that, The LIF neuron circuit comprises ten LIF neuron units.

9. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 8, characterized in that, Each LIF neuron unit includes a LIF neuron signal amplification circuit and a LIF neuron signal output unit.

10. The pulse neural network acceleration device based on hafnium-based ferroelectric memristors according to claim 9, characterized in that, The LIF neuron signal amplification circuit includes an LM324 comparator chip, and the LIF neuron signal output unit includes an LM339 comparator chip.

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