Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method of manufacturing a semiconductor device includes providing a region of semiconductor material including a top side, an edge region, a multi-shield conductor contact region within the edge region, an active region, and an upper shield contact region. The method includes providing an active trench. The active trench includes a lower shield conductor, a first shield dielectric isolating the lower shield conductor from the region of semiconductor material, an upper shield conductor, and a second shield dielectric isolating the lower shield conductor from the upper shield conductor within the active region. The lower shield conductor and the upper shield conductor are coupled together in the multi-shield conductor contact region. The method includes disposing a shield contact in the upper shield contact region coupled to the upper shield conductor in the active trench.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to semiconductor device structures and methods of forming semiconductor devices. Background Technology

[0002] Insulated-gate field-effect transistors (IGFETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are used in many power switching applications, such as DC-DC converters. In a typical MOSFET, the gate electrode provides turn-on and turn-off control by applying an appropriate gate voltage. For example, in an N-type enhancement-mode MOSFET, turn-on occurs when a conductive N-type inversion layer (i.e., the channel region) is formed in the P-type body region in response to the application of a positive gate voltage exceeding its intrinsic threshold voltage. The inversion layer connects the N-type source region to the N-type drain region and allows majority carrier conduction between these regions.

[0003] There exists a class of MOSFET devices in which the gate electrode is formed in a trench extending downward from the main surface of a semiconductor material such as silicon. In these trench-gate MOSFET devices, current flows primarily vertically through the device, and therefore the device cells can be packed more tightly. All other things being equal, a more tightly packed device cell can increase current carrying capacity and reduce the device's on-resistance.

[0004] Variations of trench-gate MOSFETs include shielded-gate MOSFETs, which place a shield electrode within the trench below and electrically isolated from the gate electrode. In some examples, the shield electrode may be connected to the source potential. The shield electrode's electrical isolation from the drift region through a thicker dielectric than the gate dielectric provides a charge-balancing effect to the drift region. This allows for higher doping within the drift region, resulting in reduced on-resistance. Additionally, the shield electrode isolates the gate electrode from the drift region, reducing the gate-drain capacitance C. gd It also improved switching performance.

[0005] In some applications, multiple shielding electrodes have been used for vertical charge control purposes to improve forward voltage loss and higher blocking capability. However, manufacturing challenges have made it difficult to realize semiconductor devices with multiple shielding electrodes, such as MOSFET devices.

[0006] Therefore, there is a need for methods and structures for manufacturing semiconductor devices comprising multiple shielding electrodes. Additionally, there is a need for methods and structures for providing electrical contacts to the multiple shielding electrodes, which are dielectrically separated. Summary of the Invention

[0007] According to a first aspect, a method for manufacturing a semiconductor device is provided, the method comprising: setting a semiconductor material region, the semiconductor material region including: a top side, an edge region, a multi-shielded conductor contact region within the edge region, an active region, and an upper shielding contact region; setting an active trench extending from the top side into the semiconductor material region, wherein the active trench includes: a lower shielding conductor, a first shielding dielectric, an upper shielding conductor, and a second shielding dielectric, the first shielding dielectric isolating the lower shielding conductor from the semiconductor material region, and the second shielding dielectric isolating the lower shielding conductor from the upper shielding conductor within the active region; the active trench extending laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region; the lower shielding conductor and the upper shielding conductor being coupled together in the multi-shielded conductor contact region; and setting a shielding contact in the upper shielding contact region coupled to the upper shielding conductor in the active trench.

[0008] According to a second aspect, a method for manufacturing a semiconductor device is provided, the method comprising: setting a semiconductor material region, the semiconductor material region including: a top side, an edge region adjacent to the top side, a multi-shielded conductor contact region, an active region adjacent to the top side, and an upper shielded contact region, the upper shielded contact region being adjacent to the top side and outside the multi-shielded conductor contact region; setting an active trench extending from the top side to the semiconductor material region, wherein: the active trench includes: a lower shielded conductor, a first shielded dielectric, an upper shielded conductor, and a second shielded dielectric, the first shielded dielectric isolating the lower shielded conductor from the semiconductor material region, and the second shielded dielectric isolating the lower shielded conductor from the upper shielded conductor within the active region; the active trench extending laterally from the active region to the multi-shielded conductor within the semiconductor material region. In the contact area; and the lower shielding conductor and the upper shielding conductor are coupled together in the multi-shielded conductor contact area; a terminating trench is provided extending from the top side into a second portion of the semiconductor material region, wherein: the terminating trench includes: the lower shielding conductor, the first shielding dielectric, the upper shielding conductor and the second shielding dielectric, the first shielding dielectric isolating the lower shielding conductor from the semiconductor material region, and the second shielding dielectric isolating the lower shielding conductor from the upper shielding conductor in the active region; the terminating trench extends laterally from the active region into the multi-shielded conductor contact area in the semiconductor material region; and the lower shielding conductor and the upper shielding conductor are coupled together in the multi-shielded conductor contact area; and a shielding contact element coupled to the upper shielding conductor in the active trench is provided in the upper shielding contact area.

[0009] According to a third aspect, a semiconductor device is provided, the semiconductor device comprising: a semiconductor material region, an active trench, and a shielding contact, wherein the semiconductor material region includes: a top side, an edge region, a multi-shielded conductor contact region, an active region, and an upper shielding contact region outside the multi-shielded conductor contact region; the active trench extends from the top side into the semiconductor material region, wherein the active trench includes: a lower shielding conductor, a first shielding dielectric, an upper shielding conductor, and a second shielding dielectric; the first shielding dielectric isolates the lower shielding conductor from the semiconductor material region; the second shielding dielectric isolates the lower shielding conductor from the upper shielding conductor within the active region; the active trench extends laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region; and the lower shielding conductor and the upper shielding conductor are coupled together in the multi-shielded conductor contact region; and the shielding contact is located in the upper shielding contact region and coupled to the upper shielding conductor in the active trench. Attached Figure Description

[0010] Figure 1 A partial top plan view of an example cell topography of a semiconductor device according to this specification is shown;

[0011] Figure 2 The image shown is taken along reference line 2A-2A. Figure 1 A partial cross-sectional view of a portion of a semiconductor device with an example cell morphology;

[0012] Figure 3 The image shown is taken along reference line 3A-3A. Figure 1 A partial cross-sectional view of a portion of a semiconductor device with an example cell morphology;

[0013] Figure 4 The image shown is taken along reference line 4A-4A. Figure 1 A partial cross-sectional view of a portion of a semiconductor device with an example cell morphology;

[0014] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 Partial cross-sectional views of semiconductor devices at various manufacturing stages are shown according to this specification;

[0015] Figure 21 The image shown is taken along reference line 21A”-21A”. Figure 1 A partial cross-sectional view of a portion of a semiconductor device with an example cell morphology;

[0016] Figure 22 A partial cross-sectional view of a portion of a semiconductor device according to this specification is shown; and

[0017] Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 and Figure 28 This specification illustrates the process of manufacturing a semiconductor device at various stages according to this specification. Figure 1 A partial cross-sectional view taken from reference line 23A-23A. Detailed Implementation

[0018] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0019] To keep the illustrations simple and clear, the components in the figures may not be drawn to scale, and the same reference numerals in different figures indicate the same components. Additionally, for the sake of brevity, descriptions and details of well-known steps and components have been omitted.

[0020] For clarity of the accompanying drawings, certain regions of the device structure, such as doped or dielectric regions, trenches, or contacts, may be illustrated as having generally straight edges and corners with precise angles. However, those skilled in the art will understand that the edges of such regions may not typically be straight and the corners may not have precise angles due to the diffusion and activation of dopants or the formation of layers.

[0021] Although semiconductor devices are interpreted herein as having certain N-type conductive regions and certain P-type conductive regions, those skilled in the art will understand that the conductivity type can be reversed, and that, in accordance with this specification, any necessary reversal of voltage polarity, transistor type, and / or current direction can also be taken into account.

[0022] Furthermore, the terminology used herein is for the purpose of describing particular examples only and is not intended to limit this disclosure. As used herein, the singular form is intended to also include the plural form unless otherwise expressly indicated in the context.

[0023] As used herein, “current-carrying electrode” refers to a component within a device that carries current through the device, such as the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, and “control electrode” refers to a component within a device that controls the current flowing through the device, such as the gate of a MOS transistor or the base of a bipolar transistor.

[0024] Additionally, when used in conjunction with a semiconductor region, wafer, or substrate, the term "master surface" refers to the surface of a semiconductor region, wafer, or substrate that forms an interface with another material such as a dielectric, insulator, conductor, or polycrystalline semiconductor. The master surface can have a morphology that varies along the x, y, and z directions.

[0025] Furthermore, the structure of the present invention can be embodied in a cellular base design (where the main area consists of multiple different and separate cellular or strip-shaped areas) or a single base design (where the main area is a single area formed by an elongated pattern, generally in the form of a serpentine pattern or a central portion with connecting appendages). However, for ease of understanding, one embodiment of this specification will be described throughout as a cellular base design. It should be understood that this specification covers both cellular base designs and single base designs.

[0026] When used in this specification, the terms “comprising,” “including,” “having,” and / or “containing” are open-ended terms that specify the presence of the stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0027] The term "or" refers to any one or more items in a list connected by "or". For example, "x or y" refers to any element in the three-element group {(x),(y),(x,y)}. Similarly, "x, y or z" refers to any element in the seven-element group {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}.

[0028] When used in this specification, the term "step" means one or more unit processes for manufacturing a semiconductor device, and may include multiple or a series of unit processes within a process step (such as an etching step, a photoresist masking step, a deposition step, or a doping step). Such unit processes may include, but are not limited to, cleaning processes, drying processes, exposure processes, development processes, stripping processes, and those unit processes commonly used in process steps.

[0029] Although the terms “first,” “second,” etc., may be used herein to describe various components, elements, regions, layers, and / or segments, these components, elements, regions, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one component, element, region, layer, and / or segment from another component, element, region, layer, and / or segment. Therefore, without departing from the teachings of this invention, for example, the first component, first element, first region, first layer, and / or first segment discussed below may be referred to as a second component, second element, second region, second layer, and / or second segment.

[0030] Those skilled in the art will understand that the phrases “during,” “at the same time,” and “when” used herein in relation to circuit operation do not precisely refer to an action occurring immediately after the initiation of the action, but rather to a possible small but reasonable delay, such as a propagation delay, between the responses triggered by the initial action. Additionally, the term “at the same time” means that an action occurs at least for a period of time during the duration of the initiation of the action.

[0031] The terms “about,” “approximately,” or “basically” are used to indicate that the value of a component is expected to be close to the declared value or position. However, it is well known in the art that there are always some small deviations that prevent the value or position from being exactly the declared value or position.

[0032] Unless otherwise specified, the phrases “above” or “on” as used herein include the orientation, placement, or relationship in which the specified element may be in direct or indirect physical contact.

[0033] Unless otherwise specified, as used herein, the phrase “overlapping with” includes the orientation, placement, or relationship in which the specified elements can at least partially or completely coincide or align on the same or different planes.

[0034] It should also be understood that the examples exemplified and described below may have examples lacking any elements not expressly disclosed herein, and / or may be implemented in the absence of any elements not expressly disclosed herein.

[0035] Generally, examples of this invention relate to semiconductor device structures and methods of manufacturing semiconductor devices, including trench-gate MOSFET devices with multiple shielding electrodes, offering improved manufacturability and performance. In some examples, structures including cell morphology configurations are described that facilitate electrical connections between the multiple shielding electrodes. Such structures may be disposed, for example, at the tip portion of an active trench. In some examples, such structures may be disposed at the end portion of the tip portion of a terminating active trench. In some examples, methods are described that improve the manufacturability of the electrical connection structures between the multiple shielding electrodes and the electrical connections to the terminating trench, thereby improving the overall reliability of the semiconductor device. Such methods include using a negative photoresist when preparing to remove portions of the shielding dielectric and using a multi-step removal process when setting the shielding conductors. Furthermore, the methods and structures simplify the interconnect scheme between the shielding conductors, thereby saving layout space, simplifying the cell morphology, and reducing the impact on die size. Based on the following description, other advantages and beneficial effects will be apparent to those skilled in the art.

[0036] In one example, a method of manufacturing a semiconductor device includes forming a semiconductor material region including a top side, an edge region, a multi-shielded conductor contact region within the edge region, an active region, and an upper shielding contact region. The method includes forming an active trench extending from the top side into the semiconductor material region. The active trench includes a lower shielding conductor, a first shielding dielectric isolating the lower shielding conductor from the semiconductor material region, an upper shielding conductor, and a second shielding dielectric isolating the lower shielding conductor from the upper shielding conductor within the active region. The active trench extends laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region, and the lower and upper shielding conductors are coupled together in the multi-shielded conductor contact region. The method includes forming shielding contacts in the upper shielding contact region that are coupled to the upper shielding conductor in the active trench.

[0037] In one example, a method of manufacturing a semiconductor device includes forming a semiconductor material region including a top side, an edge region adjacent to the top side, a multi-shielded conductor contact region, an active region adjacent to the top side, and an upper shielded contact region adjacent to the top side and outside the multi-shielded conductor contact region. The method includes forming an active trench extending from the top side into the semiconductor material region. The active trench includes a lower shielded conductor, a first shielding dielectric isolating the lower shielded conductor from the semiconductor material region, an upper shielded conductor, and a second shielding dielectric isolating the lower shielded conductor from the upper shielded conductor within the active region. The active trench extends laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region, and the lower shielded conductor and the upper shielded conductor are coupled together in the multi-shielded conductor contact region. The method includes forming a terminating trench in a second portion extending from the top side into the semiconductor material region. The terminating trench includes a lower shielded conductor, a first shielding dielectric isolating the lower shielded conductor from the semiconductor material region, an upper shielded conductor, and a second shielding dielectric isolating the lower shielded conductor from the upper shielded conductor within the active region. The termination trench extends laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region, and the lower and upper shielded conductors are coupled together in the multi-shielded conductor contact region. The method includes providing shielding contacts in the upper shielding contact region that are coupled to the upper shielded conductor in the active trench.

[0038] In one example, the semiconductor device includes a semiconductor material region comprising a top side, an edge region, a multi-shielded conductor contact region, an active region, and an upper shielding contact region outside the multi-shielded conductor contact region. An active trench extends from the top side into the semiconductor material region and includes a lower shielding conductor, a first shielding dielectric isolating the lower shielding conductor from the semiconductor material region, an upper shielding conductor, and a second shielding dielectric isolating the lower shielding conductor from the upper shielding conductor within the active region. The active trench extends laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region, and the lower and upper shielding conductors are coupled together in the multi-shielded conductor contact region. Shielding contacts in the upper shielding contact region are coupled to the upper shielding conductor in the active trench.

[0039] Other examples are included in this disclosure. Such examples can be seen in the drawings, the claims, and / or the description of this disclosure.

[0040] Figure 1 A partial top plan view of a cell topography 100 of an exemplary semiconductor device 10 according to this specification is shown. Figure 2 It shows along Figure 1 A partial cross-sectional view of a portion of the semiconductor device 10 taken along reference line 2A-2A; Figure 3 It shows along Figure 1A partial cross-sectional view of another portion of the semiconductor device 10, taken along reference line 3A-3A; and Figure 4 It shows along Figure 1 A partial cross-sectional view of another portion of the semiconductor device 10, taken along reference line 4A-4A. References are made in the following sections of this specification. Figures 1 to 4 .

[0041] Semiconductor device 10 is an example of a trench gate MOSFET including a multi-shielded electrode configuration. In this example, semiconductor device 10 includes a dual-shielded electrode configuration, wherein the shielding electrodes are separated by a shielding dielectric in one or more first portions of cell topology 100 and coupled together in one or more second portions of cell topology 100. It should be understood that this specification is not limited to MOSFET devices and is useful for other devices such as insulated-gate bipolar transistor (IIGBT) devices, thyristor devices, or devices utilizing shielding electrodes. Furthermore, although this example uses a dual-shielded electrode configuration, it should be understood that this specification relates to configurations using more than two shielding conductors.

[0042] The cell topology 100 may also include, or be referred to as, a device layout or cell layout, and the semiconductor device 10 may also be referred to as a semiconductor component, electronic device structure, or electronic component. (Reference) Figure 2 The semiconductor device 10 includes a semiconductor material region 11, which includes a top side 18 and a bottom side 19 opposite to the top side 18. In this example, the cell topography 100 of the semiconductor device 10 includes a device layout or configuration adjacent to and extending across the top side 18.

[0043] In some examples, the cell morphology includes an edge region 101 adjacent to a portion of the top side 18, a double-shielded conductor contact region 102 within the edge region 101, an active region 103 adjacent to another portion of the top side 18, an upper shielded contact region 104 adjacent to yet another portion of the top side 18, and a region 106 in which the lower shielded conductor 21A is electrically isolated from the upper shielded conductor 21B by a shielding dielectric 240. Region 106 may also include, or be referred to as, a double-shielded isolation region, wherein the shielding dielectric 240 (see (e.g.)) Figures 2 to 4 The lower shielding conductor 21A is isolated or separated from the upper shielding conductor 21B. In this example, the active region 103 and the upper shielding contact region 104 are within region 106. In addition, the upper shielding contact region 104 is outside the double shielding conductor contact region 102 or laterally spaced from it.

[0044] In some examples, edge region 101 may correspond to a portion of cell topology 100 in which active trenches 22A each terminate with a tip region 220 and a terminating trench 22B wraps around the tip region 220 of the active trench 22A and feeds into an additional active trench 22A that extends in the opposite direction and terminates with a tip region 220 at an opposite edge region of cell topology 100. In some examples, edge region 101 includes a gate contact 280 coupled to gate electrode 28 and conductor 44B (see, for example). Figure 2 ).

[0045] In some examples, cell topology 100 is suitable for medium-voltage semiconductor devices 10, such as 30-volt to 100-volt shielded gate trench MOSFET devices. However, the structures and methods described herein are also relevant to higher voltage devices. Figure 1 In the top plan view, the source conductor 44A and gate conductor 44B of the semiconductor device 10 are shown with dashed lines to better illustrate the structure below, but... Figure 2 , Figure 3 and Figure 4 Further illustrated in the cross-sectional view. It should be understood that in this example, cell topography 100 may represent the upper right portion of a device cell, and the topography shown may be replicated and reoriented (e.g., vertically and / or horizontally flipped) to provide a complete cell topography for a semiconductor device 10 having the desired number of active trenches 22A and terminating trenches 22B.

[0046] In this example, the semiconductor device 10 includes a semiconductor material body 11, which may include a semiconductor substrate 12 and a semiconductor region 14 disposed on or as part of the semiconductor substrate 12. The semiconductor device 10 also includes active trenches 22A and one or more terminating trenches 22B. In this example, the active trenches 22A are configured as a plurality of elongated active trenches, each terminating at a tip region 220. In this example, Figure 1 The active trench 22A with a tip region 220 shown can be coupled or connected at opposite edges of the cell topology 100 to, for example, the opposite side or underside of the terminating trench 22B. In this example, one or more active trenches 21A extend laterally from the active region 103 to the double-shielded conductor contact region 102 together with the semiconductor material region 11.

[0047] In this example, semiconductor device 10 includes a lower shielding conductor 21A; an upper shielding conductor 21B; a shielding dielectric 24 that isolates the lower shielding conductor 21A and the upper shielding conductor 21B from semiconductor region 14; and a gate electrode 28 located above the upper shielding conductor 21B and isolated from the upper shielding conductor 21B by an inter-electrode dielectric 27, and isolated from semiconductor region 14 by a gate dielectric 26. In this example, portions of the lower shielding conductor 21A are partially isolated from portions of the upper shielding conductor 21B by a shielding dielectric 240 to provide a double-shielded configuration. It should be understood that additional shielding conductors or electrodes and shielding dielectrics can be used to provide a multi-shielded conductor configuration for semiconductor device 10.

[0048] The shielding dielectric 24 may be an example of a first shielding dielectric, and the shielding dielectric 240 may be an example of a second shielding dielectric. The lower shielding conductor 21A may be an example of a first shielding conductor or a first shielding electrode, and the upper shielding conductor 21B may be an example of a second shielding conductor or a second shielding electrode. In this example, the dual shielding electrode 21' may be used to describe those portions of the semiconductor device 10 in which the shielding dielectric 240 isolates the lower shielding conductor 21A from the upper shielding conductor 21B (including the active trench 22A and the terminating trench 22B), and the shielding electrode 21" may be used to describe those portions of the semiconductor device 10 in which the lower shielding electrode 21A is coupled to the upper shielding conductor 21B.

[0049] According to this specification, one or more regions without shielding dielectric 240 are provided within the semiconductor device 10, and a recessed contact region 212 is provided between the lower shielding conductor 21A and the upper shielding conductor 21B (see (for example)). Figure 2 and Figure 4 More specifically, the recessed contact region 212 is located within the active trench 22A and the terminating trench 22B below the top side 18, and wherein the lower shielding conductor 21A contacts or connects to the upper shielding electrode 22B. In this example, the double-shielded conductor contact region 102 is disposed within the cell topology 100 and is an example location of the recessed contact region 212. The double-shielded conductor contact region 102 may include, or be referred to as, a multi-shielded conductor contact region, a multi-shielded conductor contact region, or a recessed shielding conductor contact region, and relates to those portions of the cell topology 100 where the recessed contact region 212 is located. In some examples, one or more recessed contact regions 212 extend laterally below the gate contact 280, such as... Figure 2 As shown in the general diagram. In this example, the double-shielded conductor contact area 102 is configured to contain no shielding contacts 210A.

[0050] In some examples, shielding contact 210A is disposed in upper shielding contact region 104 of cell topology 100 and coupled to upper shielding conductor 21B in a region of semiconductor device 10, in which shielding dielectric 240 isolates upper shielding conductor 21B from lower shielding electrode 21A (see, for example). Figure 2 and Figure 3 Thus, the upper shielding conductor 21B provides a lateral conductive path from the upper shielding contact area 104 to the double shielding conductor contact area 102, wherein the recessed contact area 212 is disposed between the lower shielding conductor 21A and the upper shielding conductor 21B. According to this specification, the interconnection scheme or layout between the lower shielding conductor 21A and the upper shielding conductor 21B is advantageous because it avoids the need for a separate shielding contact structure for the lower shielding conductor 21A. In this interconnection scheme, the shielding contact 210A provides direct contact with the upper shielding conductor 21B and indirect contact with the lower shielding conductor 21A. In particular, this saves space and avoids an increase in die size.

[0051] In this example, the termination trench 22B also includes both a lower shielding conductor 21A and an upper shielding conductor 21B. Similar to the active trench 22A, a portion of the termination trench 22B includes a shielding dielectric 240 that isolates the lower shielding conductor 21A from the upper shielding conductor 21B, wherein the shielding dielectric is (e.g.) Figure 2 and Figure 3 As shown in the figure. In this example, one of the recessed contact regions 212 couples the lower shielding conductor 21A and the upper shielding conductor 21B together in the double-shielded conductor contact region 102 of the unit topology 100, which in Figure 2 and Figure 4 This is further illustrated in the text.

[0052] refer to Figure 3 and Figure 4 The semiconductor device 10 includes a semiconductor material region 11, which may also include or be referred to as a semiconductor material body, semiconductor workpiece, semiconductor region, or semiconductor material. In some examples, the semiconductor material region 11 includes silicon. In other examples, the semiconductor material region 11 or a portion thereof may include other semiconductor materials, including but not limited to silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, silicon carbide, gallium nitride, or other related or equivalent materials known to those skilled in the art.

[0053] In some examples, the semiconductor material region 11 may include a substrate 12 (such as an N-type silicon substrate) and a semiconductor region 14 adjacent to the substrate 12. The substrate 12 may also be referred to as a semiconductor substrate or a starting substrate, and the semiconductor region 14 may also be referred to as a semiconductor layer or an extended drain region. In some examples, the substrate 12 has a resistivity ranging from about 0.0005 ohm-cm to about 0.005 ohm-cm. For example, the substrate 12 may be doped with phosphorus, arsenic, or antimony. In the illustrated example, the substrate 12 provides a drain region, a drain contact, or a first current-carrying contact for the semiconductor device 10. The semiconductor material region 11 includes a top side 18 and a bottom side 19 opposite to the top side 18. The top side 18 may also be referred to as an upper side or a first main surface, and the bottom side 19 may also be referred to as a back side or a second main surface.

[0054] In some examples, semiconductor epitaxial growth techniques can be used to form semiconductor region 14. Alternatively, semiconductor doping and diffusion techniques or other techniques known to those skilled in the art can be used to form semiconductor region 14. In an example suitable for a 50-volt device, semiconductor region 14 may include N-type conductivity and approximately 1.0 x 10⁻⁶ volts. 16 Atoms per cubic centimeter to approximately 5.0 x 10⁻⁶ 17 The doping concentration is atoms per cubic centimeter, and the thickness can range from about 3 micrometers to about 5 micrometers. The doping concentration and thickness of semiconductor region 14 can be determined based on the desired drain-source breakdown voltage (BV) of semiconductor device 10. DSS The value may be increased or decreased depending on the rating. In some examples, semiconductor region 14 may include a gradient dopant distribution. In an alternative example, the conductivity type of substrate 12 may be opposite to that of semiconductor region 14 to form, for example, an IGBT semiconductor device.

[0055] The shielding dielectric 24 can be one or more dielectric or insulating materials. In some examples, the shielding dielectric 24 may include a thermal oxide layer having a thickness ranging from about 0.1 micrometers to about 1.5 micrometers. In some examples, the shielding dielectric 24 may be multiple layers of similar or different materials, such as thermally deposited dielectrics or insulating materials. The thickness of the shielding dielectric will vary depending on the required BV of the device. DSS And the changes, BV DSSThe higher the value, the thicker the layer required. The shielding dielectric 240 can be one or more dielectric or insulating materials. In some examples, the shielding dielectric 240 can be a thermal oxide layer having a thickness ranging from about 0.05 micrometers to about 0.5 micrometers. In some examples, the shielding dielectric 240 can be multiple layers of similar or different materials, such as thermally and deposited dielectrics or insulating materials. In some examples, the shielding dielectric 240 can include a thickness less than that of the shielding dielectric 24 and greater than that of the gate dielectric 26. In some examples, the shielding dielectric 240 can include a thickness less than that of the inter-electrode dielectric 27.

[0056] The gate dielectric 26 and the inter-electrode dielectric 27 may comprise oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric materials, combinations thereof, or other related or equivalent materials known to those skilled in the art. In some examples, the gate dielectric 26 and the inter-electrode dielectric 27 may be silicon oxide. In some examples, the gate dielectric 26 may have a thickness from about 0.02 micrometers to about 0.1 micrometers, and the inter-electrode dielectric 27 may have a thickness greater than that of the gate dielectric 26. In some examples, the inter-electrode dielectric may have a thickness from about 0.1 micrometers to about 0.5 micrometers. In some examples, the dielectric 24 may have a thickness greater than that of the gate dielectric 26 and the inter-electrode dielectric 27.

[0057] In some examples, the gate electrode 28, the lower shielding conductor 21A, and the upper shielding conductor 21B comprise a doped polycrystalline semiconductor material, such as doped polycrystalline silicon. In some examples, an N-type conductive dopant material may be used to dope the polycrystalline silicon. In some examples, a metal, silicide, or other conductor may be included as part of the gate electrode 28, the lower shielding conductor 21A, or the upper shielding conductor 21B.

[0058] Semiconductor device 10 includes a body region 31 extending inward from top side 18 into a semiconductor material region 11 adjacent to an active trench 22A (e.g., extending inward into semiconductor region 14). Body region 31 may also include, or be referred to as, a doped region or base region. Body region 31 may have a conductivity type opposite to that of semiconductor region 14. For example, when semiconductor region 14 includes N-type conductivity, body region 31 includes P-type conductivity. Body region 31 includes a dopant concentration suitable for forming inversion layers that serve as channel regions of semiconductor device 10. In some examples, body region 31 may extend from top side 18 to a depth of about 0.3 micrometers to about 1.5 micrometers. Doping techniques such as ion implantation and annealing can be used to form body region 31. In some examples, body region 31 is a single, continuous, interconnected region. In other examples, body region 31 may be multiple regions comprising separate or discrete regions or cells.

[0059] The semiconductor device 10 may further include a doped region 33 within a body region 31. In some examples, the body region 31 adjacent to the termination trench 22B may not contain a doped region 33. The doped region 33 may also be referred to as a source region, a current-carrying region, or a current-conducting region. When the body region 31 includes P-type conductivity, the doped region 33 includes N-type conductivity and may be formed using, for example, phosphorus or arsenic dopant sources. In some examples, an ion implantation doping process may be used to form the doped region 33 within the body region 31. The doped region 33 may extend from the top side 18 to a depth of, for example, about 0.2 micrometers to about 0.5 micrometers. The doped region 33 may be an example of a second current-carrying region.

[0060] In some examples, the semiconductor device 10 further includes an interlayer dielectric (ILD) 41 above the gate electrode 28. In some examples, the interlayer dielectric 41 includes silicon oxide, such as doped or undoped deposited silicon oxide. In some examples, the interlayer dielectric 41 may include a deposited silicon oxide layer doped with phosphorus or boron and phosphorus and an undoped oxide layer. In some examples, the interlayer dielectric 41 may have a thickness of about 0.25 micrometers to about 1.0 micrometer. In some examples, the interlayer dielectric 41 may be planarized to provide a more uniform surface topography, which improves manufacturability.

[0061] In some examples, the semiconductor device 10 also includes a body contact region 36 within the body region 31. The body contact region 36 may also be referred to as a doped region, an enhanced region, or a contact region. In some examples, the body contact region 36 may include P-type conductivity and is configured to provide a lower contact resistance with the body region 31. The body contact region 36 may be formed using ion implantation (e.g., using boron) and annealing techniques.

[0062] In some examples, the semiconductor device 10 further includes a conductive region 43 configured to provide electrical contact with the doped region 33 and the body region 31 via a body contact region 36. In some examples, the conductive region 43 includes a conductive plug or plug structure. In some examples, the conductive region 43 may include a conductive barrier structure or liner and a conductive filler material. In some examples, the barrier structure may include a metal / metal-nitride configuration, such as titanium / titanium nitride or other related or equivalent materials known to those skilled in the art. In other examples, the barrier structure may also include a metal silicide structure. In some examples, the conductive filler material includes tungsten. In some examples, the conductive region 43 may be planarized to provide a more uniform surface morphology.

[0063] In some examples, conductors 44A and 44B may be formed adjacent to the top side 18, and conductor 46 may be formed adjacent to the bottom side 19. Conductors 44A and 44B may also be referred to as top metal or top conductor, and conductor 46 may also be referred to as bottom conductor or back metal. Conductors 44A, 44B, and 46 may be configured to provide electrical connections between various units of the semiconductor device 10 and next-level components. In some examples, conductors 44A and 44B comprise titanium / titanium nitride / aluminum copper or other related or equivalent materials known to those skilled in the art and are configured as source electrodes or terminals. In some examples, conductor 46 comprises a solderable metal structure, such as titanium nickel silver, chromium nickel gold, or other related or equivalent materials known to those skilled in the art and configured as drain electrodes or terminals. In some examples, an additional passivation layer (not shown) may be formed adjacent to conductors 44A and 44B. In some examples, shielding electrodes 21' and 21" may be connected to conductor 44A such that shielding electrodes 21' and 21" are configured to be at the same potential as doped region 33 when semiconductor device 10 is in use. In other examples, shielding electrodes 21' and 21" may be configured to be independently biased or electrically floatable.

[0064] In one example, the semiconductor device 10 may operate as follows. If conductor 44A and shielding electrodes 21' and 21" are at a potential of zero volts V... S In the following operation, the gate electrode 28 will receive a 10-volt control voltage V. G It is greater than the conduction threshold of semiconductor device 10, and the drain electrode (or output terminal) 46 will be at a drain potential V less than 2.0 volts. D Next operation. V G and V S The value will cause the body region 31 to reverse the adjacent gate electrode 28 to form a channel region, which will electrically connect the doped region 33 to the semiconductor region 14 in the active trench 22A. Device current I DS The current will flow out of conductor 46 and be guided through semiconductor region 14, channel region, and doped region 33 to conductor 44B. In some examples, I DS Approximately 10.0 amperes. To switch semiconductor device 10 to the off state, a control voltage V less than the semiconductor's conductivity threshold is applied. G This control voltage will remove the channel region, and I DS No more flow will pass through semiconductor device 10. According to this specification, the configuration of semiconductor device 10 as described herein uses a multi-shielded electrode configuration with localized coupling between shielded conductors (i.e., using a double-shielded conductor contact region 102 to facilitate coupling) to achieve improved BV through charge balancing techniques. DSS Improves performance and reduces gate-drain capacitance C.gd And Qrr, thereby improving (especially) switching performance.

[0065] Figures 5 to 20 Partial cross-sectional views of semiconductor devices at various manufacturing stages are shown according to this specification. Figures 5 to 20 The methods described herein can be used to manufacture, form, or produce (e.g.) such as Figures 1 to 4 The semiconductor device 10 described herein. In particular, the methods described herein illustrate the steps for performing the following operations: providing a region of the semiconductor device 10 including a shielding dielectric 240 that isolates a lower shielding conductor 21A from an upper shielding conductor 21B, and providing a region of the semiconductor device 10 in which the lower shielding conductor 21A is coupled (including electrically coupled) to the upper shielding conductor 21B through one of the recessed contact regions 212. Although the various regions described above may be shown side-by-side in some of the following cross-sectional views, it should be understood that this is for the sake of simplicity, and the various regions may be laterally separated or arranged as shown in the following cross-sectional views. Figure 1 In certain portions of the semiconductor device 10 shown. However, in other examples, the regions may be arranged side-by-side as shown.

[0066] Figure 5 A semiconductor device 10 in an early manufacturing stage is shown. In this example, a semiconductor material region 11 may be configured to include a semiconductor substrate 12 and a semiconductor region 14, as previously described. In some examples, masking and etching processes may be used to form an active trench 22A and a terminating trench 22B extending from the top side 18 of the semiconductor material body 11 into and terminating the semiconductor region 14. When the semiconductor material region 11 comprises silicon, the active trench 22A and the terminating trench 22B may be provided using fluorine etching chemistry or similar chemistry known to those skilled in the art. In some examples, the active trench 22A may have a width in the range of about 500 nanometers to about 700 nanometers, and the terminating trench 22B may have a width similar to or different from that of the active trench 22A. In some examples, the active trench 22A is configured to include, as in... Figure 1 and Figure 2 The tip region 220 shown is an elongated trench. In some examples, the active trench 22A and the terminating trench 22B may include sloping sidewall surfaces and a circular lower surface. In a next step, a dielectric 246 is disposed over the top side 18 and over the surfaces of the active trench 22A and the terminating trench 22B. In some examples, the dielectric 246 comprises a thermal oxide having a thickness ranging from about 0.1 micrometers to about 1.5 micrometers.

[0067] Figure 6The semiconductor device 10 after further processing is shown. In this example, dielectric 247 may be disposed on dielectric 246. In some examples, dielectric 247 may comprise deposited oxide formed using chemical vapor deposition (CVD) technology. In some examples, dielectric 247 may have a thickness of about 0.05 micrometers to about 0.3 micrometers. In this example, dielectric 246 and dielectric 247 form a shielding dielectric 24 of the semiconductor device 10.

[0068] Figure 7 The semiconductor device 10 after further processing is shown. In this example, conductive material 211A is disposed within active trench 22A and termination trench 22B. Conductive material 211A may include, or be referred to as, a shielding conductor or shielding conductive material. In some examples, conductive material 211A includes a polycrystalline semiconductor material, such as doped polycrystalline silicon. In some examples, conductive material 211A includes polycrystalline silicon doped with N-type dopant and may be provided using CVD technology. In some examples, a planarization process may be used to planarize and remove the portion of conductive material 211A above the top side 18, leaving the remaining portion of conductive material 211A within the active trench 22A and termination trench 22B. In some examples, chemical mechanical planarization (CMP) technology may be used to planarize conductive material 211A. In some examples, the planarization process makes the top side of conductive material 211A substantially coplanar with the top side of dielectric 247. Conductive material 211A may be an example of a first conductive material.

[0069] Figure 8 The semiconductor device 10 after further processing is shown. In this example, a portion of the conductive material 211A is removed from the upper portion of the active trench 22A and the terminating trench 22B to form the lower shielding conductor 21A. In some examples, when the conductive material 211A comprises polysilicon, a dry etching technique incorporating fluorine chemistry can be used to form the lower shielding conductor 21A. In some examples, the lower shielding conductor 21A may have a thickness or height ranging from about 0.3 micrometers to about 2.0 micrometers.

[0070] Next, a shielding dielectric 240 can be placed above the lower shielding conductor 21A, such as... Figure 9 As shown. In some examples, the shielding dielectric 240 comprises thermal oxides. In some examples, the shielding dielectric 240 may have a thickness of about 0.03 micrometers to about 0.15 micrometers.

[0071] Figure 10 and Figure 11 The semiconductor device 10 after further processing is shown. More specifically, Figure 10 and Figure 11The diagram illustrates the process steps for performing the following operation: forming a recessed contact region 212 in a selected area of ​​a semiconductor device 10 while leaving a shielding dielectric 240 in other areas of the semiconductor device 10. In this example, a photoresist layer 51 is disposed over the semiconductor material region 11, including within an active trench 22A and a termination trench 22B. Experiments have shown that, in some examples, it is preferred that the photoresist layer 51 comprises a negative photoresist layer, rather than a positive photoresist, when removing the shielding dielectric 240 from a specific area of ​​the semiconductor device 10. It has been found that, when using a positive photoresist, overexposure of the positive photoresist is required to remove it from the active trench 22A and termination trench 22B from which the shielding dielectric 240 is to be removed. In some cases, complete removal of the positive photoresist after exposure is difficult and inconsistent, leading to reduced manufacturing yield and cycle time. When using positive photoresist, exposure to UV light is necessary to alter the chemical structure of the resist, making it more soluble in the photoresist developer. Conversely, when using negative photoresist, exposure to UV light causes the chemical structure of the photoresist to polymerize, the opposite of positive photoresist. The exposed negative photoresist does not become more soluble in the photoresist developer; instead, it becomes less soluble. Therefore, when photoresist layer 51 contains negative photoresist, overexposure to the depths of the trenches is unnecessary; instead, exposure is only required to reach the portions adjacent to the active trench 22A and the terminating trench 22B on the top side 18.

[0072] like Figure 10 As shown, a mask 52 is disposed over the area of ​​semiconductor device 10 where one or more recessed contact regions 212 are to be formed, and a photoresist layer 51 is exposed to a UV light source 53. In this example, this causes the photoresist layer 51 to polymerize over the left side of the active trench 22A and over the terminating trench 22B. After exposure to the UV light source 53, the photoresist layer 51 is developed, which removes the unexposed portions of the photoresist layer 51 above and inside the first portion forming the opening 510 on the right side of the active trench 22A, such as... Figure 11 As shown. For example, the first portion may be within the tip region 220, wherein the active trench 22A is configured as an elongated active trench. It should be understood that the exposed portion of the photoresist layer 51 may be retained on the right side of the active trench 22A in a second portion located in the active region 103 of the cell morphology 100 (which may be (e.g.) Figure 10 The second part is above or covers the left side of the active trench in the diagram. According to this specification, by providing a photoresist layer 51 containing a negative photoresist, manufacturing yield and cycle time are improved.

[0073] After removing the photoresist layer 51 to provide the opening 510, the shielding dielectric 240 can be removed from the active trench 22A exposed through the opening 510 using a wet or dry dielectric etching process. In some examples, the removal of the shielding dielectric 240 may also remove the exposed portion of dielectric 247 and the portion of dielectric 246 that allows the recessed edge portion 510A to abut against the active trench 22A exposed through the opening 510. After removing the shielding dielectric 240, the photoresist layer 51 can be removed using conventional processing techniques.

[0074] Figure 12 The semiconductor device 10 after further processing is shown. In this example, conductive material 211B is disposed within the active trench 22A and the terminating trench 23 above the lower shielding conductor 21A. The conductive material 211B may include, or be referred to as, the shielding conductor or the shielding conductive material. In some examples, the conductive material 211B includes a polycrystalline semiconductor material, such as doped polycrystalline silicon. In some examples, the conductive material 211B includes polycrystalline silicon doped with N-type dopant and may be provided using CVD technology. In some examples, a planarization process may be used to planarize and remove the portion of the conductive material 211B above the top side 18, leaving the remaining portions of the conductive material 211B within the active trench 22A and the terminating trench 22B. In some examples, after the planarization process, a portion 211B' of the conductive material 211B may remain above the recessed edge portion 510A. In some examples, CMP technology may be used to planarize the conductive material 211B. In some examples, the planarization process makes the top side of the conductive material 211B substantially coplanar with the top side of the dielectric 247. By previously removing the shielding dielectric 240 in one of the right sides of the active trench 22A, the lower shielding conductor 21A is coupled (including electrically coupled) to the upper shielding conductor 21B through one of the recessed contact regions 212. The shielding dielectric 240 electrically isolates the lower shielding conductor 21A from the upper shielding conductor 21B in one of the left sides of the active trench 22A and in the terminating trench 22B. The conductive material 211B is an example of a second conductive material.

[0075] Figure 13The semiconductor device 10 after further processing is shown. In this example, in a first recess step as part of a two-step removal process according to this specification, a portion including portion 211B' of the conductive material portion 211B is removed from the upper portion of the active trench 22A and the terminating trench 22B. This first step may include, or be referred to as, a blanket removal step, a bulk removal step, or a maskless removal step. In some examples, the first recess step sets the upper side of the conductive material 211B in both the active trench 22A and the terminating trench 21B below the upper side of the dielectric 247 and adjacent to the top side 18. In some examples, when the conductive material 211B comprises polysilicon, the first recess step may be performed using a dry etching technique incorporating fluorine chemistry. In this example, the first recess step sets the upper shielding conductor 21B in the terminating trench 22B.

[0076] Figure 14 The semiconductor device 10 after further processing is shown. In this example, a mask layer 53 is disposed over the top side 18 and patterned to provide an opening 530 exposing the active trench 22A. A portion of the mask layer 53 remains over the terminating trench 22B. Other portions of the mask layer 53 also remain over the tip region 220 of the active trench 22A (e.g., in the edge region 101 of the cell topology 100) and at the locations where the shielding contact 210A is disposed (e.g., in the upper shielding contact region 104 of the cell topology 100). In some examples, the mask layer 53 may contain a photoresist material. Next, in a second recessing step, additional portions of the conductive material 211B are removed to provide the upper shielding conductor 21B in the active trench 22A. After the second recessing step, the mask layer 53 can be removed. In this example, the upper shielding conductor 21B in the active trench 22A is recessed by a larger distance below the top side 18 compared to the upper shielding conductor 21B in the termination trench 22B. In some examples, the upper shielding conductor 21B in the active trench 22A may have a thickness ranging from about 0.5 micrometers to about 3.0 micrometers.

[0077] Figure 13 and Figure 14 The method shown is an exemplary process improvement in which the first recess is provided in a two-step process. Experiments have shown that, without... Figure 13 In the case of the first recessed step described herein, an undercut effect occurs in the upper shielding conductor 21B within the termination trench 22B. This undercut effect results in an incorrect upper topographic shape of the upper shielding conductor 21B and increases the likelihood of... Figure 1 and Figure 21 The probability of contact breakage or floating occurs in the shielding contact 210B in the termination trench 22B shown. The two-step recess process described herein improves the quality of the upper morphology and reduces the breakage and floating contact problems associated with the single-step recess process.

[0078] Figure 15 The semiconductor device 10 after further processing is shown. In this example, dielectric 270 is disposed above the top side 18, which includes the upper side of shielding conductor 21B. In some examples, dielectric 270 may comprise a borosilicate glass (BSG) dielectric or a thermal oxide. In subsequent steps, planarization processes may be used to remove portions of dielectric 270, dielectric 247, and dielectric 246, such as... Figure 16 As shown in the figure. In some examples, CMP can be used to provide the upper side of dielectric 270 that is substantially coplanar with the top side 18 of semiconductor material region 11.

[0079] Figure 17 The semiconductor device 10 after further processing is shown. In this example, an etching process using hydrofluoric (HF) acid can be used to remove the portions of dielectrics 247 and 246 located above the top side 18. In some examples, this step may concave dielectrics 246 and 247 below the top side 18, wherein dielectric 247 is etched at a faster rate than dielectric 246 when dielectric 247 contains deposited oxide and dielectric 246 contains thermal oxide.

[0080] Figure 18 The semiconductor device 10 after further processing is shown. In this example, a mask layer 54 is disposed over the top side 18 and patterned to provide an opening 540 exposing the active trench 22A. The mask layer 54 remains over the terminating trench 22B. In some examples, the mask layer 54 includes a photoresist layer. In some examples, after forming the opening 540, buffered oxide etching (BOE) can be used to further remove portions of dielectrics 270, 247, and 246. In this example, this forms an interlayer dielectric 27 over the upper shielding conductor 21B and exposes the upper sidewalls of the active trench 22A.

[0081] In subsequent steps, the mask layer 54 can be removed, and the gate dielectric 26 can be disposed on the exposed upper sidewall of the active trench 22A, such as... Figure 19As shown. The gate dielectric 26 and interlayer dielectric 27 may include oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric materials, combinations thereof, or other related or equivalent materials known to those skilled in the art. In some examples, the gate dielectric 26 may be silicon oxide formed using a thermal oxidation technique. In some examples, the gate dielectric 26 may have a thickness of about 0.02 micrometers to about 0.1 micrometers. In some examples, when forming the gate dielectric 26, dielectric 261 may be disposed above the shielding conductor 21B in the termination trench 22B. Based on the polycrystalline structure of the upper shielding conductor 21B, dielectric 261 may have a greater thickness than the gate dielectric 26.

[0082] Figure 20 The semiconductor device 10 after further processing is shown. In this example, a gate conductor may be disposed above the top side 18 and planarized to provide a gate electrode 28 in an active trench 22A. In some examples, the gate electrode 28 comprises a doped polycrystalline semiconductor material such as doped polycrystalline silicon and may be formed using a CVD processing technique. In some examples, CMP may be used to planarize the deposited material to provide the gate electrode 28. The semiconductor device 10 may be further processed to provide the body region 31, doped region 33, body contact region 36, ILD 41, conductive region 43, and conductors 44a, 44B, and 46 as previously described. According to this specification, Figures 5 to 20 The method provides a semiconductor device 10, the semiconductor device including: a region including a shielding dielectric 240 that isolates a lower shielding conductor 21A from an upper shielding conductor 21B; and a region in which the lower shielding conductor 21A is coupled to the upper shielding conductor 21B through one or more recessed contact regions 212.

[0083] Figure 21 It shows along Figure 1 The reference line 21A”-21A” shows a partial cross-sectional view of the termination trench 22B of the semiconductor device 10. In this example, a shielding contact 210B is disposed in the peripheral region of the cell topology 100 and contacts the upper shielding conductor 21B at a location on the semiconductor device 10 where a shielding dielectric 240 isolates the upper shielding conductor 21B from the lower shielding electrode 21A. Thus, the upper shielding conductor 21A provides a lateral conductive path to a double-shielded conductor contact area 102, in which one of the recessed contact areas 212 couples the upper shielding conductor 21B to the lower shielding conductor 21A in the termination trench 22B. The shielding contact 210B is an example of a second shielding contact.

[0084] Figure 22 A partial cross-sectional view of an exemplary semiconductor device 10A according to this specification is illustrated. Figure 22Semiconductor device 10A is structurally similar to semiconductor device 10, and this similarity will not be described further here. In this example, semiconductor device 10A includes a shielding silicide 218B over the upper shielding conductor 21B, which can be used to reduce shielding resistance. In some examples, semiconductor device 10A may further include a shielding silicide 218A over the lower shielding conductor 21A to further reduce shielding resistance. In examples including shielding silicide 218A, shielding dielectric 240 may include deposited oxide. Shielding silicide 218A and shielding silicide 218B may include cobalt silicide or other materials known to those skilled in the art. In some examples, semiconductor device 10A includes a gate silicide 282 over the gate electrode 28, which can be used to reduce gate resistance. In some examples, shielding silicide 218A may be used where the lower shielding conductor 21A is coupled to the upper shielding conductor 21B in the recessed contact region 212.

[0085] Figures 23 to 28 Partial cross-sectional views of the semiconductor device 10 at various manufacturing stages according to this specification are shown. More specifically, Figures 23 to 28 It is along Figure 1 The reference line 23A-23A shows an example of a semiconductor device 10, which corresponds to a portion of the double-shielded conductor contact region 102 of the cell topology 100, in which the recessed contact region 212 couples the lower shield conductor 21A to the upper shield conductor 21B in the active trench 22A and the terminating trench 22B.

[0086] Figure 23 A semiconductor device 10 is shown in a manufacturing step in which a lower shielding conductor 21B has been disposed within an active trench 22A and a terminating trench 22B, and a shielding dielectric 240 has been disposed over the lower shielding conductor 21B. In this example, Figure 23 One of the active trenches 22A on the right corresponds to one of the tip regions 220, and the other of the active trenches 22A on the left corresponds to an active trench extending in the opposite direction from the terminating trench 22B, as shown. Figure 1 As shown.

[0087] Figure 24 The semiconductor device 10 after further processing is shown. In this example, a mask layer 56 is disposed over the top side 18 and patterned to provide openings 560 exposing the active trench 22A and the terminating trench 22B. According to this specification, the mask layer 56 preferably includes, as previously described, […]. Figure 10 and Figure 11 The aforementioned negative photoresist. Next, the shielding dielectric 240 is removed from the active trench 22A and the termination trench 22B using a wet or dry etching process, such as... Figure 25As shown. In some examples, the dielectric 247 can be removed at a location above the top side 18 where the mask layer 56 is not present. The mask layer 56 remains in situ during the etching process to protect the shielding dielectric 240 located in those locations where the desired shielding dielectric 240 of the semiconductor device 10 isolates the lower shielding conductor 21A from the upper shielding conductor 21B. The mask layer 56 can then be removed.

[0088] Figure 26 The semiconductor device 10 after further processing is shown. In this example, conductive material 211B is disposed within the active trench 22A and the terminating trench 22B, and coupled to the lower shielding conductor 21A via the recessed contact region 212. This can be achieved as previously described by... Figure 12 The manner described provides conductive material 211B.

[0089] Figure 27 The semiconductor device 10 after further processing is shown. In this example, as previously described, by... Figure 13 In the first recessing step, a portion of the conductive material 211B is removed from the upper part of the active trench 22A and the terminal 22B. In this example, the first recessing step provides an upper shielding conductor 21B in the terminating trench 22B.

[0090] Figure 28 The semiconductor device 10 after further processing is shown. In this example, a mask layer 53 is disposed over the top side 18 and patterned to provide an opening 530 exposing the active trench 22A. A portion of the mask layer 53 remains over the terminating trench 22B. In some examples, the mask layer 53 may contain a photoresist material. Next, in a second recessing step, additional portions of the conductive material 211B are removed to form an upper shielding conductor 21B in the active trench 22A. After the second recessing step, the mask layer 53 can be removed.

[0091] Figure 27 and Figure 28 The method shown has the same characteristics as the previous one. Figure 13 and Figure 14 The same advantages include improved contact surfaces for the upper shielding conductor 21B in the terminating trench 22B. For example... Figure 1 and Figure 21 As shown, the improved contact surface reduces the likelihood of disconnection or floating contact with the shielding contact 210B in the termination trench 22B.

[0092] In summary, structures and methods for semiconductor devices with improved manufacturability and performance have been described. In some examples, the structures include cell topology structures that facilitate electrical connections between multiple shielding electrodes. Such structures can be disposed at, for example, the tip portion of an active trench. In some examples, such structures can be disposed at the end portion of the tip portion of a terminating active trench. In some examples, methods are described that improve the manufacturability of the electrical connection structures between multiple shielding electrodes and the electrical connections to the terminating trench, thereby improving the overall reliability of the semiconductor device. Furthermore, the methods and structures simplify the interconnect scheme between shielding conductors, thus saving layout space, simplifying the cell topology, and reducing the impact on die size.

[0093] In some examples, a negative photoresist is used as a part of the method to provide a mask layer that protects the portions of the structure in which the shielding dielectric remains in situ. In some examples, a two-step recess process is used to provide the top shielding conductor in both the active trench and the termination trench.

[0094] It should be understood that although this specification may refer to the lower shield conductor 21A as a plurality of lower shield conductors 21A and the upper shield conductor 21B as a plurality of upper shield conductors 21B, in some examples, the lower shield conductor 21A or the upper shield conductor 21B may be a single continuous structure.

[0095] It should be understood that the different examples described herein can be combined with any other examples described herein to obtain different implementation schemes.

[0096] Although the subject matter of the invention has been described in conjunction with specific preferred examples, the foregoing figures and description are merely illustrative of typical examples of the subject matter and should not be construed as limiting the scope of the invention. It will be apparent to those skilled in the art that many alternatives and variations will be readily apparent. For example, the conductivity type of each region can be reversed. Furthermore, other IV-IV semiconductor materials besides SiC, such as SiGe or SiGeC, can be used. Additionally, other compound semiconductor materials can be used. Moreover, the structures and methods described herein can be used for higher voltage devices (e.g., greater than 100 volts) or lower voltage devices (e.g., less than 30 volts).

[0097] As reflected in the claims below, various aspects of the invention may have fewer features than all the features of a single example disclosed above. Therefore, the claims set forth below are hereby expressly incorporated into this detailed description, wherein each claim represents an independent example of the invention. Furthermore, although some examples described herein include some features included in other examples but not all of those features, those skilled in the art will understand that combinations of features from different examples are intended to fall within the scope of the invention and to form different examples.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A semiconductor material region is provided, the semiconductor material region including: a top side, an edge region, a multi-shielded conductor contact region, an active region, and an upper shielding contact region within the edge region; An active trench is provided, extending from the top side to the semiconductor material region. The active trench includes: a lower shielding conductor, a first shielding dielectric, an upper shielding conductor, and a second shielding dielectric. The first shielding dielectric isolates the lower shielding conductor from the semiconductor material region, and the second shielding dielectric isolates the lower shielding conductor from the upper shielding conductor within the active region. The active trench extends laterally from the active region into the multi-shielded conductor contact area within the semiconductor material region. The lower shielding conductor and the upper shielding conductor are coupled together in the multi-shielded conductor contact area. A shielding contact is provided in the upper shielding contact area, which is coupled to the upper shielding conductor in the active trench.

2. The method according to claim 1, wherein, Setting the active trench includes: A recessed contact area is provided between the lower shielding conductor and the upper shielding conductor in the multi-shielded conductor contact area.

3. The method according to claim 1, wherein, Setting the semiconductor material region includes: The multi-shielded conductor contact area is provided, and the multi-shielded conductor contact area does not contain any shielding contact element that contacts the upper surface of the upper shielding conductor.

4. The method according to claim 1, further comprising: A termination trench is provided in the second portion extending from the top side into the semiconductor material region. The termination trench includes: a lower shielding conductor, a first shielding dielectric, an upper shielding conductor, and a second shielding dielectric. The first shielding dielectric isolates the lower shielding conductor from the semiconductor material region, and the second shielding dielectric isolates the lower shielding conductor from the upper shielding conductor within the active region. The termination trench extends laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region. The lower shielding conductor and the upper shielding conductor are coupled together in the multi-shielded conductor contact region.

5. The method according to claim 4, further comprising: A second shielding contact is provided outside the multi-shielded conductor contact area, and the second shielding contact is coupled to the upper shielding conductor in the termination trench.

6. The method according to claim 4, wherein, Setting the active trench and the termination trench includes: The lower shielding conductor is disposed within the active trench and the termination trench; A conductive material is disposed above the lower shielding conductor within the active trench and the termination trench; Remove the first portion of the conductive material located within the active trench and the termination trench; A mask layer is disposed on the conductive material in the termination trench; and The second portion of the conductive material located in the active trench is removed to provide the upper shielding conductor in the active trench.

7. The method according to claim 6, wherein, Setting the mask layer includes: The mask layer is applied after the first portion is removed.

8. The method according to claim 6, wherein: Remove the first part and place the upper shielding conductor in the termination trench.

9. The method according to claim 1, wherein, Setting the active trench region includes: The active trench is configured as an elongated active trench, the elongated active trench including a pointed portion located within the multi-shielded conductor contact area; The first shielding dielectric is disposed within the elongated active trench; The lower shielding conductor is disposed on top of the first shielding dielectric; The second shielding dielectric is disposed on the lower shielding conductor; The mask layer comprises a negative photoresist and an opening, wherein the opening exposes the second shielding dielectric located in a first portion of the elongated active trench in the multi-shielded conductor contact area; and the mask layer covers a second portion of the elongated active trench within the active area; Remove the second shielding dielectric from the elongated active trench in the multi-shielded conductor contact area; and Remove the mask layer to leave the second shielding dielectric located above the lower shielding conductor in the active region.

10. The method according to claim 1, wherein setting the active trench region comprises: An interlayer dielectric is disposed on the upper shielding conductor; A gate dielectric is disposed along the upper sidewall of the active trench; as well as A gate electrode is disposed within the active trench.

11. The method according to claim 10, further comprising: A gate contact is provided coupled to the gate electrode, wherein: Setting the active trench includes: providing a recessed contact area between the lower shielding conductor and the upper shielding conductor in the multi-shielded conductor contact area; The gate contact is located in the multi-shielded conductor contact area; and In a cross-sectional view, the gate contact covers the recessed contact area.

12. The method according to claim 1, further comprising: A shielding silicide is disposed on the upper shielding conductor.

13. A method for manufacturing a semiconductor device, the method comprising: A semiconductor material region is provided, the semiconductor material region including: a top side, an edge region adjacent to the top side, a multi-shielded conductor contact region, an active region adjacent to the top side, and an upper shielded contact region, the upper shielded contact region being adjacent to the top side and outside the multi-shielded conductor contact region; An active trench is provided, extending from the top side to the semiconductor material region, wherein: the active trench includes: a lower shielding conductor, a first shielding dielectric, an upper shielding conductor, and a second shielding dielectric; the first shielding dielectric isolates the lower shielding conductor from the semiconductor material region; the second shielding dielectric isolates the lower shielding conductor from the upper shielding conductor within the active region; the active trench extends laterally from the active region into the multi-shielded conductor contact area within the semiconductor material region; and the lower shielding conductor and the upper shielding conductor are coupled together in the multi-shielded conductor contact area; A termination trench is provided extending from the top side into a second portion of the semiconductor material region, wherein: the termination trench includes: a lower shielding conductor, a first shielding dielectric, an upper shielding conductor, and a second shielding dielectric, the first shielding dielectric isolating the lower shielding conductor from the semiconductor material region, and the second shielding dielectric isolating the lower shielding conductor from the upper shielding conductor within the active region; the termination trench extends laterally from the active region into the multi-shielded conductor contact area within the semiconductor material region; and the lower shielding conductor and the upper shielding conductor are coupled together in the multi-shielded conductor contact area; and A shielding contact is provided in the upper shielding contact area, which is coupled to the upper shielding conductor in the active trench.

14. The method according to claim 13, further comprising: A second shielding contact is provided, which is coupled to the upper shielding conductor in the termination trench and is outside the multi-shielding conductor contact area.

15. The method according to claim 13, wherein, Setting the active trench and the termination trench includes: The lower shielding conductor is disposed within the active trench and the termination trench; A conductive material is disposed above the lower shielding conductor within the active trench and the termination trench; Remove the first portion of the conductive material located within the active trench and the termination trench; After removing the first portion, a mask layer is disposed on the conductive material in the termination trench; and The second portion of the conductive material located in the active trench is removed to provide the upper shielding conductor in the active trench.

16. The method of claim 13, wherein setting the active trench comprises: The active trench is configured as an elongated active trench, the elongated active trench including a pointed portion located within the multi-shielded conductor contact area; The first shielding dielectric is disposed within the elongated active trench; The lower shielding conductor is disposed on top of the first shielding dielectric; The second shielding dielectric is disposed on the lower shielding conductor; A mask layer comprising a negative photoresist and an opening is provided, wherein: the opening exposes the second shielding dielectric located in a first portion of the elongated active trench in the multi-shielded conductor contact area; and the mask layer covers a second portion of the elongated active trench within the active area; Remove the second shielding dielectric from the elongated active trench in the multi-shielded conductor contact area; and Remove the mask layer to leave the second shielding dielectric located above the lower shielding conductor in the active region.

17. A semiconductor device, the semiconductor device comprising: Semiconductor material regions, active trenches, and shielding contacts. The semiconductor material region includes: a top side, an edge region, a multi-shielded conductor contact region, an active region, and an upper shielding contact region outside the multi-shielded conductor contact region; The active trench extends from the top side to the semiconductor material region, wherein the active trench includes: a lower shielding conductor, a first shielding dielectric, an upper shielding conductor, and a second shielding dielectric; the first shielding dielectric isolates the lower shielding conductor from the semiconductor material region; the second shielding dielectric isolates the lower shielding conductor from the upper shielding conductor within the active region; the active trench extends laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region; and the lower shielding conductor and the upper shielding conductor are coupled together in the multi-shielded conductor contact region; and The shielding contact is located in the upper shielding contact area and is coupled to the upper shielding conductor in the active trench.

18. The semiconductor device according to claim 17, wherein: The multi-shielded conductor contact area is the edge region; and The multi-shielded conductor contact area does not contain any shielding contacts that contact the upper surface of the upper shielded conductor.

19. The semiconductor device of claim 17, further comprising: A termination trench that extends from the top side into a second portion of the semiconductor material region; The termination trench includes: a lower shielding conductor, a first shielding dielectric, an upper shielding conductor, and a second shielding dielectric; the first shielding dielectric isolates the lower shielding conductor from the semiconductor material region; the second shielding dielectric isolates the lower shielding conductor from the upper shielding conductor within the active region. The termination trench extends laterally from the active region into the multi-shielded conductor contact region within the semiconductor material region; and The lower shielding conductor and the upper shielding conductor are coupled together in the contact area of ​​the multiple shielding conductors.

20. The semiconductor device of claim 19, further comprising: The second shielding contact is outside the multi-shielded conductor contact area and coupled to the upper shielding conductor in the termination trench.

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