Heterojunction cell, manufacturing method thereof and photovoltaic module

Abstract

The invention relates to a heterojunction cell, a manufacturing method thereof and a photovoltaic module. The heterojunction battery comprises a substrate; the first intrinsic silicon layer and the first doping layer are sequentially stacked on the first surface of the substrate; the first transparent conductive layer and the protective layer are stacked on the side, away from the substrate, of the first doping layer, the first transparent conductive layer covers a partial area of the first surface, and the protective layer completely covers the first surface; the first electroplating electrode is located on the side, away from the substrate, of the protection layer and electrically connected with the first transparent conductive layer; wherein the first surface comprises an isolation region which is not covered by the first transparent conductive layer; a part of the structure of the protection layer is stacked on the part, corresponding to the isolation region, of the first doping layer. According to the heterojunction cell and the manufacturing method thereof, the efficiency of the photovoltaic module is relatively high.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a heterojunction solar cell and its manufacturing method, as well as a photovoltaic module. Background Technology

[0002] In recent years, with the rapid development of the photovoltaic industry, domestic and international markets have placed increasingly higher demands on the conversion efficiency and product performance of solar cells and photovoltaic modules. This has driven manufacturers in the industry to actively conduct research on new cell and module structures and related processes. Heterojunction (HJT) cells have advantages such as low light decay and low temperature coefficient, and can reduce energy consumption while reducing thermal damage to the silicon substrate, making them an important direction for the future development of high-efficiency cells. In heterojunction cells of related technologies, in order to reduce metallization costs, reduce metal grid line width, improve optical utilization, and improve cell efficiency, electroplating is usually used to form electrodes. Specifically, after the TCO thin film is prepared, a seed layer is first prepared, and then a patterned mask layer electrode pattern is formed through a photolithography process. The photolithography process includes processes such as film application, exposure, and development. Then, the electrodes are prepared by electroplating. After electroplating, the mask layer and seed layer need to be etched away by wet etching. However, heterojunction cells using electroplated electrodes suffer from efficiency loss due to the need for various wet chemical treatments. Summary of the Invention

[0003] Therefore, it is necessary to provide a high-efficiency heterojunction cell, its manufacturing method, and a photovoltaic module.

[0004] One embodiment of this application provides a heterojunction solar cell, including:

[0005] Substrate;

[0006] A first intrinsic silicon layer and a first doped layer are sequentially stacked on the first surface of the substrate;

[0007] A first transparent conductive layer and a protective layer are stacked on the side of the first doped layer facing away from the substrate. The first transparent conductive layer covers a portion of the first surface, and the protective layer completely covers the first surface.

[0008] The first electroplating electrode is located on the side of the protective layer away from the substrate and is electrically connected to the first transparent conductive layer.

[0009] The first surface includes an isolation region not covered by the first transparent conductive layer; a portion of the protective layer is stacked on the corresponding isolation region of the first doped layer.

[0010] In one embodiment, the protective layer completely covers the first surface and covers at least a portion of the side surface of the substrate, the side surface of the substrate being adjacent to the first surface.

[0011] In one embodiment, the protective layer completely covers the first surface, and the outer contour edge of the protective layer coincides with the edge of the first surface.

[0012] In one embodiment, a first transparent conductive layer is disposed on the surface of the first doped layer away from the substrate;

[0013] The protective layer is located on the side of the first transparent conductive layer that is away from the substrate;

[0014] The first electroplating electrode is disposed on the protective layer and is electrically connected to the first transparent conductive layer through the protective layer.

[0015] In one embodiment, the protective layer completely covers the first surface, and the outer contour edge of the protective layer coincides with the edge of the first surface;

[0016] A portion of the protective layer is stacked on the surface of the first transparent conductive layer away from the substrate, and another portion of the protective layer is stacked on the surface of the portion of the first doped layer corresponding to the isolation region.

[0017] In one embodiment, the protective layer completely covers the first surface and covers at least a portion of the side surface of the substrate, wherein the side surface of the substrate is adjacent to the first surface.

[0018] In one embodiment, the heterojunction solar cell further includes a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer sequentially stacked on a second surface of the substrate, wherein the doping type of the second doped layer is opposite to that of the first doped layer, and the second surface is disposed opposite to the first surface.

[0019] The second transparent conductive layer covers at least a portion of the second surface and the side of the substrate, and a portion of the structure of the protective layer is stacked onto the side of the second transparent conductive layer opposite to the substrate.

[0020] In one embodiment, the protective layer includes a transparent conductive oxide layer, which includes at least one of ITO, IMO, AZO, SCOT, and SnOx.

[0021] In one embodiment, the thickness of the protective layer is 5-15 nm.

[0022] In one embodiment, a protective layer is disposed on the surface of the first doped layer away from the substrate; a first transparent conductive layer is located on the side of the protective layer away from the substrate.

[0023] The first electroplating electrode is disposed on the first transparent conductive layer.

[0024] In one embodiment, the protective layer completely covers the first surface, and the outer contour edge of the protective layer coincides with the edge of the first surface.

[0025] In one embodiment, the protective layer completely covers the first surface and covers at least a portion of the side surface of the substrate, wherein the side surface of the substrate is adjacent to the first surface.

[0026] In one embodiment, the heterojunction solar cell further includes a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer sequentially stacked on a second surface of the substrate, wherein the doping type of the second doped layer is opposite to that of the first doped layer, and the second surface is disposed opposite to the first surface.

[0027] The second doped layer covers at least a portion of the second surface and side surface, the first doped layer covers at least a portion of the first surface and side surface, and a portion of the structure of the first doped layer is stacked onto the side of the second doped layer opposite to the substrate.

[0028] The protective layer is at least partially stacked on the surface of the first doped layer away from the substrate;

[0029] The second transparent conductive layer covers at least a portion of the side surface of the second surface and the substrate, and a portion of the structure of the second transparent conductive layer is stacked onto the side of the protective layer away from the substrate.

[0030] In one embodiment, the outer contour edge of the protective layer coincides with the outer contour edge of the first doped layer.

[0031] In one embodiment, the first doped layer includes an oxygen-free microcrystalline host layer, and the protective layer includes an oxygen-doped amorphous silicon layer.

[0032] In one embodiment, the first doped layer further includes an oxygen-containing microcrystalline film layer, which is stacked between the first intrinsic silicon layer and the oxygen-free microcrystalline host layer.

[0033] In one embodiment, the thickness of the protective layer is no greater than 3 nm.

[0034] In one embodiment, a portion of the protective layer covering one side is stacked onto the first doped layer, and another portion is stacked onto the second doped layer.

[0035] In one embodiment, the heterojunction solar cell further includes a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer sequentially stacked on a second surface of the substrate, wherein the doping type of the second doped layer is opposite to that of the first doped layer, and the second surface is disposed opposite to the first surface.

[0036] The second transparent conductive layer covers at least a portion of the second surface and the side of the substrate, and a portion of the structure of the protective layer is stacked onto the side of the second transparent conductive layer opposite to the substrate.

[0037] In one embodiment, the protective layer comprises a transition metal oxide, and the polarity of the protective layer is the same as that of the first doped layer; or

[0038] The protective layer includes a dielectric passivation layer; or

[0039] The protective layer includes a transparent conductive oxide layer.

[0040] In one embodiment, when the protective layer comprises a transition metal oxide, the thickness of the protective layer is 5-30 nm;

[0041] When the protective layer includes a dielectric passivation layer, the thickness of the protective layer is 0.5-3 nm;

[0042] When the protective layer includes a transparent conductive oxide layer, the thickness of the protective layer is 5-15 nm.

[0043] In one embodiment, the substrate further includes a second surface disposed opposite to the first surface, and a side surface adjacent to the first surface and the second surface;

[0044] The heterojunction cell also includes a second electroplated electrode, and a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer sequentially stacked on the second surface. The doping type of the second doped layer is opposite to that of the first doped layer. The second electroplated electrode is electrically connected to the second transparent conductive layer.

[0045] In one embodiment, the heterojunction cell further includes a first metal seed layer and a second metal seed layer, the first metal seed layer being stacked on the surface of the first electroplated electrode facing the substrate, and the second metal seed layer being stacked on the surface of the second electroplated electrode facing the substrate.

[0046] In one embodiment, the heterojunction cell further includes an electrode protective layer, wherein the electrode protective layer located on one side of the first surface is stacked on the surface of the first electroplated electrode opposite to the substrate, and the electrode protective layer located on one side of the second surface is stacked on the surface of the second electroplated electrode opposite to the substrate.

[0047] In one embodiment, the first intrinsic silicon layer covers at least a portion of the first surface and side surface;

[0048] The second intrinsic silicon layer covers at least a portion of the second surface and side surface, and a portion of the structure of the second intrinsic silicon layer is stacked onto the side of the first intrinsic silicon layer away from the substrate.

[0049] The second doped layer covers at least a portion of the second surface and side surface, and a portion of the structure of the second doped layer is stacked onto the side of the first intrinsic silicon layer away from the substrate.

[0050] The first doped layer covers at least a portion of the first surface and side surface, and a portion of the structure of the first doped layer is stacked onto the side of the second doped layer opposite to the substrate.

[0051] In one embodiment, portions of the outer contour edge of the first transparent conductive layer are spaced from the edge of the first surface to define an annular isolation region on the first surface.

[0052] This application also provides a method for fabricating a heterojunction solar cell, including:

[0053] A substrate is provided, the substrate including a substrate, and a first intrinsic silicon layer and a first doped layer sequentially stacked on a first surface of the substrate;

[0054] A first transparent conductive layer and a protective material layer are formed on the side of the first doped layer away from the substrate. The first transparent conductive layer covers a portion of the first surface, and the first surface includes an isolation region not covered by the first transparent conductive layer. The protective material layer completely covers the first surface, and a portion of the structure of the protective material layer is stacked on the corresponding isolation region of the first doped layer.

[0055] A first electroplating electrode is formed by electroplating on the side of the protective material layer away from the substrate, and the first electroplating electrode is electrically connected to the first transparent conductive layer.

[0056] In one embodiment, the step of forming the protective material layer includes:

[0057] The second surface of the substrate is oriented towards the support frame of the carrier plate;

[0058] A protective material layer is formed on the side of the first doped layer away from the substrate;

[0059] The protective material layer completely covers the first surface and at least a portion of the side surface of the substrate; or, the protective material layer completely covers the first surface, and the outer contour edge of the protective material layer coincides with the edge of the first surface.

[0060] In one embodiment, in the step of forming the first transparent conductive layer:

[0061] The first surface of the substrate is oriented towards the support frame of the carrier plate;

[0062] A first transparent conductive layer is formed on the side of the first doped layer away from the substrate, and the location of the formation of the first transparent conductive layer corresponds to the hollow portion of the bearing frame.

[0063] In one embodiment, the step of forming a first transparent conductive layer and a protective material layer stacked on each other on the side of the first doped layer away from the substrate specifically includes:

[0064] A first transparent conductive layer is formed on the surface of the first doped layer that is away from the substrate.

[0065] A protective material layer is formed on the surface of the first transparent conductive layer away from the substrate.

[0066] In one embodiment, the step of forming a first transparent conductive layer on the substrate-away surface of the first doped layer specifically includes:

[0067] The first surface of the substrate is oriented toward the support frame of the carrier plate, and the portion of the first doped layer located on the first surface is supported by the support frame.

[0068] In the portion of the first doped layer covering one side of the first surface, the area not obscured by the bearing frame forms a first transparent conductive layer.

[0069] In one embodiment, the step of forming a protective material layer on the substrate-away surface of the first transparent conductive layer specifically includes:

[0070] The second surface of the substrate is supported on one side of the support frame of the carrier plate;

[0071] A protective material layer is formed on the surface of the first transparent conductive layer away from the substrate; the protective material layer is partially stacked on the surface of the first transparent conductive layer away from the substrate, and partially stacked on the surface of the portion of the first doped layer corresponding to the isolation region.

[0072] In one embodiment, the substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface; the step of forming the first transparent conductive layer and the step of forming the protective material layer further includes:

[0073] A second transparent conductive layer is formed on the side of the second doped layer away from the substrate.

[0074] In one embodiment, the substrate further includes a side surface adjacent to the first surface and the second surface;

[0075] The second transparent conductive layer covers at least a portion of the side surface of the second surface and the substrate;

[0076] The protective material layer also covers at least a portion of the side surface, and a portion of the protective material layer is stacked onto the side of the second transparent conductive layer opposite to the substrate; or

[0077] The outer contour edge of the protective material layer coincides with the edge of the first surface.

[0078] In one embodiment, the step of forming a first transparent conductive layer and a protective material layer stacked on each other on the side of the first doped layer away from the substrate specifically includes:

[0079] A protective material layer is formed on the surface of the first doped layer away from the substrate.

[0080] A first transparent conductive layer is formed on the surface of the protective material layer away from the substrate.

[0081] In one embodiment, the substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface; the substrate also includes a side surface adjacent to the first surface and the second surface;

[0082] The step of forming a protective material layer on the substrate-away surface of the first doped layer includes:

[0083] A second transparent conductive layer is formed on the surface of the second doped layer away from the substrate, the second transparent conductive layer covering at least a portion of the second surface and side surfaces.

[0084] In one embodiment, the step of forming a protective material layer on the substrate-away surface of the first doped layer specifically includes:

[0085] A protective material layer is formed on the side of the first doped layer away from the substrate. The protective material layer completely covers the first surface and at least a portion of the side surface, and the protective material layer is stacked onto the second transparent conductive layer.

[0086] In one embodiment, the step of forming a first transparent conductive layer on the substrate-away surface of the protective material layer specifically includes:

[0087] The first surface of the substrate is oriented toward the support frame of the carrier plate, and the portion of the protective material layer located on the first surface is supported by the support frame.

[0088] In the portion of the protective material layer covering one side of the first surface, the area not obscured by the bearing frame forms a first transparent conductive layer.

[0089] In one embodiment, the substrate further includes a second surface disposed opposite to the first surface, and a side surface adjacent to the first surface and the second surface;

[0090] The step of forming a protective material layer on the substrate-away surface of the first doped layer includes:

[0091] A protective material layer is formed on the side of the first doped layer away from the substrate, the protective material layer covering at least a portion of the first surface and side surface.

[0092] In one embodiment, the step of forming a first transparent conductive layer on the substrate-away surface of the protective material layer specifically includes:

[0093] The first surface of the substrate is oriented toward the support frame of the carrier plate, and the portion of the protective material layer located on the first surface is supported by the support frame.

[0094] In the portion of the protective material layer covering one side of the first surface, the area not obscured by the bearing frame forms a first transparent conductive layer.

[0095] In one embodiment, the substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on the second surface;

[0096] Following the step of forming the first transparent conductive layer on the substrate-facing surface of the protective material layer, the following steps are also included:

[0097] A second transparent conductive layer is formed on the surface of the second doped layer away from the substrate. The second transparent conductive layer covers a portion of the second surface and side surfaces, and is stacked onto the protective material layer.

[0098] In one embodiment, the substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface;

[0099] In the step of forming a protective material layer on the surface of the first doped layer away from the substrate:

[0100] A protective material layer covers at least a portion of the first surface and side surface, and the protective material layer is stacked onto the side of the second doped layer opposite to the substrate.

[0101] In one embodiment, during the step of forming a protective material layer on the substrate-away surface of the first doped layer:

[0102] The protective material layer covers at least a portion of the first surface and side surface; the outer contour edge of the protective material layer coincides with the outer contour edge of the first doped layer.

[0103] In one embodiment, the first doped layer includes an oxygen-free microcrystalline host layer;

[0104] The steps for forming the protective material layer include:

[0105] An oxygen-containing amorphous silicon layer is formed on the surface of the first doped layer away from the substrate as a protective material layer. The oxygen-containing amorphous silicon layer has the same doping type as the first doped layer.

[0106] In one embodiment, the first doped layer further includes an oxygen-containing microcrystalline film layer, which is stacked between the first intrinsic silicon layer and the oxygen-free microcrystalline host layer.

[0107] In one embodiment, the oxygen-containing microcrystalline sublayer and the oxygen-free microcrystalline host layer are formed by the following steps:

[0108] Hydrogen, silane, diborane, and carbon dioxide gases are introduced into the reaction chamber, wherein the molar volume ratio of hydrogen, silane, diborane, and carbon dioxide gases is 300:1:0.005:0.2-600:1:0.01:0.5, and the reaction pressure in the reaction chamber is 4-6 mbar, so as to form an oxygen-containing microcrystalline film layer on the substrate-away surface of the first intrinsic silicon layer.

[0109] Hydrogen, silane, and diborane gases are introduced into the reaction chamber, wherein the molar volume ratio of hydrogen, silane, and diborane gases is 300:1:0.01-500:1:0.04, and the reaction pressure in the reaction chamber is 2-3 mbar, so as to form an oxygen-free microcrystalline host layer on the surface of the oxygen-containing microcrystalline film layer away from the substrate.

[0110] In one embodiment, the step of forming an oxygen-doped amorphous silicon layer as a protective material layer includes:

[0111] Hydrogen, silane, diborane, and carbon dioxide gases are introduced into the reaction chamber, wherein the molar volume ratio of hydrogen, silane, diborane, and carbon dioxide gases is 8:1:3:1 to 12:1:5:1.5; the reaction pressure in the reaction chamber is about 2-3 mbar, so as to form an oxygen-doped amorphous silicon layer on the surface of the oxygen-free microcrystalline host layer.

[0112] In one embodiment, the protective material layer comprises a transition metal oxide, and the polarity of the protective material layer is the same as that of the first doped layer; or

[0113] The protective material layer includes a dielectric passivation layer; or

[0114] The protective material layer includes a transparent conductive oxide layer.

[0115] In one embodiment, the substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface;

[0116] Other methods for fabricating heterojunction solar cells include:

[0117] A second transparent conductive layer is formed on the surface of the second doped layer that is away from the substrate.

[0118] A second electroplated electrode is formed on one side of the second surface of the substrate by electroplating.

[0119] In one embodiment, the protective material layer completely covers the first surface and covers at least a portion of the side surface of the substrate;

[0120] In the steps of forming the first electroplating electrode and forming the second electroplating electrode, at least a portion of the protective material layer is also removed to form a protective layer.

[0121] In one embodiment, the portion of the protective material layer that is removed includes the portion of the protective material layer located on one side; or

[0122] The removed portions of the protective material layer include the portions covering one side and the portion covering the isolation area; or

[0123] The portion of the protective material layer that is removed includes the portion of the protective material layer covering one side of the side and the portion of the protective material layer corresponding to the non-metallic contact area of ​​the first surface.

[0124] In one embodiment, the steps of forming the first electroplating electrode and forming the second electroplating electrode specifically include:

[0125] A first metal seed material layer is formed on one side of the first surface of the substrate, and a second metal seed material layer is formed on the surface of the second transparent conductive layer opposite to the substrate, wherein the first metal seed material layer is located on the one of the first transparent conductive layer and the protective material layer that is farther away from the substrate;

[0126] A first electroplating electrode is formed by electroplating a patterned mask layer on the surface of a first metal seed material layer, and a second electroplating electrode is formed by electroplating a second metal seed material layer.

[0127] Remove the mask layer;

[0128] The portion of the first metal seed material layer not covered by the first electroplating electrode is removed to form the first metal seed layer, and the portion of the second metal seed material layer not covered by the second electroplating electrode is removed to form the second metal seed layer.

[0129] In one embodiment, the patterned mask layer is formed by the following steps:

[0130] A patterned first mask material layer is formed on the side of the first metal seed material layer and the second metal seed material layer away from the substrate. The first mask material layer is hollowed out at the position of the metal contact area of ​​the first surface and at the position of the metal contact area of ​​the second surface.

[0131] An insulating adhesive is applied to one side of the substrate.

[0132] In one embodiment, after removing the portion of the first metal seed material layer not covered by the first electroplating electrode and removing the portion of the second metal seed material layer not covered by the second electroplating electrode, the method further includes forming an electrode protective layer on the surface of the first electroplating electrode and the second electroplating electrode.

[0133] In one embodiment, in the steps of removing the portion of the first metal seed material layer not covered by the first electroplating electrode, removing the portion of the second metal seed material layer not covered by the second electroplating electrode, and / or forming the electrode protective layer, at least a portion of the protective material layer is removed to form the protective material layer.

[0134] In one embodiment, the substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface;

[0135] The specific steps for providing a substrate include:

[0136] A first intrinsic silicon layer is formed on a first surface of the substrate, and a second intrinsic silicon layer is formed on a second surface of the substrate;

[0137] A second doped layer is formed on the surface of the second intrinsic silicon layer away from the substrate, and a first doped layer is formed on the surface of the first intrinsic silicon layer away from the substrate.

[0138] In one embodiment, the substrate further includes a side surface adjacent to the first surface and the second surface;

[0139] The first intrinsic silicon layer covers at least a portion of the first surface and side surface;

[0140] The second intrinsic silicon layer covers at least a portion of the second surface and side surface, and a portion of the structure of the second intrinsic silicon layer is stacked onto the side of the first intrinsic silicon layer away from the substrate.

[0141] The second doped layer covers at least a portion of the second surface and side surface, and a portion of the structure of the second doped layer is stacked onto the side of the first intrinsic silicon layer away from the substrate.

[0142] The first doped layer covers at least a portion of the first surface and side surface, and a portion of the structure of the first doped layer is stacked onto the side of the second doped layer opposite to the substrate.

[0143] This application also provides a heterojunction battery, which is manufactured using the above-described heterojunction battery manufacturing method.

[0144] This application also provides a photovoltaic module, including at least one cell string, the cell string including at least two heterojunction cells as described above.

[0145] The aforementioned heterojunction solar cells, their fabrication methods, and the beneficial effects of photovoltaic modules are as follows:

[0146] By setting a protective layer, a portion of the protective layer is stacked on the corresponding isolation region of the first doped layer. The first electroplating electrode is located on the side of the protective layer away from the substrate; therefore, the formation of the protective layer occurs before the first electroplating electrode. During the electroplating process to form the first electroplating electrode, the portion of the corresponding isolation region of the first doped layer is protected by the protective layer and thus will not be eroded by the plating solution. No defects are generated in the surface structure of the portion of the corresponding isolation region of the first doped layer. Compared to related technologies where the first doped layer is partially etched away, resulting in insufficient lateral conductivity and poor carrier collection ability, the lateral conductivity and carrier collection ability of the first doped layer remain unaffected, effectively avoiding the decrease in battery efficiency caused by corrosion and damage to the first doped layer. Furthermore, the protective layer stacked on the portion of the first doped layer corresponding to the isolation region also improves the passivation capability of the first doped layer, thus improving the efficiency of the heterojunction battery. Furthermore, the complete coverage of the first surface by the protective layer further enhances the back reflection effect on one side of the first surface. Attached Figure Description

[0147] Figure 1 This is a schematic diagram of the structure of a heterojunction battery provided in an embodiment of this application;

[0148] Figure 2 A schematic diagram of another structure of a heterojunction battery provided in an embodiment of this application;

[0149] Figure 3 A schematic diagram of another structure of the heterojunction battery provided in the embodiments of this application;

[0150] Figure 4a A schematic diagram of another structure of the heterojunction battery provided in the embodiments of this application;

[0151] Figure 4b A schematic diagram of another structure of the heterojunction battery provided in the embodiments of this application;

[0152] Figure 5 A schematic diagram of another structure of the heterojunction battery provided in the embodiments of this application;

[0153] Figure 6 A schematic diagram of another structure of the heterojunction battery provided in the embodiments of this application;

[0154] Figure 7 A schematic diagram of another structure of the heterojunction battery provided in the embodiments of this application;

[0155] Figure 8 A schematic flowchart illustrating the fabrication method of a heterojunction solar cell provided in an embodiment of this application;

[0156] Figure 9A schematic diagram of the substrate used in the fabrication method of the heterojunction solar cell provided in the embodiments of this application;

[0157] Figure 10 A schematic diagram of forming a first transparent conductive layer and a second transparent conductive layer on a substrate in the method for fabricating a heterojunction battery provided in the embodiments of this application;

[0158] Figure 11 A schematic diagram illustrating the formation of a protective material layer in the fabrication method of a heterojunction solar cell provided in this application embodiment;

[0159] Figure 12 A schematic diagram illustrating the formation of a first metal seed layer and a second metal seed layer in the method for fabricating a heterojunction solar cell provided in this application embodiment;

[0160] Figure 13 This is a schematic diagram illustrating the formation of a patterned first mask material layer and insulating adhesive in the method for fabricating a heterojunction battery according to an embodiment of this application.

[0161] Figure 14 A schematic diagram illustrating the formation of a protective material layer in another method for fabricating a heterojunction solar cell provided in an embodiment of this application;

[0162] Figure 15 A schematic diagram of forming a first transparent conductive layer and a second transparent conductive layer in another method for fabricating a heterojunction battery provided in an embodiment of this application;

[0163] Figure 16 A schematic diagram of forming a first metal seed layer and a second metal seed layer in another method for fabricating a heterojunction solar cell provided in an embodiment of this application;

[0164] Figure 17 A schematic diagram of forming a patterned first mask material layer and insulating adhesive in another method for fabricating a heterojunction battery provided in an embodiment of this application;

[0165] Figure 18 A schematic diagram of forming a second transparent conductive layer in another method of fabricating a heterojunction battery provided in an embodiment of this application;

[0166] Figure 19 A schematic diagram of forming a protective material layer and a first transparent conductive layer in another method for fabricating a heterojunction battery provided in an embodiment of this application;

[0167] Figure 20 A schematic diagram of forming a first metal seed layer and a second metal seed layer in another method for fabricating a heterojunction solar cell provided in an embodiment of this application;

[0168] Figure 21A schematic diagram of forming a patterned first mask material layer and insulating adhesive in another method for fabricating a heterojunction battery provided in an embodiment of this application;

[0169] Figure 22 A schematic diagram of another structure of the heterojunction battery provided in the embodiments of this application;

[0170] Figure 23 A schematic diagram showing the formation of a protective material layer on a substrate in another method of fabricating a heterojunction solar cell provided in this application embodiment;

[0171] Figure 24 A schematic diagram showing the formation of a first transparent conductive layer and a second transparent conductive layer in another method of fabricating a heterojunction battery provided in an embodiment of this application;

[0172] Figure 25 A schematic diagram illustrating the formation of a first metal seed layer and a second metal seed layer in another fabrication method of a heterojunction solar cell provided in this application embodiment;

[0173] Figure 26 This is a schematic diagram illustrating the formation of a patterned first mask material layer and insulating adhesive in another fabrication method of a heterojunction solar cell provided in this application embodiment;

[0174] Figure 27 This is a schematic diagram of another structure of the heterojunction battery provided in the embodiments of this application.

[0175] Explanation of icon numbers:

[0176] 100. Heterojunction solar cell; 101. Substrate;

[0177] 10. Substrate;

[0178] 21. First intrinsic silicon layer; 22. Second intrinsic silicon layer; 31. First doped layer; 32. Second doped layer; 41. First transparent conductive layer; 42. Second transparent conductive layer; 50. Protective layer; 500. Protective material layer; 61. First metal seed layer; 610. First metal seed material layer; 62. Second metal seed layer; 620. Second metal seed material layer; 71. First mask material layer; 72. Insulating adhesive; 73. Electrode protective layer; 81. First electroplating electrode; 82. Second electroplating electrode;

[0179] F, First surface; S, Second surface; C, Side surface; W, Isolation zone; Z, Metal contact zone; Detailed Implementation

[0180] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0181] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0182] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0183] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0184] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0185] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0186] The following description, in conjunction with the accompanying drawings, illustrates the heterojunction solar cell, its fabrication method, and photovoltaic module according to embodiments of this application.

[0187] Figure 1 This is a schematic diagram of the structure of a heterojunction battery provided in an embodiment of this application. Figure 2 This is a schematic diagram of another structure of a heterojunction battery provided in an embodiment of this application. Figures 3-7 This is a schematic diagram of other structural forms of heterojunction batteries provided in the embodiments of this application.

[0188] It should be noted that the accompanying drawings of this application only illustrate the structure of one corner of the heterojunction solar cell 100 in a longitudinal sectional view along the thickness direction. The same applies to other parts of the heterojunction solar cell 100 not shown in the sectional view, and will not be described further here. Furthermore, since only one corner is shown in these drawings, only a schematic diagram of the film structure on one side of the heterojunction solar cell 100 is displayed. The film structure covering at least some of the other sides of the heterojunction solar cell 100 is the same, and will not be described further here.

[0189] Reference Figures 1-7 The heterojunction solar cell 100 provided in this application embodiment includes: a substrate 10, a first intrinsic silicon layer 21, a first doped layer 31, a first transparent conductive layer 41, a protective layer 50, and a first electroplated electrode 81.

[0190] A first intrinsic silicon layer 21 and a first doped layer 31 are sequentially stacked on the first surface F of the substrate 10. A first transparent conductive layer 41 and a protective layer 50 are stacked on the side of the first doped layer 31 facing away from the substrate 10. The first transparent conductive layer 41 covers a portion of the first surface F, and the protective layer 50 completely covers the first surface F. A first electroplating electrode 81 is located on the side of the protective layer 50 facing away from the substrate 10 and is electrically connected to the first transparent conductive layer 41. The first surface F includes an isolation region W not covered by the first transparent conductive layer 41, and a portion of the structure of the protective layer 50 is stacked on the corresponding isolation region W of the first doped layer 31.

[0191] By setting a protective layer 50, a portion of the protective layer 50 is stacked on the corresponding isolation region W of the first doped layer 31. The first electroplating electrode 81 is located on the side of the protective layer 50 facing away from the substrate 10. Therefore, the formation step of the protective layer 50 is performed before the first electroplating electrode 81. During the electroplating process to form the first electroplating electrode 81, the portion of the corresponding isolation region W of the first doped layer 31 is protected by the protective layer 50 and is not eroded by the plating solution. The surface structure of the portion of the corresponding isolation region W of the first doped layer 31 will not have defects. Compared with the situation in related technologies where the first doped layer 31 is partially etched away, resulting in insufficient lateral conductivity and poor carrier collection ability, the lateral conductivity and carrier collection ability of the first doped layer 31 are not affected, thus effectively avoiding the decrease in battery efficiency caused by the corrosion and damage of the first doped layer 31. Furthermore, since the protective layer 50 is stacked on the portion of the first doped layer 31 corresponding to the isolation region W, the passivation ability of the first doped layer 31 is also improved, thereby improving the efficiency of the heterojunction battery 100. Furthermore, the protective layer 50 completely covers the first surface F, which can further enhance the back reflection effect on one side of the first surface F.

[0192] Additionally, it should be noted that the term "coverage" mentioned in the embodiments of this application refers to the size relationship of the set area. For example, one structure covers another structure. The "covered portion" refers to the overlapping portion generated when one structure is projected onto the other structure along the stacking direction of the two structures. It does not limit whether the two structures are in direct contact. For example, if the first transparent conductive layer 41 covers a part of the first surface F, it means that the orthographic projection of the first transparent conductive layer 41 on the first surface F is only located in a local area of ​​the first surface F. In fact, at least the first intrinsic silicon layer 21 and the first doped layer 31 are between the first transparent conductive layer 41 and the first surface F, and the first transparent conductive layer 41 and the first surface F will not be in direct contact. If the protective layer 50 completely covers the first surface F, it means that the orthographic projection of the protective layer 50 on the first surface F coincides with the first surface F. In fact, at least the first intrinsic silicon layer 21 and the first doped layer 31 are between the protective layer 50 and the first surface F, and the protective layer 50 and the first surface F will not be in direct contact.

[0193] In this embodiment, the substrate 10 further includes a second surface S disposed opposite to the first surface F, and a side surface C adjacent to the first surface F and the second surface S. The first intrinsic silicon layer 21 and the first doped layer 31 are sequentially stacked on the first surface F of the substrate 10, meaning that the first intrinsic silicon layer 21 is stacked on the first surface F, and the first doped layer 31 is stacked on the surface of the first intrinsic silicon layer 21 that is away from the substrate 10.

[0194] The first transparent conductive layer 41 and the protective layer 50 are stacked on the side of the first doped layer 31 facing away from the substrate 10, meaning that the first transparent conductive layer 41 and the protective layer 50 are stacked on top of each other. For example, they can be stacked as follows: Figure 1 , Figure 2 , Figure 3 As shown, a first transparent conductive layer 41 is stacked on the surface of the first doped layer 31 facing away from the substrate 10, and a protective layer 50 is stacked on the surface of the first transparent conductive layer 41 facing away from the substrate 10. In some other embodiments, it may also be as follows... Figure 4a , Figure 4b , Figure 5 , Figure 6 , Figure 7 As shown, the protective layer 50 is stacked on the surface of the first doped layer 31 away from the substrate 10, and the first transparent conductive layer 41 is stacked on the surface of the protective layer 50 away from the substrate 10.

[0195] The first electroplated electrode 81 is located on the side of the protective layer 50 facing away from the substrate 10 and is electrically connected to the first transparent conductive layer 41. The first electroplated electrode 81 is an electrode formed by an electroplating process.

[0196] As previously described, the first transparent conductive layer 41 covers a portion of the first surface F, which includes an isolation region W not covered by the first transparent conductive layer 41. This means that when viewed from the first surface F side of the heterojunction cell 100, a portion of the first surface F is not obscured by the first transparent conductive layer 41 and is exposed from it. In other words, when the first transparent conductive layer 41 is projected orthogonally onto the first surface F, the isolation region W is the portion of the first surface F that does not overlap with the projection of the first doped layer 31. A portion of the protective layer 50 is stacked on the corresponding isolation region W of the first doped layer 31. Combined with the fact that the protective layer 50 completely covers the first surface F, the protective layer 50 can completely cover the corresponding isolation region W of the first doped layer 31.

[0197] In some embodiments, each portion on the outer contour edge of the first transparent conductive layer 41 is spaced from the edge of the first surface F to define an annular isolation region W on the first surface F.

[0198] The isolation region W is the area on the first surface F of the heterojunction battery 100. The uncoated area formed by the first transparent conductive layer 41 during the coating process due to the shielding of the carrier plate is directly opposite the isolation region W, and its width is generally between 0.2 mm and 1 mm. The protective layer 50 covers the portion of the first doped layer 31 corresponding to the isolation region W. On the one hand, it prevents the sputtered material during the formation of the first metal seed layer 61 (described later) from directly depositing onto the surface of the first doped layer 31, affecting the battery performance and reliability. On the other hand, it can effectively protect the exposed surface of the first doped layer 31 from damage caused by the wet chemical solution during the post-electroplating process.

[0199] In the embodiments of this application, reference is made to Figures 1-7 The heterojunction solar cell 100 further includes a second intrinsic silicon layer 22, a second doped layer 32, and a second transparent conductive layer 42 sequentially stacked on the second surface S of the substrate 10. The doping type of the second doped layer 32 is opposite to that of the first doped layer 31. Additionally, the heterojunction solar cell 100 includes a second electroplating electrode 82, which is disposed on one side of the second surface S of the substrate 10 and is electrically connected to the second transparent conductive layer 42.

[0200] In this embodiment, the second intrinsic silicon layer 22, the second doped layer 32, and the second transparent conductive layer 42 are all configured to cover at least a portion of the second surface S and the side surface C of the substrate 10. Alternatively, in some other embodiments, at least one of the second intrinsic silicon layer 22, the second doped layer 32, and the second transparent conductive layer 42 may only cover the second surface S. Similarly, the first intrinsic silicon layer 21 and the first doped layer 31 are both configured to cover at least a portion of the first surface F and the side surface C of the substrate 10. Alternatively, in some other embodiments, at least one of the first intrinsic silicon layer 21 and the first doped layer 31 may only cover the first surface F.

[0201] For example, such as Figures 1-7 As shown, in one possible implementation, a first intrinsic silicon layer 21 covers at least a portion of the first surface F and the side surface C. A second intrinsic silicon layer 22 covers at least a portion of the second surface S and the side surface C, and a portion of the structure of the second intrinsic silicon layer 22 is stacked onto the side of the first intrinsic silicon layer 21 facing away from the substrate 10. A second doped layer 32 covers at least a portion of the second surface S and the side surface C, and a portion of the structure of the second doped layer 32 is stacked onto the side of the first intrinsic silicon layer 21 facing away from the substrate 10. A first doped layer 31 covers at least a portion of the first surface F and the side surface C, and a portion of the structure of the first doped layer 31 is stacked onto the side of the second doped layer 32 facing away from the substrate 10. It is understood that the stacking relationship between the various film layers is not limited to this and can be configured according to actual needs.

[0202] Furthermore, continue to refer to Figures 1-7The heterojunction solar cell 100 further includes a first metal seed layer 61 and a second metal seed layer 62. The first metal seed layer 61 is stacked on the surface of the first electroplating electrode 81 facing the substrate 10, and the second metal seed layer 62 is stacked on the surface of the second electroplating electrode 82 facing the substrate 10. This arrangement facilitates the formation of the first electroplating electrode 81 and the second electroplating electrode 82 during the electroplating process.

[0203] Furthermore, the heterojunction solar cell 100 also includes an electrode protective layer 73. The electrode protective layer 73 located on the first surface F side is stacked on the surface of the first electroplated electrode 81 facing away from the substrate 10, and the electrode protective layer 73 located on the second surface S side is stacked on the surface of the second electroplated electrode 82 facing away from the substrate 10. The electrode protective layer 73 may be, for example, a chemical plating protective layer.

[0204] In this embodiment, the substrate 10 is a crystalline silicon wafer, N-type or P-type doped, with the first surface F being a backlight surface and having a textured structure thereon, or the first surface F being a polished structure and the second surface S being a light-receiving surface and having a textured structure thereon.

[0205] The first intrinsic silicon layer 21 contains at least one of elements such as oxygen, carbon, and nitrogen, and is amorphous or microcrystalline, predominantly amorphous. In some embodiments, the first intrinsic silicon layer 21 may completely cover the first surface F and the side surface C, and may partially extend to the second surface S. Alternatively, the first intrinsic silicon layer 21 may only cover the first surface F and the side surface C. Or, the first intrinsic silicon layer 21 may only cover the first surface F.

[0206] The first doped layer 31 is N-type or P-type doped. The first doped layer 31 contains at least one of the elements oxygen, carbon, and nitrogen, and can be amorphous or microcrystalline, predominantly microcrystalline. The first doped layer 31 can completely cover the first surface F and the side surface C, and can partially extend to the second surface S. Alternatively, the first doped layer 31 can only cover the first surface F and the side surface C.

[0207] The first transparent conductive layer 41 comprises a composite film structure consisting of one or more different transparent conductive film layers stacked together. The transparent conductive film layer may be, for example, one of ITO, IMO, AZO, SCOT, or SnOx.

[0208] The first metal seed layer 61 includes metals or metal alloys such as copper, aluminum, nickel, and titanium, with a thickness of 10-200 nm.

[0209] The first electroplating electrode 81 comprises a low-cost metal such as copper or a nickel-copper alloy, and the thickness of the first electroplating electrode 81 can be 5-20 μm.

[0210] The second intrinsic silicon layer 22 contains at least one of elements such as oxygen, carbon, and nitrogen, and is amorphous or microcrystalline, predominantly amorphous. In some embodiments, the second intrinsic silicon layer 22 can completely cover the second surface S and the side surface C, and can partially extend to the first surface F. Alternatively, the second intrinsic silicon layer 22 can only cover the second surface S and the side surface C. Or, the second intrinsic silicon layer 22 can only cover the second surface S.

[0211] The second doped layer 32 is N-type or P-type doped, and the doping type of the second doped layer 32 is opposite to that of the first doped layer 31. The second doped layer 32 contains at least one of the elements such as oxygen, carbon, and nitrogen, and can be amorphous or microcrystalline, predominantly microcrystalline. The second doped layer 32 can completely cover the second surface S and the side surface C, and can partially extend the structure to the first surface F. Alternatively, the second doped layer 32 can only cover the second surface S and the side surface C. Alternatively, the second doped layer 32 can only cover the second surface S.

[0212] The second transparent conductive layer 42 comprises a composite film structure consisting of one or more different transparent conductive film layers stacked together. The transparent conductive film layer may be, for example, one of ITO, IMO, AZO, SCOT, or SnOx.

[0213] The second electroplating electrode 82 includes a low-cost metal such as copper or a nickel-copper alloy, and the thickness of the first electroplating electrode 81 can be 5-20 μm.

[0214] The second metal seed layer 62 includes metals or metal alloys such as copper, aluminum, nickel, and titanium, with a thickness of 10-200 nm.

[0215] The electrode protective layer 73 includes at least one of nickel, tin, silver, etc.

[0216] In this embodiment of the application, the range of the protective layer 50 can be, for example, as follows: Figure 2 , Figure 4a , Figure 5 , Figure 7 As shown, the protective layer 50 completely covers the first surface F and at least a portion of the side surface C of the substrate 10. Alternatively, in some other embodiments, it may be as follows... Figure 1 , Figure 6 As shown, the protective layer 50 completely covers the first surface F, and the outer contour edge of the protective layer 50 coincides with the edge of the first surface F. That is, the protective layer 50 is entirely located on one side of the first surface F, and there is no portion extending to the side C.

[0217] In this embodiment of the application, as described above, the first transparent conductive layer 41 and the protective layer 50 are stacked on the side of the first doped layer 31 away from the substrate 10, and their stacking order can be interchanged.

[0218] Reference Figure 1 , Figure 2 , Figure 3 In one possible implementation, a first transparent conductive layer 41 is disposed on the surface of the first doped layer 31 facing away from the substrate 10. A protective layer 50 is located on the side of the first transparent conductive layer 41 facing away from the substrate 10. A first electroplating electrode 81 is disposed on the protective layer 50 and electrically connected to the first transparent conductive layer 41 through the protective layer 50. In this configuration, the first transparent conductive layer 41 is first formed on the first doped layer 31, and then the protective layer 50 is deposited and formed on the first transparent conductive layer 41.

[0219] Furthermore, referring to Figure 1 The protective layer 50 completely covers the first surface F, and the outer contour edge of the protective layer 50 coincides with the edge of the first surface F. At this time, a portion of the protective layer 50 is stacked on the surface of the first transparent conductive layer 41 facing away from the substrate 10, and another portion of the protective layer 50 is stacked on the surface of the portion of the first doped layer 31 corresponding to the isolation region W. This arrangement of the protective layer 50 can completely cover and protect the exposed surface of the first doped layer 31, and it is not placed on the side C, which is beneficial to improving battery efficiency.

[0220] Reference Figure 2 In other embodiments, the protective layer 50 may completely cover the first surface F and at least a portion of the side surface C of the substrate 10. The coverage area of ​​the protective layer 50 over the side surface C can be set according to actual needs; for example, it may completely cover the side surface C or only cover the portion of the side surface C adjacent to the first surface F.

[0221] exist Figure 2 In the example, the second transparent conductive layer 42 covers at least a portion of the second surface S and the side surface C of the substrate 10, and a portion of the protective layer 50 is stacked onto the side of the second transparent conductive layer 42 facing away from the substrate 10. The coverage area of ​​the second transparent conductive layer 42 on the side surface C can be set according to actual needs; for example, it can cover the portion of the side surface C adjacent to the second surface S, or it can completely cover the side surface C. In this case, Figure 3 In one example, the protective layer 50 may partially cover the first surface F, for example, the outer contour edge of the protective layer 50 may coincide with the edge of the first electroplated electrode 81. Thus, the protective layer 50 is actually stacked between the first transparent conductive layer 41 and the first electroplated electrode 81. In the case where the heterojunction cell 100 also includes a first metal seed layer 61, the protective layer 50 is stacked between the first metal seed layer 61 and the first transparent conductive layer 41.

[0222] exist Figure 1 , Figure 2 , Figure 3In the example, the protective layer 50 is sandwiched between the first transparent conductive layer 41 and the first electroplated electrode 81. To prevent the protective layer 50 from affecting the carrier collection efficiency, the protective layer 50 can be made of a conductive material. For example, the protective layer 50 includes a transparent conductive oxide layer, which includes at least one of ITO, IMO, AZO, SCOT, and SnOx. Further, the thickness of the protective layer 50 is 5-15 nm. The material of the protective layer 50 is preferably SnOx, because the film containing SnOx has better chemical resistance and lower conductivity, which can effectively serve as a protective layer while also preventing short circuits that may occur when the protective layer 50 is in contact with both the first transparent conductive layer 41 and the second transparent conductive layer 42.

[0223] Furthermore, the protective layer 50 is a single-layer structure or a composite layer structure consisting of multiple layers of sub-films made of different materials. The single-layer structure may include one of ITO, IMO, AZO, SCOT, and SnOx. The film materials of each sub-film in the composite layer structure may be different, and the sub-films may be one of ITO, IMO, AZO, SCOT, and SnOx respectively.

[0224] In the embodiments of this application, reference is made to Figure 4a , Figure 4b , Figure 5 , Figure 6 , Figure 7 In another possible implementation, the protective layer 50 is disposed on the surface of the first doped layer 31 facing away from the substrate 10. The first transparent conductive layer 41 is located on the side of the protective layer 50 facing away from the substrate 10. In this case, the first electroplating electrode 81 is disposed on the first transparent conductive layer 41.

[0225] Furthermore, referring to Figure 6 The protective layer 50 completely covers the first surface F, and the outer contour edge of the protective layer 50 coincides with the edge of the first surface F. Thus, the protective layer 50 is only disposed on one side of the first surface F and not on the side surface C. The protective layer 50 can insulate against the second transparent conductive layer 42 extending to the side surface, further improving the battery efficiency of the heterojunction cell 100. It is understood that even if the protective layer 50 extends to the side surface C and simultaneously contacts the first transparent conductive layer 41 and the second transparent conductive layer 42, the resulting efficiency loss would be far less than the efficiency gain brought to the heterojunction cell 100 by the presence of the protective layer 50. In this embodiment, the protective layer 50 is actually made of a material with high sheet resistance, effectively avoiding this efficiency loss.

[0226] And in Figure 4a , Figure 5 , Figure 7In the example, the protective layer 50 completely covers the first surface F and covers at least a portion of the side surface C of the substrate 10.

[0227] Among them, reference Figure 4a and Figure 7 In one example, the second doped layer 32 covers at least a portion of the second surface S and the side surface C, the first doped layer 31 covers at least a portion of the first surface F and the side surface C, and a portion of the structure of the first doped layer 31 is stacked onto the side of the second doped layer 32 opposite to the substrate 10.

[0228] The protective layer 50 is at least partially stacked on the surface of the first doped layer 31 facing away from the substrate 10. The second transparent conductive layer 42 covers at least a portion of the second surface S and the side surface C of the substrate 10, with a portion of the structure of the second transparent conductive layer 42 stacked onto the side of the protective layer 50 facing away from the substrate 10. That is, on the side surface C, a portion of the structure of the second transparent conductive layer 42 is stacked on the second doped layer 32, and a portion of the structure is stacked on the protective layer 50. The portion of the second transparent conductive layer 42 on the side surface C may completely cover the side surface C, or may only cover the portion of the side surface C adjacent to the second surface S.

[0229] exist Figure 4a In the example, the portion of the protective layer 50 covering side C has a part stacked onto the first doped layer 31 and another part stacked onto the second doped layer 32. That is, the protective layer 50 extends to the second doped layer 32.

[0230] And in Figure 7 In the example, the outer contour edge of the protective layer 50 coincides with the outer contour edge of the first doped layer 31. That is, the area of ​​the protective layer 50 overlaps with the area of ​​the first doped layer 31. In this case, the first doped layer 31 may include an oxygen-free microcrystalline host layer, and the protective layer 50 is an oxygen-doped amorphous silicon layer. This gives the protective layer 50 better corrosion resistance. In this case, the thickness of the protective layer 50 is no greater than 3 nm. Figure 7 In the example, the protective layer 50 can be formed after the formation of the first doped layer 31, so as to be stacked on the surface of the protective layer 50.

[0231] And in Figure 4b In the example, the protective layer 50 partially covers the first surface F, and its area on one side of the first surface F is the same as the area of ​​the first transparent conductive layer 41. The protective layer 50 also covers at least a portion of the side surface C of the substrate 10. That is, with Figure 4a In contrast, it is obtained by removing the portion of the protective layer 50 located on the isolation zone W.

[0232] Furthermore, the first doped layer 31 also includes an oxygen-containing microcrystalline sublayer, which is stacked between the first intrinsic silicon layer 21 and the oxygen-free microcrystalline host layer. In this way, during the formation of the first doped layer 31, the oxygen-containing microcrystalline sublayer can serve as an incubation layer, and the oxygen-free microcrystalline host layer is deposited on the oxygen-containing microcrystalline sublayer, which is beneficial for crystallization.

[0233] Reference Figure 5 The second transparent conductive layer 42 covers at least a portion of the second surface S and the side surface C of the substrate 10, and a portion of the structure of the protective layer 50 is stacked onto the side of the second transparent conductive layer 42 facing away from the substrate 10. That is, on the side surface C, the second transparent conductive layer 42 is inside the heterojunction cell 100, and the protective layer 50 is on the outside.

[0234] In this embodiment of the application, for Figure 4a , Figure 5 , Figure 6 For example, the protective layer 50 comprises a transition metal oxide, and the polarity of the protective layer 50 is the same as that of the first doped layer 31.

[0235] Alternatively, the protective layer 50 may include a dielectric passivation layer.

[0236] Alternatively, the protective layer 50 may include a transparent conductive oxide layer.

[0237] In the example where the protective layer 50 includes a transition metal oxide, the transition metal oxide is an undoped carrier transport layer. When the first doped layer 31 is p-type doped, the polarity of the transition metal oxide is also p-type. The protective layer 50 may include at least one of MO3, V2O5, CrO3, NiO, Cu2O, CoO, and ReO3. When the first doped layer 31 is n-type doped, the polarity of the transition metal oxide is also n-type. The protective layer 50 may include at least one of TiO2, ZnO, Ta2O5, Nb2O5, CdO, MgO, BaO, SnO2, LiF, TiN, and TaN. When the protective layer 50 includes a transition metal oxide, the thickness of the protective layer 50 may be 5-30 nm. It is understood that while the protective layer 50 protects the corresponding isolation region W of the first doped layer 31, it also provides field passivation due to its similar polarity to the first doped layer 31.

[0238] In the example where the protective layer 50 includes a dielectric passivation layer, the material of the dielectric passivation layer can be SiOx, AlOx, etc., and the thickness of the protective layer 50 can be 0.5-3nm. In this case, the protective layer 50 can effectively passivate the surface of the first doped layer 31 while protecting the corresponding isolation region W of the first doped layer 31. Because the thickness is set relatively thin, carriers can effectively tunnel through.

[0239] In an example where the protective layer 50 includes a transparent conductive oxide layer, the transparent conductive oxide layer may include, for example, SnOx, ITO, IMO, SCOT, AZO, etc. In this case, the thickness of the protective layer 50 can be 5-15 nm. Exemplarily, the material of the protective layer 50 can be selected to better match the work function of the first doped layer 31. Alternatively, the work function can be adjusted through the deposition process. For example, if the first doped layer 31 is p-type doped, a TCO material with a high work function can be selected as the protective layer 50, or the work function of the protective layer 50 can be increased by adjusting the oxygen content during the TCO material deposition process, etc., so that it has a smaller contact resistance with the p-type first doped layer 31.

[0240] In the embodiments of this application, reference is made to Figure 27 The protective layer 50 is positioned on the first surface F side, covering only the corresponding isolation region W of the first doped layer 31, and also covers the side surface C. The structure and material of each film layer, such as the first intrinsic silicon layer 21, the first doped layer 31, the first transparent conductive layer 41, the second intrinsic silicon layer 22, the second doped layer 32, and the second transparent conductive layer 42, are the same as described above and have been discussed in detail previously, so they will not be repeated here.

[0241] At this time, the protective layer 50 may include materials such as thermosetting / thermoplastic resins, UV-curable resins, and nanomaterials. For example, a coating of silicone resin, epoxy resin, or nano-silica may be used, which can be achieved by spraying, spin coating, or other methods, thereby covering the corresponding isolation region W of the first doped layer 31 and the side C to form a protective layer. This protective layer 50 can have good chemical resistance and a certain back reflection effect, which can improve the current of the heterojunction cell. Figure 8 This is a schematic flowchart illustrating the fabrication method of a heterojunction solar cell provided in an embodiment of this application.

[0242] Figures 9-13 This diagram illustrates the various stages of fabrication of a heterojunction solar cell in the method provided in this application. Figures 9-13 Reference for the fabrication method of heterojunction solar cells. Figure 1 , Figure 2 , Figure 3 Examples.

[0243] Figures 14-17 This diagram illustrates the various stages of a heterojunction solar cell fabrication method provided in this application embodiment. Utilizing... Figures 14-17 Reference for the fabrication method of heterojunction solar cells. Figure 4a Examples.

[0244] Figures 18-21This diagram illustrates the various stages of a heterojunction solar cell fabrication method provided in this application embodiment. Utilizing... Figures 18-21 Reference for the fabrication method of heterojunction solar cells. Figure 5 , Figure 6 , Figure 22 Examples.

[0245] Figures 23-26 This diagram illustrates the various stages of a heterojunction solar cell fabrication method provided in this application embodiment. Utilizing... Figures 23-26 Reference for the fabrication method of heterojunction solar cells. Figure 7 Examples.

[0246] Reference Figure 8 , Figures 9-26 This application also provides a method for fabricating a heterojunction solar cell, the method comprising:

[0247] S10. A substrate 101 is provided, the substrate 101 including a substrate 10, and a first intrinsic silicon layer 21 and a first doped layer 31 sequentially stacked on the first surface F of the substrate 10.

[0248] S20. A first transparent conductive layer 41 and a protective material layer 500 are formed on the side of the first doped layer 31 away from the substrate 10. The first transparent conductive layer 41 covers a portion of the first surface F, and the first surface F includes an isolation region W not covered by the first transparent conductive layer 41. The protective material layer 500 completely covers the first surface F, and a portion of the structure of the protective material layer 500 is stacked on the corresponding isolation region W of the first doped layer 31.

[0249] S30. A first electroplating electrode 81 is formed on the side of the protective material layer 500 away from the substrate 10 by electroplating. The first electroplating electrode 81 is electrically connected to the first transparent conductive layer 41.

[0250] By forming a protective material layer 500, a portion of the protective material layer 500 is stacked on the corresponding isolation region W of the first doped layer 31. A first electroplating electrode 81 is formed on the side of the protective material layer 500 facing away from the substrate 10 through electroplating. During the electroplating process of the first electroplating electrode 81, the portion of the corresponding isolation region W of the first doped layer 31 is protected by the protective material layer 500 and is therefore not corroded by the plating solution. The surface structure of the portion of the corresponding isolation region W of the first doped layer 31 does not develop defects. Compared to related technologies where the first doped layer is partially etched away, resulting in insufficient lateral conductivity and poor carrier collection ability, the lateral conductivity and carrier collection ability of the first doped layer 31 are not affected. This effectively avoids the decrease in battery efficiency caused by corrosion and damage to the first doped layer 31. Furthermore, the presence of the protective material layer 500 on the portion of the first doped layer 31 corresponding to the isolation region W also improves the passivation ability of the first doped layer 31, thereby improving the efficiency of the heterojunction battery 100. Furthermore, the protective material layer 500 completely covers the first surface F, which can further enhance the anti-reflection effect on one side of the first surface F.

[0251] In this embodiment of the application, in step S20, the step of forming the protective material layer 500:

[0252] You can refer to Figure 11 , Figure 14 , Figure 19 , Figure 23 The second surface S side of the substrate 101 is oriented towards the bearing frame of the carrier plate (not shown). A protective material layer 500 is formed on the side of the first doped layer 31 facing away from the substrate 10.

[0253] The protective material layer 500 completely covers the first surface F and at least a portion of the side surface C of the substrate 10. Alternatively, the protective material layer 500 completely covers the first surface F, and the outer contour edge of the protective material layer 500 coincides with the edge of the first surface F.

[0254] This configuration ensures that the protective material layer 500 can fully cover the first surface F without leaving any uncovered areas, particularly covering the surface of the corresponding isolation region W of the first doped layer 31. During this process, the protective material layer 500 also forms on the side surface C.

[0255] Furthermore, in step S20, the step of forming the first transparent conductive layer 41:

[0256] You can refer to Figure 10 , Figure 15 , Figure 19 , Figure 24The first surface F of the substrate 101 is oriented towards the support frame of the carrier plate. A first transparent conductive layer 41 is formed on the side of the first doped layer 31 facing away from the substrate 10, and the formation position of the first transparent conductive layer 41 corresponds to the hollow portion of the support frame. At this time, the isolation region W on the first surface F is also the part of the area facing the support frame of the carrier plate, and generally the isolation region W appears as a square when viewed from the first surface F.

[0257] Combination Figure 10 and Figure 11 In step S20, the step of forming a first transparent conductive layer 41 and a protective material layer 500 stacked on the surface of the first doped layer 31 facing away from the substrate 10 specifically includes:

[0258] A first transparent conductive layer 41 is formed on the surface of the first doped layer 31 away from the substrate 10.

[0259] A protective material layer 500 is formed on the surface of the first transparent conductive layer 41 that is away from the substrate 10.

[0260] Furthermore, referring to Figure 9 and Figure 10 The step of forming the first transparent conductive layer 41 on the surface of the first doped layer 31 away from the substrate 10 specifically includes:

[0261] The first surface F side of the substrate 101 is oriented toward the support frame of the carrier plate, and the portion of the first doped layer 31 located on the first surface F side is supported on the support frame.

[0262] In the portion of the first doped layer 31 covering one side of the first surface F, the area not obscured by the bearing frame forms a first transparent conductive layer 41.

[0263] Furthermore, referring to Figure 11 The step of forming a protective material layer 500 on the surface of the first transparent conductive layer 41 facing away from the substrate 10 specifically includes:

[0264] The second surface S side of the substrate 101 is supported by the support frame of the carrier plate.

[0265] A protective material layer 500 is formed on the surface of the first transparent conductive layer 41 facing away from the substrate 10. The protective material layer 500 is partially stacked on the surface of the first transparent conductive layer 41 facing away from the substrate 10, and partially stacked on the surface of the portion of the first doped layer 31 corresponding to the isolation region W. This arrangement facilitates the protective material layer 500 completely covering one side of the first surface F. In some embodiments, the protective material layer 500 may also cover the entire side surface C.

[0266] In the embodiments of this application, reference is made to Figure 9 , Figure 10 , Figure 11 The substrate 101 further includes a second intrinsic silicon layer 22 and a second doped layer 32 sequentially stacked on the second surface S of the substrate 10, with the second surface S opposite to the first surface F. The process includes, after the step of forming the first transparent conductive layer 41 and before the step of forming the protective material layer 500, the following steps:

[0267] A second transparent conductive layer 42 is formed on the side of the second doped layer 32 facing away from the substrate 10.

[0268] In this embodiment, the second transparent conductive layer 42 covers at least a portion of the second surface S and the side surface C of the substrate 10. This can be achieved as follows: Figure 11 As shown, the protective material layer 500 also covers at least a portion of the side surface C, and a portion of the structure of the protective material layer 500 is stacked onto the side of the second transparent conductive layer 42 facing away from the substrate 10. Alternatively, in some other embodiments, the outer contour edge of the protective material layer 500 may coincide with the edge of the first surface F. The coincidence of the outer contour edge of the protective material layer 500 with the edge of the first surface F means that the entire protective material layer 500 is located on one side of the first surface F.

[0269] In this embodiment of the application, for Figures 4a-7 The heterojunction cell 100 with the structure shown can first form a protective material layer 500, and then form a first transparent conductive layer 41.

[0270] In specific implementation, refer to Figure 14 and Figure 15 , Figure 19 , Figure 23 and Figure 24 In step S20, the step of forming a first transparent conductive layer 41 and a protective material layer 500 stacked on the surface of the first doped layer 31 facing away from the substrate 10 specifically includes:

[0271] A protective material layer 500 is formed on the surface of the first doped layer 31 away from the substrate 10.

[0272] A first transparent conductive layer 41 is formed on the surface of the protective material layer 500 away from the substrate 10.

[0273] First refer to Figure 4a as well as Figures 14-17 , Figure 7 as well as Figures 23-26 The described example includes the step of forming a protective material layer 500 on the surface of the first doped layer 31 away from the substrate 10, which includes:

[0274] A protective material layer 500 is formed on the side of the first doped layer 31 facing away from the substrate 10. The protective material layer 500 covers at least a portion of the first surface F and the side surface C. The protective material layer 500 may cover the entire side surface C or cover the area of ​​the side surface C adjacent to the first surface F.

[0275] It is understandable that in this step, the protective material layer 500 can be formed with one side of the second surface S of the substrate 101 supported by the support frame of the carrier plate. This facilitates the formation of a protective material layer 500 that covers the entire surface of the first surface F.

[0276] Furthermore, referring to Figure 15 and Figure 24 The step of forming a first transparent conductive layer 41 on the surface of the protective material layer 500 facing away from the substrate 10 specifically includes:

[0277] The first surface F side of the substrate 101 is oriented toward the bearing frame of the carrier plate, and the portion of the protective material layer 500 located on the first surface F side is supported by the bearing frame.

[0278] In the portion of the protective material layer 500 covering one side of the first surface F, a first transparent conductive layer 41 is formed in the area not obscured by the bearing frame.

[0279] Furthermore, as previously described, the substrate 101 also includes a second intrinsic silicon layer 22 and a second doped layer 32 sequentially stacked on the second surface S.

[0280] Continue to refer to Figure 15 and Figure 24 After the step of forming the first transparent conductive layer 41 on the surface of the protective material layer 500 facing away from the substrate 10, the method further includes:

[0281] A second transparent conductive layer 42 is formed on the surface of the second doped layer 32 facing away from the substrate 10. The second transparent conductive layer 42 covers a portion of the second surface S and the side surface C, and is stacked onto the protective material layer 500. The second transparent conductive layer 42 may cover the entire side surface C, or it may only cover the area of ​​the side surface C adjacent to the second surface S.

[0282] Reference Figure 4a and Figure 11 In the step of forming a protective material layer 500 on the surface of the first doped layer 31 away from the substrate 10: the protective material layer 500 covers at least a portion of the first surface F and the side surface C, and the protective material layer 500 is stacked onto the side of the second doped layer 32 away from the substrate 10.

[0283] And in Figure 7 In the example, combined Figure 23In the step of forming a protective material layer 500 on the surface of the first doped layer 31 away from the substrate 10:

[0284] The protective material layer 500 covers at least a portion of the first surface F and the side surface C. The outer contour edge of the protective material layer 500 coincides with the outer contour edge of the first doped layer 31. That is, the protective material layer 500 and the first doped layer 31 have the same film layer coverage.

[0285] Continue to refer to Figure 7 and Figure 23 The first doped layer 31 includes an oxygen-free microcrystalline host layer (not shown).

[0286] The steps for forming the protective material layer 500 include:

[0287] An oxygen-doped amorphous silicon layer is formed on the surface of the first doped layer 31 away from the substrate 10 as a protective material layer 500. The oxygen-doped amorphous silicon layer has the same doping type as the first doped layer 31. Since the oxygen-doped amorphous silicon layer has better resistance to chemical corrosion, it provides better protection for the first doped layer 31.

[0288] In some embodiments, the first doped layer 31 further includes an oxygen-containing microcrystalline sublayer, which is stacked between the first intrinsic silicon layer 21 and the oxygen-free microcrystalline host layer.

[0289] Furthermore, the oxygen-containing microcrystalline sublayer and the oxygen-free microcrystalline host layer included in the first doped layer 31 are formed through the following steps:

[0290] Hydrogen, silane, diborane, and carbon dioxide gases are introduced into the reaction chamber, wherein the molar volume ratio of hydrogen, silane, diborane, and carbon dioxide gases is 300:1:0.005:0.2-600:1:0.01:0.5, and the reaction pressure in the reaction chamber is 4-6 mbar, so as to form an oxygen-containing microcrystalline film layer on the surface of the first intrinsic silicon layer 21 away from the substrate 10.

[0291] Hydrogen, silane, and diborane gases are introduced into the reaction chamber, wherein the molar volume ratio of hydrogen, silane, and diborane gases is 300:1:0.01-500:1:0.04, and the reaction pressure in the reaction chamber is 2-3 mbar, so as to form an oxygen-free microcrystalline host layer on the surface of the oxygen-containing microcrystalline film layer away from the substrate 10.

[0292] Furthermore, the step of forming an oxygen-doped amorphous silicon layer as a protective material layer 500 includes:

[0293] Hydrogen, silane, diborane, and carbon dioxide gases are introduced into the reaction chamber, wherein the molar volume ratio of hydrogen, silane, diborane, and carbon dioxide gases is between 8:1:3:1 and 12:1:5:1.5. The reaction pressure inside the reaction chamber is approximately 2-3 mbar, in order to form an oxygen-doped amorphous silicon layer on the surface of the oxygen-free microcrystalline substrate.

[0294] exist Figure 5 , Figure 6 , Figure 22 In the illustrated heterojunction cell 100, combined with Figures 18-22 The process includes the step of forming a protective material layer 500 on the surface of the first doped layer 31 away from the substrate 10, prior to the step of forming a protective material layer 500.

[0295] A second transparent conductive layer 42 is formed on the surface of the second doped layer 32 facing away from the substrate 10. The second transparent conductive layer 42 covers at least a portion of the second surface S and the side surface C. The second transparent conductive layer 42 may cover the entire side surface C, or it may only cover the area of ​​the side surface C adjacent to the second surface S.

[0296] Furthermore, referring to Figure 19 The step of forming a protective material layer 500 on the surface of the first doped layer 31 away from the substrate 10 specifically includes:

[0297] A protective material layer 500 is formed on the side of the first doped layer 31 away from the substrate 10. The protective material layer 500 completely covers the first surface F and covers at least a portion of the side surface C. The protective material layer 500 is stacked onto the second transparent conductive layer 42.

[0298] In some embodiments, before forming the protective material layer 500, the second surface S side of the substrate 101 can be oriented towards the support frame of the carrier plate, and the second transparent conductive layer 42 can be supported on the support frame. In this way, the formed protective material layer 500 can cover the entire first surface F.

[0299] In some embodiments, the step of forming a first transparent conductive layer 41 on the surface of the protective material layer 500 facing away from the substrate 10 specifically includes:

[0300] The first surface F side of the substrate 101 is oriented toward the bearing frame of the carrier plate, and the portion of the protective material layer 500 located on the first surface F side is supported by the bearing frame.

[0301] In the portion of the protective material layer 500 covering one side of the first surface F, a first transparent conductive layer 41 is formed in the area not obscured by the bearing frame.

[0302] In this embodiment of the application, for Figure 4a , Figure 5 , Figure 6 , Figure 22The illustrated heterojunction solar cell 100 may include a protective material layer 500, which may comprise a transition metal oxide and have the same polarity as the first doped layer 31. Alternatively, the protective material layer 500 may comprise a dielectric passivation layer. Or, the protective material layer 500 may comprise a transparent conductive oxide layer.

[0303] In the example where the protective material layer 500 includes a transition metal oxide, the transition metal oxide is an undoped carrier transport layer. When the first doped layer 31 is p-type doped, the polarity of the transition metal oxide is also p-type. The protective material layer 500 may include at least one of MO3, V2O5, CrO3, NiO, Cu2O, CoO, and ReO3. When the first doped layer 31 is n-type doped, the polarity of the transition metal oxide is also n-type. The protective material layer 500 may include at least one of TiO2, ZnO, Ta2O5, Nb2O5, CdO, MgO, BaO, SnO2, LiF, TiN, and TaN. When the protective material layer 500 includes a transition metal oxide, the thickness of the protective material layer 500 may be 5-30 nm. It is understood that while the protective material layer 500 protects the corresponding isolation region W of the first doped layer 31, it can also provide field passivation due to its similar polarity to the first doped layer 31.

[0304] In the example where the protective material layer 500 includes a dielectric passivation layer, the material of the dielectric passivation layer can be SiOx, AlOx, etc., and the thickness of the protective material layer 500 can be 0.5-3 nm. In this case, the protective material layer 500 can effectively passivate the surface of the first doped layer 31 while protecting the corresponding isolation region W portion of the first doped layer 31. Due to the relatively thin thickness, carriers can effectively tunnel through.

[0305] In an example where the protective material layer 500 includes a transparent conductive oxide layer, the transparent conductive oxide layer may include, for example, SnOx, ITO, IMO, SCOT, AZO, etc. In this case, the thickness of the protective material layer 500 can be 5-15 nm. Exemplarily, the material of the protective material layer 500 can be selected to better match the work function of the first doped layer 31. Alternatively, the work function can be adjusted through the deposition process. For example, if the first doped layer 31 is p-type doped, a TCO material with a high work function is selected as the protective material layer 500, or the work function of the protective material layer 500 can be increased by adjusting the oxygen content during the TCO material deposition process, etc., so that it has a smaller contact resistance with the p-type first doped layer 31.

[0306] In this embodiment of the application, the method for fabricating a heterojunction solar cell further includes:

[0307] A second transparent conductive layer 42 is formed on the surface of the second doped layer 32 away from the substrate 10.

[0308] A second electroplating electrode 82 is formed on one side of the second surface S of the substrate 10 by electroplating.

[0309] In the examples described above, the protective material layer 500 completely covers the first surface F and at least a portion of the side surface C of the substrate 10. Alternatively, the protective material layer 500 only completely covers the first surface F and is not formed on other surfaces.

[0310] In the steps of forming the first electroplating electrode 81 and the second electroplating electrode 82, at least a portion of the protective material layer 500 is removed to form the protective layer 50. For example, as Figure 1 , 3 The heterojunction cell 100 is shown in 6, 22, and 27.

[0311] In the example where the protective material layer 500 is partially removed, it can be as follows: Figure 1 , Figure 6 As shown, the portion of the protective material layer 500 that is removed includes the portion of the protective material layer 500 located on side C. Alternatively, it can be as follows: Figure 22 As shown, the removed portion of the protective material layer 500 includes the portion of the protective material layer 500 covering side C and the portion covering the isolation area W. Alternatively, it can be as follows: Figure 3 As shown, the removed portion of the protective material layer 500 includes the portion of the protective material layer 500 covering one side of the side C, and the portion of the protective material layer 500 corresponding to the non-metallic contact area of ​​the first surface F.

[0312] Of course, the protective material layer 500 may also remain unaffected. In this case, the protective material layer 500 directly forms the protective layer 50, for example... Figure 2 , Figure 4a , Figure 5 , Figure 7 The heterojunction cell 100 shown.

[0313] In the examples shown in the figures above, refer to Figure 12 and Figure 13 , Figure 16 and Figure 17 , Figure 20 and Figure 21 , Figure 25 and Figure 26 The steps of forming the first electroplating electrode 81 and the second electroplating electrode 82 specifically include:

[0314] A first metal seed material layer 610 is formed on one side of the first surface F of the substrate 10, and a second metal seed material layer 620 is formed on the surface of the second transparent conductive layer 42 that is away from the substrate 10. The first metal seed material layer 610 is located on the one that is farther away from the substrate 10, the first transparent conductive layer 41 and the protective material layer 500.

[0315] A first electroplating electrode 81 is formed by electroplating a patterned mask layer on the surface of the first metal seed material layer 610, and a second electroplating electrode 82 is formed by electroplating a patterned mask layer on the surface of the second metal seed material layer 620.

[0316] Remove the mask layer.

[0317] The portion of the first metal seed material layer 610 not covered by the first electroplating electrode 81 is removed to form the first metal seed layer 61, and the portion of the second metal seed material layer 620 not covered by the second electroplating electrode is removed to form the second metal seed layer 62.

[0318] Furthermore, the patterned mask layer is formed by the following steps:

[0319] A patterned first mask material layer 71 is formed on the side of the first metal seed material layer 610 and the second metal seed material layer 620 facing away from the substrate 10. The first mask material layer 71 is cut out at the position corresponding to the metal contact area Z of the first surface F, and also cut out at the position corresponding to the metal contact area Z of the second surface S. Insulating adhesive 72 is coated on the side surface C of the substrate 10. In this way, all surfaces of the substrate 101 are covered, exposing only the positions where the first electroplating electrode 81 and the second electroplating electrode 82 will be formed.

[0320] Furthermore, after removing the portion of the first metal seed material layer 610 not covered by the first electroplating electrode 81 and the portion of the second metal seed material layer 620 not covered by the second electroplating electrode, the method further includes forming an electrode protective layer 73 on the surfaces of the first electroplating electrode 81 and the second electroplating electrode 82. The electrode protective layer 73 may be, for example, a chemical plating protective layer.

[0321] Furthermore, in the steps of removing the portion of the first metal seed material layer 610 not covered by the first electroplating electrode 81, removing the portion of the second metal seed material layer 620 not covered by the second electroplating electrode, and / or forming the electrode protective layer 73, at least a portion of the protective material layer 500 is removed to form the protective layer 50. Since the steps of removing the portion of the first metal seed material layer 610 not covered by the first electroplating electrode 81, removing the portion of the second metal seed material layer 620 not covered by the second electroplating electrode, and / or forming the electrode protective layer 73 are all acidic, if the material of the protective layer 50 is not acid-resistant, the exposed portion of the protective layer 50 may be at least partially removed in these two steps.

[0322] In the embodiments of this application, reference is made to Figure 6 In step S10, the step of providing a substrate 101 specifically includes:

[0323] A first intrinsic silicon layer 21 is formed on the first surface F of the substrate 10, and a second intrinsic silicon layer 22 is formed on the second surface S of the substrate 10.

[0324] A second doped layer 32 is formed on the surface of the second intrinsic silicon layer 22 away from the substrate 10, and a first doped layer 31 is formed on the surface of the first intrinsic silicon layer 21 away from the substrate 10.

[0325] In the above steps, the first intrinsic silicon layer 21 covers at least a portion of the first surface F and the side surface C. The second intrinsic silicon layer 22 covers at least a portion of the second surface S and the side surface C, and a portion of the structure of the second intrinsic silicon layer 22 is stacked onto the side of the first intrinsic silicon layer 21 facing away from the substrate 10. The second doped layer 32 covers at least a portion of the second surface S and the side surface C, and a portion of the structure of the second doped layer 32 is stacked onto the side of the first intrinsic silicon layer 21 facing away from the substrate 10. The first doped layer 31 covers at least a portion of the first surface F and the side surface C, and a portion of the structure of the first doped layer 31 is stacked onto the side of the second doped layer 32 facing away from the substrate 10.

[0326] The following examples illustrate the fabrication method of heterojunction solar cells according to embodiments of this application.

[0327] Example 1

[0328] The method for fabricating a heterojunction solar cell in this embodiment is used to form Figure 1 , Figure 2 , Figure 3 The heterojunction cell 100 is illustrated.

[0329] Methods for fabricating heterojunction solar cells include:

[0330] Step A: Prepare a silicon wafer as substrate 10, clean it, and texturize it. Texturing can be done on both sides, or texturing can be done on the second surface S of substrate 10 while polishing the first surface F of substrate 10. It is understood that, in this embodiment, the texturized structure of the first surface F and / or the second surface S is omitted for ease of observation.

[0331] Step B, refer to Figure 9 A first intrinsic silicon layer 21 is formed on the first surface F of the substrate 10, and a second intrinsic silicon layer 22 is formed on the second surface S of the substrate 10. The first intrinsic silicon layer 21 covers the first surface F and partially covers the side surface C, while the second intrinsic silicon layer 22 covers the second surface S and partially covers the side surface C. A portion of the second intrinsic silicon layer 22 also covers the first intrinsic silicon layer 21. The first intrinsic silicon layer 21 and the second intrinsic silicon layer 22 are generally formed using a plate-type device, thus it is a single-sided film deposition method.

[0332] Step C, continue to refer to Figure 9 A second doped layer 32 is formed on the surface of the second intrinsic silicon layer 22 facing away from the substrate 10, and a first doped layer 31 is formed on the surface of the first intrinsic silicon layer 21 facing away from the substrate 10, thus forming the substrate 101. A portion of the second doped layer 32 is located on one side of the second surface S, and a portion is located on the side surface C. The portion of the second doped layer 32 located on side surface C covers the portion of the second intrinsic silicon layer 22 located on side surface C, and also covers a portion of the first intrinsic silicon layer 21. A portion of the first doped layer 31 is located on one side of the first surface F, and a portion is located on side surface C. The portion of the first doped layer 31 located on side surface C covers the portion of the first intrinsic silicon layer 21 located on side surface C, and also covers a portion of the second doped layer 32.

[0333] Step D, refer to Figure 10 The substrate 10, after the formation of the first doped layer 31, is placed on a carrier plate (not shown). That is, with the first surface F of the substrate 10 facing the carrier plate, the side of the substrate 10 with the first doped layer 31 is placed on the support frame of the carrier plate. The portion of the edge of the first doped layer 31 corresponding to the isolation region W is blocked by the support frame of the carrier plate, and a local area inside the edge of the first doped layer 31 is exposed from the cutout area of ​​the support frame of the carrier plate. A first transparent conductive layer 41 is formed on the surface of the first doped layer 31 exposed from the support frame of the carrier plate. The first transparent conductive layer 41 is not formed on the portion of the first doped layer 31 that is blocked by the support frame of the carrier plate and corresponds to the isolation region W. Then, a second transparent conductive layer 42 is formed on the surface of the second doped layer 32 away from the substrate 10. Part of the structure of the second transparent conductive layer 42 is located on the side C. In the portion of the second transparent conductive layer 42 located on the side C, part of it can cover the second doped layer 32 and part of it can cover the first doped layer 31.

[0334] Step E, refer to Figure 11 The structure formed in step D is flipped upside down so that the second surface S side of the substrate 10 faces the carrier plate. Figure 11 On the lower side of the substrate 10, the side with the second doped layer 32 is supported on the support frame of the carrier plate. A protective material layer 500 is formed on the surface of the first transparent conductive layer 41 facing away from the substrate 10. The protective material layer 500 covers the entire first surface F and covers a portion of the corresponding isolation region W of the first doped layer 31. Part of the structure of the protective material layer 500 is also located on the side surface C. The portion of the protective material layer 500 covering the side surface C partially covers the portion of the first doped layer 31 located on the side surface and partially covers the portion of the second transparent conductive layer 42 located on the side surface.

[0335] Step F, refer to Figure 12 A first metal seed material layer 610 is formed on the surface of the protective material layer 500 away from the substrate 10. The first metal seed material layer 610 is located on the first surface F and does not cover the isolation area W. A second metal seed material layer 620 is formed on the surface of the second transparent conductive layer 42 away from the substrate 10. Part of the structure of the second metal seed material layer 620 is located on one side of the second surface S, and part of the structure is located on the side C.

[0336] Step G, refer to Figure 13 Photoresist / photosensitive ink is printed or spin-coated onto one side of the first surface F and one side of the second surface S of the structure formed in step F. After exposure and development, a patterned first mask material layer 71 is formed. The positions on the first mask material layer 71 corresponding to the metal contact areas Z of the first surface F and the second surface S are cut out. The remaining parts of the first surface F and the second surface S are covered by the first mask material layer 71, that is, the positions on the first metal seed material layer 610 and the second metal seed material layer 620 where the gate lines will be formed are exposed. Insulating adhesive 72 or other protective materials are coated on the side surface C of the structure formed in step F to edge the side surface C. Then, copper is electroplated to form a first electroplating electrode 81 on the first metal seed material layer 610 on the first surface F side of the substrate 10, and a second electroplating electrode 82 on the second metal seed layer 620 on the second surface S side of the substrate 10.

[0337] Then, a chemical solution, typically an alkaline solution, is used to clean and remove the first mask material layer 71 and the insulating adhesive 72. Since the corresponding isolation region W of the first doped layer 31 is covered by the protective material layer 500, the alkaline solution will not damage the first doped layer 31.

[0338] Step H, Combination Figure 13 and Figure 2The portion of the first metal seed material layer 610 not covered by the first electroplating electrode 81 is cleaned and removed using a metal etching solution (e.g., H2SO4 + H2O2) to form the first metal seed layer 61. Similarly, the portion of the second metal seed material layer 620 not covered by the second electroplating electrode 82 is cleaned and removed to form the second metal seed layer 62. Then, an electrode protective layer 73 (e.g., tin / silver) is formed on the side of the first and second electroplating electrodes 81 and 82 facing away from the substrate 10 using methods such as chemical plating. Figure 2 The heterojunction solar cell 100 shown can be formed in a manner not limited to chemical plating, but also by electroplating. It should be noted that in this step, the portion of the protective material layer 500 located on the side surface C or the first surface F may be partially removed to form the protective layer. Figure 2 In the example, part of the structure of the protective material layer 500 is located on one side of the first surface F, and part of the structure is located on the side surface C, that is... Figure 2 In the example, the protective material layer 500 was not removed. Figure 2 The heterojunction cell is denoted as A1. Figure 1 In the example, the entire protective layer 50 formed after the protective material layer 500 is partially removed is located on one side of the first surface F. Figure 1 The heterojunction cell is denoted as A2. Figure 3 In the example, only the region of the protective material layer 500 corresponding to the metal contact area Z of the first surface F is retained to form the protective layer 50. That is, only the portion of the protective material layer 500 located under the first electroplating electrode 81 is retained, while the rest is completely removed. Figure 3 The heterojunction cell is denoted as A3.

[0339] Example 2

[0340] The method for fabricating a heterojunction solar cell in this embodiment is used to form Figure 4a The heterojunction cell 100 is illustrated.

[0341] This embodiment improves upon the steps of step D and thereafter, based on the first embodiment described above. Steps A, B, and C are the same as in the first embodiment and will not be repeated here.

[0342] After steps A, B, and C, the fabrication method of a heterojunction solar cell also includes:

[0343] Step I, refer to Figure 14 The second surface S side of the substrate 10 is oriented towards the carrier plate. Figure 14On the lower side of the substrate 10, the side with the second doped layer 32 is supported on the support frame of the carrier plate. A protective material layer 500 is formed on the surface of the first doped layer 31 facing away from the substrate 10. The protective material layer 500 covers the entire first surface F and covers the corresponding isolation region W of the first doped layer 31. Part of the structure of the protective material layer 500 is also located on the side C. In the portion of the protective material layer 500 covering the side C, a portion covers the portion of the first doped layer 31 located on the side C, and another portion covers the portion of the second doped layer 32 located on the side C.

[0344] Step J, refer to Figure 15 The structure formed in step I is flipped over so that the first surface F of the substrate 10 faces the carrier plate. The side of the substrate 10 with the protective material layer 500 is placed on the carrier plate's support frame. The edge of the protective material layer 500 corresponding to the isolation region W is blocked by the carrier plate's support frame. A local area inside the edge of the protective material layer 500 is exposed from the cutout area of ​​the carrier plate's support frame. A first transparent conductive layer 41 is formed on the surface of the protective material layer 500 exposed from the carrier plate's support frame. The position on the protective material layer 500 corresponding to the isolation region W is not formed with the first transparent conductive layer 41. Then, a second transparent conductive layer 42 is formed on the surface of the second doped layer 32 away from the substrate 10. Part of the second transparent conductive layer 42 is located on side C, covering a portion of side C. Part of the second transparent conductive layer 42 can cover the second doped layer 32, and part can cover the protective material layer 500. In this embodiment, the protective material layer 500 can be a transition metal oxide with the same polarity as the first doped layer 31. Alternatively, the protective material layer 500 may include a dielectric passivation layer, such as SiOx, AlOx, etc. Alternatively, the protective material layer 500 may also include a transparent conductive oxide (TCO) layer, such as SnOx, ITO, IMO, SCOT, AZO, etc.

[0345] Step K, Reference Figure 16 A first metal seed material layer 610 is formed on the surface of the first transparent conductive layer 41 away from the substrate 10. The first metal seed material layer 610 is located on the first surface F and does not cover the isolation area W. A second metal seed material layer 620 is formed on the surface of the second transparent conductive layer 42 away from the substrate 10. Part of the structure of the second metal seed material layer 620 is located on one side of the second surface S, and part of the structure is located on the side C.

[0346] Step L, refer to Figure 17Photoresist / photosensitive ink is printed or spin-coated onto one side of the first surface F and the second surface S of the structure formed in step K. After exposure and development, a patterned first mask material layer 71 is formed. The positions on the first mask material layer 71 corresponding to the metal contact areas Z of the first surface F and the second surface S are cut out. The remaining parts of the first surface F and the second surface S are covered by the first mask material layer 71, that is, the positions on the first metal seed material layer 610 and the second metal seed material layer 620 where the gate lines will be formed are exposed. Insulating adhesive 72 or other protective materials are coated on the side surface C of the structure formed in step K to edge the side surface C. Then, copper is electroplated to form a first electroplating electrode 81 on the first metal seed material layer 610 on the first surface F of the substrate 10, and a second electroplating electrode 82 on the second metal seed layer 620 on the second surface S of the substrate 10.

[0347] Then, a chemical solution, typically an alkaline solution, is used to clean and remove the first mask material layer 71 and the insulating adhesive 72. Since the corresponding isolation region W of the first doped layer 31 is covered by the protective material layer 500, the alkaline solution will not damage the first doped layer 31.

[0348] Step M, Combination Figure 17 and Figure 4a The portion of the first metal seed material layer 610 not covered by the first electroplating electrode 81 is cleaned and removed using a metal etching solution (e.g., H2SO4 + H2O2) to form the first metal seed layer 61. Similarly, the portion of the second metal seed material layer 620 not covered by the second electroplating electrode 82 is cleaned and removed to form the second metal seed layer 62. Then, an electrode protective layer 73 (e.g., tin / silver) is formed on the side of the first and second electroplating electrodes 81 and 82 facing away from the substrate 10 using methods such as chemical plating. Figure 4a The heterojunction solar cell 100 shown can be formed in a manner not limited to chemical plating, but also by electroplating. It should be noted that in this step, a portion of the protective material layer 500 located on the side surface C or the first surface F is partially removed to form the protective layer 50. Figure 4a In the example, part of the protective layer 50 is located on one side of the first surface F, and part of the structure is located on the side surface C. Figure 4a The heterojunction cell is denoted as A4. Alternatively, in some other embodiments, it can be denoted as follows: Figure 4b As shown, the portion of the protective material layer 500 not covered by the first transparent conductive layer 41 and the second transparent conductive layer 42 is cleaned and removed, exposing the corresponding isolation region W of the first doped layer 31 to form the protective layer 50.

[0349] Example 3

[0350] The method for fabricating a heterojunction solar cell in this embodiment is used to form Figure 5 , Figure 6 , Figure 22 The heterojunction cell 100 is illustrated.

[0351] This embodiment improves upon the steps of step I and thereafter, based on the above embodiment two. Steps A, B, and C are the same as in embodiment two, and will not be repeated here.

[0352] After steps A, B, and C, the fabrication method of a heterojunction solar cell also includes:

[0353] Step N, refer to Figure 18 The substrate 10, after the first doped layer 31 is formed, is placed on the support frame of the carrier plate (not shown). That is, with the first surface F of the substrate 10 facing the carrier plate, the side of the substrate 10 with the first doped layer 31 is placed on the support frame of the carrier plate. A second transparent conductive layer 42 is formed on the surface of the second doped layer 32 away from the substrate 10. Part of the structure of the second transparent conductive layer 42 is located on the second surface S, and part of the structure is located on the side C. The second transparent conductive layer 42 covers the part of the side C, and part of it can cover the second doped layer 32 and part of it can cover the first doped layer 31.

[0354] Step O, refer to Figure 19 The substrate 10 is positioned with its second surface S facing the carrier plate. The side of the substrate 10 with the second doped layer 32 is placed on the carrier frame of the carrier plate. A protective material layer 500 is formed on the surface of the first doped layer 31 facing away from the substrate 10. The protective material layer 500 covers the entire first surface F and a portion of the corresponding isolation region W of the first doped layer 31. A portion of the protective material layer 500 is also located on the side C, covering the portion of the first doped layer 31 on the side C and the portion of the second transparent conductive layer 42 on the side C. The substrate 10 is then flipped so that its first surface F faces the carrier plate. The side of the substrate 10 with the protective material layer 500 is placed on the carrier frame of the carrier plate. The edge of the protective material layer 500 corresponding to the isolation region W is blocked by the carrier frame of the carrier plate. A local area inside the edge of the protective material layer 500 is exposed from the cutout area of ​​the carrier frame of the carrier plate. A first transparent conductive layer 41 is formed on the surface of the exposed area of ​​the bearing frame of the self-supporting plate of the protective material layer 500, but no first transparent conductive layer 41 is formed on the protective material layer 500 at the position corresponding to the isolation area W.

[0355] Step P, refer to Figure 20A first metal seed material layer 610 is formed on the surface of the first transparent conductive layer 41 away from the substrate 10. The first metal seed material layer 610 is located on one side of the first surface F, but does not cover the isolation area W. A second metal seed material layer 620 is formed on the surface of the second transparent conductive layer 42 away from the substrate 10. Part of the structure of the second metal seed material layer 620 is located on one side of the second surface S, and part of the structure is located on the side C.

[0356] Step Q, refer to Figure 21 Photoresist / photosensitive ink is printed or spin-coated onto one side of the first surface F and the second surface S of the structure formed in step P. After exposure and development, a patterned first mask material layer 71 is formed. The positions on the first mask material layer 71 corresponding to the metal contact areas Z of the first surface F and the second surface S are cut out. The remaining parts of the first surface F and the second surface S are covered by the first mask material layer 71, that is, the positions on the first metal seed material layer 610 and the second metal seed material layer 620 where the gate lines will be formed are exposed. Insulating adhesive 72 or other protective materials are coated on the side surface C of the structure formed in step P to edge the side surface C. Then, copper is electroplated to form a first electroplating electrode 81 on the first metal seed material layer 610 on the first surface F side of the substrate 10, and a second electroplating electrode 82 on the second metal seed layer 620 on the second surface S side of the substrate 10.

[0357] Then, a chemical solution, typically an alkaline solution, is used to clean and remove the first mask material layer 71 and the insulating adhesive 72. Since the corresponding isolation region W of the first doped layer 31 is covered by the protective material layer 500, the alkaline solution will not damage the first doped layer 31.

[0358] Step R, Combination Figure 21 and Figure 5 The portion of the first metal seed material layer 610 not covered by the first electroplating electrode 81 is cleaned and removed using a metal etching solution (e.g., H2SO4 + H2O2) to form the first metal seed layer 61. Similarly, the portion of the second metal seed material layer 620 not covered by the second electroplating electrode 82 is cleaned and removed to form the second metal seed layer 62. Then, an electrode protective layer 73 (e.g., tin / silver) is formed on the side of the first and second electroplating electrodes 81 and 82 facing away from the substrate 10 using methods such as chemical plating. Figure 5 The heterojunction solar cell 100 shown can be formed in a manner not limited to chemical plating, but also by electroplating. It should be noted that in this step, the portion of the protective material layer 500 located on the side surface C or the first surface F may be partially removed or not removed to form the protective layer 50. Figure 5In the example, part of the structure of the protective material layer 500 is located on one side of the first surface F, and part of the structure is located on the side surface C, that is... Figure 5 In the example, the protective material layer 500 is retained to form the protective layer 50; if it is not removed, it will... Figure 5 The heterojunction cell is denoted as A5. Alternatively, refer to... Figure 6 In some other embodiments, the entire protective layer 50 may be located on one side of the first surface F, that is, the portion of the protective material layer 500 covering the side surface C may be removed separately. Alternatively, in some other embodiments, reference may be made to... Figure 22 As shown, the portion of the protective material layer 500 not covered by the first transparent conductive layer 41 is cleaned and removed to form a protective layer 50 with the same coverage area as the first transparent conductive layer 41. In this scheme, the corresponding isolation region W of the first doped layer 31 will ultimately be exposed. That is, only the portion of the protective material layer 500 located below the first transparent conductive layer 41 is retained. Figure 22 The heterojunction cell is denoted as A6.

[0359] Example 4

[0360] The method for fabricating a heterojunction solar cell in this embodiment is used to form Figure 7 The heterojunction cell 100 is illustrated.

[0361] This embodiment improves upon the steps of step I and thereafter, based on the above embodiment two. Steps A, B, and C are the same as in embodiment two, and will not be repeated here.

[0362] After steps A, B, and C, the fabrication method of a heterojunction solar cell also includes:

[0363] Step S

[0364] Reference Figure 23 A protective material layer 500 is formed on the surface of the first doped layer 31 facing away from the substrate 10. The protective material layer 500 has the same area as the first doped layer 31, that is, a portion of the structure of the protective material layer 500 corresponds to the entire first surface F and covers a portion of the corresponding isolation region W of the first doped layer 31. A portion of the structure of the protective material layer 500 is also located on the side surface C, and the portion of the protective material layer 500 located on the side surface C covers the portion of the first doped layer 31 located on the side surface C.

[0365] In specific implementation, step C, the step of forming the first doped layer 31, includes:

[0366] Hydrogen, silane, diborane, and carbon dioxide gases are introduced into the reaction chamber, wherein the molar volume ratio of hydrogen:silane:diborane:carbon dioxide is 300:1:0.005:0.2-600:1:0.01:0.5. The reaction pressure within the chamber is approximately 4-6 mbar, thereby forming an oxygen-containing microcrystalline film layer on the surface of the first intrinsic silicon layer 21 facing away from the substrate 10. As the oxygen-containing microcrystalline film layer gradually deposits, the carbon dioxide gas flow rate gradually decreases, while the diborane flow rate gradually increases, and the hydrogen dilution ratio gradually increases, resulting in an oxygen-containing microcrystalline film layer with a thickness of not less than 5 nm.

[0367] Then, hydrogen, silane, and diborane gases are introduced into the reaction chamber to continue depositing the subsequent oxygen-free microcrystalline host layer on the oxygen-containing microcrystalline sublayer. The molar volume ratio of hydrogen:silane:diborane gas is 300:1:0.01 to 500:1:0.04, the reaction pressure in the chamber is about 2-3 mbar, and the thickness of the formed oxygen-free microcrystalline host layer is not less than 10 nm.

[0368] The step of forming a protective material layer 500 on the surface of the first doped layer 31 opposite to the substrate 10 specifically includes:

[0369] Hydrogen, silane, diborane, and carbon dioxide gases are introduced into the reaction chamber, wherein the molar volume ratio of hydrogen:silane:diborane:carbon dioxide is 8:1:3:1 to 12:1:5:1.5; the reaction pressure in the reaction chamber is approximately 2-3 mbar, thereby forming a protective material layer 500 (oxygen-doped amorphous silicon layer) on the surface of the oxygen-free microcrystalline host layer, and the thickness of the protective material layer 500 is no more than 3 nm.

[0370] Step T, refer to Figure 24 The substrate 10, with the protective material layer 500 formed on one side, is placed on the support frame of the carrier plate. The edge of the protective material layer 500 corresponding to the isolation region W is blocked by the support frame of the carrier plate. A local area inside the edge of the protective material layer 500 is exposed from the cutout area of ​​the support frame of the carrier plate. A first transparent conductive layer 41 is formed on the surface of the protective material layer 500 exposed from the support frame of the carrier plate. The first transparent conductive layer 41 is not formed at the position on the protective material layer 500 corresponding to the isolation region W. Then, a second transparent conductive layer 42 is formed on the surface of the second doped layer 32 facing away from the substrate 10. Part of the second transparent conductive layer 42 is located on the side surface C, covering a portion of the side surface C. Part of the second transparent conductive layer 42 can cover the second doped layer 32, and part can cover the protective material layer 500.

[0371] Step U, refer to Figure 25A first metal seed material layer 610 is formed on the surface of the first transparent conductive layer 41 away from the substrate 10. The first metal seed material layer 610 is located on one side of the first surface F and does not cover the isolation area W. A second metal seed material layer 620 is formed on the surface of the second transparent conductive layer 42 away from the substrate 10. Part of the structure of the second metal seed material layer 620 is located on one side of the second surface S and part of the structure is located on the side C.

[0372] Step V, refer to Figure 26 Photoresist / photosensitive ink is printed or spin-coated onto one side of the first surface F and the second surface S of the structure formed in step U. After exposure and development, a patterned first mask material layer 71 is formed. Positions on the first mask material layer 71 corresponding to the metal contact areas Z of the first surface F and the second surface S are cut out. The remaining portions of the first surface F and the second surface S are covered by the first mask material layer 71, exposing the positions on the first metal seed material layer 610 and the second metal seed material layer 620 where gate lines will be formed. Insulating adhesive 72 or other protective material is coated onto the side surface C of the structure formed in step U to edge the side surface C. Then, copper is electroplated to form a first electroplating electrode 81 on the first metal seed material layer 610 on the first surface F of the substrate 10, and a second electroplating electrode 82 on the second metal seed layer 620 on the second surface S of the substrate 10.

[0373] Then, a chemical solution, typically an alkaline solution, is used to clean and remove the first mask material layer 71 and the insulating adhesive 72. Since the isolation region W is covered by the protective material layer 500, the alkaline solution will not damage the first doped layer 31.

[0374] Step X, Combination Figure 26 and Figure 7 The portion of the first metal seed material layer 610 not covered by the first electroplating electrode 81 is cleaned and removed using a metal etching solution (e.g., H2SO4 + H2O2) to form the first metal seed layer 61. Similarly, the portion of the second metal seed material layer 620 not covered by the second electroplating electrode 82 is cleaned and removed to form the second metal seed layer 62. Then, an electrode protective layer 73 (e.g., tin / silver) is formed on the side of the first and second electroplating electrodes 81 and 82 facing away from the substrate 10 using methods such as chemical plating. Figure 7 The heterojunction cell 100 shown is formed by means of electrode protective layer 73, which is not limited to chemical plating, but can also be formed by electroplating.

[0375] Such heterojunction cells are formed as Figure 7 As shown. Figure 7 The heterojunction cell is denoted as A7.

[0376] Comparative Example

[0377] Step 1: Prepare a silicon wafer as a substrate.

[0378] Step 2: Form a first intrinsic silicon layer on the first surface of the substrate and a second intrinsic silicon layer on the second surface of the substrate.

[0379] Step 3: Form a second doped layer on the surface of the second intrinsic silicon layer away from the substrate, and form a first doped layer on the surface of the first intrinsic silicon layer away from the substrate.

[0380] Step 4: Place the substrate with the first doped layer formed on the carrier plate, that is, with one side of the first surface of the substrate facing the carrier plate, place the side of the substrate with the first doped layer formed on the carrier plate's support frame. The portion of the edge of the first doped layer corresponding to the isolation region is blocked by the carrier plate's support frame, while a local area inside the edge of the first doped layer is exposed from the cutout area of ​​the carrier plate's support frame. A first transparent conductive layer is formed on the surface of the first doped layer in the area exposed from the carrier plate's support frame. The portion of the first doped layer that is blocked by the carrier plate's support frame and corresponds to the isolation region does not have a first transparent conductive layer formed. Then, a second transparent conductive layer is formed on the surface of the second doped layer facing away from the substrate.

[0381] Step 5: A first metal seed material layer is formed on the surface of the first transparent conductive layer away from the substrate. The first metal seed material layer is located on the first surface and does not cover the isolation area. A second metal seed material layer is formed on the surface of the second transparent conductive layer away from the substrate. Part of the structure of the second metal seed material layer is located on one side of the second surface, and part of the structure is located on the side.

[0382] Step Six: Form patterned mask layers on one side of the first surface and one side and side of the second surface of the structure formed in Step Five, exposing the metal contact area on one side of the first surface and the metal contact area on one side of the second surface. Then, electroplate copper to form a first electroplating electrode on the first metal seed material layer on one side of the first surface of the substrate and a second electroplating electrode on the second metal seed material layer on the second surface of the substrate.

[0383] Then, a chemical solution, usually an alkaline solution, is used to clean and remove the patterned mask layer. Since the corresponding isolation region of the first doped layer is partially exposed, it will be etched by the alkaline solution, thus causing damage to the first doped layer.

[0384] Step 7: Use a metal etching solution to clean and remove the portion of the first metal seed material layer not covered by the first electroplating electrode to form the first seed layer. Then, clean and remove the portion of the second metal seed material layer not covered by the second electroplating electrode to form the second seed layer. Next, form a chemical plating protective layer on the side of the first and second electroplating electrodes facing away from the substrate using methods such as chemical plating. The battery fabricated using the comparative method is designated B1.

[0385] The heterojunction solar cells A1, A2, A3, A4, A5, A6, A7 and the comparative solar cell B1 were tested for cell performance, and the test results are recorded in Table 1 below. Where Isc is the short-circuit current; Uoc is the open-circuit voltage; FF is the fill factor; Eta is the conversion efficiency; Rsh is the parallel resistance; Rs is the series resistance; Jsc is the short-circuit current density; and PFF is the pseudo-fill factor.

[0386] Table 1: Performance test results of heterojunction cells A1, A2, A3, A4, A5, A6, and A7 of this application and heterojunction cell B1 of the comparative example.

[0387] Group Isc(A) Uoc(V) FF (%) Eta(%) Rsh(ohm) Rs(ohm) <![CDATA[Jsc(A / cm 2 )]]> PFF (%) B1 8.809 0.750 85.86 25.74 1362 0.00084 0.03995 87.01 A1 8.828 0.751 86.48 25.99 878 0.00061 0.04004 87.34 A2 8.837 0.750 86.55 26.02 1435 0.00053 0.04008 87.30 A3 8.808 0.750 86.43 25.89 1337 0.00053 0.03995 87.21 A4 8.833 0.750 86.27 25.93 812 0.00060 0.04006 87.21 A5 8.830 0.750 86.21 25.92 786 0.00064 0.04005 87.18 A6 8.806 0.750 86.46 25.89 1390 0.00053 0.03994 87.30 A7 8.808 0.750 86.44 25.89 1348 0.00061 0.03995 87.33

[0388] The experimental results above show that, compared with the heterojunction cell B1 in the comparative example, the heterojunction cell A1 fabricated using the heterojunction cell fabrication method of the present application has the following characteristics: Isc short-circuit current increases; Uoc open-circuit voltage increases; FF fill factor increases; Eta conversion efficiency increases; Rsh parallel resistance decreases; Rs series resistance decreases; Jsc short-circuit current density increases; and PFF pseudo-fill factor increases.

[0389] Compared to the comparative heterojunction cell B1, the heterojunction cell A2 fabricated using the method described in this application exhibits the following characteristics: Isc short-circuit current increases; Uoc open-circuit voltage remains unchanged; FF fill factor increases; Eta conversion efficiency increases; Rsh parallel resistance increases; Rs series resistance decreases; Jsc short-circuit current density increases; and PFF pseudo-fill factor increases.

[0390] Compared to the comparative heterojunction cell B1, the heterojunction cell A3 fabricated using the heterojunction cell fabrication method of the present application has the following characteristics: Isc short-circuit current remains basically the same; Uoc open-circuit voltage remains unchanged; FF fill factor increases; Eta conversion efficiency increases; Rsh parallel resistance decreases; Rs series resistance decreases; Jsc short-circuit current density remains unchanged; and PFF pseudo-fill factor increases.

[0391] Compared to the comparative heterojunction cell B1, the heterojunction cell A4 fabricated using the method described in this application exhibits the following characteristics: Isc short-circuit current increases; Uoc open-circuit voltage remains unchanged; FF fill factor increases; Eta conversion efficiency increases; Rsh parallel resistance decreases; Rs series resistance decreases; Jsc short-circuit current density increases; and PFF pseudo-fill factor increases.

[0392] Compared to the comparative heterojunction cell B1, the heterojunction cell A5 fabricated using the method described in this application exhibits the following characteristics: Isc short-circuit current increases; Uoc open-circuit voltage remains unchanged; FF fill factor increases; Eta conversion efficiency increases; Rsh parallel resistance decreases; Rs series resistance decreases; Jsc short-circuit current density increases; and PFF pseudo-fill factor increases.

[0393] Compared to the comparative heterojunction cell B1, the heterojunction cell A6 fabricated using the method described in this application has the following characteristics: Isc short-circuit current remains essentially the same; Uoc open-circuit voltage remains unchanged; FF fill factor increases; Eta conversion efficiency increases; Rsh parallel resistance increases; Rs series resistance decreases; Jsc short-circuit current density remains essentially the same; and PFF pseudo-fill factor increases.

[0394] Compared to the comparative heterojunction cell B1, the heterojunction cell A7 fabricated using the method described in this application exhibits the following characteristics: Isc short-circuit current remains essentially the same; Uoc open-circuit voltage remains unchanged; FF fill factor increases; Eta conversion efficiency increases; Rsh parallel resistance decreases; Rs series resistance decreases; Jsc short-circuit current density remains unchanged; and PFF pseudo-fill factor increases.

[0395] Therefore, it can be seen that the heterojunction solar cell fabricated using the method of this embodiment has a high efficiency.

[0396] This application also provides a heterojunction cell 100, which is manufactured using the heterojunction cell manufacturing method described above.

[0397] This application also provides a photovoltaic module, which includes at least one cell string, and the cell string includes at least two heterojunction cells 100 as described above.

[0398] The heterojunction cells 100 can be connected together by string welding, thereby collecting the electrical energy generated by each individual heterojunction cell 100 for subsequent transmission. Of course, the heterojunction cells 100 can be arranged at intervals or stacked together in a shingled manner.

[0399] For example, a photovoltaic module also includes an encapsulation layer and a cover plate, the encapsulation layer being used to cover the surface of the battery string and the cover plate being used to cover the surface of the encapsulation layer away from the battery string.

[0400] This application also provides a photovoltaic system, including the photovoltaic module described above.

[0401] Photovoltaic systems can be applied in photovoltaic power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios of photovoltaic systems are not limited to these; that is, photovoltaic systems can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation network as an example, a photovoltaic system can include photovoltaic arrays, combiner boxes, and inverters. A photovoltaic array can be a combination of multiple photovoltaic modules; for example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic arrays are connected to combiner boxes, which collect the current generated by the photovoltaic arrays. The collected current flows through an inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.

[0402] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0403] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A heterojunction battery, characterized in that, include: Substrate; A first intrinsic silicon layer and a first doped layer are sequentially stacked on the first surface of the substrate; A first transparent conductive layer and a protective layer are stacked on the side of the first doped layer away from the substrate. The first transparent conductive layer covers a portion of the first surface, and the protective layer completely covers the first surface. as well as The first electroplating electrode is located on the side of the protective layer away from the substrate and is electrically connected to the first transparent conductive layer. The first surface includes an isolation region not covered by the first transparent conductive layer; a portion of the protective layer is stacked on the portion of the first doped layer corresponding to the isolation region.

2. The heterojunction solar cell according to claim 1, characterized in that, The protective layer completely covers the first surface and covers at least a portion of the side surface of the substrate, the side surface of the substrate being adjacent to the first surface.

3. The heterojunction solar cell according to claim 1, characterized in that, The protective layer completely covers the first surface, and the outer contour edge of the protective layer coincides with the edge of the first surface.

4. The heterojunction battery according to claim 1, characterized in that, The first transparent conductive layer is disposed on the surface of the first doped layer opposite to the substrate; The protective layer is located on the side of the first transparent conductive layer that is away from the substrate; The first electroplating electrode is disposed on the protective layer and is electrically connected to the first transparent conductive layer through the protective layer.

5. The heterojunction battery according to claim 4, characterized in that, The protective layer completely covers the first surface, and the outer contour edge of the protective layer coincides with the edge of the first surface; A portion of the protective layer is stacked on the surface of the first transparent conductive layer opposite to the substrate, and another portion of the protective layer is stacked on the surface of the portion of the first doped layer corresponding to the isolation region.

6. The heterojunction solar cell according to claim 4, characterized in that, The protective layer completely covers the first surface and covers at least a portion of the side surface of the substrate, wherein the side surface of the substrate is adjacent to the first surface.

7. The heterojunction battery according to claim 6, characterized in that, The heterojunction solar cell further includes a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer sequentially stacked on the second surface of the substrate. The doping type of the second doped layer is opposite to that of the first doped layer, and the second surface is disposed opposite to the first surface. The second transparent conductive layer covers at least a portion of the side surface of the second surface and the substrate, and a portion of the structure of the protective layer is stacked onto the side of the second transparent conductive layer opposite to the substrate.

8. The heterojunction solar cell according to claim 4, characterized in that, The protective layer includes a transparent conductive oxide layer, which includes at least one of ITO, IMO, AZO, SCOT, and SnOx.

9. The heterojunction battery according to claim 8, characterized in that, The thickness of the protective layer is 5-15 nm.

10. The heterojunction solar cell according to claim 1, characterized in that, The protective layer is disposed on the surface of the first doped layer opposite to the substrate; the first transparent conductive layer is located on the side of the protective layer opposite to the substrate; The first electroplating electrode is disposed on the first transparent conductive layer.

11. The heterojunction solar cell according to claim 10, characterized in that, The protective layer completely covers the first surface, and the outer contour edge of the protective layer coincides with the edge of the first surface.

12. The heterojunction solar cell according to claim 10, characterized in that, The protective layer completely covers the first surface and covers at least a portion of the side surface of the substrate, wherein the side surface of the substrate is adjacent to the first surface.

13. The heterojunction solar cell according to claim 12, characterized in that, The heterojunction solar cell further includes a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer sequentially stacked on the second surface of the substrate. The doping type of the second doped layer is opposite to that of the first doped layer, and the second surface is disposed opposite to the first surface. The second doped layer covers at least a portion of the second surface and the side surface, the first doped layer covers at least a portion of the first surface and the side surface, and a portion of the structure of the first doped layer is stacked onto the side of the second doped layer opposite to the substrate. The protective layer is at least partially stacked on the surface of the first doped layer opposite to the substrate; The second transparent conductive layer covers at least a portion of the side surface of the second surface and the substrate, and a portion of the structure of the second transparent conductive layer is stacked onto the side of the protective layer opposite to the substrate.

14. The heterojunction solar cell according to claim 13, characterized in that, The outer contour edge of the protective layer coincides with the outer contour edge of the first doped layer.

15. The heterojunction solar cell according to claim 14, characterized in that, The first doped layer includes an oxygen-free microcrystalline host layer, and the protective layer includes an oxygen-doped amorphous silicon layer.

16. The heterojunction solar cell according to claim 15, characterized in that, The first doped layer further includes an oxygen-containing microcrystalline sublayer, which is stacked between the first intrinsic silicon layer and the oxygen-free microcrystalline host layer.

17. The heterojunction solar cell according to claim 15, characterized in that, The thickness of the protective layer is no greater than 3 nm.

18. The heterojunction solar cell according to claim 13, characterized in that, The protective layer covers a portion of one side of the side, with a portion of the structure stacked on the first doped layer and another portion of the structure stacked on the second doped layer.

19. The heterojunction solar cell according to claim 12, characterized in that, The heterojunction solar cell further includes a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer sequentially stacked on the second surface of the substrate. The doping type of the second doped layer is opposite to that of the first doped layer, and the second surface is disposed opposite to the first surface. The second transparent conductive layer covers at least a portion of the side surface of the second surface and the substrate, and a portion of the structure of the protective layer is stacked onto the side of the second transparent conductive layer opposite to the substrate.

20. The heterojunction solar cell according to claim 18 or 19, characterized in that, The protective layer comprises a transition metal oxide, and the polarity of the protective layer is the same as that of the first doped layer; or The protective layer includes a dielectric passivation layer; or The protective layer includes a transparent conductive oxide layer.

21. The heterojunction solar cell according to claim 20, characterized in that, When the protective layer comprises a transition metal oxide, the thickness of the protective layer is 5-30 nm; When the protective layer includes a dielectric passivation layer, the thickness of the protective layer is 0.5-3 nm; When the protective layer includes a transparent conductive oxide layer, the thickness of the protective layer is 5-15 nm.

22. The heterojunction battery according to any one of claims 1-19, characterized in that, The substrate further includes a second surface disposed opposite to the first surface, and a side surface adjacent to the first surface and the second surface; The heterojunction solar cell further includes a second electroplated electrode, and a second intrinsic silicon layer, a second doped layer and a second transparent conductive layer sequentially stacked on the second surface. The doping type of the second doped layer is opposite to that of the first doped layer, and the second electroplated electrode is electrically connected to the second transparent conductive layer.

23. The heterojunction solar cell according to claim 22, characterized in that, The heterojunction solar cell further includes a first metal seed layer and a second metal seed layer, wherein the first metal seed layer is stacked on the surface of the first electroplated electrode facing the substrate, and the second metal seed layer is stacked on the surface of the second electroplated electrode facing the substrate.

24. The heterojunction solar cell according to claim 23, characterized in that, The heterojunction solar cell further includes an electrode protective layer, wherein the electrode protective layer located on one side of the first surface is stacked on the surface of the first electroplated electrode away from the substrate, and the electrode protective layer located on one side of the second surface is stacked on the surface of the second electroplated electrode away from the substrate.

25. The heterojunction solar cell according to claim 22, characterized in that, The first intrinsic silicon layer covers at least a portion of the first surface and the side surface; The second intrinsic silicon layer covers at least a portion of the second surface and the side surface, and a portion of the structure of the second intrinsic silicon layer is stacked onto the side of the first intrinsic silicon layer facing away from the substrate; The second doped layer covers at least a portion of the second surface and the side surface, and a portion of the structure of the second doped layer is stacked onto the side of the first intrinsic silicon layer opposite to the substrate; The first doped layer covers at least a portion of the first surface and the side surface, and a portion of the structure of the first doped layer is stacked onto the side of the second doped layer opposite to the substrate.

26. The heterojunction battery according to any one of claims 1-19, characterized in that, Each portion of the outer contour edge of the first transparent conductive layer is spaced from the edge of the first surface to define an annular isolation region on the first surface.

27. A method for fabricating a heterojunction solar cell, characterized in that, include: A substrate is provided, the substrate comprising a substrate, and a first intrinsic silicon layer and a first doped layer sequentially stacked on a first surface of the substrate; A first transparent conductive layer and a protective material layer are formed on the side of the first doped layer away from the substrate, wherein the first transparent conductive layer covers a portion of the first surface, the first surface includes an isolation region not covered by the first transparent conductive layer, the protective material layer completely covers the first surface, and a portion of the structure of the protective material layer is stacked on the portion of the first doped layer corresponding to the isolation region. A first electroplating electrode is formed by electroplating on the side of the protective material layer opposite to the substrate, and the first electroplating electrode is electrically connected to the first transparent conductive layer.

28. The method for fabricating a heterojunction solar cell according to claim 27, characterized in that, In the step of forming the protective material layer: The second surface of the substrate is oriented towards the support frame of the carrier plate; The protective material layer is formed on the side of the first doped layer opposite to the substrate; Wherein, the protective material layer completely covers the first surface and covers at least a portion of the side surface of the substrate; or, the protective material layer completely covers the first surface, and the outer contour edge of the protective material layer coincides with the edge of the first surface.

29. The method for fabricating a heterojunction solar cell according to claim 28, characterized in that, In the step of forming the first transparent conductive layer: The first surface of the substrate is oriented towards the support frame of the carrier plate; The first transparent conductive layer is formed on the side of the first doped layer away from the substrate, and the location of the formation of the first transparent conductive layer corresponds to the hollow portion of the bearing frame.

30. The method for fabricating a heterojunction solar cell according to claim 27, characterized in that, The step of forming a first transparent conductive layer and a protective material layer stacked on the side of the first doped layer opposite to the substrate specifically includes: A first transparent conductive layer is formed on the surface of the first doped layer that is away from the substrate; A protective material layer is formed on the surface of the first transparent conductive layer that is away from the substrate.

31. The method for fabricating a heterojunction solar cell according to claim 30, characterized in that, The step of forming a first transparent conductive layer on the surface of the first doped layer away from the substrate specifically includes: The first surface of the substrate is oriented toward the support frame of the carrier plate, and the portion of the first doped layer located on the first surface is supported by the support frame. In the portion of the first doped layer covering one side of the first surface, the area not obscured by the bearing frame forms the first transparent conductive layer.

32. The method for fabricating a heterojunction solar cell according to claim 31, characterized in that, The step of forming a protective material layer on the surface of the first transparent conductive layer opposite to the substrate specifically includes: The second surface of the substrate is supported on the support frame of the carrier plate; A protective material layer is formed on the surface of the first transparent conductive layer away from the substrate; the protective material layer is partially stacked on the surface of the first transparent conductive layer away from the substrate, and partially stacked on the surface of the portion of the isolation region corresponding to the first doped layer.

33. The method for fabricating a heterojunction solar cell according to claim 32, characterized in that, The substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface; the step of forming the first transparent conductive layer and the step of forming the protective material layer further includes: A second transparent conductive layer is formed on the side of the second doped layer that is away from the substrate.

34. The method for fabricating a heterojunction solar cell according to claim 33, characterized in that, The substrate also includes a side surface adjacent to the first surface and the second surface; The second transparent conductive layer covers at least a portion of the side surface of the second surface and the substrate; The protective material layer also covers at least a portion of the side surface, and a portion of the structure of the protective material layer is stacked onto the side of the second transparent conductive layer opposite to the substrate; or The outer contour edge of the protective material layer coincides with the edge of the first surface.

35. The method for fabricating a heterojunction solar cell according to claim 27, characterized in that, The step of forming a first transparent conductive layer and a protective material layer stacked on the side of the first doped layer opposite to the substrate specifically includes: A protective material layer is formed on the surface of the first doped layer that is away from the substrate; A first transparent conductive layer is formed on the surface of the protective material layer opposite to the substrate.

36. The method for fabricating a heterojunction solar cell according to claim 35, characterized in that, The substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface; the substrate also includes a side surface adjacent to the first surface and the second surface; The step of forming a protective material layer on the surface of the first doped layer away from the substrate includes, prior to the step of: A second transparent conductive layer is formed on the surface of the second doped layer opposite to the substrate, the second transparent conductive layer covering at least a portion of the second surface and the side surface.

37. The method for fabricating a heterojunction solar cell according to claim 36, characterized in that, The step of forming a protective material layer on the surface of the first doped layer away from the substrate specifically includes: A protective material layer is formed on the side of the first doped layer away from the substrate, the protective material layer completely covering the first surface and covering at least a portion of the side surface, and the protective material layer is stacked onto the second transparent conductive layer.

38. The method for fabricating a heterojunction solar cell according to claim 37, characterized in that, The step of forming a first transparent conductive layer on the surface of the protective material layer opposite to the substrate specifically includes: The first surface of the substrate is oriented toward the support frame of the carrier plate, and the portion of the protective material layer located on the first surface is supported by the support frame. In the portion of the protective material layer covering one side of the first surface, the area not obscured by the supporting frame forms the first transparent conductive layer.

39. The method for fabricating a heterojunction solar cell according to claim 35, characterized in that, The substrate further includes a second surface disposed opposite to the first surface, and a side surface adjacent to the first surface and the second surface; The step of forming a protective material layer on the surface of the first doped layer away from the substrate includes: A protective material layer is formed on the side of the first doped layer opposite to the substrate, the protective material layer covering at least a portion of the first surface and the side surface.

40. The method for fabricating a heterojunction solar cell according to claim 39, characterized in that, The step of forming a first transparent conductive layer on the surface of the protective material layer opposite to the substrate specifically includes: The first surface of the substrate is oriented toward the support frame of the carrier plate, and the portion of the protective material layer located on the first surface is supported by the support frame. In the portion of the protective material layer covering one side of the first surface, the area not obscured by the supporting frame forms the first transparent conductive layer.

41. The method for fabricating a heterojunction solar cell according to claim 40, characterized in that, The substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on the second surface; After the step of forming the first transparent conductive layer on the surface of the protective material layer opposite to the substrate, the method further includes: A second transparent conductive layer is formed on the surface of the second doped layer opposite to the substrate. The second transparent conductive layer covers a portion of the second surface and the side surface, and is stacked onto the protective material layer.

42. The method for manufacturing a heterojunction solar cell according to any one of claims 39-41, characterized in that, The substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface; In the step of forming a protective material layer on the surface of the first doped layer away from the substrate: The protective material layer covers at least a portion of the first surface and the side surface, and the protective material layer is stacked onto the side of the second doped layer opposite to the substrate.

43. The method for manufacturing a heterojunction solar cell according to any one of claims 39-41, characterized in that, In the step of forming a protective material layer on the surface of the first doped layer away from the substrate: The protective material layer covers at least a portion of the first surface and the side surface; the outer contour edge of the protective material layer coincides with the outer contour edge of the first doped layer.

44. The method for fabricating a heterojunction solar cell according to claim 43, characterized in that, The first doped layer includes an oxygen-free microcrystalline host layer; The steps for forming the protective material layer include: An oxygen-doped amorphous silicon layer is formed on the surface of the first doped layer away from the substrate as a protective material layer, wherein the doping type of the oxygen-doped amorphous silicon layer is the same as that in the first doped layer.

45. The method for fabricating a heterojunction solar cell according to claim 44, characterized in that, The first doped layer further includes an oxygen-containing microcrystalline sublayer, which is stacked between the first intrinsic silicon layer and the oxygen-free microcrystalline host layer.

46. ​​The method for fabricating a heterojunction solar cell according to claim 45, characterized in that, The oxygen-containing microcrystalline sub-film layer and the oxygen-free microcrystalline host layer are formed through the following steps: Hydrogen, silane, diborane, and carbon dioxide gases are introduced into the reaction chamber, wherein the molar volume ratio of the hydrogen, silane, diborane, and carbon dioxide gases is 300:1:0.005:0.2-600:1:0.01:0.5, and the reaction pressure in the reaction chamber is 4-6 mbar, so as to form the oxygen-containing microcrystalline film layer on the surface of the first intrinsic silicon layer away from the substrate; Hydrogen, silane, and diborane gases are introduced into the reaction chamber, wherein the molar volume ratio of the hydrogen, silane, and diborane gases is 300:1:0.01-500:1:0.04, and the reaction pressure in the reaction chamber is 2-3 mbar, so as to form the oxygen-free microcrystalline host layer on the surface of the oxygen-containing microcrystalline film layer away from the substrate.

47. The method for fabricating a heterojunction solar cell according to claim 44, characterized in that, The step of forming the oxygen-doped amorphous silicon layer as a protective material layer includes: Hydrogen, silane, diborane, and carbon dioxide are introduced into the reaction chamber, wherein the molar volume ratio of the hydrogen, silane, diborane, and carbon dioxide is from 8:1:3:1 to 12:1:5:1.5; the reaction pressure in the reaction chamber is 2-3 mbar, so as to form the oxygen-doped amorphous silicon layer on the surface of the oxygen-free microcrystalline host layer.

48. The method for fabricating a heterojunction solar cell according to claim 35, characterized in that, The protective material layer comprises a transition metal oxide, and the polarity of the protective material layer is the same as that of the first doped layer; or The protective material layer includes a dielectric passivation layer; or The protective material layer includes a transparent conductive oxide layer.

49. The method for manufacturing a heterojunction solar cell according to any one of claims 27-41, characterized in that, The substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface; The method for fabricating the heterojunction solar cell further includes: A second transparent conductive layer is formed on the surface of the second doped layer that is away from the substrate; A second electroplated electrode is formed on one side of the second surface of the substrate by electroplating.

50. The method for fabricating a heterojunction solar cell according to claim 49, characterized in that, The protective material layer completely covers the first surface and covers at least a portion of the side surface of the substrate; In the steps of forming the first electroplating electrode and forming the second electroplating electrode, at least a portion of the protective material layer is also removed to form a protective layer.

51. The method for fabricating a heterojunction solar cell according to claim 50, characterized in that, The portion of the protective material layer that is removed includes the portion of the protective material layer located on one side of the side surface; or The portion of the protective material layer that is removed includes the portion of the protective material layer covering one side of the side and the portion covering the isolation area; or The removed portion of the protective material layer includes the portion of the protective material layer covering one side of the side surface, and the portion of the protective material layer corresponding to the non-metallic contact area of ​​the first surface.

52. The method for fabricating a heterojunction solar cell according to claim 51, characterized in that, The steps of forming the first electroplating electrode and forming the second electroplating electrode specifically include: A first metal seed material layer is formed on one side of the first surface of the substrate, and a second metal seed material layer is formed on the surface of the second transparent conductive layer opposite to the substrate, wherein the first metal seed material layer is located on the one of the first transparent conductive layer and the protective material layer that is farther away from the substrate; A first electroplating electrode is formed by electroplating on the surface of the first metal seed material layer using a patterned mask layer, and a second electroplating electrode is formed by electroplating on the surface of the second metal seed material layer. Remove the mask layer; The portion of the first metal seed material layer not covered by the first electroplating electrode is removed to form a first metal seed layer, and the portion of the second metal seed material layer not covered by the second electroplating electrode is removed to form a second metal seed layer.

53. The method for fabricating a heterojunction solar cell according to claim 52, characterized in that, The patterned mask layer is formed by the following steps: A patterned first mask material layer is formed on the side of the first metal seed material layer and the second metal seed material layer away from the substrate. The first mask material layer is hollowed out at the position of the metal contact area of ​​the first surface and at the position of the metal contact area of ​​the second surface. An insulating adhesive is applied to one side of the substrate.

54. The method for fabricating a heterojunction solar cell according to claim 52, characterized in that, After the steps of removing the portion of the first metal seed material layer not covered by the first electroplating electrode and removing the portion of the second metal seed material layer not covered by the second electroplating electrode, the method further includes the step of forming an electrode protective layer on the surfaces of the first electroplating electrode and the second electroplating electrode.

55. The method for fabricating a heterojunction solar cell according to claim 54, characterized in that, In the steps of removing the portion of the first metal seed material layer not covered by the first electroplating electrode, removing the portion of the second metal seed material layer not covered by the second electroplating electrode, and / or forming the electrode protective layer, at least a portion of the protective material layer is removed to form the protective material layer.

56. The method for fabricating a heterojunction solar cell according to claim 27, characterized in that, The substrate further includes a second intrinsic silicon layer and a second doped layer sequentially stacked on a second surface of the substrate, the second surface being disposed opposite to the first surface; The step of providing a substrate specifically includes: A first intrinsic silicon layer is formed on a first surface of the substrate, and a second intrinsic silicon layer is formed on a second surface of the substrate; A second doped layer is formed on the surface of the second intrinsic silicon layer opposite to the substrate, and a first doped layer is formed on the surface of the first intrinsic silicon layer opposite to the substrate.

57. The method for fabricating a heterojunction solar cell according to claim 56, characterized in that, The substrate also includes a side surface adjacent to the first surface and the second surface; The first intrinsic silicon layer covers at least a portion of the first surface and the side surface; The second intrinsic silicon layer covers at least a portion of the second surface and the side surface, and a portion of the structure of the second intrinsic silicon layer is stacked onto the side of the first intrinsic silicon layer facing away from the substrate; The second doped layer covers at least a portion of the second surface and the side surface, and a portion of the structure of the second doped layer is stacked onto the side of the first intrinsic silicon layer opposite to the substrate; The first doped layer covers at least a portion of the first surface and the side surface, and a portion of the structure of the first doped layer is stacked onto the side of the second doped layer opposite to the substrate.

58. A heterojunction battery, characterized in that, It is manufactured using the method described in any one of claims 27-57 for a heterojunction solar cell.

59. A photovoltaic module, characterized in that, It includes at least one battery string, said battery string comprising at least two heterojunction cells as described in any one of claims 1-26 and 58.

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