Array substrate and display device

Abstract

Provided are an array substrate and a display device. The array substrate includes a display area and a non-display area, and a plurality of light-sensing transistors. The non-display area has a plurality of signal lines. The plurality of light-sensing transistors include a first transistor and at least one second transistor. The first transistor and the second transistor are configured to match color resist materials of different colors. The plurality of signal lines include a first source line and at least one second source line. A source of the first transistor is connected to the first source line. A source of the second transistor is connected to the second source line. A first distance is present between a gate of the first transistor and the second source line connected to the source of the first transistor. A second distance is present between a gate of the second transistor and the second source line connected to the source of the second transistor. The second distance is greater than the first distance. A filling portion is present between the gate of the second transistor and the second source line connected to the source of the second transistor. The array substrate can reduce the risk of Rubbing Mura.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to an array substrate and a display device. Background Technology

[0002] With the continuous development of the display industry, television has developed rapidly, from bulky black and white televisions to color televisions, and now to large-screen smart televisions. The pace of technological innovation has never stopped.

[0003] With continuous product updates and iterations, and the increasing demands from users for display products, traditional technologies need to be constantly broken down to drive innovation. The panel industry faces fierce competition in areas such as low cost, high transmittance, and high contrast. To increase market share and enhance customer loyalty, intelligent display solutions are being incorporated into display product designs. For example, adding light and temperature sensors can detect ambient light brightness and temperature, allowing for corresponding adjustments to improve the user experience. Summary of the Invention

[0004] At least one embodiment of this disclosure provides an array substrate, including a substrate, a display area and a non-display area located on the substrate, and a plurality of photosensitive transistors. At least a portion of the non-display area surrounds the display area, and the non-display area has a plurality of signal lines, each of which at least a portion surrounds the display area. The plurality of photosensitive transistors are located on the substrate and within the non-display area, and are disposed around the display area. Each photosensitive transistor includes a source, a gate, and a drain. The plurality of photosensitive transistors include a first transistor and at least one second transistor, the first transistor and the second transistor being configured to match color resist materials of different colors. The plurality of signal lines... The line includes a first source line and at least one second source line. The source of the first transistor is connected to the first source line. The at least one second source line corresponds one-to-one with the at least one second transistor. The source of the second transistor is connected to the second source line. There is a first distance between the gate of the first transistor and the first source line connected to the source of the first transistor. There is a second distance between the gate of the second transistor and the second source line connected to the source of the second transistor. The second distance is greater than the first distance. A filling portion is provided between the gate of the second transistor and the second source line connected to the source of the second transistor.

[0005] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the filling portion located between the gate of the second transistor and the second source line to which the second transistor is connected is part of the source of the second transistor.

[0006] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the filling portion located between the gate of the second transistor and the second source line corresponding to the second transistor is electrically connected to the second source line corresponding to the second transistor.

[0007] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the length of the first source line is less than the length of the second source line, the first source line is spaced apart from the source of the second transistor, and the extension of the first source line intersects with the fill portion located between the gate of the second transistor and the second source line connecting the second transistor.

[0008] For example, according to at least one embodiment of the present disclosure, the array substrate includes at least one first portion, at least a portion of the second source line extends along a first direction, and the at least portion of the second source line is located on one side of the display area in a second direction, both the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction, on the side of the display area, and in the second direction, the first portion overlaps with the gate of the second transistor connected to the second source line.

[0009] For example, according to at least one embodiment of the array substrate provided in this disclosure, the at least one second source line includes a first type source line, a second type source line, and a third type source line; the at least one second transistor includes a first type transistor, a second type transistor, and a third type transistor; the source of the first type transistor is connected to the first type source line; the source of the second type transistor is connected to the second type source line; the source of the third type transistor is connected to the third type source line; the gate of the first type transistor and the first type source line have a first sub-distance in a direction perpendicular to the first type source line; the gate of the second type transistor and the second type source line have a second sub-distance in a direction perpendicular to the second type source line; the gate of the third type transistor and the third type source line have a third sub-distance in a direction perpendicular to the third type source line; the first sub-distance is smaller than the second sub-distance; and the second sub-distance is smaller than the third sub-distance.

[0010] For example, according to at least one embodiment of the array substrate provided in this disclosure, at least a portion of the first source line extends along the first direction; a first portion located between the gate of the first type transistor and the first type source line includes a first extension portion, the extension direction of the first extension portion being the same as the extension direction of the first source line, and an extension line of the first source line passing through the first extension portion; a first portion located between the gate of the second type transistor and the second type source line includes a second extension portion, the extension direction of the second extension portion being the same as the extension direction of the first type source line, and an extension line of the first type source line passing through the second extension portion; a first portion located between the gate of the third type transistor and the third type source line includes a third extension portion, the extension direction of the third extension portion being the same as the extension direction of the second type source line, and an extension line of the second type source line passing through the third extension portion.

[0011] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the at least one second source line includes a specific source line, the at least one second transistor includes a specific transistor, the source of the specific transistor is electrically connected to the specific source line, on one side of the display area, the first portion extends along the first direction, N second source lines are provided between the first source line and the specific source line, the filling portion located between the gate of the specific transistor and the specific source line is a part of the source of the specific transistor, and the number of the at least one first portion of the filling portion of the specific transistor is N+1, where N is an integer greater than or equal to zero.

[0012] For example, in an array substrate provided according to at least one embodiment of the present disclosure, on one side of the display area and in the second direction, there is a third distance between the first source line and an adjacent second source line, and the ratio between the distance between the second source line and the adjacent first portion and the third distance is 0.9 to 1.1.

[0013] For example, according to at least one embodiment of the present disclosure, the array substrate includes a plurality of first portions on one side of the display area, wherein the distance between adjacent first portions in the second direction is substantially equal to the third distance.

[0014] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the width of the first source line and the width of the second source line are substantially equal, and both are equal to the width of the first portion, wherein the width of the first portion is greater than the third distance.

[0015] For example, according to at least one embodiment of the array substrate provided in this disclosure, the filling portion includes at least one second portion, the second portion intersecting the extending direction of the first portion, the width of the second portion being smaller than the width of the first portion, wherein the second source line is connected to the adjacent first portion through the second portion, and / or the adjacent first portion is connected through the second portion.

[0016] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the first portion and the second portion are connected end to end.

[0017] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the filling portion located between the gate of the second transistor and the second source line connected to the second transistor is a part of the source of the second transistor. The source of the second transistor further includes a third portion in addition to the filling portion. The third portion includes a first sub-portion and a second sub-portion. One end of the first sub-portion is connected to one end of the second sub-portion, and the other end of the second sub-portion is connected to the filling portion. On one side of the display area, the first sub-portion extends along the first direction, and the extension direction of the second sub-portion intersects the extension direction of the first sub-portion. At least a portion of the first sub-portion overlaps with the gate of the second transistor in a direction perpendicular to the substrate. The width of the first sub-portion is smaller than the width of the second sub-portion.

[0018] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of signal lines include drain lines, the drain of each photosensitive transistor is connected to the drain lines, the drain lines are located on the side of the plurality of photosensitive transistors near the display area, the drain of the second transistor includes a third sub-part and a fourth sub-part, the third sub-part is connected to the fourth sub-part, on the side of the display area, the third sub-part extends along a first direction, the extension direction of the fourth sub-part intersects the extension direction of the third sub-part, the third sub-part is connected to the drain lines through the fourth sub-part, the third sub-part is spaced apart from the first sub-part, and the third sub-part overlaps with the gate of the second transistor in a direction perpendicular to the substrate, a fourth distance exists between the mutually distant edges of the second sub-part and the fourth sub-part of the second transistor, and the length of the first part is substantially equal to the fourth distance.

[0019] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of signal lines further include a plurality of first control lines and second control lines, the plurality of first control lines being located on the side of the plurality of photosensitive transistors near the display area; the second control lines being located between the plurality of photosensitive transistors and the plurality of first control lines; the array substrate further includes a plurality of electrostatic rings, the plurality of electrostatic rings being arranged sequentially at intervals in the circumferential direction of the display area and located on the side of the plurality of photosensitive transistors near the display area, each of the first control lines being connected to the second control line through the electrostatic ring, at least a portion of the electrostatic rings corresponding one-to-one with at least a portion of the photosensitive transistors in the arrangement direction perpendicular to the plurality of photosensitive transistors, and the extension line of the center line of the first control line connected to the electrostatic ring passing through the photosensitive transistor corresponding to the electrostatic ring.

[0020] For example, according to at least one embodiment of the array substrate provided in this disclosure, the drain of the second transistor includes a bent portion, the orthographic projection of the bent portion on the substrate being "C" shaped, and the extension of the center line of the first control line connected to the electrostatic ring passing through the bent portion to divide the bent portion into two parts located on both sides of the extension of the center line, the ratio of the dimensions of the two parts in the direction perpendicular to the center line being 0.9 to 1.1.

[0021] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of photosensitive transistors include a plurality of transistor groups, the array substrate includes a color resist layer, the color resist layer is located on the side of the plurality of transistor groups away from the substrate, each transistor group includes the same number of photosensitive transistors, the color resist layer includes a plurality of color resist portions of different colors, and the plurality of color resist portions of different colors correspond one-to-one with the plurality of transistor groups, each color resist portion is located on the side of the corresponding transistor group away from the substrate, and the number of extension lines of the center line of the first control line overlapping with each color resist portion is equal.

[0022] For example, in an array substrate provided according to at least one embodiment of the present disclosure, adjacent color resist portions are disposed close together, and the plurality of first control lines include specific control lines, the extension of the center line of the specific control lines serving as the boundary line between adjacent color resist portions.

[0023] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of transistor groups include a plurality of measurement transistor groups and a reference transistor group, the plurality of color resist portions of different colors include a plurality of measurement color resist portions and a reference color resist portion, each of the measurement color resist portions being located on the side of the measurement transistor group away from the substrate, the reference color resist portion being located on the side of the reference transistor group away from the substrate, the array substrate further includes a light-shielding layer, the light-shielding layer being located on the side of the color resist layer away from the substrate, and the light-shielding layer covering the reference transistor group, the light-shielding layer including a plurality of openings, the openings exposing at least a portion of the channel region of the photosensitive transistor in the measurement transistor group.

[0024] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of measurement transistor groups include a first type of transistor group and a second type of transistor group, the plurality of measurement color resist portions include a first color resist portion and a second color resist portion, the first color resist portion is located on the side of the first type of transistor group away from the substrate, the second color resist portion is located on the side of the second type of transistor group away from the substrate, the transmittance of the first color resist portion is greater than the transmittance of the second color resist portion, the plurality of openings include a plurality of first openings and a plurality of second openings, the first openings expose at least a portion of the channel region of the photosensitive transistor in the first type of transistor group, the second openings expose at least a portion of the channel region of the photosensitive transistor in the second type of transistor group, and the orthographic projection area of ​​the first opening on the substrate is smaller than the orthographic projection area of ​​the second opening on the substrate.

[0025] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of signal lines further include temperature sensing lines located on the side of the plurality of photosensitive transistors away from the display area. The temperature sensing lines include a plurality of first temperature sensing portions and a plurality of second temperature sensing portions, which are alternately arranged in sequence. The first temperature sensing portions are connected to the second temperature sensing portions. At least a portion of the first temperature sensing portions extends along the arrangement direction of the plurality of photosensitive transistors. The extension direction of the second temperature sensing portions intersects with the extension direction of the first temperature sensing portions. At least a portion of the photosensitive transistors and at least a portion of the second temperature sensing portions correspond one-to-one in the arrangement direction perpendicular to the plurality of photosensitive transistors. The center line of the first control line passing through the photosensitive transistors also passes through the second temperature sensing portion corresponding to the photosensitive transistors.

[0026] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of signal lines further include a common electrode line located on the side of the temperature-sensing line away from the plurality of photosensitive transistors. The array substrate further includes a transparent structure located between the temperature-sensing line and the common electrode line and disposed around the display area. The transparent structure includes a plurality of spaced-apart transparent substructures. At least a portion of the first temperature-sensing portion and at least a portion of the transparent substructures correspond one-to-one in a direction perpendicular to the arrangement of the plurality of photosensitive transistors. An extension of the center line of the first control line passing through the second temperature-sensing portion passes through the gap between adjacent transparent substructures.

[0027] For example, according to at least one embodiment of the present disclosure, the display area has a plurality of sub-pixels arranged in an array, and the distance between adjacent measuring transistor groups is the sum of the sizes of 5 to 10 consecutively arranged sub-pixels in the arrangement direction of the plurality of photosensitive transistors.

[0028] At least one embodiment of this disclosure provides a display device, which includes an array substrate, a counter substrate, and a liquid crystal layer provided in any embodiment of this disclosure, wherein the counter substrate is disposed opposite to the array substrate; and the liquid crystal layer is located between the array substrate and the counter substrate. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0030] Figure 1 This is a partial planar schematic diagram of an array substrate.

[0031] Figure 2 This is a planar schematic diagram of an array substrate provided for at least one embodiment of the present disclosure.

[0032] Figure 3 This is a partial planar schematic diagram of an array substrate provided for at least one embodiment of the present disclosure.

[0033] Figure 4 A partial planar schematic diagram of another array substrate provided for at least one embodiment of the present disclosure.

[0034] Figure 5 A partial planar schematic diagram of another array substrate provided for at least one embodiment of the present disclosure.

[0035] Figure 6 for Figure 5 An enlarged schematic diagram of the bent portion of the drain electrode of the second transistor.

[0036] Figure 7 An equivalent circuit diagram of a light-sensing unit provided for at least one embodiment of the present disclosure.

[0037] Figure 8A A partial planar schematic diagram of another array substrate provided for at least one embodiment of the present disclosure.

[0038] Figure 8B A partial cross-sectional schematic diagram of an array substrate provided for at least one embodiment of the present disclosure.

[0039] Figure 9 A partial planar schematic diagram of another array substrate provided for at least one embodiment of the present disclosure.

[0040] Figure 10 This is a schematic diagram of the connection between the gate and gate line of a photosensitive transistor in an array substrate provided for at least one embodiment of the present disclosure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0043] The features "perpendicular," "parallel," and "identical" used in this disclosure include features in the strict sense of "perpendicular," "parallel," and "identical," as well as cases where "approximately perpendicular," "approximately parallel," and "approximately identical" include certain errors. Considering measurement and errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. The "center" in this disclosure can include a strictly geometrically central location and a roughly central location within a small area surrounding the geometrically central location.

[0044] Figure 1 This is a partial planar schematic diagram of an array substrate.

[0045] like Figure 1 As shown, the array substrate includes multiple signal lines and multiple phototransistors 200, each phototransistor 200 including a source 201, a gate 203, and a drain 202. The multiple signal lines include multiple source lines, such as source line 110, source line 1201, source line 1202, and source line 1203. For example, the lengths of each source line in its extension direction are different, and the types of phototransistors 200 connected to them are different. For example, the different types of phototransistors refer to the different color resist materials matched to the multiple phototransistors, resulting in different colors of received light. For example, some phototransistors can be matched with a red color resist layer, thereby receiving red light. For example, the transistor connected to source line 110 is the first transistor, and the transistor connected to source line 1201 is the second transistor. The multiple signal lines also include a drain line 130 and a gate line 014. The drain 202 of each phototransistor 200 is connected to the drain line 130, and the gate of each phototransistor 200 is connected to the gate line 014.

[0046] according to Figure 1 It is known that the distance between the gate 203 and the corresponding source line of different types of phototransistors 200 is different, and the length (including the part of the source 201 that overlaps with the gate 203 and the part that extends to the outside of the gate 203 to connect with the source line 110) and shape of the source 201 of different types of phototransistors 200 are different, so as to have different wiring methods. This results in different wiring densities in regions A0, A1, A2 and A3, and the film thickness of each region is different, which will cause differences in the rubbing environment, thereby increasing the risk of rubbing mura.

[0047] At least one embodiment of this disclosure provides an array substrate, including a substrate, a display area and a non-display area located on the substrate, and a plurality of photosensitive transistors. At least a portion of the non-display area surrounds the display area, and the non-display area has a plurality of signal lines, each signal line at least partially surrounding the display area. The plurality of photosensitive transistors are located on the substrate and within the non-display area, and are arranged around the display area. Each photosensitive transistor includes a source, a gate, and a drain. The plurality of photosensitive transistors include a first transistor and at least one second transistor, the first transistor and the second transistor being configured to interact with color resist materials of different colors. The matching consists of multiple signal lines, including a first source line and at least one second source line. The source of a first transistor is connected to the first source line. The at least one second source line corresponds one-to-one with at least one second transistor. The source of the second transistor is connected to the second source line. There is a first distance between the gate of the first transistor and the first source line connected to the source of the first transistor. There is a second distance between the gate of the second transistor and the second source line connected to the source of the second transistor. The second distance is greater than the first distance. A filling portion is provided between the gate of the second transistor and the second source line connected to the source of the second transistor.

[0048] In at least one embodiment of the array substrate provided in this disclosure, a first distance between the gate of a first transistor and a first source line connected to the source of the first transistor is smaller than a second distance between the gate of a second transistor and a second source line connected to the source of the second transistor, and a filling portion is provided between the gate of the second transistor and the second source line connected to the source of the second transistor, thereby reducing the difference in film thickness between the gate of the first transistor and the corresponding first source line and between the gate of the second transistor and the corresponding second source line, thereby making the rubbing environment more uniform and reducing the risk of rubbing mura.

[0049] At least one embodiment of this disclosure also provides a display device, which includes an array substrate provided in any embodiment of this disclosure.

[0050] The array substrate and display device provided in the embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings, so that the corresponding technical solutions can be clearer and easier to understand.

[0051] Figure 2 A plan view of an array substrate provided in at least one embodiment of this disclosure; Figure 3 This is a partial planar schematic diagram of an array substrate provided for at least one embodiment of the present disclosure.

[0052] like Figure 2As shown, the array substrate includes a substrate 001 and a display area 10 and a non-display area 20 located on the substrate 001. The display area 10 is configured to display an image. At least a portion of the non-display area 20 surrounds the display area 10. For example, the display area 10 is surrounded by the non-display area 20. For example, the non-display area 20 may also be referred to as a peripheral area. The non-display area 20 has a plurality of signal lines 100, each signal line 100 having at least a portion surrounding the display area 10. For example, the plurality of signal lines 100 may include a ground wire GND, an internal jumper wire ISR, an electrostatic discharge connection element ESDC, etc. The embodiments of this disclosure do not limit the type of signal lines 100.

[0053] like Figure 2 and Figure 3 As shown, the array substrate also includes a plurality of photosensitive transistors 200 located on the substrate 001. The plurality of photosensitive transistors 200 are located in the non-display area 20 and are arranged around the display area 10. For example, the photosensitive transistors 200 can detect changes in ambient light brightness and make appropriate adjustments by adjusting elements (e.g., backlight elements) to ensure brightness uniformity across the entire array substrate. In some cases, the plurality of photosensitive transistors 200 can also reflect the color temperature of the environment.

[0054] like Figure 2 and Figure 3 As shown, the photosensitive transistor 200 includes a source 201, a gate 203, and a drain 202. Multiple photosensitive transistors 200 include a first transistor 210 and at least one second transistor 220, the first transistor 210 and the second transistor 220 being configured to match different colors of color resist materials. For example, the first transistor 210 and the second transistor 220 are configured to receive different colors of light to sense changes in the brightness of different colors of light.

[0055] like Figure 2 and Figure 3 As shown, the multiple signal lines 100 include a first source line 110 and at least one second source line 120. The source 201 of the first transistor 210 is connected to the first source line 110, and the at least one second source line 120 corresponds one-to-one with at least one second transistor 220. The source 201 of the second transistor 220 is connected to the second source line 120. For example, the multiple signal lines 100 also include a gate line 014 and a drain line 130. The gates 203 of multiple photosensitive transistors 200 are all connected to the gate line 014, and the drains 202 of multiple photosensitive transistors 200 are all connected to the drain line 130. For example, the gate line 014, the first source line 110, the second source line 120, the drain line 130, and the photosensitive transistors 200 can all be located on the first side S1, the second side S2, and the third side S3 of the display area 10. For clarity, Figure 3The following description will take the portion of the gate line 014, the first source line 110, the second source line 120, the drain line 130, and the photosensitive transistor 200 located on the first side S1 as an example. For instance, on the first side S1 of the display area 10, the gate line 014, the first source line 110, the second source line 120, and the drain line 130 extend along the first direction X and are arranged along the second direction Y.

[0056] like Figure 2 and Figure 3 As shown, there is a first distance L1 between the gate 203 of the first transistor 210 and the first source line 110 connected to the source 201 of the first transistor 210, and a second distance L2 between the gate 203 of the second transistor 220 and the second source line 120 connected to the source 201 of the second transistor 220. The second distance L2 is greater than the first distance L1. For example, in the second direction Y, the first distance L1 can be the average distance between the gate 203 of the first transistor 210 and the first source line 110 connected to the source 201 of the first transistor 210, and the second distance L2 can be the average distance between the gate 203 of the second transistor 220 and the second source line 120 connected to the source 201 of the second transistor 220.

[0057] like Figure 2 and Figure 3 As shown, a filling portion 300 is provided between the gate 203 of the second transistor 220 and the second source line 120 connected to the source 201 of the second transistor 220. For example, on the first side S1 of the display area 10, the filling portion 300 overlaps with the gate 203 of the second transistor 220. For example, the filling portion 300 may have a specific shape depending on the size of the layout space, and the embodiments of this disclosure are not limited in this respect.

[0058] In at least one embodiment of the array substrate provided in this disclosure, a first distance between the gate of a first transistor and a first source line connected to the source of the first transistor is smaller than a second distance between the gate of a second transistor and a second source line connected to the source of the second transistor, and a filling portion is provided between the gate of the second transistor and the second source line connected to the source of the second transistor, thereby reducing the difference in film thickness between the gate of the first transistor and the corresponding second source line and between the gate of the second transistor and the corresponding second source line, thereby making the rubbing environment more uniform and reducing the risk of rubbing mura.

[0059] For example, such as Figure 3As shown, the fill portion 300 located between the gate 203 of the second transistor 220 and the corresponding second source line 120 of the second transistor 220 is a part of the source 201 of the second transistor 220. For example, the fill portion 300 is a part of the source 201 of the second transistor 220 located on the side of the gate 203 near the second source line 120, and the fill portion 300 is connected to the corresponding second source line 120 of the second transistor 220.

[0060] This configuration helps to make the signal transmitted to the source of the second transistor more uniform and simplifies the manufacturing process.

[0061] For example, such as Figure 3 As shown, the length of the first source line 110 is less than the length of the second source line 120. The first source line 110 is spaced apart from the source 201 of the second transistor 220 (e.g., in the first direction X), and the extension line 1101 of the first source line 110 intersects with the fill portion 300 located between the gate 203 of the second transistor 220 and the corresponding second source line 120 of the second transistor 220. For example, on the first side S1 of the display area 10, both the first source line 110 and the second source line 120 extend along the first direction X, and the length of the first source line 110 refers to its dimension in its extension direction. For example, the fill portion 300 includes a portion extending along the first direction X, and this portion intersects with the first source line 110.

[0062] With this configuration, while at least a portion of the space between the second transistor and its corresponding second source line is occupied by the filling portion, the difference in film thickness between the region between the gate of the first transistor and the first source line and the region between the gate of the second transistor and the second source line can be reduced by making the filling portion intersect with the extension line of the first source line, so as to make the rubbing environment more uniform.

[0063] For example, such as Figure 3 As shown, the filling portion 300 includes at least one first portion 310, at least a portion of the second source line 120 extends along the first direction X, and at least a portion of the second source line 120 is located on one side of the display area 10 in the second direction Y. In the second direction Y, the first portion 310 overlaps with the gate 203 of the second transistor 220 connected to the second source line 120. For example, on the first side S1 of the display area 10, both the first portion 310 and the second source line 120 extend along the first direction X. The first portion 310 is located between the gate 203 of the second transistor 220 and the second source line 120 to which the second transistor 220 is connected, and the first portion 310 intersects with the extension line 1101 of the first source line 110.

[0064] By having a first portion between the gate of the second transistor and its connected second source line, and the first portion extending in the same direction as the first source line, the rubbing environment between the gate of the second transistor and its connected second source line can be improved by the first portion. For example, in the second direction Y, the difference between the rubbing environment between the first transistor and the first source line and the rubbing environment between the second transistor and the second source line can be smaller, thereby reducing the risk of rubbing mura.

[0065] For example, such as Figure 3 As shown, at least one second source line in the array substrate includes a first type source line 1201, a second type source line 1202, and a third type source line 1203. For example, on the first side S1 of the display area 10, the first type source line 1201, the second type source line 1202, and the third type source line 1203 are spaced apart in the second direction Y and all extend along the first direction X. For example, at least one second transistor 220 in the array substrate includes a first type transistor 2201, a second type transistor 2202, and a third type transistor 2203. The source 201 of the first type transistor 2201 is connected to the first type source line 1201, the source 201 of the second type transistor 2202 is connected to the second type source line 1202, and the source 201 of the third type transistor 2203 is connected to the third type source line 1203. For example, the first transistor 210, the first type transistor 2201, the second type transistor 2202, and the third type source line 1203 are arranged sequentially on one side of the display area 10 (e.g., the first side S1).

[0066] For example, such as Figure 3 As shown, the gate 203 of the first type transistor 2201 and the first type source line 1201 have a first sub-distance M1 in the direction perpendicular to the first type source line; the gate 203 of the second type transistor 2202 and the second type source line 1202 have a second sub-distance M2 in the direction perpendicular to the second type source line; and the gate 203 of the third type transistor 2203 and the third type source line 1203 have a third sub-distance M3 in the direction perpendicular to the third type source line. The first sub-distance M1 is smaller than the second sub-distance M2, and the second sub-distance M2 is smaller than the third sub-distance M3. For example, the aforementioned first type source line direction, second type source line direction, and third type source line direction all refer to the extension direction. For example, on the first side S1 of the display area 10, the first type source line direction, the second type source line direction, and the third type source line direction are all the first direction X.

[0067] Therefore, the layout space between the gate and the source line of the first type of transistor is relatively small, the layout space between the gate and the source line of the second type of transistor is next, and the layout space between the gate and the source line of the third type of transistor is relatively large.

[0068] For example, such as Figure 3 As shown, at least a portion of the first source line 110 extends along a first direction X. The first portion 310 located between the gate 203 of the first type transistor 2201 and the first type source line 1201 includes a first extension portion 3101. The extension direction of the first extension portion 3101 is the same as the extension direction of the first source line 110, and the extension line 1101 of the first source line 110 passes through the first extension portion 3101. For example, on the first side S1 of the display area 10, both the first extension portion 3101 and the first type source line 1201 extend along the first direction X, and the first extension portion 3101 coincides with the extension line 1101 of the first source line 110.

[0069] For example, such as Figure 3 As shown, the first portion 310 located between the gate 203 of the second type transistor 2202 and the second type source line 1202 includes a second extension portion 3102. The extension direction of the second extension portion 3102 is the same as the extension direction of the first type source line 1201, and the extension line of the first type source line 1201 passes through the second extension portion 3102. For example, on the first side S1 of the display area 10, both the second extension portion 3102 and the first type source line 1201 extend along the first direction X, and the second extension portion 3102 coincides with the extension line of the first type source line 1201.

[0070] For example, such as Figure 3 As shown, the first portion 310 located between the gate 203 of the third type transistor 2203 and the third type source line 1203 includes a third extension portion 3103. The extension direction of the third extension portion 3103 is the same as the extension direction of the second type source line 1202, and the extension line of the second type source line 1202 passes through the third extension portion 3103. For example, on the first side S1 of the display area 10, both the second extension portion 3102 and the second type source line 1202 extend along the first direction X, and the second extension portion 3102 coincides with the extension line of the second type source line 1202.

[0071] By ensuring that the first portion between the gate and the corresponding source line of each type of transistor includes an extension that coincides with the extension of the source line corresponding to the adjacent transistor, the wiring density in the extension direction of the source line (e.g., in the first direction X) can be made more uniform and the layout space utilization more reasonable. This helps to reduce the difference in film thickness of the array substrate and reduce the risk of Rubbing Mura.

[0072] For example, such as Figure 3 As shown, the at least one second source line 120 in the array substrate includes a specific source line 1200, and the at least one second transistor 220 includes a specific transistor 2200, with the source 201 of the specific transistor 2200 electrically connected to the specific source line 1200. For example, if there are N second source lines 120 between the first source line 110 and the specific source line 1200, then the number of the first portion 310 of the filling portion 300 of the specific transistor 2200 is N+1, where N is an integer greater than or equal to zero.

[0073] For example, such as Figure 3 As shown, the specific source line 1200 is one of the at least one second source line 120 in the array substrate. For example, a first type source line 1201, a second type source line 1202, or a third type source line 1203 can be used as the specific source line 1200. For example, the specific transistor 2200 is one of the at least one second transistor 220, such as a first type transistor 2201, a second type transistor 2202, or a third type transistor 2203.

[0074] For example, such as Figure 3 As shown, taking a specific source line 1200 as a first type source line 1201 and a specific transistor 2200 as a first type transistor 2201 as an example, there are zero second source lines 120 between the first source line 110 and the first type source line 1201, so the number of the first portion 310 of the filling portion 300 of the first type transistor 2201 is 1.

[0075] For example, such as Figure 3 As shown, taking a specific source line 1200 as a second type source line 1202 and a specific transistor 2200 as a second type transistor 2202 as an example, there is one second source line 120 (i.e., the first type source line 1201) between the first source line 110 and the second type source line 1202, so the number of the first portion 310 of the filling portion 300 of the second type transistor 2202 is 2.

[0076] For example, such as Figure 3 As shown, taking a specific source line 1200 as a third type source line 1203 and a specific transistor 2200 as a third type transistor 2203 as an example, there are two second source lines 120 (i.e., the first type source line 1201 and the second type source line 1202) between the first source line 110 and the third type source line 1203, so the number of the first portion 310 of the filling portion 300 of the third type transistor 2203 is 3.

[0077] This configuration allows for a more balanced number of traces extending circumferentially along the display area on the side of the gate of a specific transistor that is furthest from the display area. This helps to make the wiring density in the first direction more uniform, thereby balancing the impact of the number of traces on the uniformity of the film thickness and reducing the risk of Rubbing Mura.

[0078] For example, such as Figure 3 As shown, in the second type transistor 2202, the first portion 310 of the filling portion 300 near the gate 203 intersects with the first source line 110, and the first portion 310 of the filling portion 300 away from the gate 203 intersects with the extension of the first type source line 1201. For example, in the third type transistor 2203, the first portion 310 of the filling portion 300 near the gate 203 intersects with the first source line 110, another first portion 310 adjacent to this first portion 310 intersects with the extension of the first type source line 1201, and the first portion 310 of the filling portion 300 away from the gate 203 intersects with the extension of the second type source line 1202.

[0079] This configuration can further make the wiring density more uniform in the extension direction of the source line and balance the impact of the number of traces on the uniformity of film thickness, thereby reducing the risk of Rubbing Mura.

[0080] For example, such as Figure 3 As shown, in the second direction Y, there is a third distance L3 between the first source line 110 and the adjacent second source line 120 (e.g., the first type source line 1201), and the distance between the second source line 120 and the adjacent first portion 310 is substantially equal to the third distance L3. For example, the distances between the first type source line 1201, the second type source line 1202, or the third type source line 1203 and the adjacent first portion 310 are all equal to the third distance L3.

[0081] This allows for a more uniform wiring density in the arrangement direction of multiple second source lines, which helps to reduce the phenomenon of uneven film thickness.

[0082] For example, such as Figure 3 As shown, when the filling portion 300 includes a plurality of first portions 310, the distance between adjacent first portions 310 in the arrangement direction of the plurality of second source lines 120 (such as in the second direction Y) is approximately equal to the third distance L3.

[0083] Thus, the differences in wiring density can be balanced by multiple first parts, and the rubbing mura caused by differences in film thickness can be reduced.

[0084] For example, such as Figure 3 As shown, the width of the first source line 110 and the width of the second source line 120 are basically equal, and both are equal to the width of the first portion 310. This arrangement simplifies the process, facilitates uniform wiring, and allows for better control of the film thickness in each region of the array substrate.

[0085] For example, such as Figure 3 As shown, the width N1 of the first part 310 is greater than the third distance L3, which can reduce the transmission resistance of the first part, so as to ensure the stability of signal transmission while controlling the risk of Rubbing Mura.

[0086] For example, such as Figure 3 As shown, the third distance L3 can be 10 to 13 micrometers, such as 11 micrometers, 11.5 micrometers, 12 micrometers, or 12.5 micrometers, and can be set according to design requirements. For example, the width N1 of the first part 310 can be 12 to 16 micrometers, such as 13 micrometers, 14 micrometers, 14.5 micrometers, or 15 micrometers, and the embodiments disclosed herein do not limit this.

[0087] For example, such as Figure 3 As shown, the filling portion 300 may include at least one second portion 320 extending along a direction perpendicular to the arrangement direction of the plurality of second source lines 120 (e.g., the second direction Y). The second source lines 120 are connected to the adjacent first portion 310 through the second portion 320. For example, the second portion 320 may be a part of the filling portion 300. The first portion 310 and the second portion 320 are connected end-to-end. For example, for the filling portion 300 located between the gate 203 of the first type transistor 2201 and the first type source line 1201, the filling portion 300 includes a second portion 320, one end of which is connected to one end of the first portion 310, and the other end of which is connected to the second source line 120.

[0088] For example, such as Figure 3 As shown, the filling portion 300 located between the gate 203 and the source line 1202 of the second type transistor 2202 includes a plurality of first portions 310 and a plurality of second portions 320. Adjacent first portions 310 are connected through second portions 320, and the second type source line 1202 is connected to the adjacent first portion 310 through the second portion 320. For example, the length of the second portion 320 is less than the length of the first portion 310. For example, the length of the second portion 320 can be substantially the same as the third distance L3 described above.

[0089] For example, such as Figure 3As shown, the fill portion 300 located between the gate 203 of the second transistor 220 and the corresponding second source line 120 of the second transistor 220 is part of the source 201 of the second transistor 220. The source 201 of the second transistor 220 also includes a third portion 330 in addition to the fill portion 300. For example, the third portion 330 is located on the side of the fill portion 300 near the gate 203 of the second transistor 220, and the third portion 330 is connected to the fill portion 300.

[0090] For example, such as Figure 3 As shown, the third part 330 includes a first sub-part 3301 and a second sub-part 3302. One end of the first sub-part 3301 is connected to one end of the second sub-part 3302, and the other end of the second sub-part 3302 is connected to the filling part 300. The extending direction of the second sub-part 3302 intersects the extending direction of the first sub-part 3301; for example, the extending direction of the second sub-part 3302 is perpendicular to the extending direction of the first sub-part 3301. For example, on the first side S1 of the display area 10, the first sub-part 3301 extends along a first direction X, and the second sub-part 3302 extends along a second direction Y.

[0091] For example, such as Figure 3 As shown, at least a portion of the first sub-part 3301 overlaps with the gate 203 of the second transistor 220 in a direction perpendicular to the substrate 001, and the width of the first sub-part 3301 is smaller than the width of the second sub-part 3302. For example, one end of the first sub-part 3301 is located outside the gate 203 of the second transistor 220 and is connected to the second sub-part 3302, such that the second sub-part 3302 is spaced apart from the gate 203 of the second transistor 220.

[0092] By making the width of the first sub-part smaller than the width of the second sub-part, the parasitic capacitance between the first sub-part and the gate can be reduced, and the signal transmission channel can be expanded through the second sub-part, which is beneficial for uniform and stable signal transmission.

[0093] For example, such as Figure 3 As shown, the width of the second sub-part 3302 is smaller than the width N1 of the first part 310, thereby further expanding the signal transmission channel through the first part 310 to enable effective signal transmission.

[0094] For example, such as Figure 3 As shown, the width N2 of the second part 320 is smaller than the width N1 of the first part 310. For example, the width N2 of the second part 320 can be substantially the same as the width of the second sub-part 3302, which helps to make the trace width uniform in the extension direction of the second part (such as the second direction Y), so as to ensure the uniformity of the rubbing environment.

[0095] For example, such as Figure 3 As shown, the multiple signal lines 100 in the array substrate include drain lines 130. The drains 202 of each phototransistor 200 are connected to the drain lines 130, and the drain lines 130 are located on the side of the multiple phototransistors 200 closer to the display area 10.

[0096] For example, such as Figure 3 As shown, the drain 202 of the second transistor 2202 includes a third sub-part 2021 and a fourth sub-part 2022. The third sub-part 2021 and the fourth sub-part 2022 are connected, and the extending direction of the fourth sub-part 2022 intersects the extending direction of the third sub-part 2021. For example, the extending direction of the fourth sub-part 2022 is perpendicular to the extending direction of the third sub-part 2021. For example, the extending direction of the third sub-part 2021 is the same as the extending direction of the first part 310, and the extending direction of the fourth sub-part 2022 is the same as the extending direction of the second part 320. For example, on the first side S1 of the display area 10, the third sub-part 2021 extends along the first direction X, and the fourth sub-part 2022 extends along the second direction Y.

[0097] For example, such as Figure 3 As shown, the third sub-part 2021 is connected to the drain line 130 via the fourth sub-part 2022. The third sub-part 2021 is spaced apart from the first sub-part 3301, and the third sub-part 2021 overlaps with the gate 203 of the second transistor 220 in a direction perpendicular to the substrate 001. For example, in the second direction Y, there is a fourth distance L4 between the edges of the second sub-part 3302 and the fourth sub-part 2022 of the second transistor 220 that are far apart from each other, and the length of the first part 310 is substantially equal to the fourth distance L4.

[0098] This configuration ensures that the length of the first part corresponding to each second transistor is uniform, which helps to improve the utilization of layout space.

[0099] It should be noted that, Figure 3 The relative positions of the components in the display panel and the structural features of each component are shown only schematically, and do not represent the actual dimensions of each component.

[0100] Figure 4 A partial planar schematic diagram of another array substrate provided for at least one embodiment of the present disclosure.

[0101] For example, such as Figure 4 As shown, the array substrate and Figure 3 The difference between the shown photosensitive transistors lies in the source 201 of the second transistor 220, and the array substrate also includes multiple dummy transistors 2204. The remaining structures can be found in the embodiments described above. Figure 3The relevant descriptions will not be repeated here.

[0102] For example, such as Figure 4 As shown, the array substrate includes a plurality of second transistors 220. A filler portion 300 located between the gate 203 of a second transistor 220 and the corresponding second source line 120 of that second transistor 220 is electrically connected to the corresponding second source line 120. For example, the plurality of second transistors 220 includes a first-type transistor 2201, a second-type transistor 2202, and a third-type transistor 2203. The source 201 of the first-type transistor 2201 is connected to the first-type source line 1201, the source 201 of the second-type transistor 2202 is connected to the second-type source line 1202, and the source 201 of the third-type transistor 2203 is connected to the third-type source line 1203. For example, the plurality of second transistors 220 may include a plurality of first-type transistors 2201, and the sources of the plurality of first-type transistors 2201 may have different structural forms.

[0103] For example, such as Figure 4 As shown, the source 201 of the first type transistor 2201 can overlap with the gate 203 of the dummy transistor 2204. For example, the source 201 of the first type transistor 2201 can overlap with the gate 203 of the first type transistor 2201. For example, the lengths of the sources 201 of multiple first type transistors 2201 are not the same, and the embodiments of this disclosure do not limit the structural form of the source of the first type transistor.

[0104] For example, refer to Figure 4 The plurality of second transistors 220 may include a plurality of second-type transistors 2202, and the sources 201 of the plurality of second-type transistors 2202 may also have different structural forms. For example, a portion of the source 201 of the second-type transistor 2202 may be located between the gate 203 of the first-type transistor 2201 and the first-type source line 1201, or may overlap with the gate 203 of the dummy transistor 2204. For example, a portion of the source 201 of the second-type transistor 2202 may also overlap with the gate 203 of the first-type transistor 2201, and another portion of the source 201 of the second-type transistor 2202 may overlap with the gate 203 of the dummy transistor 2204. Specifically, it can be flexibly designed according to the layout space to reduce the difference in film thickness in each region.

[0105] For example, refer to Figure 4The plurality of second transistors 220 may include a plurality of third-type transistors 2203, and the sources 201 of the plurality of third-type transistors 2203 may also have different structural forms. For example, a portion of the source 201 of the third-type transistor 2203 may be located between the gate 203 of the second-type transistor 2202 and the second-type source line 1202, or may overlap with the gate 203 of the dummy transistor 2204. For example, a portion of the source 201 of the third-type transistor 2203 may also overlap with the gate 203 of the second-type transistor 2202, and another portion of the source 201 of the third-type transistor 2203 may overlap with the gate 203 of the dummy transistor 2204. Specifically, it can be flexibly designed according to the layout space, thereby reducing the difference in film thickness in each region.

[0106] Figure 5 A partial planar schematic diagram of another array substrate provided for at least one embodiment of the present disclosure; Figure 6 for Figure 5 An enlarged schematic diagram of the bent portion of the drain electrode of the second transistor.

[0107] For example, such as Figure 5 As shown, the multiple signal lines 100 in the array substrate include multiple first control lines 140 and second control lines 150. The multiple first control lines 140 are located on the side of the multiple photosensitive transistors 200 near the display area 10, and the second control lines 150 are located between the multiple photosensitive transistors 200 and the multiple first control lines 140. For example, the first control lines 140 are configured to transmit data signals to multiple sub-pixels in the display area 10. For example, the multiple first control lines 140 are spaced apart along a first direction X, and each first control line 140 extends along a second direction Y. For example, the width of the first control lines 140 is 8 to 10 micrometers, such as 8 micrometers, 9 micrometers, 9.5 micrometers, or 10 micrometers. For example, in the second direction Y, the distance between the second control line 150 and the gate line 014 is 25 to 35 micrometers, such as 28 micrometers, 30 micrometers, or 32 micrometers; the embodiments of this disclosure do not limit this.

[0108] For example, such as Figure 5 As shown, the array substrate also includes multiple electrostatic rings 400, which are located on the side of the multiple photosensitive transistors 200 near the display area 10, and are arranged at intervals in the arrangement direction of the multiple photosensitive transistors 200. Each first control line 140 is connected to a second control line 150 through an electrostatic ring 400. For example, multiple first control lines 140 are respectively connected to the second control line 150 through electrostatic rings 400 to release static electricity through the second control line 150. Figure 5 The structure of the electrostatic ring is shown only schematically, but the embodiments of this disclosure do not limit the structure of the electrostatic ring.

[0109] For example, such as Figure 5 As shown, at least a portion of the electrostatic rings 400 correspond one-to-one with at least a portion of the photosensitive transistors 200 in a circumferential direction perpendicular to the display area 10. For example, on the first side S1 of the display area 10, a plurality of electrostatic rings 400 are arranged at intervals along a first direction X, and a plurality of photosensitive transistors 200 are arranged at intervals along the first direction X. For example, the electrostatic rings 400 and their corresponding photosensitive transistors 200 overlap in a second direction Y. For example, the extension of the center line of the first control line 140 connected to the electrostatic ring 400 passes through the photosensitive transistor 200 corresponding to the electrostatic ring 400. For example, the first control line 140 may be located on the same layer as the source and drain of the photosensitive transistor 200 and formed using the same patterning process.

[0110] By having the photosensitive transistor and its corresponding electrostatic ring pass through the extension of the center line of the same first control line, it is beneficial to make the film thickness more uniform in each direction of the first control line, thereby helping to ensure the uniformity of the Rubbing environment.

[0111] For example, such as Figure 5 As shown, the drain 202 of the second transistor 2202 includes a bent portion 2002, and the orthographic projection of the bent portion 2002 on the substrate 001 is "C" shaped. For example, the extension of the center line of the first control line 140 connected to the electrostatic ring 400 passes through the bent portion 2002 to divide the bent portion 2002 into two parts located on both sides of the extension of the center line of the first control line 140, the ratio of the dimensions of the two parts in the direction perpendicular to the center line of the first control line 140 being 0.9 to 1.1.

[0112] For example, such as Figure 5 and Figure 6 As shown, on the first side S1 of the display area 10, the center line of the first control line 140 extends along the second direction Y, and the two portions of the curved portion 2002 located on both sides of the extension line of the center line of the first control line 140 have dimensions P1 and P2 respectively in the first direction X. For example, P1 and P2 are substantially equal.

[0113] This configuration ensures that the two parts of the curved portion located on either side of the extension of the center line of the first control line occupy approximately the same amount of layout space, thereby making the influence of these two parts on the film thickness more uniform and thus helping to ensure the uniformity of the Rubbing environment.

[0114] For example, such as Figure 5As shown, the plurality of photosensitive transistors 200 include a plurality of transistor groups 2000, and each transistor group 2000 includes the same number (e.g., 40-50) of photosensitive transistors 200. The array substrate includes a color resist layer 500, and the color resist layer 500 is located on the side of the plurality of transistor groups 2000 away from the substrate 001. For example, the color resist layer 500 covers the plurality of transistor groups 2000. For example, the color resist layer 500 includes a plurality of color resist portions 5000 of different colors, and the plurality of color resist portions 5000 of different colors correspond one-to-one with the plurality of transistor groups 2000. Each color resist portion 5000 is located on the side of the corresponding transistor group 2000 away from the substrate 001. For example, one color resist portion 5000 is located on the side of one transistor group 2000 away from the substrate 001. For example, the color resist portion 5000 can serve as a filter layer. For example, when ambient light reaches the color resist section 5000 of different colors, it is filtered by the color resist section 5000. The portion of light with the same color as the color resist section 5000 reaches the transistor group 2000 corresponding to the color resist section 5000, and then each photosensitive transistor 200 responds to the corresponding electrical signal according to the received light.

[0115] For example, such as Figure 5 As shown, in the first direction X, the size of the color resist portion 5000 is 8000 to 9000 micrometers, such as 8200 micrometers, 8500 micrometers, 8600 micrometers, or 8800 micrometers. For example, in the second direction Y, the size of the color resist portion 5000 is 600 to 650 micrometers, such as 610 micrometers, 620 micrometers, 630 micrometers, or 640 micrometers, and the embodiments of this disclosure are not limited thereto.

[0116] For example, such as Figure 5 As shown, the number of extension lines of the center line of the first control line 140 that overlaps with each color resist portion 5000 is equal. For example, on the first side S1 of the display area 10, the bent portion 2002 of each photosensitive transistor 200 located on the side of the color resist portion 5000 near the substrate 001 is traversed by the extension line of the center line of the first control line 140. Since the number of photosensitive transistors 200 in the plurality of transistor groups 2000 is equal, the number of extension lines of the center line of the first control line 140 located on the side of the plurality of color resist portions 5000 near the substrate 001 is the same.

[0117] For example, such as Figure 5 As shown, adjacent color resist portions 5000 are arranged close together, meaning that no other color resist portions are arranged between adjacent color resist portions 5000. For example, the plurality of first control lines 140 includes a specific control line 1400, and the extension of the center line of the specific control line 1400 serves as the boundary line between adjacent color resist portions 5000. For example, the specific control line 1400 is one of the plurality of first control lines 140. Adjacent color resist portions 5000 are located on both sides of the specific control line 1400.

[0118] This configuration allows for a more uniform film thickness on both sides of the specific control line in the display area, and also a more uniform film thickness on both sides of the specific control line in the non-display area. This helps improve the uniformity of the rubbing environment in both the display and non-display areas, thereby reducing the risk of rubbing mura.

[0119] For example, such as Figure 5 As shown, the multiple transistor groups 2000 include multiple measurement transistor groups 2010 and reference transistor groups 2020. Multiple color resist units 5000 of different colors include multiple measurement color resist units 5010 and reference color resist units 5020. Each measurement color resist unit 5010 is located on the side of the measurement transistor group 2010 away from the substrate 001, and each reference color resist unit 5020 is located on the side of the reference transistor group 2020 away from the substrate 001. For example, the multiple measurement color resist units 5010 may include red, green, and blue color resist units. For example, when ambient light reaches a color resist unit of a different color, it is filtered to obtain light of the same color as that color resist unit, and then incident on the measurement transistor group. For example, the reference color resist unit 5010 may be a blocked color resist unit; therefore, the photosensitive transistors 200 in the reference transistor group 2020 cannot receive ambient light.

[0120] For example, such as Figure 5 As shown, in the first direction X, the distance between adjacent measurement transistor groups 2010 can be the sum of the sizes of multiple consecutively arranged sub-pixels, for example, the sum of the sizes of 5 to 10 consecutively arranged sub-pixels. For example, the sum of the aforementioned sizes can be 500 to 1200 micrometers, but is not limited thereto.

[0121] This configuration minimizes the amount of light that the measurement transistor group receives after being filtered by the measurement color resist section of the adjacent measurement transistor group, thereby improving the accuracy of the electrical signal output by the measurement transistor group.

[0122] Figure 7 An equivalent circuit diagram of a photosensing unit is provided for at least one embodiment of this disclosure. For example, a plurality of measuring transistor groups and a reference transistor group can constitute a set of photosensing units.

[0123] For example, such as Figure 7 As shown, the multiple measurement transistor groups include a first color transistor group 5001, a second color transistor group 5002, and a third color transistor group 5003. For example, the first color transistor group 5001 is covered with a red color resist portion 5000 (see [link to documentation]). Figure 5 To receive red light, a green color resist 5000 is covered on the second color transistor group 5002 (see [link]). Figure 5To receive green light, the third color transistor group 5003 is covered with a blue color resist section 5000 (see [link]). Figure 5 It receives blue light.

[0124] For example, such as Figure 7 As shown, after the first color transistor group 5001, the second color transistor group 5002, and the third color transistor group 5003 receive light of their respective colors, the drain 202 of the photosensitive transistor in the first color transistor group 5001 generates a leakage current Ioff1, the drain 202 of the photosensitive transistor in the second color transistor group 5002 generates a leakage current Ioff2, and the drain 202 of the photosensitive transistor in the third color transistor group 5003 generates a leakage current Ioff3. Leakage currents Ioff1, Ioff2, and Ioff3 serve as feedback signals. For example, if a light-shielding material is provided on the reference transistor group 2020, the reference transistor cannot receive ambient light. Therefore, the leakage current Ioff4 generated by the drain 202 of the photosensitive transistor in the reference transistor group 2020 may remain unchanged and can be used as reference data.

[0125] For example, by monitoring the changes in the aforementioned feedback signal with ambient light (e.g., the brightness of ambient light), different ambient light intensities can be determined. When the light intensity increases, the number of photogenerated carriers increases, leading to an increase in leakage current; conversely, when the light intensity decreases, the leakage current decreases.

[0126] Figure 8A A partial planar schematic diagram of another array substrate provided for at least one embodiment of the present disclosure; Figure 8B A partial cross-sectional schematic diagram of an array substrate provided for at least one embodiment of the present disclosure.

[0127] For example, such as Figure 8A and Figure 8B As shown, the array substrate also includes a light-shielding layer BM, which is located on the side of the color resist layer 500 away from the substrate 001. For example, the light-shielding layer BM covers the reference transistor group 2020, so that the photosensitive transistor 200 in the reference transistor group 2020 cannot generate a responsive feedback signal according to changes in ambient light. In some embodiments, light leakage may occur in the array substrate, that is, some ambient light may also illuminate the photosensitive transistor in the reference transistor group, so that the photosensitive transistor 200 generates a weak feedback signal as a reference, that is, the feedback signal corresponding to the reference transistor group may not be zero.

[0128] For example, such as Figure 8A and Figure 8BAs shown, the light-shielding layer BM includes a plurality of openings BMO, and the openings BMO expose at least a portion of the channel region of the photosensitive transistor 200 in the measurement transistor group 2010. For example, the channel region of the photosensitive transistor 200 exposed by the openings BMO can receive light of a corresponding color, thereby generating a corresponding feedback signal. For example, when the transmittance of the plurality of measurement color resist portions on the side of the plurality of measurement transistor groups 2010 away from the substrate 001 is not the same, the opening areas of the plurality of openings BMO in the light-shielding layer BM may be different.

[0129] For example, such as Figure 8A and Figure 8B As shown, the plurality of measurement transistor groups 2000 include a first type transistor group 22010 and a second type transistor group 22020, and the plurality of measurement color resist sections 5010 include a first color resist section 50101 and a second color resist section 50102. The first color resist section 50101 is located on the side of the first type transistor group 22010 away from the substrate 001, and the second color resist section 50102 is located on the side of the second type transistor group 22020 away from the substrate 001. The transmittance of the first color resist section 50101 is greater than the transmittance of the second color resist section 50102. For example, the first color resist section 50101 can be a red color resist section or a blue color resist section, and the second color resist section 50102 can be a green color resist section.

[0130] For example, transmittance here refers to the proportion of light of the same color as the color resist that is transmitted. For example, the thickness of each color resist may be uniform, but the materials may be different, thus resulting in different proportions of light of the corresponding color being transmitted.

[0131] For example, such as Figure 8A and Figure 8B As shown, the multiple openings BMO of the light-shielding layer BM include multiple first openings BMO1 and multiple second openings BMO2. The first openings BMO1 expose at least a portion of the channel region of the photosensitive transistor 200 in the first type transistor group 22010, and the second openings BMO2 expose at least a portion of the channel region of the photosensitive transistor 200 in the second type transistor group 22020. The orthogonal projection area of ​​the first openings BMO1 on the substrate 001 is smaller than the orthogonal projection area of ​​the second openings BMO2 on the substrate 001.

[0132] This configuration allows for flexible adjustment of the opening area in the light-shielding layer based on the different transmittance of the color resist in the measurement section. This reduces the impact of differences in transmittance between different color resist sections, ensuring that the amount of light received by transistors in different types of transistor groups is relatively small, thus making the feedback signal more accurate.

[0133] For example, such as Figure 8A and Figure 8BAs shown, the orthographic projection of the opening BMO of the light-shielding layer BM onto the substrate 001 can be rectangular, and the side length of the rectangle is 40 micrometers to 55 micrometers, for example, 42 micrometers, 45 micrometers, 48 ​​micrometers, 50 micrometers, 52 micrometers, or 55 micrometers. For example, the orthographic projection of the first opening BMO1 onto the substrate 001 is a first rectangle, and the side length of the first rectangle can be 50 to 55 micrometers. The orthographic projection of the second opening BMO2 onto the substrate 001 is a second rectangle, and the side length of the second rectangle can be 45 to 50 micrometers, but is not limited thereto, and the embodiments disclosed herein do not limit this.

[0134] about Figure 8A and Figure 8B For other structures in the array substrate shown, please refer to the above embodiments regarding... Figure 5 The description of that will not be repeated here.

[0135] For example, such as Figure 5 As shown, the array substrate also includes a temperature sensing line 160, which is located on the side of the plurality of photosensitive transistors 200 away from the display area 10. For example, the temperature sensing line 160 can monitor the ambient temperature in real time. For example, the temperature sensing line 160 is arranged around the display area 10.

[0136] For example, such as Figure 5 As shown, the temperature sensing line 160 includes a plurality of first temperature sensing portions 1610 and a plurality of second temperature sensing portions 1620. The plurality of first temperature sensing portions 1610 and the plurality of second temperature sensing portions 1620 are arranged alternately in sequence, and the first temperature sensing portions 1610 and the second temperature sensing portions 1620 are connected. At least a portion of the plurality of photosensitive transistors 200 in the first temperature sensing portion 1610 extends in the arrangement direction, and the extension direction of the second temperature sensing portion 1620 intersects the extension direction of the first temperature sensing portion 1610. For example, on the first side S1 of the display area 10, at least a portion of the first temperature sensing portion 1610 extends along the first direction X, and the second temperature sensing portion 1620 extends along the second direction Y.

[0137] For example, such as Figure 5 As shown, at least a portion of the photosensitive transistors 200 and at least a portion of the second temperature-sensing portions 1620 correspond one-to-one in the circumferential direction perpendicular to the display area 10, and the center line of the first control line 140 passing through the photosensitive transistors 200 also passes through the second temperature-sensing portions 1620 corresponding to the photosensitive transistors 200. For example, on the first side S1 of the display area 10, the second temperature-sensing portions 1620 and the corresponding photosensitive transistors 200 overlap in the second direction Y.

[0138] This configuration helps to make the distribution of temperature sensing lines in the non-display area more uniform. For example, it can be basically evenly divided by the extension lines of the center lines of multiple first control lines, thereby making the influence of temperature sensing lines on film thickness smaller and helping to generate smaller Rubbing environment differences.

[0139] For example, such as Figure 5 As shown, the multiple signal lines 100 also include a common electrode line 170, which is located on the side of the temperature-sensing line 160 away from the multiple photosensitive transistors 200. The array substrate also includes a transparent structure 600, which is located between the temperature-sensing line 160 and the common electrode line 170 and is disposed around the display area 10. For example, the transparent structure 600 may be made of indium tin oxide (ITO), but is not limited thereto.

[0140] On the one hand, the transparent structure can reduce the difference in film thickness between the area between the temperature sensing line and the common electrode line and other areas in the array substrate, thereby reducing the risk of Rubbing Mura; on the other hand, the transparent structure can also isolate static electricity, reducing the damage to the array substrate caused by electrostatic discharge.

[0141] For example, such as Figure 5 As shown, the transparent structure 600 includes a plurality of spaced-apart transparent substructures 610, with at least a portion of the first temperature-sensing portion 1610 corresponding one-to-one with the transparent substructures 610 in a direction perpendicular to the arrangement of the plurality of photosensitive transistors 200. For example, on the first side S1 of the display area 10, the transparent substructures 610 extend along a first direction X. The transparent substructures 610 overlap with the corresponding first temperature-sensing portions 1610 in a second direction Y. For example, the extension of the center line of the first control line 140 passing through the second temperature-sensing portion 1620 also passes through the gap between adjacent transparent substructures 610. For example, at least one transparent substructure 610 is disposed between the extensions of the center lines of adjacent first control lines 140. For example, in the first direction X, the gap between adjacent transparent substructures 610 is 6 to 10 micrometers, such as 6 micrometers, 8 micrometers, or 10 micrometers. For example, in the first direction X, the distance between the extension of the center line of the first control line 140 and the transparent substructures 610 on both sides is substantially equal, for example, it can be 3.5 micrometers, 4 micrometers or 5 micrometers, and the embodiments of this disclosure are not limited to this.

[0142] This configuration allows multiple transparent substructures to be evenly distributed along the circumference of the display area, resulting in uniform film thickness on both sides of the extension of the center line of the first control line, thereby reducing the risk of Rubbing Mura.

[0143] For example, such as Figure 5As shown, the size of the transparent substructure 610 in the second direction Y can be 35-45 micrometers, such as 38 micrometers, 40 micrometers, or 42 micrometers. The size of the transparent substructure 610 in the first direction X can be 90-100 micrometers, such as 90 micrometers, 95 micrometers, or 97 micrometers. For example, the minimum distance between the transparent substructure 610 and the temperature sensing line 160 in the second direction Y is 20-25 micrometers, such as 22 micrometers, 23 micrometers, or 25 micrometers; however, the embodiments of this disclosure do not limit this.

[0144] For example, such as Figure 5 As shown, in a direction perpendicular to the arrangement of the multiple photosensitive transistors, such as the second direction Y, the distance between the transparent electrode 600 and the common electrode line 170 is not less than half the distance between the temperature sensing line 160 and the common electrode line 170. For example, the distance between the temperature sensing line 160 and the common electrode line 170 can be 120-135 micrometers, such as 125 micrometers, 128 micrometers, 130 micrometers, or 132 micrometers. For example, the distance between the transparent electrode 600 and the common electrode line 170 can be 60-70 micrometers, such as 62 micrometers, 64 micrometers, 66 micrometers, or 68 micrometers; the embodiments of this disclosure do not limit this.

[0145] Figure 9 A partial planar schematic diagram of another array substrate provided for at least one embodiment of the present disclosure.

[0146] For example, such as Figure 9 As shown, the array substrate and Figure 5 The difference between the array substrates shown lies in their transparent structure; other structures can be found in the embodiments described above. Figure 5 The description will not be repeated here.

[0147] For example, such as Figure 9 As shown, the transparent structure 600 extends continuously along the arrangement direction of the plurality of photosensitive transistors 200 in the display area 10. For example, the transparent structure 600 may be elongated. The extension of the center line of the first control line 140 passes through the transparent structure 600.

[0148] This configuration allows for a better reduction of the film thickness difference between the area between the temperature sensing line and the common electrode line and other areas in the array substrate through a transparent structure, thereby reducing the risk of Rubbing Mura and effectively preventing electrostatic discharge from damaging the array substrate.

[0149] Figure 10 This is a schematic diagram of the connection between the gate and gate line of a photosensitive transistor in an array substrate provided for at least one embodiment of the present disclosure.

[0150] For example, such as Figure 10As shown, the gate 203 of the phototransistor 200 includes a portion overlapping the drain line 130, and the orthographic projection of this portion onto the substrate is "T"-shaped. For example, the "T"-shaped portion of the gate 203 of the phototransistor 200 is connected to the connector 2040 through a first via N1, and the connector 2040 is connected to the gate line 014 through a second via N2. For example, the edge of the gate 203 of the phototransistor 200 away from the channel region 2030 is flush with the gate line 014, thereby improving the flatness of the connector 2040, making the film thickness in this region uniform, and reducing the risk of rubbing mura.

[0151] In at least one embodiment of this disclosure, the array substrate further includes a color filter layer, at least a portion of which is located in the display area and on the light-emitting side of a sub-pixel within the display area. For example, the color filter layer may be a structure for filtering the color of light. For example, the color resist layer in the above embodiments of this disclosure may be located in the same layer as the color filter layer, and the two may be a co-layer structure.

[0152] At least one embodiment of this disclosure also provides a display device, which includes an array substrate provided in the embodiments of this disclosure (e.g., the array substrate described in the above embodiments). Therefore, the technical effects of the array substrate can also be reflected in this display device, and will not be repeated here. For example, the display device further includes a counter substrate and a liquid crystal layer, with the array substrate and the counter substrate disposed opposite to each other, the liquid crystal layer located between the array substrate and the counter substrate, and the liquid crystal molecules in the liquid crystal layer being deflected under the action of the array substrate and the counter substrate, thereby achieving display.

[0153] For example, the display device can be an organic light-emitting diode display device or other display device, as well as any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator that includes the display device. This embodiment is not limited to this.

[0154] The following points need to be explained:

[0155] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0156] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0157] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. An array substrate, comprising: A substrate, and a display area and a non-display area located on the substrate, wherein at least a portion of the non-display area surrounds the display area, and the non-display area has a plurality of signal lines, each of the signal lines at least a portion of which surrounds the display area; as well as Multiple photosensitive transistors are located on the substrate and in the non-display area. The multiple photosensitive transistors are arranged around the display area, and each photosensitive transistor includes a source, a gate, and a drain. The plurality of photosensitive transistors include a first transistor and at least one second transistor, wherein the first transistor and the second transistor are configured to match color resist materials of different colors. The plurality of signal lines include a first source line and at least one second source line, wherein the source of the first transistor is connected to the first source line, the at least one second source line corresponds one-to-one with the at least one second transistor, and the source of the second transistor is connected to the second source line. There is a first distance between the gate of the first transistor and the first source line connected to the source of the first transistor, and there is a second distance between the gate of the second transistor and the second source line connected to the source of the second transistor, the second distance being greater than the first distance, and a filling portion is provided between the gate of the second transistor and the second source line connected to the source of the second transistor.

2. The array substrate according to claim 1, wherein, The fill portion located between the gate of the second transistor and the second source line to which the second transistor is connected is part of the source of the second transistor.

3. The array substrate according to claim 1, wherein, The fill portion located between the gate of the second transistor and the second source line to which the second transistor is connected is electrically connected to the second source line corresponding to the second transistor.

4. The array substrate according to claim 1, wherein, The length of the first source line is less than the length of the second source line. The first source line is spaced apart from the source of the second transistor, and the extension of the first source line intersects with the fill portion located between the gate of the second transistor and the second source line connecting the second transistor.

5. The array substrate according to claim 1, wherein, The filling portion includes at least one first portion, at least a portion of the second source line extends along a first direction, and the at least portion of the second source line is located on one side of the display area in a second direction. Both the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction. On one side of the display area, and in the second direction, the first portion and the gate of the second transistor connected to the second source line overlap.

6. The array substrate according to claim 5, wherein, The at least one second source line includes a first type source line, a second type source line, and a third type source line; the at least one second transistor includes a first type transistor, a second type transistor, and a third type transistor; the source of the first type transistor is connected to the first type source line; the source of the second type transistor is connected to the second type source line; and the source of the third type transistor is connected to the third type source line. The gate of the first type of transistor and the source line of the first type have a first sub-distance in a direction perpendicular to the source line of the first type; the gate of the second type of transistor and the source line of the second type have a second sub-distance in a direction perpendicular to the source line of the second type; and the gate of the third type of transistor and the source line of the third type have a third sub-distance in a direction perpendicular to the source line of the third type. The first sub-distance is smaller than the second sub-distance, and the second sub-distance is smaller than the third sub-distance.

7. The array substrate according to claim 6, wherein, At least a portion of the first source line extends along the first direction. The first portion located between the gate of the first type of transistor and the source line of the first type includes a first extension portion, the extension direction of the first extension portion is the same as the extension direction of the first source line, and the extension line of the first source line passes through the first extension portion. The first portion located between the gate of the second type transistor and the source line of the second type includes a second extension portion, the extension direction of the second extension portion being the same as the extension direction of the first type source line, and the extension line of the first type source line passing through the second extension portion; The first portion located between the gate of the third type transistor and the third type source line includes a third extension portion, the extension direction of which is the same as the extension direction of the second type source line, and the extension line of the second type source line passes through the third extension portion.

8. The array substrate according to claim 5, wherein, The at least one second source line includes a specific source line, the at least one second transistor includes a specific transistor, the source of the specific transistor is electrically connected to the specific source line, and on the side of the display area, the first portion extends along the first direction. There are N second source lines between the first source line and the specific source line. The filling portion between the gate of the specific transistor and the specific source line is a part of the source of the specific transistor. The number of at least one first portion of the filling portion of the specific transistor is N+1, where N is an integer greater than or equal to zero.

9. The array substrate according to claim 5, wherein, On one side of the display area, and in the second direction, there is a third distance between the first source line and the adjacent second source line, and the ratio between the distance between the second source line and the adjacent first portion and the third distance is 0.9 to 1.

1.

10. The array substrate according to claim 9, wherein, The filling portion includes a plurality of the first portions. On one side of the display area, the distance between adjacent first portions in the second direction is substantially equal to the third distance.

11. The array substrate according to claim 9 or 10, wherein, The width of the first source line and the width of the second source line are substantially equal, and both are equal to the width of the first part, the width of the first part being greater than the third distance.

12. The array substrate according to any one of claims 5-7, wherein, The filling portion includes at least one second portion, which intersects the extending direction of the first portion, and the width of the second portion is smaller than the width of the first portion. Wherein, the second source line is connected to the adjacent first portion through the second portion, and / or the adjacent first portion is connected through the second portion.

13. The array substrate according to claim 12, wherein, The first part and the second part are connected end to end.

14. The array substrate according to claim 12, wherein, The fill portion located between the gate of the second transistor and the second source line to which the second transistor is connected is part of the source of the second transistor. The source of the second transistor further includes a third portion in addition to the filling portion. The third portion includes a first sub-portion and a second sub-portion. One end of the first sub-portion is connected to one end of the second sub-portion, and the other end of the second sub-portion is connected to the filling portion. On one side of the display area, the first sub-part extends along the first direction, the second sub-part extends in a direction intersecting the extension direction of the first sub-part, at least a portion of the first sub-part overlaps with the gate of the second transistor in a direction perpendicular to the substrate, and the width of the first sub-part is smaller than the width of the second sub-part.

15. The array substrate according to claim 14, wherein, The plurality of signal lines include drain lines, and the drain of each photosensitive transistor is connected to the drain line. The drain line is located on the side of the plurality of photosensitive transistors closer to the display area. The drain of the second transistor includes a third sub-section and a fourth sub-section, the third sub-section being connected to the fourth sub-section. On one side of the display area, the third sub-part extends along the first direction, the extension direction of the fourth sub-part intersects the extension direction of the third sub-part, the third sub-part is connected to the drain line through the fourth sub-part, the third sub-part is spaced apart from the first sub-part, and the third sub-part overlaps with the gate of the second transistor in a direction perpendicular to the substrate, there is a fourth distance between the edges of the second sub-part of the second transistor and the fourth sub-part that are far apart from each other, and the length of the first part is substantially equal to the fourth distance.

16. The array substrate according to claim 1 or 2, wherein, The multiple signal lines also include: Multiple first control lines are located on the side of the multiple photosensitive transistors closest to the display area; The second control line is located between the plurality of photosensitive transistors and the plurality of first control lines; The array substrate further includes multiple electrostatic rings, which are arranged sequentially at intervals around the circumference of the display area and located on the side of the multiple photosensitive transistors closest to the display area. Each of the first control lines is connected to the second control line through the electrostatic ring. At least some of the electrostatic rings correspond one-to-one with at least some of the photosensitive transistors in a direction perpendicular to the arrangement of the plurality of photosensitive transistors, and the extension of the center line of the first control line connected to the electrostatic ring passes through the photosensitive transistor corresponding to the electrostatic ring.

17. The array substrate according to claim 16, wherein, The drain of the second transistor includes a bent portion, the bent portion having a "C" shape in its orthographic projection onto the substrate. The extension of the center line of the first control line connected to the electrostatic ring passes through the bend to divide the bend into two parts located on both sides of the extension of the center line, the ratio of the dimensions of the two parts in the direction perpendicular to the center line being 0.9 to 1.

1.

18. The array substrate according to claim 16, wherein, The plurality of photosensitive transistors includes a plurality of transistor groups, and the array substrate includes a color resist layer located on the side of the plurality of transistor groups away from the substrate. Each transistor group includes the same number of photosensitive transistors. The color resist layer includes multiple color resist portions of different colors, and each of the multiple color resist portions corresponds to one of the multiple transistor groups. Each color resist portion is located on the side of the corresponding transistor group away from the substrate, and the number of extension lines of the center line of the first control line overlapping with each color resist portion is equal.

19. The array substrate according to claim 18, wherein, Adjacent color resist sections are arranged close together, and the plurality of first control lines include a specific control line, the extension of the center line of the specific control line serving as the boundary line between adjacent color resist sections.

20. The array substrate according to claim 17, wherein, The plurality of transistor groups includes a plurality of measurement transistor groups and a reference transistor group. The plurality of color resist sections of different colors include a plurality of measuring color resist sections and a reference color resist section. Each of the measuring color resist sections is located on the side of the measuring transistor group away from the substrate, and each reference color resist section is located on the side of the reference transistor group away from the substrate. The array substrate further includes a light-shielding layer located on the side of the color resist layer away from the substrate, and the light-shielding layer covers the reference transistor group. The light-shielding layer includes a plurality of openings that expose at least a portion of the channel region of the photosensitive transistors in the measurement transistor array.

21. The array substrate according to claim 20, wherein, The plurality of measurement transistor groups include a first type of transistor group and a second type of transistor group. The plurality of measuring color resist sections include a first color resist section and a second color resist section. The first color resist section is located on the side of the first type of transistor group away from the substrate, and the second color resist section is located on the side of the second type of transistor group away from the substrate. The transmittance of the first color resist section is greater than the transmittance of the second color resist section. The plurality of openings includes a plurality of first openings and a plurality of second openings, the first openings exposing at least a portion of the channel region of the photosensitive transistor in the first type of transistor group, the second openings exposing at least a portion of the channel region of the photosensitive transistor in the second type of transistor group, and the orthographic projection area of ​​the first openings on the substrate is smaller than the orthographic projection area of ​​the second openings on the substrate.

22. The array substrate according to claim 16, wherein, The plurality of signal lines also includes a temperature sensing line, which is located on the side of the plurality of photosensitive transistors away from the display area. The temperature sensing line includes a plurality of first temperature sensing portions and a plurality of second temperature sensing portions, which are alternately arranged in sequence. The first temperature sensing portions are connected to the second temperature sensing portions. At least a portion of the first temperature sensing portions extends along the arrangement direction of the plurality of photosensitive transistors, and the extension direction of the second temperature sensing portions intersects with the extension direction of the first temperature sensing portions. The at least some of the photosensitive transistors and at least some of the second temperature sensing parts correspond one-to-one in the arrangement direction perpendicular to the plurality of photosensitive transistors, and the center line of the first control line passing through the photosensitive transistors also passes through the second temperature sensing part corresponding to the photosensitive transistors.

23. The array substrate according to claim 22, wherein, The plurality of signal lines also include a common electrode line, which is located on the side of the temperature sensing line away from the plurality of phototransistors. The array substrate further includes a transparent structure located between the temperature sensing line and the common electrode line, and disposed around the display area. The transparent structure includes a plurality of spaced-apart transparent substructures, with at least a portion of the first temperature-sensing portion corresponding one-to-one with at least a portion of the transparent substructures in a direction perpendicular to the arrangement of the plurality of photosensitive transistors. The extension of the center line of the first control line passing through the second temperature sensing part also passes through the gap between adjacent transparent substructures.

24. The array substrate according to claim 20, wherein, The display area contains an array of multiple sub-pixels. In the arrangement direction of the plurality of photosensitive transistors, the distance between adjacent measurement transistor groups is the sum of the sizes of 5 to 10 consecutively arranged sub-pixels.

25. A display device, comprising: The array substrate according to any one of claims 1-24; The opposing substrate is disposed opposite to the array substrate; as well as A liquid crystal layer is located between the array substrate and the opposing substrate.

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