Silicon-on-insulator substrate and preparation method thereof

Abstract

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and the preparation method comprises the steps: providing a donor substrate and a supporting substrate, the donor substrate is provided with an ion implantation layer, and a first oxide layer is formed on the surface of the donor substrate; depositing a charge trapping layer on the surface of the supporting substrate at a first temperature, wherein the charge trapping layer is a nitrogen-containing dielectric material layer; performing heat treatment on the support substrate deposited with the charge trapping layer at a second temperature, wherein the second temperature is higher than the first temperature; bonding the side, provided with the first oxide layer, of the donor substrate with the side, provided with the charge trapping layer, of the supporting substrate to form a bonding structure; the donor substrate is peeled off along the ion implantation layer, a part of the donor substrate is transferred to the supporting substrate, an insulating buried layer and top silicon are formed on the supporting substrate, and the insulating buried layer comprises the charge trapping layer and the first oxide layer which are stacked.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to silicon-on-insulator substrates and methods for their fabrication. Background Technology

[0002] With the explosive growth of big data processing and artificial intelligence applications, the semiconductor industry is accelerating its evolution towards high-density, high-speed three-dimensional integrated architectures, such as three-dimensional vertically stacked memories and logic devices. In these advanced architectures, silicon-on-insulator (SOI) substrates, with their inherent vertical insulating properties, have become a key material for suppressing crosstalk between device cells, reducing leakage current, and improving radiation resistance.

[0003] To further enhance the integration and functionality of devices, related technologies are dedicated to developing SOI substrates with more functional characteristics, such as endowing the substrate with certain information storage capabilities or better electric field shielding capabilities. However, in attempting to integrate functional dielectric materials into SOI structures, the compatibility challenges between material properties and manufacturing processes are often encountered. How to endow the substrate with excellent electrical properties while ensuring wafer-level structural integrity, bonding strength, and production yield is a technical challenge that urgently needs to be overcome in the current semiconductor substrate manufacturing field. Summary of the Invention

[0004] This application provides a silicon-on-insulator substrate and its fabrication method; by using a nitrogen-containing dielectric material as a charge trapping layer and combining it with a specific reverse thermal budget degassing process, the bonding defect problem caused by hydrogen evolution inside the deposited layer is solved, while improving the storage performance and electrical isolation characteristics of the substrate.

[0005] The technical solution of this application is implemented as follows: In a first aspect, embodiments of this application provide a method for fabricating a silicon-on-insulator substrate, the method comprising: A donor substrate and a support substrate are provided, wherein the donor substrate has an ion implantation layer and a first oxide layer is formed on the surface of the donor substrate; A charge trapping layer is deposited on the surface of the support substrate at a first temperature. The charge trapping layer is a nitrogen-containing dielectric material layer. The support substrate on which the charge trapping layer is deposited is heat-treated at a second temperature, which is higher than the first temperature. The donor substrate having the first oxide layer is bonded to the support substrate having the charge trapping layer to form a bonding structure; and By peeling the donor substrate along the ion implantation layer, a portion of the donor substrate is transferred onto the support substrate to form an insulating buried layer and a top silicon layer on the support substrate, the insulating buried layer comprising the stacked charge trapping layer and the first oxide layer.

[0006] In some embodiments, the charge trapping layer is a silicon nitride layer or a silicon carbonitride layer.

[0007] In some embodiments, the first temperature is less than 450°C; the second temperature is 450°C to 550°C.

[0008] In some embodiments, prior to depositing the charge trapping layer, the fabrication method further includes: forming a second oxide layer on the surface of the supporting substrate; The deposition step includes depositing the charge trapping layer on the second oxide layer.

[0009] In some embodiments, the thickness of the first oxide layer is 5 nm to 200 nm, the thickness of the second oxide layer is 1 nm to 100 nm, and the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

[0010] In some embodiments, the thickness of the charge trapping layer is 30 nm to 100 nm.

[0011] In some embodiments, the surface roughness of the charge trapping layer after the heat treatment is less than 0.3 nm.

[0012] In some embodiments, after the stripping step, the preparation method further includes: The top silicon layer is planarized, and the planarization process includes rapid thermal annealing or chemical mechanical polishing.

[0013] In some embodiments, the rapid thermal annealing process is carried out in a hydrogen-containing atmosphere at a temperature of 1100°C to 1300°C.

[0014] In some embodiments, the planarization process further includes: growing a sacrificial oxide layer on the top silicon surface by a rapid thermal oxidation process, and removing the sacrificial oxide layer.

[0015] Secondly, this application provides a silicon-on-insulator substrate, which is prepared by the method for preparing a silicon-on-insulator substrate according to the first aspect, the silicon-on-insulator substrate comprising: Support substrate; Insulating buried layer; The top silicon layer, wherein the insulating buried layer is located between the supporting substrate and the top silicon layer; The insulating buried layer includes a charge trapping layer and a first oxide layer stacked together. The charge trapping layer is located between the supporting substrate and the first oxide layer, and the charge trapping layer is a nitrogen-containing dielectric material layer.

[0016] In some embodiments, the insulating buried layer further includes a second oxide layer located between the supporting substrate and the charge trapping layer; the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

[0017] In some embodiments, the charge trapping layer is a silicon carbonitride layer or a silicon nitride layer.

[0018] This application provides a silicon-on-insulator substrate and its fabrication method. The method first involves low-temperature deposition of a nitrogen-containing dielectric material as a charge trapping layer on a supporting substrate. A heat treatment process above the deposition temperature is then used to pre-remove volatile components from the layer. Subsequently, the substrate is bonded to a donor substrate with a pre-formed oxide layer and then peeled off. This method not only ingeniously integrates charge storage functionality into the substrate fabrication stage, effectively avoiding the physical isolation seam problem caused by high aspect ratio deposition in traditional 3D memory manufacturing, but also significantly reduces bubbles and voids at the bonding interface through a specific heat treatment strategy. This results in a high-performance substrate with both excellent physical isolation properties and reliable charge storage functionality, providing an ideal base material for high-density memory devices such as vertical channel transistors. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating a method for fabricating a silicon-on-insulator substrate provided in an embodiment of this application.

[0020] Figure 2 A process flow diagram of the method for fabricating silicon-on-insulator substrates provided in the embodiments of this application.

[0021] Figure 3 A schematic cross-sectional view of a silicon-on-insulator substrate provided in an embodiment of this application.

[0022] Figure 4 Ultrasonic scanning microscope image of the bonding interface of the silicon-on-insulator substrate provided for Comparative Example 2.

[0023] Figure 5 Ultrasonic scanning microscope image of the bonding interface of the silicon-on-insulator substrate provided in Embodiment 1 of this application. Detailed Implementation

[0024] The technical solutions in this application will now be clearly and completely described with reference to the accompanying drawings.

[0025] In the development of novel silicon-on-insulator substrates for high-density 3D storage applications, to address the issue of the limited functionality of traditional buried silicon dioxide layers, it is typically necessary to introduce dielectric materials with specific band structures as charge trapping layers. Research and development experiments and mechanistic exploration revealed that when nitrogen-containing dielectric materials, such as thin films prepared by chemical vapor deposition, which can provide deep-level traps and possess low dielectric constants, are used as functional layers, although their electrical properties meet the requirements of storage devices, interface bonding failure is highly likely to occur during subsequent wafer bonding processes.

[0026] Through in-depth microscopic analysis and thermodynamic simulation of the failed samples, it was identified that the root cause of this problem was not merely the cleanliness or flatness of the wafer surface, but rather the deep contradiction between the chemical stability of the material and thermal budget management.

[0027] Specifically, to obtain the desired band structure, the deposition process typically "freezes" a large amount of hydrogen components in the form of chemical bonds within the amorphous network of the dielectric material. These deeply bound hydrogen components remain stable at low temperatures, but during the high-temperature enhanced annealing process that must be undergone after bonding, they gain sufficient thermal energy to break and release. Since the functional layer is physically sealed by the bonding interface at this point, the released gas components cannot escape, thus accumulating at the interface and generating enormous internal pressure, ultimately leading to the formation of microscopic voids or even film peeling.

[0028] Based on the aforementioned unique insights into the physical mechanism, the inventors recognized that conventional surface activation or cleaning methods alone cannot reach the fundamental problem of the bulk phase of the thin film. It is necessary to break through the limitations of thermal budgets in conventional processes and actively induce and release these unstable chemical components before bonding and sealing through a specific reverse thermal treatment mechanism. Based on this, the embodiments of this application propose a novel preparation method.

[0029] See Figure 1 This application provides a method for fabricating a silicon-on-insulator substrate in some embodiments. The method mainly includes five core steps: substrate preparation, functional layer deposition, degassing heat treatment, wafer bonding, and lift-off transfer. Specifically, the method includes steps S100 to S500.

[0030] In step S100, a donor substrate and a support substrate are provided. The donor substrate has an ion implantation layer and a first oxide layer is formed on the surface of the donor substrate.

[0031] Step S100 serves as the starting point of the preparation process. Its main task is to pre-construct the "top" and "bottom" of the final SOI product and pre-set the separation mechanism.

[0032] The donor substrate is a wafer used to provide high-quality single-crystal silicon thin films, and its quality directly determines the performance of the active region of the final device. The donor substrate 200 is typically a commercially available polished single-crystal silicon wafer, such as a Czochralski single-crystal silicon wafer with a diameter of 300 mm.

[0033] First, a first oxide layer 210 is formed on the surface of the donor substrate 200. This first oxide layer 210 is, for example, a silicon dioxide layer formed by a furnace tube thermal oxidation process. The thermal oxidation process involves reacting the silicon surface with oxygen in an oxidizing atmosphere at a high temperature, such as 800°C to 1100°C, to generate silicon dioxide. Oxide layers generated in this way exhibit high density, fewer pinhole defects, and excellent interface state density. Alternatively, as another optional implementation, the first oxide layer 210 can also be formed using a high-density plasma chemical vapor deposition (HDCVD) process. HDCVD can obtain films with significantly higher density and purity than conventional PECVD while maintaining a lower deposition temperature, for example, less than 400°C. The film quality is close to that of thermally oxidized films, and it has lower internal stress, is less prone to microcracks, and is suitable for structures sensitive to thermal budgets. As an insulating layer that directly contacts the top silicon layer in the final product, the first oxide layer 210 not only serves as an insulation layer but also acts as a charge retention layer. Its high-quality interface effectively reduces surface scattering of charge carriers and improves device mobility.

[0034] In some specific embodiments, the thickness of the first oxide layer 210 is controlled between 5 nm and 200 nm, such as between 100 nm and 200 nm, for example, set to 150 nm. This thickness setting is based on several considerations: on the one hand, a thicker oxide layer helps prevent charge leakage due to tunneling effect under high-voltage operation, ensuring data retention time; on the other hand, this thickness also serves as a buffer layer for subsequent ion implantation, protecting the underlying single-crystal silicon surface from physical bombardment damage by high-energy ions.

[0035] Next, an ion implantation process is performed on the donor substrate 200. The ion beam is typically hydrogen ion H+. + Helium ions (He) + Or a combination of both, with specific energy and dosage, penetrates the first oxide layer 210 and is injected into the single-crystal silicon lattice of the donor substrate 200.

[0036] As the implantation process proceeds, ions accumulate at the end of the implantation range, forming a high-concentration defect band, namely the ion implantation layer 220, at a predetermined depth below the first oxide layer 210. This ion implantation layer 220 is microscopically composed of numerous microbubbles and lattice defects, defining the physical plane for subsequent wafer separation. Exemplarily, the implantation energy can be between 5 keV and 100 keV, and the implantation dose can be 2 × 10⁻⁶. 16 Up to 1×10 17atoms / cm 2 The specific values ​​can be precisely adjusted based on the required thickness of the top silicon layer.

[0037] The support substrate 300 provides the mechanical strength of the final SOI wafer, enabling it to be compatible with standard semiconductor production line equipment. See also Figure 2 A second oxide layer 310 may be pre-formed on the surface of the support substrate 300. The second oxide layer 310 may be a silicon oxide layer formed by thermal oxidation or by chemical vapor deposition.

[0038] According to some embodiments of this application, an asymmetric oxide layer design is provided. Specifically, the process control ensures that the thickness of the first oxide layer 210 is greater than the thickness of the second oxide layer 310. For example, the thickness of the second oxide layer 310 is controlled between 10 nm and 100 nm, such as 50 nm. In other words, the first oxide layer 210 located below the top silicon layer is thicker and mainly responsible for charge retention and high-field blocking; while the second oxide layer 310 located above the supporting substrate is thinner and mainly serves as an etching stop layer and blocks the upward diffusion of substrate metal impurities. Because the second oxide layer is thinner, this helps to alleviate the thermal stress mismatch caused by multilayer film stacking, prevents severe bowing or warping of the wafer in subsequent high-temperature processes, thereby improving the accuracy of photolithography alignment.

[0039] After preparation step S100 is completed, step S200 can be executed. In step S200, a charge trapping layer is deposited on the surface of the support substrate at a first temperature. The charge trapping layer is a nitrogen-containing dielectric material layer.

[0040] Step S200 is a crucial step in constructing the insulating buried layer with storage capabilities. See also... Figure 2 Specifically, the deposition step involves depositing a charge trapping layer 320 on the surface of the second oxide layer 310 facing away from the support substrate 300.

[0041] The charge trapping layer 320 is selected from nitrogen-containing dielectric materials, and in specific embodiments, it is preferably silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxynitride (SiON / Si). X N y Unlike semiconductor materials used in radio frequency applications in related technologies, such as polycrystalline silicon and silicon carbide, which typically exhibit polycrystalline or monocrystalline structures, the nitrogen-containing dielectric material layer prepared by chemical vapor deposition in the embodiments of this application exhibits an amorphous structure.

[0042] Because the material used in this application has an amorphous structure, its charge storage mechanism is completely different from that of polycrystalline materials. Unlike polycrystalline materials, which rely on grain boundaries to store charge, amorphous materials rely on intrinsic deep-level defects and dangling bonds generated by the disordered arrangement of atoms within the bulk phase to capture charge. These defects are more stable under high-temperature thermal conditions and are not easily eliminated by annealing, thus ensuring that the device maintains excellent storage performance even after undergoing subsequent high-temperature manufacturing processes.

[0043] For example, when silicon carbonitride (SiCN) is used, the introduction of carbon atoms effectively reduces the material's polarizability, resulting in a dielectric constant, or k-value, of approximately 4.5-5.5, significantly lower than that of pure silicon nitride, which has a k-value of approximately 7.5. In three-dimensional vertically stacked memory architectures, the distance between bit lines and word lines is extremely small, making parasitic capacitance a bottleneck restricting device speed and power consumption. Using low-k-value SiCN as a buried layer can significantly reduce parasitic capacitive coupling and decrease signal transmission delay.

[0044] In some examples, step S200 can employ plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) processes. The substrate temperature during the deposition process is defined as a first temperature T1. To prevent excessive thermal damage to the underlying structure and to control film stress, this first temperature T1 is typically set below 450°C, for example, between 350°C and 400°C.

[0045] When depositing silicon nitride (SiN), a mixture of silane (SiH4) and ammonia (NH3) or nitrogen (N2) is typically used, with the flow ratio of ammonia to silane (NH3:SiH4) usually controlled between 1:1 and 4:1. When depositing silicon carbonitride, the mixed gas source introduced into the reaction chamber includes a silicon source gas, such as silane (SiH4), a nitrogen source gas, such as ammonia (NH3) or nitrogen (N2), and a carbon source gas, such as methane (CH4). By precisely controlling the flow ratio of this carbon source gas, the carbon content in the deposited silicon carbonitride can be adjusted. For example, the flow ratio of silane, nitrogen, and methane can be controlled between 1:10:1 and 1:20:2. Increasing the carbon content can deepen the trap energy levels, improve data retention at high temperatures, and further reduce the dielectric constant.

[0046] After the charge trapping layer 320 is formed, step S300 can be performed. In step S300, the support substrate on which the charge trapping layer is deposited is heat-treated at a second temperature higher than the first temperature.

[0047] By performing step S300, the problem of "hydrogen-induced voids" in the application of PECVD thin films to bonding technology can be solved.

[0048] During the deposition process in step S200, due to the use of hydride precursors such as SiH4 and NH3, a large number of hydrogen atoms enter the thin film and bind to the amorphous network in the form of silicon-hydrogen bonds (Si-H), nitrogen-hydrogen bonds (NH), or carbon-hydrogen bonds (CH). These chemically bonded hydrogens are relatively stable at low temperatures. However, wafer bonding usually requires subsequent high-temperature annealing, such as above 800°C, to enhance the interfacial adhesion. Once the subsequent process temperature increases, these metastable hydrogen bonds will break, releasing hydrogen gas. If the charge trapping layer is already sandwiched between two wafers at this time, i.e., after the bonding step, the released hydrogen gas cannot diffuse outward and will accumulate in the weakest region of the bonding interface, generating internal pressure, eventually forcing open the interface and forming visible bubbles or micron-sized voids.

[0049] This application addresses this problem by introducing a post-degassing heat treatment. The key point of the degassing heat treatment is that the second temperature T2 of the degassing heat treatment is set higher than the first temperature T1 during deposition.

[0050] From a thermodynamic perspective, the breaking of chemical bonds requires crossing a certain energy barrier. Only when the thermal energy provided by the environment exceeds the binding energy of certain metastable hydrogen bonds in the deposition state can these deeply bound hydrogen components acquire sufficient activation energy to break. Subsequently, driven by the concentration gradient, free hydrogen atoms or molecules diffuse within the film and eventually escape from the film surface into the environment.

[0051] Specifically, when the second temperature T2 is higher than the first temperature T1, not only do metastable chemical bonds (such as Si-H and NH bonds) break inside the film, but the amorphous network structure also reorganizes. This reorganization causes the micropores inside the film to collapse or shrink due to the local migration of atoms, thereby significantly increasing the film density of the charge trapping layer 320 while expelling gas. This pre-completed densification not only eliminates the risk of gas escaping in subsequent processes but also enhances the dielectric strength of the material, helping to improve the charge trapping layer's resistance to breakdown under high electric fields.

[0052] In some embodiments, the first temperature is below 450°C, while the second temperature is set to a range of 450°C to 550°C, and is, for example, at least 50°C higher than the first temperature.

[0053] Setting the second temperature T2 significantly higher than the first temperature T1 (e.g., at least 50°C higher) establishes a thermal budget safety valve. During the deposition stage, the lower first temperature T1 (<450°C) aims to reduce initial film-forming stress and control defect density. However, in the separate heat treatment stage before bonding, the higher second temperature T2 (450°C to 550°C) simulates and prematurely triggers the highest energy environment that may be encountered in subsequent bonding-enhancing annealing or peeling annealing. Because this degassing process takes place in an open surface state, the escaping hydrogen can enter the environmental chamber without hindrance, effectively preventing the formation of localized high-pressure centers at the closed interface after bonding.

[0054] This artificially set temperature difference drives the premature release of bulk hydrogen, allowing the charge trapping layer 320 to complete the "degassing" and "densification" processes before bonding. In subsequent bonding annealing, even if the temperature rises again, there is no excess hydrogen to release from inside the film, thus completely eliminating the source of bubbles at the bonding interface.

[0055] High-temperature degassing may cause microscopic reconstruction on the film surface, slightly increasing the surface roughness. Direct bonding, however, places extremely high demands on surface flatness, typically requiring a root mean square roughness Ra < 0.5 nm. Therefore, after the heat treatment step and before the bonding step, this fabrication method may also include chemical mechanical polishing (CMP) of the surface of the charge trapping layer 320. CMP removes surface micro-protrusions, reducing the surface roughness to below 0.3 nm, ensuring atomically close contact.

[0056] In some embodiments, after CMP, a plasma process, such as O2 or N2 plasma, can be used to activate the surface of the charge trapping layer 320, followed by a hydrophilic cleaning, such as SC-1 cleaning. This series of treatments removes organic contaminants from the surface and introduces a high density of hydroxyl groups (-OH) into the surface. When two wafers come into contact, these hydroxyl groups can instantly form a large number of hydrogen bonds, providing extremely high initial bonding strength.

[0057] After ensuring that the surface of the charge trapping layer on the supporting substrate has reached an ideal bonding state with atomically flat surface and rich in active groups through the above treatment, the wafer-level bonding stage can be entered. Specifically, step S400 is performed. In step S400, the side of the donor substrate with the first oxide layer is bonded to the side of the supporting substrate with the charge trapping layer to form a bonding structure.

[0058] See also Figure 2The donor substrate 200 is flipped so that the surface with the first oxide layer 210 is precisely positioned and in contact with the surface with the charge trapping layer 320 of the support substrate 300. This process is typically carried out in a low-vacuum or atmospheric pressure environment with extremely high cleanliness, and the vacuum pressure in the bonding cavity can be controlled, for example, in the range of 0.001 mbar to 1000 mbar. Under room temperature or slightly heated conditions, due to van der Waals forces or hydrogen bonding, once the two extremely flat and hydrophilic surfaces come into contact, the bonding wave rapidly diffuses throughout the entire wafer, forming a physically tightly bonded structure 400.

[0059] At this point, the charge trapping layer 320 is sealed between the second oxide layer 310 and the first oxide layer 210, forming a sandwich structure of "oxide layer-charge trapping layer-oxide layer". Since the charge trapping layer 320 has undergone sufficient degassing treatment, its internal hydrogen content has dropped below the safe threshold. Therefore, even if a long-term high-temperature annealing is subsequently performed to convert hydrogen bonds into covalent bonds, no gas will be released to damage the interface.

[0060] Finally, step S500 is performed, in which the donor substrate is peeled off along the ion implantation layer and a portion of the donor substrate is transferred to the support substrate to form the silicon-on-insulator substrate 10.

[0061] See Figure 2 The bonded structure 400 is subjected to a peeling anneal or mechanical peeling process. Under thermal conditions, such as temperatures between 400°C and 600°C (e.g., 500°C), and with the heat treatment time adjusted according to the implantation process, typically lasting 1 to 3 hours (e.g., 1 hour), or under external force, the microbubbles within the ion-implanted layer 220 undergo thermal expansion and lateral coalescence, forming cracks that penetrate the wafer plane, causing the donor substrate 200 to fracture and separate along this layer. Most of the donor substrate 200 is removed, while the ion-implanted layer 220 remains on the support substrate 300 side, becoming the top silicon 230 of the silicon-on-insulator substrate.

[0062] The main portion of the donor substrate 200 removed in step S500 can be recycled. Specifically, through refurbishment processes such as chemical mechanical polishing, wet etching, and cleaning, the damaged layer and residues on its surface are removed, restoring its surface quality to its initial state that meets bonding requirements. The refurbished donor substrate 200' can then be reused as a donor substrate in subsequent production processes. Figure 2 Step S600 in the process. This recycling of donor wafers avoids the waste of expensive single-crystal silicon materials, significantly reduces the cost of single-wafer fabrication of silicon-on-insulator substrates, and thus improves the material utilization rate and economic benefits of large-scale industrial production.

[0063] In some embodiments of this application, after the stripping step S500, the preparation method further includes a post-processing step S700 to repair lattice damage on the stripped surface and further planarize the surface. In some embodiments, a portion of the donor substrate transferred onto the support substrate, i.e., the top silicon 230, is subjected to rapid thermal annealing (RTP) in a hydrogen-containing atmosphere (such as an H2 / Ar mixture). For example, the RTP processing temperature is between 1100°C and 1300°C, the H2 to Ar mixing ratio is 1:20 to 1:2, and the time is 10 seconds to 60 seconds. Utilizing the surface migration and reconstruction effect of silicon atoms at high temperature, i.e., the hydrogen annealing effect, surface roughness is eliminated, resulting in an atomically smooth top silicon surface, while simultaneously repairing lattice damage caused by ion implantation.

[0064] Furthermore, in some embodiments, a rapid thermal oxidation (RTO) process can be used to treat the top silicon 230. Specifically, a sacrificial oxide layer with a thickness of less than 100 nm is grown on the surface of the top silicon using the RTO process. This oxidation process can consume the damaged layer remaining on the stripped surface. Subsequently, the sacrificial oxide layer is removed by methods such as wet etching, thereby obtaining a surface with a flatter surface and fewer defects. This RTO process can be used alone or in combination with the aforementioned RTP annealing process.

[0065] The product obtained using the above preparation method has structural features that distinguish it from related technologies. See also... Figure 3 The silicon-on-insulator substrate 10 comprises, from bottom to top: a support substrate 300, a second oxide layer 310, a charge trapping layer 320, a first oxide layer 210, and a top silicon layer 230. The specific details of each part of the silicon-on-insulator substrate 10 are described below.

[0066] The support substrate 300 serves as a mechanical substrate and is typically a single-crystal silicon with high or standard resistivity.

[0067] A second oxide layer 310 is disposed on the support substrate 300. Its material can be selected from silicon oxide, silicon oxynitride, aluminum oxide, or hafnium oxide. This layer is relatively thin, for example, in the range of 1 nm to 100 nm, and mainly serves to block the upward transport of substrate impurities and relieve stress.

[0068] A charge trapping layer 320 is disposed on the side of the second oxide layer 310 facing away from the supporting substrate 300. The charge trapping layer 320 is composed of a nitrogen-containing dielectric material (such as SiCN), wherein the carbon doping ratio is modulated to optimize the trap depth. The charge trapping layer 320 has an amorphous structure with a dense microstructure formed after degassing at a temperature higher than the deposition temperature, and its internal hydrogen content is significantly lower than that of conventional PECVD deposits. Carriers can be trapped using deep-level defects in the energy band of the charge trapping layer 320.

[0069] A first oxide layer 210 is disposed on the side of the charge trapping layer 320 opposite to the second oxide layer 310. The thickness of the first oxide layer 210 can be in the range of 5 nm to 200 nm, and is greater than the thickness of the second oxide layer 310, forming an asymmetric structure. Since the first oxide layer 210 is usually generated by thermal oxidation, its density and breakdown field strength are generally superior to those of the second oxide layer 310. A clear bonding interface 410 exists between the charge trapping layer 320 and the first oxide layer 210. Under a transmission electron microscope, this interface may appear as a discontinuous atomic arrangement or extremely small oxide gaps. Importantly, there are no bubbles or micropore defects at this interface, and the surface roughness Ra is less than 0.3 nm.

[0070] The top silicon layer 230 is disposed on the side of the first oxide layer 210 away from the charge trapping layer 320, and is a single-crystal silicon thin film, serving as the active region for manufacturing semiconductor devices.

[0071] To further verify the beneficial effects of the silicon-on-insulator substrate and its preparation method provided in this application on improving bonding quality and optimizing electrical performance, this application provides multiple sets of experimental data. The specific preparation process, testing conditions, and experimental results analysis of each embodiment and comparative example will be described in detail below.

[0072] Preparation process of the examples and comparative examples Example 1 This embodiment uses the nitrogen-containing dielectric material proposed in this application combined with a reverse thermal budget degassing process to prepare a silicon-on-insulator substrate.

[0073] Specifically, two single-crystal silicon wafers with a diameter of 300 mm are first selected as the donor substrate and the support substrate, respectively. A first oxide layer, i.e., a silicon dioxide layer, with a thickness of, for example, 150 nm, is grown on the surface of the donor substrate by thermal oxidation, and hydrogen ion implantation is performed to form an ion implantation layer. A second oxide layer, i.e., a silicon dioxide layer, with a thickness of, for example, 50 nm, is grown on the surface of the support substrate by thermal oxidation.

[0074] Subsequently, a 50 nm thick silicon nitride (SiN) layer was deposited on the second oxide layer of the supporting substrate using plasma-enhanced chemical vapor deposition (PECVD) as a charge trapping layer. The initial temperature during the deposition process was controlled at 400 °C, and the reaction gases were silane and ammonia.

[0075] After deposition but before bonding, the support substrate is placed in an annealing furnace for degassing heat treatment. The second temperature of the heat treatment is set to 500°C, which is 100°C higher than the deposition temperature, and the duration is 2 hours to remove hydrogen components from the inside of the film.

[0076] After heat treatment, the silicon nitride surface is chemically and mechanically polished and plasma activated, and then bonded to the donor substrate. Finally, the donor substrate is peeled off along the ion implantation layer by annealing at 500°C, and the transferred top silicon is rapidly thermally annealed and planarized to obtain the final silicon-on-insulator substrate.

[0077] Example 2 This embodiment is similar to Embodiment 1, except that the material and deposition parameters of the charge trapping layer are different.

[0078] In this embodiment, silicon carbonitride (SiCN) is selected as the charge trapping layer. During the deposition step, silane, ammonia, and methane gases are introduced into the reaction chamber, and the deposition temperature (first temperature) is controlled at 380°C.

[0079] In the subsequent degassing heat treatment step, the second temperature was set to 480°C, which is 100°C higher than the deposition temperature, and the duration was 2 hours. The remaining bonding and stripping steps were consistent with those in Example 1.

[0080] Comparative Example 1 This comparative example represents a silicon-on-insulator substrate used in radio frequency applications in related technologies. The difference lies in the use of undoped polysilicon (Poly-Si) for the charge trapping layer. The polysilicon layer is formed by low-pressure chemical vapor deposition at 620°C. Due to the high deposition temperature of polysilicon and the absence of significant hydrogen bonding, this comparative example does not undergo specialized degassing heat treatment. Instead, the polysilicon surface is directly lightly oxidized and polished before bonding to the donor substrate.

[0081] Comparative Example 2 This comparative example aims to verify the necessity of the degassing process.

[0082] The preparation process is basically the same as in Example 1, except that the high-temperature degassing heat treatment step is omitted after the silicon nitride layer is deposited. The deposited support substrate is directly subjected to chemical mechanical polishing and surface activation, and then bonded to the donor substrate and subsequently subjected to lift-off annealing.

[0083] The following performance tests were performed on the substrate prepared above: Bonding interface quality: The bonding interface was non-destructively tested using a scanning acoustic microscope (SAM), and the density of micropores (bubbles) with a diameter greater than 50 micrometers was statistically analyzed.

[0084] Dielectric constant (k value): The dielectric constant of the buried layer material is extracted by capacitance-voltage (CV) measurement after fabricating a metal-insulator-semiconductor (MIS) capacitor structure.

[0085] High-frequency parasitic capacitance effect: The signal loss and harmonic distortion of the substrate at high frequencies are measured using a coplanar waveguide (CPW) transmission line test structure to evaluate the degree of parasitic capacitance coupling.

[0086] Charge retention characteristics: After injecting charge into the charge trapping layer, it is baked at high temperature (150°C), and the flat band voltage drift is measured to estimate the charge retention rate after 10 years.

[0087] Experimental Results and Analysis The specific test data is summarized in Tables 1 and 2 below.

[0088] Table 1: Comparison Table of Process Condition Settings

[0089] Table 2: Performance Test Results Comparison Table

[0090] Results Analysis First, regarding the decisive impact of the degassing process on bonding quality.

[0091] Comparative Example 1 and Comparative Example 2 both employed PECVD technology to deposit silicon nitride. Comparative Example 2 omitted the degassing step, as... Figure 4 As shown, after bonding, annealing at 400℃ for 2 hours revealed dense white spots at the bonding interface under a scanning acoustic microscope, with a micropore density exceeding 10 per square centimeter. This indicates that a large amount of hydrogen remaining inside the film was released during the bonding annealing process, resulting in severe interface delamination and bubbles. As the annealing time increases, more gas will be released at the bonding surface, leading to large-area bonding defects.

[0092] Conversely, Example 1 employed the reverse thermal budgeting process proposed in this application, i.e., degassing was performed at 500°C (above the deposition temperature). Figure 5 As shown, after degassing and annealing at 400°C for 2 hours, the test results showed that the micropore density of Example 1 was less than 0.1 pores / cm², achieving essentially void-free bonding. This stark contrast powerfully demonstrates that for hydrogen-containing chemical vapor deposition films, "degassing treatment above the deposition temperature" is a necessary and critical setting for achieving high-quality wafer bonding.

[0093] Second, regarding the improvement of electrical performance through material selection.

[0094] Comparing Example 2 with Comparative Example 1, Comparative Example 1 uses polysilicon as the trapping layer. Although polysilicon is widely used in the radio frequency field, its dielectric constant is as high as 11.9, and as a semiconductor material, if it is not completely depleted at high frequencies, a conductive layer will be generated, resulting in severe parasitic capacitive coupling and signal loss.

[0095] In contrast, the silicon carbonitride material used in Example 2 has a reduced dielectric constant of approximately 4.8. This is due to the reduction in polarizability caused by the introduction of carbon atoms. At the same thickness, using silicon carbonitride as a buried layer results in only about 40% of the parasitic capacitance of the polycrystalline silicon solution. This significant improvement is crucial for high-density 3D memory arrays, effectively reducing RC delay between bit lines and word lines and improving device read / write speeds.

[0096] Third, regarding the advantages of the charge storage mechanism.

[0097] In the charge retention characteristic test, both Examples 1 and 2 exhibited excellent data retention capabilities. This is because the amorphous dielectric material used in this application utilizes deep-level defects within the bulk phase, such as dangling bonds, to trap charges. These deep-level traps have good thermal stability at high temperatures, making it difficult for charges to escape. In contrast, the polycrystalline silicon in Comparative Example 1 mainly relies on grain boundaries to trap charges. During high-temperature processing, grains are prone to secondary growth, leading to a reduction in grain boundaries and a decrease in trap density, thereby causing a degradation in charge retention characteristics.

[0098] In summary, the experimental data further confirm that by using nitrogen-containing dielectric materials and combining them with a specific degassing process, this application has successfully solved the problem of bonded bubbles and simultaneously achieved low parasitic capacitance and high-reliability charge storage.

[0099] It should be noted that the technical solutions described in this application can be combined arbitrarily without conflict.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a silicon-on-insulator substrate, characterized in that, The preparation method includes: A donor substrate and a support substrate are provided, wherein the donor substrate has an ion implantation layer and a first oxide layer is formed on the surface of the donor substrate; A charge trapping layer is deposited on the surface of the support substrate at a first temperature. The charge trapping layer is a nitrogen-containing dielectric material layer. The support substrate on which the charge trapping layer is deposited is heat-treated at a second temperature, which is higher than the first temperature. The donor substrate having the first oxide layer is bonded to the support substrate having the charge trapping layer to form a bonding structure; and By peeling the donor substrate along the ion implantation layer, a portion of the donor substrate is transferred onto the support substrate to form an insulating buried layer and a top silicon layer on the support substrate, the insulating buried layer comprising the stacked charge trapping layer and the first oxide layer.

2. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The charge trapping layer is a silicon nitride layer or a silicon carbonitride layer.

3. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, Before depositing the charge trapping layer, the fabrication method further includes: forming a second oxide layer on the surface of the supporting substrate; The deposition step includes depositing the charge trapping layer on the second oxide layer.

4. The method for preparing a silicon-on-insulator substrate according to claim 3, characterized in that, The thickness of the first oxide layer is 5 nm to 200 nm, the thickness of the second oxide layer is 1 nm to 100 nm, and the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

5. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The thickness of the charge trapping layer is 30 nm to 100 nm.

6. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The surface roughness of the charge trapping layer after the heat treatment is less than 0.3 nm.

7. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, Following the stripping step, the preparation method further includes: The top silicon layer is planarized. The planarization process includes rapid thermal annealing or chemical mechanical polishing.

8. The method for preparing a silicon-on-insulator substrate according to claim 7, characterized in that, The rapid thermal annealing process is carried out in a hydrogen-containing atmosphere at a temperature of 1100°C to 1300°C.

9. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The first temperature is less than 450°C; the second temperature is between 450°C and 550°C.

10. A silicon-on-insulator substrate, characterized in that, The silicon-on-insulator substrate is prepared by the method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 9, wherein the silicon-on-insulator substrate comprises: Support substrate; Insulating buried layer; The top silicon layer, wherein the insulating buried layer is located between the supporting substrate and the top silicon layer; The insulating buried layer includes a charge trapping layer and a first oxide layer stacked together. The charge trapping layer is located between the supporting substrate and the first oxide layer, and the charge trapping layer is a nitrogen-containing dielectric material layer.

11. The silicon-on-insulator substrate according to claim 10, characterized in that, The insulating buried layer further includes a second oxide layer, which is located between the supporting substrate and the charge trapping layer; the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

12. The silicon-on-insulator substrate according to claim 10, characterized in that, The charge trapping layer is a silicon carbonitride layer or a silicon nitride layer.

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