Packaging structure and manufacturing method thereof
By forming inclined sidewall cavities and setting conductive pillars on the substrate, the problem of high aspect ratio vias in the packaging structure is solved, achieving stable electrical lead-out of electronic components and simplifying the process, which is suitable for miniaturized electronic products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LEADING INTERCONNECT SEMICON TECH SHENZHEN CO LTD
- Filing Date
- 2024-11-18
- Publication Date
- 2026-05-22
AI Technical Summary
Existing technologies make it difficult to achieve high aspect ratio vias in packaging structures, especially for electronic components with small thicknesses that require vias with an aspect ratio greater than 1.2:1, which cannot meet design requirements.
A cavity with a wide end and a narrow end is formed on the substrate. An electronic component is held in place by an inclined sidewall. A conductive post is provided on the electronic component. The conductive post is covered by an encapsulation layer and exposed, forming an encapsulation structure that is electrically connected to the circuit layer.
It enables stable electrical extraction of thin electronic components within a deep cavity, simplifying the process, reducing costs, and making it suitable for mass production.
Smart Images
Figure CN122074017A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of packaging technology, and in particular to a packaging structure and its manufacturing method. Background Technology
[0002] With the miniaturization of electronic products, the size of packaging structures is constantly decreasing, while the number of mounted electronic components is increasing, leading to a proliferation of intricate circuitry. To meet this design requirement, it is typically necessary to embed electronic components inside the packaging structure, and then achieve electrical conductivity by laser-drilling holes on the front and back of the packaging structure.
[0003] However, due to the wide variety and functions of electronic components, especially the need to embed electronic components of different heights within the same packaging layer, when embedding multiple electronic components with a large height difference within the same packaging layer, the via aspect ratio (the ratio of the via depth to the via diameter) may be relatively large for electronic components with smaller thickness. It usually needs to reach 3:1 to 5:1 or even larger. This poses a huge challenge to processes such as laser drilling and copper plating. Currently, the maximum aspect ratio that can be achieved for vias is around 1.2:1, which is almost impossible to meet the aforementioned high aspect ratio requirements. Summary of the Invention
[0004] In view of this, in order to solve at least one of the above problems, this application needs to provide a method for manufacturing an encapsulation structure.
[0005] In addition, this application also needs to provide a packaging structure manufactured using the aforementioned packaging structure manufacturing method.
[0006] This application provides a method for fabricating a circuit structure, comprising: forming a cavity on a substrate, wherein the cavity includes a first end and a second end disposed opposite to each other along the thickness direction of the substrate, and the inner diameter of the cavity decreases sequentially from the first end to the second end; disposing an electronic component within the cavity, the electronic component including an electronic component body and a conductive post electrically connected to the electronic component body, the electronic component body being held against the sidewall of the substrate corresponding to the second end, and the conductive post extending out of the cavity; filling the cavity with an encapsulation layer to cover the electronic component, and exposing the conductive post through the encapsulation layer; and forming a first circuit layer on the surfaces of the encapsulation layer and the substrate, the first circuit layer being electrically connected to the conductive post, thereby obtaining the encapsulation structure.
[0007] In some possible embodiments, the first dimension of the conductive post is 50 μm to 100 μm along the extension direction of the substrate, and the second dimension of the conductive post is 50 μm to 500 μm along the thickness direction of the substrate.
[0008] In some possible embodiments, the ratio of the second dimension to the first dimension is 3:1 to 5:1.
[0009] In some possible embodiments, the conductive post is a wire.
[0010] In some possible embodiments, the electronic component is tilted at an angle of 1° to 80° relative to the surface of the substrate near the second end.
[0011] In some possible embodiments, the conductive post is exposed from the encapsulation layer by a brushing process.
[0012] In some possible embodiments, after the step of forming a first circuit layer on the surface of the encapsulation layer and the substrate, the fabrication method further includes: forming at least one second circuit layer on the surface of the first circuit layer, the second circuit layer being electrically connected to the first circuit layer.
[0013] This application embodiment also provides a packaging structure manufactured by the packaging structure manufacturing method described above, including: a base layer, an electronic component, a packaging layer, and a first circuit layer. A cavity is formed on the base layer. Along the thickness direction of the base layer, the cavity includes a first end and a second end disposed opposite to each other. The inner diameter of the cavity decreases sequentially from the first end to the second end. The electronic component is located in the cavity. The electronic component includes an electronic component body and a conductive post electrically connected to the electronic component body. The electronic component body is held on the sidewall of the base layer corresponding to the second end, and the conductive post extends out of the cavity. The packaging layer fills the cavity and covers the electronic component, and the conductive post is exposed by the packaging layer. The first circuit layer is located on the surface of the packaging layer and the substrate, and the first circuit layer is electrically connected to the conductive post.
[0014] In some possible embodiments, the first dimension of the conductive post is 50μm to 100μm along the extension direction of the substrate, and the second dimension of the conductive post is 50μm to 500μm along the thickness direction of the substrate.
[0015] In some possible embodiments, the ratio of the second dimension to the first dimension is 3:1 to 5:1; and / or, the conductive post is a wire.
[0016] Compared to existing technologies, the packaging structure and manufacturing method provided in this application, by forming a cavity with a wide end and a narrow end on the base layer, and the sidewall of the base layer corresponding to the cavity being inclined sidewalls, can hold the electronic component body within the cavity, improving the stability of the electronic component and increasing the yield of electrical leads. By directly setting conductive posts on the electronic component body to achieve conductivity between the electronic component body and external circuitry, the height of the conductive posts can be designed according to actual needs, enabling electrical leads of a thin electronic component body within a deep cavity, making electrical leads more convenient, flexible, and simple, simplifying the process of electrical leads of the electronic component body, and eliminating the need for traditional via forming processes. The inclined sidewalls can hold the electronic component in place, and together with the conductive posts on the electronic component, allow for large-angle displacement of the electronic component within the cavity, ensuring stable fixation after displacement while achieving good electrical leads.
[0017] In addition, the packaging structure manufacturing method of this application embodiment is simple and easy to operate. Compared with the traditional method of embedding electronic components, it saves the manufacturing process of vias, can realize the manufacturing of a large aspect ratio of more than 3:1, has low cost, and is easy to achieve large-scale mass production. Attached Figure Description
[0018] Figure 1 A flowchart illustrating the method for fabricating the packaging structure provided in this application embodiment.
[0019] Figure 2 This is a schematic diagram of the structure of the substrate provided in an embodiment of this application.
[0020] Figure 3 In order to be in Figure 2 A schematic diagram of a structure in which a window is formed on the first metal layer.
[0021] Figure 4 In order to be in Figure 3 A schematic diagram of a cavity formed on a substrate.
[0022] Figure 5 In order to be in Figure 4 A schematic diagram of the structure in which electronic components are placed inside the cavity.
[0023] Figure 6 for Figure 5 A schematic diagram of the structure of the electronic components.
[0024] Figure 7 This is a schematic diagram of the packaging structure of a typical embedded electronic component.
[0025] Figure 8 In order to be in Figure 5 A schematic diagram of the structure in which the cavity is filled with an encapsulation layer.
[0026] Figure 9 To remove Figure 7 A schematic diagram of the structure in which the middle encapsulation layer exposes the first metal layer and the conductive pillar.
[0027] Figure 10 In order to be in Figure 5 A schematic diagram of a structure in which an encapsulation layer is filled inside a cavity and electronic components are offset within the encapsulation layer.
[0028] Figure 11 In order to be in Figure 5 Another schematic diagram of a structure in which the cavity is filled with an encapsulation layer and the electronic components are offset within the encapsulation layer.
[0029] Figure 12 In order to be in Figure 8 A schematic diagram of a structure in which a second metal layer is formed on the surface of the first metal layer and the encapsulation layer.
[0030] Figure 13 In order to be in Figure 12 A schematic diagram of the structure in which the first circuit layer is formed on the surface of the base layer and the encapsulation layer.
[0031] Figure 14 In order to be in Figure 10 A schematic diagram of the structure in which the first circuit layer is formed on the surface of the base layer and the encapsulation layer.
[0032] Figure 15 In order to be in Figure 11 A schematic diagram of the structure in which the first circuit layer is formed on the surface of the base layer and the encapsulation layer.
[0033] Figure 16 In order to be in Figure 13 A schematic diagram of the structure of the insulation layer laminated on the first line layer.
[0034] Figure 17 In order to be in Figure 16 A schematic diagram of a structure with openings in the insulating layer.
[0035] Figure 18 This is a schematic diagram of the packaging structure provided in one embodiment of this application.
[0036] Explanation of main component symbols
[0037] Package structure 100,100'
[0038] Substrate 10
[0039] 1,1'
[0040] Side wall 11
[0041] First metal layer 2
[0042] Open window 21
[0043] Cavity 20, 20'
[0044] First end 201
[0045] Second end 202
[0046] Electronic components 30, 3'
[0047] Electronic component body 3
[0048] Conductor post 4
[0049] Encapsulation layer 40
[0050] Second metal layer 50
[0051] First Line Layer 5
[0052] Second line layer 6
[0053] Insulation layer 60
[0054] Inner diameter L
[0055] Thickness direction a
[0056] Extension direction b
[0057] Angle β
[0058] Through hole 4'
[0059] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0060] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0061] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. When a component is said to be "set on" another component, it can be directly set on the other component or there may be an intervening component.
[0062] Please see Figure 1 As shown, please refer to the following: Figures 2 to 13 As shown in the figure, this application embodiment provides a method for manufacturing a packaging structure 100, the method specifically including the following steps:
[0063] Step S1, as follows Figures 2 to 4As shown, a cavity 20 is formed on a substrate 10. Along the thickness direction a of the substrate 10, the cavity 20 includes a first end 201 and a second end 202 disposed opposite to each other. From the first end 201 to the second end 202, the inner diameter L of the cavity 20 decreases sequentially.
[0064] Step S1 specifically includes the following steps:
[0065] Step S11, as follows Figure 2 As shown, a substrate 10 is provided, the substrate 10 including a base layer 1 and a first metal layer 2 disposed on at least one surface of the base layer 1.
[0066] In some embodiments, the first metal layer 2 is provided on both opposite surfaces of the base layer 1.
[0067] In some embodiments, the base layer 1 may be made of insulating resin.
[0068] Step S12, as follows Figure 3 As shown, a window 21 is formed on the first metal layer 2, so that the base layer 1 is exposed through the window 21.
[0069] In some embodiments, a portion of the first metal layer 2 may be removed by etching to form the window 21.
[0070] In some embodiments, when the first metal layer 2 is provided on both surfaces of the base layer 1, the opening 21 can be formed on both first metal layers 2, and the projections of the opening 21 on the two first metal layers 2 on the base layer 1 overlap along the thickness direction a of the substrate 10, so as to facilitate the subsequent formation of the cavity 20.
[0071] Step S13, as follows Figure 4 As shown, the cavity 20 is formed by penetrating the base layer 1 exposed by the window 21, and the cavity 20 is connected to the window 21.
[0072] In some embodiments, the cavity 20 can be formed by laser cavity opening. During the laser cavity opening process, the side wall 11 of the cavity 20 corresponding to the base layer 1 needs to be formed into an inclined surface so that the inner diameter L of the cavity 20 decreases sequentially from the first end 201 to the second end 202. For example, the cross-section of the cavity 20 can be trapezoidal.
[0073] Step S2, as follows Figure 5 and Figure 6As shown, an electronic component 30 is disposed in the cavity 20. The electronic component 30 includes an electronic component body 3 and a conductive post 4 electrically connected to the electronic component body 3. The electronic component body 3 is held in place on the side wall 11 of the base layer 1 corresponding to the second end 202, and the conductive post 4 extends out of the cavity 20.
[0074] Specifically, by designing the inner diameter of the cavity 20 to decrease sequentially from the first end 201 to the second end 202, the sidewall 11 forms an inclined surface. When the electronic component 30 is placed inside the cavity 20, it can be held in place by the sidewall 11 corresponding to the smaller inner diameter of the second end 202. This improves the stability of the electronic component 30 within the cavity 20 and prevents it from being displaced due to impact during the subsequent filling of the encapsulant, which could affect its electrical lead-out. Furthermore, the larger inner diameter of the first end 201 facilitates the placement of the electronic component 30.
[0075] like Figure 7 As shown, in the previous design of the encapsulation structure 100' for embedded electronic components 3', the electronic component 3' needs to be first embedded in the cavity 20' formed on the substrate 1' and encapsulated. Then, through-holes 4' are formed in the encapsulation layer by drilling and electroplating to achieve electrical lead-out of the electronic component 3'. However, when multiple electronic components 3' of different thicknesses need to be embedded, the electronic component 3' with a smaller thickness requires a larger depth of through-hole 4', and the through-hole 4' has a larger aspect ratio (e.g., ...). Figure 7 When the aspect ratio exceeds 5:1, the existing through-hole forming process can only achieve a maximum aspect ratio of around 1.2:1, making it almost impossible to achieve through-holes with aspect ratios of 3:1 or even higher. In such cases, using traditional through-hole forming processes will result in issues such as... Figure 7 As shown in the diagram, the via 4' cannot reach the position of the electronic component 3', and therefore cannot achieve communication with the electronic component 3'.
[0076] In this application, a conductive post 4 is directly provided on the electronic component body 3 to enable electrical connection between the electronic component body 3 and external circuitry. The height of the conductive post 4 can be designed according to actual needs; any excess height can be removed later. This allows for electrical lead-out of the electronic component body 3 with greater depth, making electrical lead-out more convenient, flexible, and simple. It simplifies the process of electrical lead-out of the electronic component body 3, eliminating the need for traditional through-hole forming processes.
[0077] In some embodiments, along the extending direction b of the substrate 10, the first dimension (i.e., the radial dimension of the conductive post 4) is 50μm to 100μm, and along the thickness direction a of the substrate 10, the second dimension (i.e., the length of the conductive post 4) is 50μm to 500μm. In this case, the ratio of the second dimension to the first dimension of the conductive post 4 can be 1:1 to 10:1, for example, 1:1, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, etc. The dimensions of the conductive post 4 can be flexibly set according to actual needs to meet the electrical lead-out requirements of electronic component bodies 3 of different thicknesses. Understandably, the length of the conductive post 4 is usually designed to be longer, extending beyond the cavity 20 to facilitate subsequent electrical conduction operations.
[0078] By adopting the method of this application, electronic components 30 of various thicknesses can be led out from the front and back of the substrate 10, or led out from both the front and back simultaneously, which is more flexible.
[0079] In some embodiments, the ratio of the second dimension to the first dimension can be 3:1 to 5:1, which can meet the current electrical lead-out requirements of the embedded electronic components 30.
[0080] In some embodiments, such as Figure 6 As shown, the conductive post 4 can be a wire. Specifically, the conductive post 4 can be pre-soldered to the output terminal 31 of the electronic component body 3.
[0081] Understandably, the thickness of the base layer 1 can be selected according to the thickness of the thickest electronic component 30 that needs to be embedded. Through the design of the conductive post 4, electronic components 30 of different thicknesses can be embedded. For example, the thickness of the base layer 1 can be approximately 600 μm, and the thickness of the embedded electronic component 30 can be 100 μm, 150 μm, 200 μm, 300 μm, 400 μm, 550 μm, etc. The radial dimension of the conductive post 4 can be 60 μm, and its length can be adjusted according to the thickness of different electronic components 30.
[0082] Step S3, as follows Figure 8 and Figure 9 As shown, an encapsulation layer 40 is filled inside the cavity 20 to cover the electronic component 30, and the conductive post 4 is exposed from the encapsulation layer 40.
[0083] The encapsulation layer 40 can be formed by filling and curing encapsulation material into the cavity 20. Specifically, after the electronic component 30 is placed inside the cavity 20, it is held in place by the sidewall 11 at the narrow end of the cavity 20. Encapsulation material is then filled into the cavity 20, completely covering the electronic component 30. Furthermore, because the encapsulation material is in a flowing state during filling, the electronic component 30 will not experience significant positional displacement due to the impact of the encapsulation material, thus preventing any impact on the electrical lead-out of the conductive post 4.
[0084] Understandably, during the placement of the electronic component 30 and subsequent filling with encapsulation material, the electronic component 30 may experience some displacement. In some embodiments, the tilt angle of the electronic component 30 relative to the surface of the substrate 10 near the second end 202 can be 1° to 80°, meaning the angle at which the electronic component 30 shifts can be 1° to 80°. Due to the holding effect of the tilted sidewall 11, even if the electronic component 30 experiences a large angle of displacement, it can be stably held within the cavity 20. Furthermore, because the electronic component 30 is provided with a conductive post 4, even if the electronic component 30 shifts, good electrical lead-out can still be achieved. Therefore, the tilted sidewall 11 corresponding to the cavity 20, in conjunction with the conductive post 4 of the electronic component 30 itself, allows the electronic component 30 to undergo a large angle of displacement within the cavity without affecting stability and electrical lead-out. For example, for ease of description, let's consider... Figure 10 and Figure 11 Taking the cross-sectional view shown as an example, the angle β of the electronic component 30 is approximately 30°. Although the conductive post 4 is tilted at this time, it will not affect the electrical lead-out of the conductive post 4.
[0085] In some embodiments, after the encapsulation layer 40 is filled, the surface of the encapsulation layer 40 needs to be polished to expose the first metal layer 2 and the conductive post 4. If the height of the conductive post 4 exceeds the surface of the encapsulation layer 40, the excess part of the conductive post 4 can be polished away to make the surface of the conductive post 4 flush with the first metal layer 2, so as to facilitate the subsequent formation of circuits.
[0086] In some embodiments, brushing can be used to polish the encapsulation layer 40 and the conductive post 4.
[0087] Step S4, as follows Figures 12 to 18 As shown, a first circuit layer 5 is formed on the surface of the encapsulation layer 40 and the substrate 10. The first circuit layer 5 is electrically connected to the conductive post 4, thereby obtaining the encapsulation structure 100.
[0088] Step S4 may include the following steps:
[0089] Step S41, as follows Figure 12As shown, a second metal layer 50 is formed on the surface of the first metal layer 2, the encapsulation layer 40 and the conductive post 4.
[0090] Step S42, as follows Figure 13 As shown, the first metal layer 2 and the second metal layer 50 are patterned to form the first circuit layer 5. The patterning can be performed using conventional circuit fabrication processes.
[0091] The method described in this application eliminates the need for drilling and electroplating to form vias in the encapsulation layer 40. The electronic component body 3 directly connects to the first circuit layer 5 via the conductive post 4, simplifying the process and reducing operational difficulty. Furthermore, the first circuit layer 5 can be simultaneously deployed on both the front and back sides of the encapsulation layer 40, meaning wiring can be implemented on the corresponding surface of the cavity 20. This significantly increases wiring density without increasing the volume of the encapsulation structure 100, aligning with the miniaturization trend of electronic products. Traditional via methods cannot achieve wiring at this location.
[0092] From such Figure 14 and Figure 15 As can be seen, when the electronic component 30 shifts within the cavity 20, the polished surface of the conductive post 4 is flush with the surface of the encapsulation layer 40, completely unaffecting the layout of the first circuit layer 5 and its connection with the conductive post 4. For this type of electronic component 30 that has shifted to a certain extent, the connection method of this embodiment, used to achieve connection between the electronic component body 3 and the first circuit layer 5, eliminates the need for a high-precision tilted via design, making the operation simpler, more convenient, and less difficult.
[0093] After step S42, the method further includes:
[0094] Step S43, as follows Figures 16 to 18 As shown, at least one second circuit layer 6 is formed on the surface of the first circuit layer 5, and the second circuit layer 6 is electrically connected to the first circuit layer 5.
[0095] An insulating layer 60 can be laminated onto the surface of the first circuit layer 5 using conventional layering methods, and at least one second circuit layer 6 can be formed on the surface of the insulating layer 60, thereby obtaining a package structure 100 with multi-layer circuitry, further enhancing the multifunctionality of the package structure 100.
[0096] Based on the same inventive concept, such as Figure 18As shown in the figure, this application embodiment also provides a packaging structure 100 manufactured by the aforementioned packaging structure manufacturing method. The packaging structure 100 includes: a base layer 1, an electronic component 30, a packaging layer 40, and a first circuit layer 5. A cavity 20 is formed on the base layer 1. Along the thickness direction a of the base layer 1, the cavity 20 includes a first end 201 and a second end 202 disposed opposite to each other. From the first end 201 to the second end 202, the inner diameter L of the cavity 20 decreases sequentially. The electronic component 30 is located inside the cavity 20. The electronic component 30 includes an electronic component body 3 and a conductive post 4 electrically connected to the electronic component body 3. The electronic component body 3 is held on the side wall 11 of the base layer 1 corresponding to the second end 202, and the conductive post 4 extends out of the cavity 20. The encapsulation layer 40 fills the cavity 20 and covers the electronic component 30, and the conductive post 4 is exposed through the encapsulation layer 40; the first circuit layer 5 is located on the surface of the base layer 1 and the encapsulation layer 40, the first circuit layer 5 is electrically connected to the conductive post 4, and the first circuit layer 5 has a window 21 corresponding to the cavity 20.
[0097] In some embodiments, the first circuit layer 5 is provided on the two opposite surfaces of the base layer 1, which can realize flexible double-sided lead-out of the embedded electronic components 30.
[0098] In some embodiments, the base layer 1 may be made of insulating resin.
[0099] In some embodiments, the tilt angle of the electronic component 30 relative to the surface of the substrate 10 near the second end 202 can be 1° to 80°.
[0100] In some embodiments, along the extension direction b of the base layer 1, the first dimension (i.e., the radial dimension of the conductive post 4) is 50μm to 100μm, and along the thickness direction a of the base layer 1, the second dimension (i.e., the length of the conductive post 4) is 50μm to 500μm. In this case, the ratio of the second dimension to the first dimension of the conductive post 4 can be 1:1 to 10:1, for example, 1:1, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, etc. The dimensions of the conductive post 4 can be flexibly set according to actual needs to meet the electrical lead-out requirements of electronic component bodies 3 of different thicknesses. Understandably, the length of the conductive post 4 is usually designed to be longer, extending beyond the cavity 20 to facilitate subsequent electrical conduction operations.
[0101] In some embodiments, the ratio of the second dimension to the first dimension can be 3:1 to 5:1, which can meet the current electrical lead-out requirements of the embedded electronic components 30.
[0102] In some embodiments, the conductive post 4 can be a wire.
[0103] In some embodiments, at least one second circuit layer 6 is formed on the surface of the first circuit layer 5, and the second circuit layer 6 is electrically connected to the first circuit layer 5. At least one second circuit layer 6 can be formed on the surface of the first circuit layer 5 using conventional layer-addition methods, thereby obtaining a package structure 100 with multi-layer circuitry, further enhancing the multifunctionality of the package structure 100.
[0104] Compared to existing technologies, the packaging structure 100 and its manufacturing method provided in this application, by forming a cavity 20 with a wide end and a narrow end on the base layer 1, and the sidewall 11 of the base layer 1 corresponding to the cavity 20 being an inclined sidewall, can hold the electronic component body 3 inside the cavity 20, improving the stability of the electronic component 30 within the cavity 20 and increasing the yield of electrical leads. By directly setting the conductive post 4 on the electronic component body 3, the electronic component body 3 can be connected to external circuits. The height of the conductive post 4 can be designed according to actual needs, enabling the electrical lead-out of the thin electronic component body 3 within the deep cavity 20, making electrical lead-out more convenient and flexible, simplifying the process of electrical lead-out of the electronic component body 3, and eliminating the need for traditional through-hole forming processes. The inclined sidewall 11 can hold the electronic component 30 in place, and in conjunction with the conductive post 4 on the electronic component 30, it can allow the electronic component 30 to deviate at a large angle within the cavity 20, and after deviating, it can be stably fixed while achieving good electrical lead-out.
[0105] Furthermore, the manufacturing method of the packaging structure 100 in this application embodiment is simple and easy to operate. Compared with the traditional method of embedding electronic components, it saves the manufacturing process of vias, enables the fabrication of conductive paths with a large aspect ratio of more than 3:1, has lower cost, and is easy to achieve large-scale mass production.
Claims
1. A method for manufacturing an encapsulation structure, characterized in that, include: A cavity is formed on a substrate. Along the thickness direction of the substrate, the cavity includes a first end and a second end disposed opposite to each other. The inner diameter of the cavity decreases sequentially from the first end to the second end. An electronic component is disposed within the cavity. The electronic component includes an electronic component body and a conductive post electrically connected to the electronic component body. The electronic component body is held in place on the side wall of the substrate corresponding to the second end, and the conductive post extends out of the cavity. The cavity is filled with an encapsulation layer to cover the electronic component, and the conductive post is exposed through the encapsulation layer. as well as A first circuit layer is formed on the surface of the encapsulation layer and the substrate, and the first circuit layer is electrically connected to the conductive post to obtain the encapsulation structure.
2. The method for manufacturing the packaging structure as described in claim 1, characterized in that, Along the extension direction of the substrate, the first dimension of the conductive post is 50μm to 100μm, and along the thickness direction of the substrate, the second dimension of the conductive post is 50μm to 500μm.
3. The method for manufacturing the packaging structure as described in claim 2, characterized in that, The ratio of the second dimension to the first dimension is 3:1 to 5:
1.
4. The method for manufacturing the packaging structure as described in claim 2, characterized in that, The conductive post is a wire.
5. The method for manufacturing the packaging structure as described in claim 1, characterized in that, The electronic component is tilted at an angle of 1° to 80° relative to the surface of the substrate near the second end.
6. The method for manufacturing the packaging structure as described in claim 1, characterized in that, The conductive post is exposed from the encapsulation layer by a brushing process.
7. The method for manufacturing the packaging structure as described in claim 1, characterized in that, After the step of forming a first circuit layer on the surface of the encapsulation layer and the substrate, the manufacturing method further includes: At least one second circuit layer is formed on the surface of the first circuit layer, and the second circuit layer is electrically connected to the first circuit layer.
8. A packaging structure manufactured by the method for manufacturing the packaging structure according to claim 1, characterized in that, include: A base layer, on which a cavity is formed, the cavity having a first end and a second end disposed opposite each other along the thickness direction of the base layer, the inner diameter of the cavity decreasing sequentially from the first end to the second end; An electronic component is located within the cavity. The electronic component includes an electronic component body and a conductive post electrically connected to the electronic component body. The electronic component body is held in place on the side wall of the base layer corresponding to the second end, and the conductive post extends out of the cavity. An encapsulation layer is filled within the cavity and covers the electronic component, with the conductive post exposed through the encapsulation layer; as well as A first circuit layer is located on the surface of the encapsulation layer and the substrate, and the first circuit layer is electrically connected to the conductive post.
9. The packaging structure as described in claim 8, characterized in that, Along the extension direction of the substrate, the first dimension of the conductive post is 50μm to 100μm, and along the thickness direction of the substrate, the second dimension of the conductive post is 50μm to 500μm.
10. The packaging structure as described in claim 9, characterized in that, The ratio of the second dimension to the first dimension is 3:1 to 5:1; and / or The conductive post is a wire.