Semiconductor device and method of forming the same

Abstract

A method of forming a semiconductor device includes forming a package assembly including: an interposer including a first redistribution structure; an integrated circuit die attached to the first redistribution structure; forming a package substrate including: forming a second redistribution structure and a third redistribution structure over opposing sides of a substrate core; singulating the substrate core to form assembly substrates; attaching the first assembly substrate and the second assembly substrate to a carrier, the first assembly substrate and the second assembly substrate laterally offset by a gap; and forming a bonding layer over the first assembly substrate and the second assembly substrate; attaching the package assembly to the package substrate; and forming external connections over the package substrate, the external connections configured to electrically couple signal routing, power routing, or ground routing of the integrated circuit die to another package assembly. Embodiments of the present disclosure also provide semiconductor devices.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, these improvements in integration density stem from iterative reductions in the smallest component size, allowing more components to be integrated into a given area. As the demand for miniaturized electronics grows, so too does the need for smaller and more innovative semiconductor die packaging technologies. Summary of the Invention

[0003] Some embodiments of this disclosure provide a method for forming a semiconductor device, the method comprising: forming a package assembly including: an interposer including a first redistribution structure; a plurality of integrated circuit dies attached to a first side of the first redistribution structure; forming a package substrate, the forming of the package substrate including: forming a second redistribution structure and a third redistribution structure over opposite sides of substrate dies; dicing the substrate dies to form a plurality of component substrates; attaching the first component substrate and the second component substrate to a carrier, the first component substrate and the second component substrate being laterally offset from each other by a gap; forming a bonding layer over the first component substrate and the second component substrate; attaching the package assembly to the package substrate; and forming an external connector over the package substrate, the external connector being configured to electrically couple signal wiring, power wiring, or ground wiring of the plurality of integrated circuit dies to an additional package assembly.

[0004] Other embodiments of this disclosure provide a method for forming a semiconductor device, the method comprising: forming a first set of through-substrate vias (TSVs) and a second set of TSVs through a substrate core; forming a first redistribution structure over the first set of TSVs; forming a second redistribution structure over the second set of TSVs, the second redistribution structure being electrically isolated from the first redistribution structure and the first set of TSVs; performing a dicing process to form a first component substrate and a second component substrate, wherein the first component substrate includes a first portion of the substrate core, the first set of TSVs and the first redistribution structure, and wherein the second component substrate includes a second portion of the substrate core, the second set of TSVs and the second redistribution structure; attaching the first component substrate and the second component substrate to a carrier, the first component substrate and the second component substrate being laterally offset by a gap; filling the gap with a molding material; forming a third redistribution structure over the first component substrate and the second component substrate, wherein after forming the third redistribution structure, the first component substrate and the second component substrate are electrically connected; and attaching a package assembly to the third redistribution structure, wherein each of the package assembly includes a plurality of integrated circuit dies disposed over an interposer.

[0005] Another embodiment of this disclosure provides a semiconductor device comprising: a packaging substrate including: a first component substrate including a first redistribution structure; a second component substrate including a second redistribution structure, the second component substrate being laterally offset from the first component substrate; a molding material disposed between the first component substrate and the second component substrate; and a third redistribution structure disposed above the first component substrate and the second component substrate, the third redistribution structure being electrically connected to both the first component substrate and the second component substrate; and a first packaging assembly attached to the third redistribution structure, the first packaging assembly including a first integrated circuit die disposed above a first interposer layer. Attached Figure Description

[0006] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a cross-sectional view of an integrated circuit die according to some embodiments.

[0008] Figures 2A to 2B This is a cross-sectional view of a chip stack according to some embodiments.

[0009] Figures 3 to 16 This is a cross-sectional view of an intermediate stage in the manufacturing of an integrated circuit package according to some embodiments.

[0010] Figures 17 to 22 This is a cross-sectional view of an intermediate stage in the manufacturing of an integrated circuit package according to some embodiments.

[0011] Figures 23 to 24 This is a cross-sectional view of various integrated circuit packages according to some other embodiments.

[0012] Figures 25 to 33 This is a cross-sectional view of an intermediate stage in the manufacturing of an integrated circuit package according to some embodiments.

[0013] Figure 34 This is a plan view of an integrated circuit package according to some other embodiments.

[0014] Figures 35 to 37 This is a cross-sectional view of various integrated circuit packages according to some other embodiments.

[0015] Figure 38 This is a plan view of an integrated circuit package according to some other embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or instances of various components for implementing this application. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Additionally, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for clarity and simplicity and does not, in itself, indicate a relationship between the individual embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] According to various embodiments, an integrated circuit package includes one or more package components attached to and electrically connected to a package substrate. For example, a package component may include an integrated circuit die, multiple integrated circuit dies bonded to an interposer (e.g., chip-on-wafer), and / or multiple stacked chips (e.g., system-on-chip). Specifically, one or more redistribution structures are formed over a substrate die in wafer form. The substrate die is then diced into different component substrates, and multiple diced component substrates are bonded to a carrier with gaps between adjacent component substrates. A gap-filling material is then applied to fill the gaps to form a reconstructed package substrate. The reconstructed package substrate may be further processed, such as forming redistribution structures, attaching interconnect dies, and / or forming metal pillars. Despite this further processing, the resulting reconstructed package substrate experiences less warpage than the undiced wafer-form substrate die and redistribution structures. This allows the integrated circuit package to have a larger footprint (e.g., the reconstructed package substrate), which can support larger masks and / or more masks for package components. According to the embodiments discussed herein, integrated circuit packages may include larger package substrates with less warpage, which improves performance, reliability, and lifespan. Additionally, integrated circuits can have improved electrical connections between various package components (e.g., various types of package components or varying technology nodes).

[0019] Figure 1This is a cross-sectional view of integrated circuit die 50. Multiple integrated circuit dies 50 will be packaged in subsequent processes to form an integrated circuit package. Each integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC) die, microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or a combination thereof. Integrated circuit dies 50 may be formed in a wafer, which may include different die regions that are diced in subsequent steps to form multiple integrated circuit dies 50. Integrated circuit die 50 includes a semiconductor substrate 52, interconnect structures 54, die connectors 56, and a dielectric layer 58.

[0020] Semiconductor substrate 52 may be a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. Semiconductor substrate 52 has an active surface (e.g., Figure 1 (the surface facing upwards) and non-active surfaces (e.g.) Figure 1 The surface facing downwards. Devices (not shown separately) are located on the active surface of the semiconductor substrate 52. Devices can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. Non-active surfaces may not contain devices.

[0021] Interconnect structure 54 is located above the active surface of semiconductor substrate 52 and is used to electrically connect devices on semiconductor substrate 52 together to form an integrated circuit. Interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers located within the dielectric layers. Acceptable dielectric materials for dielectric layers include oxides (such as silicon oxide or aluminum oxide), nitrides (such as silicon nitride), combinations thereof (such as silicon oxynitride), etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene-based polymers (BCB), etc. Metallization layers may include conductive vias and / or wires to interconnect devices on semiconductor substrate 52. Metallization layers may be formed of conductive materials, such as metals, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The metallization layers of interconnect structure 54 may be formed by damascene processes, such as single damascene processes, double damascene processes, etc.

[0022] Die connector 56 is located at the front side 50F of integrated circuit die 50. Die connector 56 can be a conductive pillar, pad, etc., for external connection. Die connector 56 is located in and / or on interconnect structure 54. For example, die connector 56 can be part of the upper metallization layer of interconnect structure 54. Die connector 56 can be formed of metal, such as copper, aluminum, etc., and can be formed by, for example, plating.

[0023] Optionally, during the formation of the integrated circuit die 50, a solder region (not shown separately) may be provided on the die connector 56. The solder region can be used to perform chip probe (CP) testing on the integrated circuit die 50. For example, the solder region may be solder balls, solder bumps, etc., for attaching chip probes to the die connector 56. Chip probe testing can be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only integrated circuit dies 50 that are KGD undergo subsequent processing and are packaged, and dies that fail the chip probe test are not packaged. After testing, the solder region can be removed.

[0024] Dielectric layer 58 is located at the front side 50F of integrated circuit die 50. Dielectric layer 58 is located in and / or on interconnect structure 54. For example, dielectric layer 58 may be an upper dielectric layer of interconnect structure 54. Dielectric layer 58 laterally seals die connector 56. Dielectric layer 58 may be an oxide, nitride, polymer, or combination thereof, and may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The front surfaces of die connector 56 and dielectric layer 58 may be substantially coplanar at the front side 50F of integrated circuit die 50 (within the range of process variations).

[0025] Figure 2A and Figure 2BThese are cross-sectional views of die stacks 60A and 60B, respectively. Die stacks 60A and 60B may each have a single function (e.g., a logic device, a memory die, etc.) or multiple functions. In some embodiments, die stack 60A is a logic device, such as a system-on-a-chip (SoIC) device, and die stack 60B is a memory device, such as a high-bandwidth memory (HBM) device.

[0026] like Figure 2A As shown, the die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, the first integrated circuit die 50A is a logic die, and the second integrated circuit die 50B is an interface die. The interface die bridges the logic die to other package components (such as memory dies) and translates commands between the logic die and the integrated circuits (such as memory dies) of other package components. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are bonded such that the active surfaces face each other (e.g., a "face-to-face" bonding). A conductive via 62 may be formed through one of the integrated circuit dies 50, thereby enabling external interconnection of the die stack 60A. The conductive via 62 may be a substrate through-hole (TSV), such as a silicon through-hole. In the illustrated embodiment, the conductive via 62 is formed in the second integrated circuit die 50B (e.g., the interface die). Conductive vias 62 extend through the semiconductor substrate 52 of the corresponding integrated circuit die 50 to physically and electrically connect to the metallization layer of the interconnect structure 54.

[0027] like Figure 2B As shown, the die stack 60B is a stacked device comprising multiple semiconductor substrates 52. For example, the die stack 60B can be a memory device comprising multiple memory dies, such as a hybrid memory cube (HMC) device, a high-bandwidth memory (HBM) device, etc. Each semiconductor substrate 52 may (or may not) have a separate interconnect structure 54. The semiconductor substrates 52 are connected via conductive vias 62, such as TSVs.

[0028] Figures 3 to 16 This refers to the manufacture of an integrated circuit package 400 according to some embodiments (see...). Figures 13 to 16 The view of the intermediate stage in ). Figures 3 to 5The formation of package assembly 200 is illustrated. For example, a package region 100P of an interposer wafer 100 is shown, and package assembly 200 is formed in package region 100P. Although a single package region 100P is shown, it should be understood that multiple package regions 100P can be formed. For example, the interposer wafer 100 is formed to include an interposer layer 240 located in package region 100P. Integrated circuit device 150 is attached to interposer layer 240. Interposer layer 240 may include interconnect dies 110 (e.g., bridge dies) for interconnecting integrated circuit device 150 in package region 100P. Package region 100P can be diced to form package assembly 200.

[0029] Figures 6 to 12 The formation of the reconstructed package substrate 300 is illustrated. For example, a front-side redistribution structure 307 and a back-side redistribution structure 308 are formed over a core substrate 302, and this structure is diced to form different component substrates 330. Multiple diced component substrates 330 are then formed into the reconstructed package substrate 300. Further processing can then be performed to form redistribution structures, interposers, and / or interconnect dies over the component substrates.

[0030] Figures 13 to 16 The formation of an integrated circuit package 400 is illustrated. The integrated circuit package 400 includes one or more package components 200 and a reconstructed package substrate 300. For example, the package component 200 is attached to the reconstructed package substrate 300. The package substrate 300 is diced to form the integrated circuit package 400, which includes the diced package substrate 300 and diced portions of an interposer wafer 100 (e.g., interposer 240). In an embodiment, the integrated circuit package 400 is a chip-on-a-substrate package, wherein one or more integrated circuit chips may be attached to an interposer, which may be attached to the package substrate. For example, such a package may also include integrated circuit chips or dies embedded within an interposer and / or the package substrate. It should be understood that the embodiments can be applied to other three-dimensional integrated circuit (3DIC) packages.

[0031] exist Figure 3 The embodiment provides a carrier substrate 102, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 can be a wafer, thereby enabling multiple packages to be formed simultaneously on the carrier substrate 102.

[0032] Release layer 104 may be formed of a polymer-based material that can be removed together with carrier substrate 102 from the above structure to be formed in subsequent steps. In some embodiments, release layer 104 is a thermally release material based on epoxy resin that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, release layer 104 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. Release layer 104 may be dispensed and cured in liquid form and may be a laminated film laminated onto carrier substrate 102, or a similar form. The top surface of release layer 104 may be flat and may have a high degree of flatness.

[0033] Through-holes 106 are formed above the release layer 104. It should be understood that any desired number and arrangement of through-holes 106 can be formed. As an example of forming through-holes 106, a seed layer (not shown separately) is formed above the release layer 104. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using a deposition process, such as physical vapor deposition (PVD). Photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like, and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the through-holes 106. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroless plating or electroplating from the seed layer. The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and the seed layer are then removed, specifically the portions thereon where no conductive material has formed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer are removed by an acceptable etching process, such as wet etching or dry etching. The remaining portions of the conductive material and seed layer form the through-hole 106.

[0034] Still referencing Figure 3 The interconnect die 110 is placed on the release layer 104. The interconnect die 110 can be placed on the release layer 104 using, for example, a pick-and-place tool. The interconnect die 110 can be used for direct communication between integrated circuit devices (described subsequently) of the integrated circuit package 400.

[0035] Each interconnect die 110 may be a local silicon interconnect (LSI), a large-scale integrated package, an interposer die, etc. The interconnect die 110 may be a bridging die. In the illustrated cross-section, two interconnect dies 110 are attached to package region 100P. It should be understood that any desired number and arrangement of interconnect dies 110 can be attached to each package region 100P. The interconnect dies 110 may include passive devices, such as surface mount devices (SMD), two-terminal integrated passive devices (IPD), multi-terminal IPDs, or integrated voltage regulators (IVR).

[0036] Each interconnect die 110 includes a substrate 112, in which conductive components are formed and / or on the substrate 112. The substrate 112 may include a semiconductor substrate, one or more dielectric layers, etc. Additionally, each interconnect die 110 may include a through-substrate via (TSV) 114 extending into or through the substrate 112, and the TSV 114 may be coupled to the conductive components of the interconnect die 110. In the illustrated embodiment, the substrate 112 initially covers the TSV 114 on the back side of the interconnect die 110. In another embodiment, the TSV 114 is exposed on the back side of the interconnect die 110. The interconnect die 110 also includes die connectors 116 disposed on the front side of the interconnect die 110. Some die connectors 116 may be electrically coupled to the back side of the interconnect die 110 via the TSV 114. The TSV 114 may be very small, such as smaller than the through-hole 106.

[0037] In some embodiments, interconnect die 110 may include die bridge 118. Die bridge 118 may be a metallization layer formed in and / or on, for example, substrate 112, and is intended to interconnect integrated circuit devices (described subsequently) with each other. Die bridge 118 may include interconnects, redistribution lines, etc. Die bridge 118 is located on the front side of interconnect die 110. In this way, interconnect die 110 can be used to directly connect integrated circuit devices and allow communication between integrated circuit devices. In such embodiments, interconnect die 110 may be placed in corresponding regions disposed between subsequently attached integrated circuit devices, such that each interconnect die 110 overlaps with a plurality of above-ground integrated circuit devices. In some embodiments, interconnect die 110 may also include passive and / or active devices. In some embodiments, interconnect die 110 substantially contains neither active nor passive devices. Interconnect die 110 may be placed over carrier substrate 102 such that die bridge 118 faces away from carrier substrate 102 (e.g., toward subsequently attached integrated circuit devices).

[0038] Further reference Figure 3A sealant 128 is formed around each component. After the sealant 128 is formed, it laterally seals the interconnect die 110 and the through-hole 106. The sealant 128 can be a molding compound, epoxy resin, etc. The sealant 128 can be applied by compression molding, transfer molding, etc., and the sealant 128 can be formed above the carrier substrate 102 so that the interconnect die 110 and / or the through-hole 106 are buried or covered. The sealant 128 can be formed in the gap region between the components. The sealant 128 can be applied in liquid or semi-liquid form and then subsequently cured.

[0039] A removal process can optionally be performed on the sealant 128 to expose the interconnect die 110 and the through-hole 106. The removal process can remove material from the sealant 128, the interconnect die 110, and / or the through-hole 106 until the die connector 116 and the through-hole 106 are exposed. The removal process can include, for example, planarization processes, such as chemical mechanical polishing (CMP), grinding processes, etc. After the planarization process, the front surfaces of the sealant 128, the interconnect die 110 (e.g., die connector 116), and the through-hole 106 can be substantially coplanar (within the range of process variations). For example, if the through-hole 106 and the die connector 116 have already been exposed, planarization can be omitted. After the removal process, the through-hole 106 extends through the sealant 128. Thus, the through-hole 106 can be referred to as a molded through-hole (TMV).

[0040] exist Figure 4 In this configuration, a front redistribution structure 130 is formed on the front surfaces of the sealant 128, the interconnect die 110 (e.g., die connector 116), and the through-hole 106. The front redistribution structure 130 includes a dielectric layer 132 and a metallization layer 134 (sometimes referred to as a redistribution layer or redistribution line) located within the dielectric layer 132. Therefore, the front redistribution structure 130 includes metallization layers 134 spaced apart from each other by respective dielectric layers 132. The metallization layers 134 of the front redistribution structure 130 are connected to the through-hole 106 and to the interconnect die 110 (e.g., die connector 116).

[0041] In some embodiments, dielectric layer 132 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB-based polymer, etc., and the polymer can be patterned using a photomask. In other embodiments, dielectric layer 132 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, etc. Dielectric layer 132 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. After forming dielectric layer 132, dielectric layer 132 can be patterned to expose underlying conductive components, such as via 106, die connector 116, and / or portions of metallization layer 134. Patterning can be performed by any acceptable process, such as exposing dielectric layer 132 to light when dielectric layer 132 is formed of a photosensitive material, or etching using, for example, anisotropic etching. If dielectric layer 132 is formed of a photosensitive material, dielectric layer 132 can be developed after exposure.

[0042] Each of the metallization layers 134 includes a conductive via and / or a wire. The conductive via extends through the corresponding dielectric layer 132, and the wire extends along the corresponding dielectric layer 132. As an example of forming the metallization layer 134, a seed layer (not shown separately) is formed over the corresponding underlying component. For example, the seed layer may be formed on the corresponding dielectric layer 132 and in any opening through the corresponding dielectric layer 132. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using a deposition process, such as PVD. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like, and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 134. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. Conductive materials can be formed by plating, such as electroless plating or electroplating from the seed layer. The conductive material can include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and the portion of the seed layer on which no conductive material is formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed by an acceptable etching process, such as wet etching or dry etching. The remaining portion of the conductive material and the seed layer forms the metallization layer 134 of the front redistribution structure 130.

[0043] The front redistribution structure 130 is shown as an example. By performing the previously described steps any desired number of times, more or fewer dielectric layers 132 and metallization layers 134 than shown can be formed.

[0044] Other variations of the front redistribution structure 130 are considered. For example, some dielectric layers in dielectric layer 132 can be formed by a sealant, such as molding compound, epoxy resin, etc. Metallization layer 134 can be formed by plating conductive vias from wires. Dielectric layer 132 can be formed by sealing metallization layer 134. Any desired material stack can be used for dielectric layer 132.

[0045] Under-bump metallization (UBM) 136 can be formed through the upper dielectric layer 132 of the front redistribution structure 130. UBM 136 is physically and electrically coupled to the upper metallization layer 134 of the front redistribution structure 130. Each UBM 136 includes a conductive via and a conductive bump. The conductive via extends through the upper dielectric layer 132, and the conductive bump extends along the upper dielectric layer 132. UBM 136 can be formed of the same material as the metallization layer 134. In some embodiments, UBM 136 has different dimensions than the metallization layer 134.

[0046] Still referencing Figure 4 Integrated circuit devices 150 are attached to the front redistribution structure 130. Multiple integrated circuit devices 150 are placed adjacent to each other in package region 100P. Each integrated circuit device 150 in package region 100P may include logic devices 150A and memory devices 150B. Although the illustrated cross-section shows a single logic device 150A and two memory devices 150B, it should be understood that any number of logic devices 150A (e.g., more than one) and memory devices 150B can be attached. Logic devices 150A and memory devices 150B can be formed in processes at the same technology node or in processes at different technology nodes. For example, logic device 150A can be formed using a process node more advanced than that of memory device 150B.

[0047] Each logic device 150A can be a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, etc. Logic device 150A can be an integrated circuit die (similar to...) Figure 1 The described integrated circuit die 50) or it can be a die stack (similar to the one for...) Figure 2A The described die stack 60A). In some embodiments, the logic device 150A is an integrated circuit die, such as a system-on-a-chip (SoC) die. In some embodiments, the logic device 150A is a die stack, such as a system-on-a-chip (SoIC) device.

[0048] Each memory device 150B can be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high-bandwidth memory (HBM) module, etc. The memory device 150B can be an integrated circuit die (similar to...) Figure 1 The described integrated circuit die 50) or it can be a die stack (similar to the one for...) Figure 2B The described die stack 60B). In some embodiments, the memory device 150B is a die stack, such as a high-bandwidth memory (HBM) device.

[0049] In the illustrated embodiment, the integrated circuit device 150 is attached to the front redistribution structure 130 using solder bonding (such as with conductive connector 138). The conductive connector 138 may be formed of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connector 138 is formed by initially forming a solder layer using methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the conductive connector 138 into a desired bump shape. Attaching the integrated circuit device 150 to the front redistribution structure 130 may include placing the integrated circuit device 150 on the front redistribution structure 130 and reflowing the conductive connector 138. The integrated circuit device 150 may be placed on the front redistribution structure 130 using, for example, pick-and-place tools. The return conductive connector 138 attaches the die connector 140 at the front side of the integrated circuit device 150 to the UBM 136 of the front redistribution structure 130, thereby electrically connecting the front redistribution structure 130 to the integrated circuit device 150. In another embodiment, the integrated circuit device 150 is attached to the front redistribution structure 130 by direct bonding (using the die connector 140).

[0050] Further reference Figure 4 An underfill 146 is formed around the conductive connector 138 and between the front redistribution structure 130 and the integrated circuit device 150. The underfill 146 reduces stress and protects the joint from backflow caused by the conductive connector 138. The underfill 146 can be formed from an underfill material, such as molding compound, epoxy resin, etc. The underfill 146 can be formed by a capillary flow process after the integrated circuit device 150 is attached to the front redistribution structure 130, or it can be formed by a suitable deposition method before the integrated circuit device 150 is attached to the front redistribution structure 130. The underfill 146 can be applied in a liquid or semi-liquid form and then subsequently cured.

[0051] A sealant 148 is formed around each component. After the sealant 148 is formed, it laterally seals the underfill 146 (if present) and the integrated circuit device 150. The sealant 148 can be a molding compound, epoxy resin, etc. The sealant 148 can be applied by compression molding, transfer molding, etc., and the sealant 148 can be formed over the front redistribution structure 130 to bury or cover the integrated circuit device 150. The sealant 148 is also formed in the gap region between the underfill 146 (if present) and / or the integrated circuit device 150. The sealant 148 can be applied in liquid or semi-liquid form and then subsequently cured.

[0052] A removal process can optionally be performed on the sealant 148 to expose the integrated circuit device 150. The removal process may include, for example, planarization processes, such as chemical mechanical polishing (CMP), grinding processes, etc. After the planarization process, the top surfaces of the sealant 148 and the integrated circuit device 150 may be substantially coplanar (within the range of process variations). For example, if the integrated circuit device 150 has already been exposed, planarization may be omitted.

[0053] exist Figure 5 In this process, a carrier substrate stripping is performed to separate (or “peel off”) the carrier substrate 102 from the interposer wafer 100, forming a back-side redistribution structure 160. According to some embodiments, the stripping involves projecting light, such as laser or UV light, onto the release layer 104, causing the release layer 104 to decompose under the heat of the light, and allowing the carrier substrate 102 to be removed. The interposer wafer 100 is then flipped to prepare the back side of the interposer wafer 100 for processing. The interposer wafer 100 may be placed on tape, a carrier substrate, or another suitable support structure (not shown separately) for subsequent processing. It should be noted that the interposer wafer 100 may also be referred to as a reconstructed wafer.

[0054] Optionally, a removal process can be performed on substrate 112 and sealant 128 to expose via 106 and TSV 114. The removal process can remove material from sealant 128, interconnect die 110 (e.g., substrate 112 and TSV 114), and / or via 106 until TSV 114 and via 106 are exposed. The removal process can include, for example, planarization processes, such as chemical mechanical polishing (CMP), lamination processes, etc. After the planarization process, the back surfaces of sealant 128, interconnect die 110 (e.g., substrate 112 and TSV 114), and via 106 can be substantially coplanar (within the range of process variations).

[0055] As shown, a back-side redistribution structure 160 is formed on the back-side surfaces of the sealant 128, the interconnect die 110 (e.g., substrate 112 and TSV 114), and the via 106. The back-side redistribution structure 160 includes a dielectric layer 152 and a metallization layer 154 (sometimes referred to as a redistribution layer or redistribution line) located within the dielectric layer 152. Therefore, the back-side redistribution structure 160 includes metallization layers 154 spaced apart from each other by respective dielectric layers 152. The metallization layers 154 of the back-side redistribution structure 160 are connected to the via 106 and to the interconnect die 110 (e.g., TSV 114).

[0056] In some embodiments, dielectric layer 152 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB-based polymer, etc., and the polymer can be patterned using a photomask. In other embodiments, dielectric layer 152 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, etc. Dielectric layer 152 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. After forming dielectric layer 152, dielectric layer 152 can be patterned to expose underlying conductive components, such as via 106, TSV 114, and / or portions of metallization layer 154. Patterning can be performed by any acceptable process, such as exposing the dielectric layer to light when the dielectric layer is formed of a photosensitive material, or etching by, for example, anisotropic etching. If dielectric layer 152 is formed of a photosensitive material, dielectric layer 152 can be developed after exposure.

[0057] Each of the metallization layers 154 includes a conductive via and / or a wire. The conductive via extends through the corresponding dielectric layer 152, and the wire extends along the corresponding dielectric layer 152. As an example of forming the metallization layer 154, a seed layer (not shown separately) is formed over the corresponding underlying component. For example, the seed layer may be formed on the corresponding dielectric layer 152 and in any opening through the corresponding dielectric layer 152. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using a deposition process, such as PVD. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like, and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 154. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. Conductive materials can be formed by plating, such as electroless plating or electroplating from the seed layer. The conductive material can include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and the portion of the seed layer on which no conductive material is formed are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed by an acceptable etching process, such as wet etching or dry etching. The remaining portion of the conductive material and the seed layer forms the metallization layer 154 of the back-side redistribution structure 160.

[0058] The back-side redistribution structure 160 is shown as an example. By performing the previously described steps any desired number of times, more or fewer dielectric layers 152 and metallization layers 154 than shown can be formed.

[0059] Other variations of the back-side redistribution structure 160 are considered. For example, some dielectric layers in dielectric layer 152 can be formed by a sealant, such as molding compound, epoxy resin, etc. Metallization layer 154 can be formed by plating conductive vias from wires. Dielectric layer 152 can be formed by sealing such metallization layer 154. Any desired material stack can be used for dielectric layer 152.

[0060] A UBM 156 can be formed through the lower dielectric layer 152 of the back-side redistribution structure 160. The UBM 156 is physically and electrically coupled to the lower metallization layer 154 of the back-side redistribution structure 160. Each of the UBM 156 includes a conductive via and a conductive bump. The conductive via extends through the lower dielectric layer 152, and the conductive bump extends along the lower dielectric layer 152. The UBM 156 can be formed of the same material as the metallization layer 154. In some embodiments, the UBM 156 has different dimensions than the metallization layer 154.

[0061] In some embodiments, the interposer wafer 100 may undergo subsequent processing steps. For example, the package assembly 200 may be diced to form discrete package assemblies 200. The dicing process may include sawing, dicing, etc., through the interposer wafer 100 to separate the package regions 100P from each other. As discussed in more detail below, one or more package assemblies 200 will be attached to the reconstructed package substrate 300 to form an integrated circuit package 400.

[0062] Figures 6 to 13 This is a view of an intermediate stage in the fabrication of a reconstruction package substrate 300 according to some embodiments. For example, a substrate core 302 may be provided, and a substrate through-hole 306 (e.g., a glass through-hole 306) may be formed through the substrate core 302. Additionally, a redistribution structure may be formed on opposite sides of the substrate core 302 to form a component substrate 330. The component substrate 330 may then be diced into individual component substrates 330, and multiple diced component substrates 330 may be attached to a carrier to form the reconstruction package substrate 300.

[0063] exist Figure 6 In this embodiment, a substrate core 302 is provided in wafer form. The substrate core 302 may include a core material 303 and a thin film 304 along the surface of the core material 303. In some embodiments, the core material 303 may be formed of a semiconductor material, such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium indium phosphide, combinations thereof, etc., may also be used. Additionally, the substrate core 302 may be an SOI substrate. Typically, an SOI substrate comprises layers of semiconductor materials, such as layers of silicon, germanium, silicon germanium, or combinations thereof. In some embodiments, the core material 303 is an insulating material, such as a glass core (e.g., a glass fiber reinforced resin core). An exemplary core material 303 is a glass fiber resin, such as FR4. Alternative materials for the core material 303 include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. In addition, the film 304 may be a polymer film such as Ajinomoto polymer film (ABF) or other laminated materials (e.g., copper film), and the polymer film may be disposed on the opposite surface of the core material 303.

[0064] exist Figure 7In some embodiments, a substrate through-hole (TSV), such as a glass through-hole (TGV) 306 (e.g., for a glass substrate core 302), is formed to pass through the substrate core 302. For example, the substrate core 302 can be patterned to form a glass through-hole opening (e.g., through the thin film 304 and core material 303), and then the glass through-hole opening can be filled and patterned. Any suitable method can be used to form the glass through-hole opening, such as laser drilling. First, one or more pad layers (not shown separately) can be deposited over the surfaces of the substrate core 302 (including along the inner sidewall surfaces of the glass through-hole opening). Forming the pad layers may include re-laminating the same material as the thin film 304 (e.g., ABF or copper) over these exposed surfaces, and / or depositing a seed layer (e.g., an electroless copper seed layer) over the substrate core 302 and within the glass through-hole opening. A conductive material, such as copper, can then be deposited over the pad layers within the glass through-hole opening. Then, suitable methods (such as polishing processes) can be used to remove some of the excess conductive material and padding layer located outside the glass through-hole opening. The remaining portion along the main surface of the substrate core 302 can then be patterned, allowing the glass through-hole 306 to become different circuit elements.

[0065] exist Figure 8 In this embodiment, a front redistribution structure 307 and a back redistribution structure 308 are formed above opposite sides of a substrate core 302 to form a wafer-shaped component substrate 330. In some embodiments, a metal pad 310 may be formed above the back redistribution structure 308, and a passivation layer 312 may be formed above the metal pad 310. This structure may be referred to as a wafer-shaped component substrate 330. A glass through-hole 306 electrically couples the front redistribution structure 307 and the back redistribution structure 308. The front redistribution structure 307 and the back redistribution structure 308 may be formed in a similar manner to that described above with respect to the front redistribution structure 130 and / or the back redistribution structure 160 of the package assembly 200. In some embodiments, metal components (not separately labeled) may include a suitable conductive material (e.g., copper), and dielectric layers (not separately labeled) may include a suitable insulating material (e.g., ABF).

[0066] exist Figure 9 In some embodiments, the component substrate 330 is diced, and multiple diced component substrates 330 are attached to a carrier 320. For example, the carrier 320 may comprise a suitable material, such as a type of glass, or silicon dioxide (e.g., glass fiber and / or resin). Additionally, an adhesive layer 322 may be provided along the upper surface of the carrier 320. The component substrates 330 can be placed along the carrier 320 onto the adhesive layer 322 using, for example, a pick-and-place tool. As shown, gaps may laterally separate adjacent component substrates 330.

[0067] In some embodiments, acceptance testing processes (e.g., wafer acceptance testing) can be performed on the component substrate 330. It should be noted that testing can be performed before or after the component substrate 330 is cut into units. Testing identifies component substrates 330 that meet desired performance standards. These component substrates 330 that pass the test can be referred to as Known Good Substrates (KGS). KGS component substrates 330 are used to form the reconstructed package substrate 300, while others can be discarded or reused.

[0068] exist Figure 10 In the process, a gap filler material 332 is deposited above the carrier 320 and around and between the component substrate 330. As shown, the gap filler material 332 substantially fills the gaps between adjacent component substrates 330. The deposition of the gap filler material 332 incorporates the component substrate 330 into the reconstructed package wafer 340. The gap filler material 332 can be a suitable molding material, such as a polymer, resin, etc. After depositing the gap filler material 332, a planarization process can be performed so that the gap filler material 332 and the upper surface of the component substrate 330 are substantially flush.

[0069] exist Figure 11 In some embodiments, an interposer layer is formed over the component substrate 330 and the gap filler material 332. For example, metal pillars 334 may be formed over some or all of the component substrates 330, and the metal pillars 334 may be electrically connected to the component substrates 330. The metal pillars 334 may include a suitable conductive material, such as copper. Additionally, one or more interconnect dies 336 (e.g., bridging dies) may be attached over the component substrate 330 of the reconstructed package wafer 340. As shown, some interconnect dies 336 may be attached over and electrically connected to more than one component substrate 330. The interconnect dies 336 may include passive devices, such as surface mount devices (SMD), two-terminal integrated passive devices (IPD), multi-terminal IPDs, or integrated voltage regulators (IVR).

[0070] In some embodiments, interconnect dies 336 are bonded to component substrates 330 of the reconstructed package wafer 340 in a face-down configuration (e.g., active side down), and interconnect dies 336 may be electrically connected to one or more component substrates 330. As shown, some interconnect dies 336 may be connected to two diced component substrates 330. Additionally, some interconnect dies 336 may include substrate through-holes extending toward the back side of the interconnect die 336.

[0071] According to various embodiments, after the metal pillars 334 are formed and the interconnect dies 336 are attached, a molding compound 338 is formed above and around the metal pillars 334 and the interconnect dies 336. Additionally, the molding compound 338 can be planarized to expose the upper surfaces of the substrate vias of the metal pillars 334 and the interconnect dies 336. The metal pillars 334 extending through the molding compound 338 can also be referred to as intermediate layer vias (TIVs).

[0072] exist Figure 12 Interconnect structures, such as redistribution structures 350, can be formed over the metal pillars 334, interconnect dies 336, and molding compounds 338. For example, redistribution structure 350 may include a metallization layer 354 (e.g., including metal traces and metal vias) embedded in one or more dielectric layers 352. As shown, the uppermost layer of redistribution structure 350 may include a bonding layer. The bonding layer may include metal pads or bonding pads 358 embedded in the bonding layer. Bonding pads 358 will facilitate subsequent attachment of other package components.

[0073] exist Figure 13 In some embodiments, one or more packaging components 200 are attached to a rebuilt packaging wafer 300 to form an integrated circuit package 400. It should be noted that, unless otherwise described or illustrated, the packaging component 200 and the rebuilt packaging wafer 300 can be formed in a similar manner to those described above with respect to the packaging component 200 and the rebuilt packaging wafer 300. It should be noted that the packaging component 200 may include embodiments of the packaging component 200 described above, as well as HBMs, SoICs, IPDs, photonic dies, or power modules.

[0074] The back-side redistribution structure 160 of the package assembly 200 can be attached to the bonding pads 358 of the reconstructed package wafer 300 using solder bonding (such as using conductive connectors 158 disposed on the UBM of the package assembly 200). The conductive connectors 158 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium-ion immersion gold (ENEPIG) technology, etc. The conductive connectors 158 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connectors 158 are initially formed by forming a solder layer through methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been structurally formed, reflow can be performed to shape the solder into the desired bump shape of the conductive connectors 158.

[0075] Attaching the rebuilt package wafer 300 to the back-side redistribution structure 160 may include placing the rebuilt package wafer 300 onto the back-side redistribution structure 160 and reflowing the conductive connector 158. The rebuilt package wafer 300 may be placed onto the back-side redistribution structure 160 using, for example, pick-and-place tools. In some embodiments, a thermoforming bonding process may be used. For example, the conductive connector 158 is reflowed to attach bonding pads 358 to the UBM 156 of the back-side redistribution structure 160, and heat may be applied to the bonding heads (not specifically shown) when the package assembly 200 is pressed against the rebuilt package wafer 300. The conductive connector 158 connects an interposer 240 (including a metallization layer of the back-side redistribution structure 160) to the rebuilt package wafer 300 (including a metallization layer of the substrate die 302). Therefore, the rebuilt package wafer 300 is electrically connected to the integrated circuit device 150 in the package assembly 200.

[0076] Additionally, passive devices (not shown separately) can be attached to the rebuilt package wafer 300 at any suitable time, whether before or after the corresponding dicing process, or after the rebuilt package wafer 300 and package assembly 200 are attached. For example, passive devices can be attached to the rebuilt package wafer 300, such as to the same surface of the back-side redistribution structure 160 as the metal pads 156 and conductive connectors 158. Alternatively or additionally, passive devices can be attached to the rebuilt package wafer 300, such as to the same surface of the rebuilt package wafer 300 as the bonding pads 358. Passive devices can include capacitors, resistors, inductors, etc., or combinations thereof. Passive devices can be surface mount devices (SMD), 2-terminal integrated passive devices (IPD), multi-terminal IPDs, etc.

[0077] In some embodiments, a sealant 408 is formed around the various components. After the sealant 408 is formed, it laterally seals the passive device (if present), the conductive connector 158, and the redistribution structure 350. The sealant 408 may be formed between the reconstructed package wafer 300 and the back-side redistribution structure 160 of the package assembly 200. The sealant 408 may be a molding compound, epoxy resin, etc. The sealant 408 may be applied by compression molding, transfer molding, etc. The sealant 408 may be applied in liquid or semi-liquid form and then subsequently cured.

[0078] exist Figure 14In some embodiments, the carrier 320 is removed from the reconstructed package wafer 300, the adhesive layer 322 is removed, and the reconstructed package wafer 300 is sawn to diced the integrated circuit package 400. For example, the carrier 320 can be peeled off from the reconstructed package wafer by projecting light, such as laser or UV light, onto the adhesive layer 322, causing the adhesive layer 322 to decompose under the heat of the light, and the carrier 320 can be removed. Alternatively, the dicing process is performed by dividing along a scribe line area between the package region 100P and adjacent package regions (not shown separately). The dicing process can include sawing, cutting, etc. The dicing process separates the package regions from each other, wherein each package region can include multiple package components 200. Due to the dicing process, the outer walls of the redistribution structure 350 (e.g., dielectric layer 352) share a common end face laterally with the outer walls of the gap filler material 332 and the molding compound 338 (within the range of process variations).

[0079] exist Figure 15 In this configuration, an external connector 360 can be formed on the metal pad 310, similar to that described above with respect to conductive connectors 138 and 158. For example, an opening can be formed through the passivation layer 312 to expose the metal pad 310. The opening can be formed by suitable processes, such as drilling with a solder mask and / or laser drilling. In some embodiments, the conductive connector 360 is formed by initially forming a solder layer by methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on this structure, reflow can be performed to shape the conductive connector 360 into the desired bump shape. Although not specifically shown, the external connector 360 facilitates the subsequent attachment of the integrated circuit package 400 to an electronic device, and the transmission of power and / or data between the integrated circuit package 400 and the electronic device.

[0080] exist Figure 16 In this process, a metal layer 450 can be formed on the top surface of the package assembly 200 and the sealant 408. The metal layer 450 can be formed by a deposition process, such as physical vapor deposition (PVD). The metal layer 450 can be a single layer or a composite layer comprising multiple sublayers formed of different materials. Each of the single layer or multiple sublayers of the metal layer 450 can be formed of a homogeneous metal material, a metal alloy, etc. In some embodiments, the metal layer 450 is a single layer and includes copper. In some embodiments, the metal layer 450 is a composite layer comprising multiple sublayers. For example, the metal layer 450 may include an aluminum layer as a bottom sublayer, a titanium layer as a middle sublayer, and a copper layer as a top sublayer. The metal layer 450 can contact the silicon substrate in the package assembly 200 and can dissipate heat generated by the package assembly 200 during operation of the integrated circuit package 400.

[0081] Additionally, a thermal interface material (TIM) layer 460 is formed on the metal layer 450. The TIM layer 460 may include a material with high thermal conductivity, such as a metal or metal alloy. In some embodiments, the TIM layer 460 includes indium (In), tin (Sn), indium-silver (In-Ag) alloy, tin-bismuth (Sn-Bi) alloy, gallium (Ga), etc. The TIM layer 460 can be formed by plating, such as electroplating or electroless plating. The metal layer 450 can be used as a seed layer during the plating process.

[0082] Still referencing Figure 16 A cover 470 can be placed above the structure to serve as, for example, a heat sink. In some embodiments, the cover 470 may have a top portion and optionally a sidewall portion (e.g., an annular portion). In a top view, the sidewall portions of the cover 470 may (e.g., continuously or discontinuously) surround the package assembly 200. In some embodiments, the cover 470 (e.g., the top portion) may include copper, indium, or alloys thereof. An adhesive 472 (such as epoxy resin) may be applied to the bottom surface of the sidewall portions of the cover 470. The cover 470 can be attached to the reconstructed package substrate 300 via the adhesive 472. The cover 470 may be formed of a material with high thermal conductivity, such as copper, stainless steel, etc.

[0083] It should also be understood that each of the sealant 408, metal layer 450, TIM layer 460, and cap 470 is optional. For example, in some embodiments, the sealant 408 may be omitted from the integrated circuit package 400. Additionally, the metal layer 450, TIM layer 460, and / or cap 470 may be omitted from the integrated circuit package.

[0084] According to various embodiments, the integrated circuit package 400 includes one or more package components 200 attached to the reconstructed package substrate 300 as described above. Specifically, the formation of the reconstructed package substrate 300 includes forming an interposer layer (e.g., metal pillars 334 and interconnect dies 336) over a plurality of component substrates 330 reconstructed into wafer form. Additionally, redistribution structures (e.g., interconnect structures) may be formed to provide electrical wiring and connections to subsequently attached package components 200A.

[0085] It should be noted that, as described above, the integrated circuit package 400 as a device and the process steps for forming the device can represent various additional embodiments disclosed below. Furthermore, it should be understood that, according to some embodiments, the device and process steps described above can represent the integrated circuit package 400A. In this way, the integrated circuit package 400A includes one or more package components 200A attached to the reconstructed package substrate 300A as described above.

[0086] Figures 17 to 21An integrated circuit package 400B having one or more package components 200B attached to a reconstructed package substrate 300B is illustrated according to some embodiments. It should be noted that, unless otherwise stated herein, components and processes can be formed and performed in a manner similar to those described above with respect to package components 200B, reconstructed package substrate 300B, and integrated circuit package 400B. Specifically, according to some embodiments, the reconstructed package substrate 300B may have a redistribution structure 350 formed over a diced component substrate 330, with the formation of metal pillars 334 and interconnect dies 336 therebetween omitted.

[0087] exist Figure 17 In this process, the packaging substrate 330 is formed at the wafer level, diced, and attached to the carrier 320, similar to the process described above. Figures 6 to 9 As described above. Additionally, a gap filler material 332 is deposited around and between the diced packaging substrate 330, similar to the above description. Figure 10 As described.

[0088] exist Figure 18 In this process, a redistribution structure 350 can be formed over the packaging substrate 330 and the gap filler material 332 to form a reconstructed packaging wafer 300B, similar to the above. Figure 12 As described. For example, the redistribution structure 350 may include a metallization layer 354 (e.g., metal traces and metal vias) embedded in one or more dielectric layers 352. As shown, the topmost level of the redistribution structure 350 may include metal pads or bonding pads 358.

[0089] As shown and described, the reconstructed package substrate 300B is similar to the reconstructed package substrate 300A, but with some differences. For example, the reconstructed package substrate 300B omits the interposers (e.g., metal pillars 334 and interconnect dies 336 embedded in the molding compound 338) provided in the reconstructed package substrate 300A. As a result, the redistribution structure 350 of the reconstructed package substrate 300B can include a higher degree of electrical wiring from the component substrate 330 to the overlying package component 200. Furthermore, as shown, some traces of the metallization layer 354 can extend above the lateral distance between adjacent package components 330 to electrically couple them to each other, in addition to the overlying package component 200.

[0090] exist Figure 19 In this process, one or more package components 200B are attached to the reconstructed package wafer 300B, similar to the above description. Figure 13 As described above. It should be noted that, unless otherwise stated or described, package component 200B may be formed in a similar manner to that described above with respect to package component 200 (e.g., package component 200A).

[0091] exist Figure 20 In the process of removing the carrier 320 and the adhesive layer 322 from the reconstructed package wafer 300B, and sawing the reconstructed package wafer 300B to cut the integrated circuit package 200B into individual units, similar to the above process... Figure 14 As described. For example, the carrier 320 can be peeled off from the reconstructed package wafer by projecting light, such as laser or UV light, onto the adhesive layer 322, causing the adhesive layer 322 to decompose under the heat of the light, and the carrier 320 can be removed. Additionally, a dicing process is performed by dividing along a scribe line region between the package region 100P and adjacent package regions (not shown separately). The dicing process can include sawing, cutting, etc. The dicing process dices the package regions apart from each other, where each package region can include multiple package components 200B. Due to the dicing process, the outer wall of the redistribution structure 350 (e.g., dielectric layer 352) and the outer wall of the gap filler material 332 share a common end face laterally (within the range of process variations).

[0092] exist Figure 21 In this process, an external connector 360 can be formed on the metal pad 310, similar to the above-mentioned... Figure 15 As described. For example, openings can be formed through the passivation layer 312 to expose the metal pads 310. In some embodiments, the conductive connector 360 is formed by initially forming a solder layer using methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on this structure, reflow can be performed to shape the conductive connector 360 into the desired bump shape. Although not specifically shown, the external connector 360 facilitates the subsequent attachment of the integrated circuit package 400B to an electronic device, as well as the transmission of power and / or data between the integrated circuit package 400B and the electronic device.

[0093] exist Figure 22 In this process, a metal layer 450, a TIM layer 460, and a cap 470 may be attached and / or formed over the package assembly 200B and the reconstructed package substrate 300B of the integrated circuit package 400B, similar to the provisions regarding Figure 16 As described.

[0094] Figure 23 and Figure 24Exemplary embodiments of an integrated circuit package 400C, similar to the integrated circuit packages 400A and 400B described above, are shown respectively. For example, the integrated circuit package 400C is formed with a coreless reconstruction package substrate 300C. Specifically, a package assembly 330 is formed without a substrate core 302. In this way, the assembly substrate 330 includes only the redistribution structure 307. In some embodiments, layers of the redistribution structure 307 are formed in both the front and back directions. Similarly, the redistribution structure 307 can be formed by directly bonding two redistribution structures to each other. In other embodiments, the entire redistribution structure 307 is formed in one direction (e.g., the front direction).

[0095] also, Figure 23 An integrated circuit package 400C is shown, wherein the reconstructed package substrate 300C includes an interposer layer similar to the interposer layer provided in the integrated circuit package 400A. Furthermore, Figure 24 An integrated circuit package 400C is shown, wherein the reconstructed package substrate 300C lacks an interposer layer, similar to the interposer layer provided in integrated circuit package 400B.

[0096] Figures 25 to 33 An integrated circuit package 400D is illustrated according to some embodiments, the integrated circuit package 400D having one or more package components 200D attached to a reconstructed package substrate 300D. It should be noted that, unless otherwise stated herein, components and processes can be formed and performed similarly to those described above with respect to package components 200 (e.g., package components 200A, 200B, and / or 200C), reconstructed package substrates 300 (e.g., reconstructed package substrates 300A, 300B, and / or 300C), and integrated circuit packages 400 (e.g., integrated circuit packages 400A, 400B, and / or 400C). Specifically, according to some embodiments, the integrated circuit package 400D may include a reconstructed package substrate 300D having passive devices embedded in a substrate core 302.

[0097] exist Figure 25 The document provides a substrate core 302, which can be an insulating core, such as a glass core (e.g., a glass fiber reinforced resin core), similar to the above description. Figure 6 As described above. Additionally, through-substrate vias, such as glass vias 306, are formed and patterned through the substrate core 302, similar to those described above. Figure 7 As described.

[0098] exist Figure 26In the process, after forming and patterning the glass through-hole 306, a substrate core 302 is applied to the tape 370, and one or more cavities 372 are etched through the substrate core 302 (and optionally through the tape 370), whereby passive devices are accommodated.

[0099] exist Figure 27 In some embodiments, a glass carrier 374 is provided, and a main layer 308A of redistribution structures 307, 308 is formed over the glass carrier 374. Although the main layer 308A is shown as part of the back-side redistribution structure 308, similar to the above description... Figure 8 As described, however, the main layer 308A can also be part of the front redistribution structure 307. In some embodiments, an adhesive layer 375 may first be formed along the surface of the glass carrier 374. The main layer 308A of the back redistribution structure 308 is then formed over the adhesive layer 375. The main layer 308A includes a plurality of metal pads 376 (e.g., under-bump metallization (UBM)) located at corresponding locations of subsequently added passive devices.

[0100] For example, adhesive layer 375 may be a heat-release material based on epoxy resin that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, release layer 104 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. Additionally, the main layer 308A may be formed in a manner similar to that described above with respect to the front redistribution structure 130 and / or the back redistribution structure 160 of the encapsulation assembly 200. In some embodiments, metal components (not separately labeled) may include a suitable conductive material (e.g., copper), and dielectric layers (not separately labeled) may include a suitable insulating material (e.g., ABF).

[0101] exist Figure 28 In this process, the substrate core 302 is attached to the main layer 308A of the back-side redistribution structure 308. Specifically, the structures are bonded to each other along the adhesive layer 370 of the substrate core 302. The attachment process can be performed using, for example, a suitable wafer-to-wafer bonding process. As shown, some components of the main layer 308A can be kept exposed through cavities 372 in the substrate core 302.

[0102] exist Figure 29In this process, one or more passive devices 380 are attached to metal pads 376 of a main layer 308A within one or more cavities 372 in a substrate core 302. For example, solder bumps disposed on an external connector along a first side of the passive device 380 can be used to bond the passive device 380. Additionally, an underfill material can be distributed around the solder bumps between the passive device 380 and the main layer 308A. Furthermore, a removal process can be performed to remove a back-side portion of the substrate of the passive device 380. For example, the removal process may include a polishing process to remove some or all of the silicon portion of the substrate. In some embodiments, the passive device 380 may include an integrated passive device (IPD), an integrated voltage regulator (IVR), etc.

[0103] As shown in the figure, some passive devices 380 may include substrate through-holes to enable electrical connections on the front and back sides. Additionally, some passive devices 380 may have electrical connections only along their active side (e.g., the front side). In this way, some of these passive devices 380 can be placed with their active side facing down (e.g., face down) and coupled to the main layer 308A of the back-side redistribution structure. Furthermore, other passive devices 380 can be placed with their active side facing up (e.g., face up) such that the non-active side (e.g., the back side) of such passive devices 380 is adjacent to the main layer 308A. In practice, these locations on the main layer 308A may not have conductive components for electrical connections to such passive devices 380.

[0104] exist Figure 30 In the process, an ABF layer 378 is deposited to fill the remaining portion of the cavity 372. A removal process can be performed to remove excess material from the ABF layer 378 and additional portions of the substrate of the passive device. For example, the removal process may include one or more polishing processes to remove some or all of the additional silicon portions of the substrate (if present) and any other layers (e.g., oxide layers on an SOI substrate) to expose conductive components of the passive device 380 (e.g., substrate vias and / or bonding pads). After the removal process, the ABF layer 378 may be substantially flush with these conductive components and any remaining portion of the substrate of the passive device 380.

[0105] exist Figure 31 In this process, a glass carrier 374 is peeled off from a substrate core 302, and via openings 382 and 383 are formed on each side of the substrate core 302. For example, via opening 382 may include drilling through the ABF layer 378 to expose a substrate through-hole 306 above the front side of the substrate core 302. The glass carrier 374 may then be peeled off from the substrate core 302 before via opening 383 is formed above the back side of the substrate core 302. In some embodiments (not specifically shown), the substrate core 302 (e.g., via opening 382) may be cleaned, and a front redistribution structure 307 may be formed above the front side of the substrate core 302.

[0106] According to some embodiments, peeling may include projecting light, such as laser or UV light, onto the adhesive layer 375, causing the adhesive layer 375 to decompose under the heat of the light, and removing the glass carrier 374. The substrate core 302 is then flipped over to prepare the back side of the substrate core 302 for processing. The substrate core 302 may be placed on tape, a carrier substrate, or another suitable support structure (not shown separately) for subsequent processing.

[0107] The via opening 383 may include dielectric material drilled through the main layer 308A and adhesive tape 370 to expose a substrate through-hole 306 above the back side of the substrate core 302. In some embodiments (not specifically shown), the substrate core 302 (e.g., via opening 383) may be cleaned, and a back-side redistribution structure 308 may be completed above the back side of the main layer 308A and the back side of the substrate core 302.

[0108] exist Figure 32 In the above-front side of the substrate core 302, a front redistribution structure 307 is formed through the via opening 382. Furthermore, a back redistribution structure 308 is formed above the main layer 308A, above the back side of the substrate core, and through the via opening 383, similar to the above-mentioned... Figure 8 As described above, the metal components (not separately labeled) may include a suitable conductive material (e.g., copper), and the dielectric layer (not separately labeled) may include a suitable insulating material (e.g., ABF). It should be noted that the front redistribution structure 307 and the back redistribution structure 308 (and their component parts) may be formed in any suitable order. Additionally, the front redistribution structure 307 may be formed after the via opening 382 is formed above the front side of the substrate core 302 and before the glass carrier 374 is removed. Furthermore, the back redistribution structure 308 may be formed after the via opening 383 is formed above the back side of the substrate core 302 and before the front redistribution structure 307 is formed, or before the via opening 382 is formed above the front side of the substrate core 302.

[0109] exist Figure 33 In this process, the component substrate 330 is transformed into a reconstructed packaging substrate 300D, and the reconstructed packaging substrate 300D is incorporated into the integrated circuit package 400D. For example, the wafer-form component substrate 330 is sliced ​​and transformed into a reconstructed packaging substrate 300C, similar to the above process. Figures 9 to 12 As described above. It should be noted that the reconstructed package substrate 300D may include or omit an interposer layer. The package assembly 200D (similar to the package assembly 200 described above) is then attached to the reconstructed package substrate 300D, similar to what has been described above. In some embodiments, the sealant 408 around the package assembly 200D may be omitted, and the integrated circuit package 400D may then undergo subsequent processing similar to that described above.

[0110] Figure 34 A plan view (e.g., top view) of an integrated circuit package 400 according to any embodiment described above or below is shown. For example, the integrated circuit package 400 may include a reconstructed package substrate 300 comprising two or more component substrates 330 (e.g., four, six, nine component substrates 330, or any suitable number). As shown, interconnect dies at each level of the integrated circuit package 400 may facilitate interconnections between package components 200 and between the package components 200 and the component substrates 330. For example, an interconnect die disposed above the lateral distance between adjacent component substrates 330 may be an interconnect die 336 attached within an interposer. Alternatively, an interconnect die disposed within the footprint of a component substrate 330 may be an interconnect die 336 in the interposer or an interconnect die 380 attached within a substrate die 302. However, any suitable combination of the interconnect dies described above may be used.

[0111] The plan view illustrates the advantages of forming the reconstructed package substrate 300 discussed herein. For example, the reconstructed package substrate 300 can be formed to be significantly larger (e.g., several times larger) than a package substrate formed from a single continuous component substrate. The reconstructed package substrate 300 is less prone to warping during various processing steps (such as attaching package components 200). In fact, the reconstructed package substrate 300 is able to support a greater number of package components 200 (as well as other devices, such as HBM dies) and larger package components 200 in terms of size (e.g., footprint area). As shown, package components 200 can be in various sizes, such as 3.5 times and 5 times the mask size. In this way, the integrated circuit package 400 can support a total of more than 30 package components 200 of mask size. For example, in the illustrated embodiment, the integrated circuit package 400 can be formed to have a side length of about 200 mm or greater, and each component substrate 330 can have a side length of about 120 mm or greater. Furthermore, one or more integrated circuit packages 400 can be formed in a single layer such that the integrated circuit package 400 has a total side length of about 400 mm or greater, and the integrated circuit package 400 can be supported by a carrier 320 with a side length of about 500 mm or greater.

[0112] Figures 35 to 37 Various cross-sections of an additional exemplary embodiment of the integrated circuit package 400E are shown. Figure 38 A plan view (e.g., top view) of a hypothetical integrated circuit package 400E is shown, which includes... Figures 35 to 37 The combination of the embodiments shown. It should be noted that each integrated circuit package 400E is shown having a similar shape to... Figure 22The reconstructed package substrate 300A and the reconstructed package substrate 300E are examples of the reconstructed package substrate 300. However, any other embodiment of the reconstructed package substrate 300 (e.g., reconstructed package substrates 300B and 300C) may also be used. Additionally, other integrated circuit packages 400 may also include... Figure 38 The packaging assembly 200 shown includes an integrated circuit package 400E comprising an embodiment consistent with the reconstructed packaging substrate 300. Although the metal layer 450, TIM layer 460, and cap 470 are omitted from the figure for simplicity, each of these components can be included in the integrated circuit package 400E, similar to the above description. Figure 16 As described.

[0113] exist Figure 35 The cross-sectional view of an exemplary embodiment of the integrated circuit package 400E shows a plurality of package components 200E, which have a greater than one-to-one correspondence with each of the component substrates 330 shown in the reconstruction package substrate 300E. As shown, the sealant 408 is continuous between adjacent package components 200 disposed directly above the same component substrate 330. Alternatively, the sealant 408 may be continuous (as shown) or discontinuous (not specifically shown) between adjacent package components 200 disposed directly above different component substrates 330.

[0114] exist Figure 36 In the cross-sectional view of an exemplary embodiment of the integrated circuit package 400E, there are a number of package components 200E shown, which correspond one-to-one with the corresponding component substrates 330 of the reconstructed package substrate 300E. Therefore, such package components 200E can be larger in size and occupy a larger proportion of the footprint of the corresponding component substrates 330.

[0115] exist Figure 37 A cross-sectional view of an exemplary embodiment of the integrated circuit package 400E includes a number of integrated circuit devices 150 directly attached to the reconstructed package substrate 300E without an interposer 100 between them. For example, these integrated circuit devices 150 may include memory devices (e.g., HBM dies) or logic devices. This allows the integrated circuit devices 150 to be attached without being incorporated into the package assembly 200, and these integrated circuit devices 150 can rely on interconnects within the reconstructed package substrate 300.

[0116] exist Figure 38 The diagram shows a plan view (e.g., a top view) of a hypothetical integrated circuit package 400E, illustrating the layout of various embodiments of the package assembly 200E attached to the reconstructed package substrate 300E. Specifically, it shows... Figures 34 to 37The illustrated embodiments are hypothetical combinations. For example, section AA can represent any one of integrated circuit packages 400A, 400B, 400C, and 400D. Section BB can represent... Figure 35 The integrated circuit package shown is 400E. A cross-section of the CC section can be represented... Figure 36 The integrated circuit package shown is 400E. The DD cross-section can be represented as... Figure 37 The integrated circuit package shown is 400E.

[0117] Advantages achievable with this embodiment: The integrated circuit package 400 can be formed with a larger package substrate that experiences less warpage. For example, the package substrate can be a reconstructed package substrate comprising multiple component substrates embedded in a gap-filling polymer. This allows a greater number of passive devices to be incorporated into the reconstructed package substrate, and a larger number of package components to be attached to it. Reduced warpage enables the integrated circuit package to be manufactured with higher yields and to operate with improved performance, higher reliability, and increased lifespan.

[0118] In one embodiment, a method includes forming a package assembly comprising: an interposer including a first redistribution structure; a plurality of integrated circuit dies attached to a first side of the first redistribution structure; forming a package substrate, the forming of the package substrate including: forming a second redistribution structure and a third redistribution structure over opposite sides of substrate dies; dicing the substrate dies to form a plurality of component substrates; attaching the first component substrate and the second component substrate to a carrier, the first component substrate and the second component substrate being laterally offset from each other by a gap; and forming a bonding layer over the first component substrate and the second component substrate; attaching the package assembly to the package substrate; and forming an external connector over the package substrate, the external connector being configured to electrically couple signal wiring, power wiring, or ground wiring of the plurality of integrated circuit dies to an additional package assembly. In another embodiment, forming the bonding layer includes forming a fourth redistribution structure over the first component substrate and the second component substrate, wherein the fourth redistribution structure includes the bonding layer. In another embodiment, the method further includes: forming an interconnect layer over the first component substrate and the second component substrate prior to forming the fourth redistribution structure, wherein the interconnect layer includes interconnect dies embedded in a molding compound and interposer through-holes. In another embodiment, an interconnect die electrically couples a first component substrate to a second component substrate. In another embodiment, a package component is electrically connected to both the first and second component substrates. In another embodiment, the method further includes forming a substrate core, wherein forming the substrate core includes: forming a glass through-hole through a glass core; forming an opening through the glass core; and placing a passive device within the opening of the glass core. In another embodiment, a passive device electrically couples a second redistribution structure to a third redistribution structure, and wherein the glass through-hole electrically couples the second redistribution structure to the third redistribution structure.

[0119] In an embodiment, a method includes: forming a first set of substrate through-holes (TSVs) and a second set of TSVs through a substrate core; forming a first redistribution structure over the first set of TSVs; forming a second redistribution structure over the second set of TSVs, the second redistribution structure being electrically isolated from the first redistribution structure and the first set of TSVs; performing a dicing process to form a first component substrate and a second component substrate, wherein the first component substrate includes a first portion of the substrate core, the first set of TSVs, and the first redistribution structure, and wherein the second component substrate includes a second portion of the substrate core, the second set of TSVs, and the second redistribution structure; attaching the first component substrate and the second component substrate to a carrier, the first component substrate and the second component substrate being laterally offset by a gap; filling the gap with a molding material; forming a third redistribution structure over the first component substrate and the second component substrate, wherein after forming the third redistribution structure, the first component substrate and the second component substrate are electrically connected; and attaching a package assembly to the third redistribution structure, wherein each of the package assemblies includes a plurality of integrated circuit dies disposed over an interposer. In another embodiment, the method further includes: before forming the third redistribution structure: directly forming metal pillars above the first and second redistribution structures; directly attaching the first interconnect die to the molding material, the first redistribution structure, and the second redistribution structure; and forming molding compound around the metal pillars and the first interconnect die. In another embodiment, the first interconnect die is electrically coupled to the first, second, and third redistribution structures. In another embodiment, the method further includes: before forming the first and second redistribution structures: forming a first cavity and a second cavity through a substrate die; attaching the substrate die to the redistribution layer; attaching a first passive device to the redistribution layer within the first cavity; and attaching a second passive device to the redistribution layer within the second cavity. In another embodiment, attaching the first passive device includes electrically coupling the first passive device to the redistribution layer, and wherein attaching the second passive device includes bonding the non-active side of the second passive device to the redistribution layer. In another embodiment, the method further includes forming a sealant around and between the package assembly, wherein the sealant is continuous.

[0120] In one embodiment, the semiconductor device includes a packaging substrate comprising: a first component substrate including a first redistribution structure; a second component substrate including a second redistribution structure, the second component substrate being laterally offset from the first component substrate; a molding material disposed between the first and second component substrates; and a third redistribution structure disposed above the first and second component substrates, the third redistribution structure being electrically connected to both the first and second component substrates; and a first packaging assembly attached to the third redistribution structure, the first packaging assembly including a first integrated circuit die disposed above a first interposer. In another embodiment, the first packaging assembly is electrically connected to both the first and second component substrates. In another embodiment, the semiconductor device further includes a second packaging assembly attached to the third redistribution structure, wherein the second packaging assembly includes a second integrated circuit die disposed above a second interposer. In another embodiment, a third interposer is disposed between the molding material and the third redistribution structure, wherein the third interposer includes a third interconnect die, and wherein the third interconnect die is electrically coupled to the first, second, and third redistribution structures. In another embodiment, the first component substrate includes a first glass core, and wherein a first passive device is included within the first glass core. In another embodiment, the second component substrate includes a second glass core, and the second passive device is contained within the second glass core. In another embodiment, the first passive device includes two electrically active sides, and the second passive device includes a first side and a second side opposite to each other, wherein the first side is electrically active and the second side is electrically inactive.

[0121] In some embodiments of this application, a method of forming a semiconductor device is provided, the method comprising: forming a package assembly including: an interposer including a first redistribution structure; a plurality of integrated circuit dies attached to a first side of the first redistribution structure; forming a package substrate, the forming of the package substrate comprising: forming a second redistribution structure and a third redistribution structure over opposite sides of substrate dies; dicing the substrate dies to form a plurality of component substrates; attaching the first component substrate and the second component substrate to a carrier, the first component substrate and the second component substrate being laterally offset from each other by a gap; forming a bonding layer over the first component substrate and the second component substrate; attaching the package assembly to the package substrate; and forming an external interconnect over the package substrate, the external interconnect being configured to electrically couple signal wiring, power wiring, or ground wiring of the plurality of integrated circuit dies to an additional package assembly. In some embodiments, forming the bonding layer includes forming a fourth redistribution structure over the first component substrate and the second component substrate, wherein the fourth redistribution structure includes the bonding layer. In some embodiments, the method of forming a semiconductor device further includes forming an interconnect layer over the first component substrate and the second component substrate prior to forming the fourth redistribution structure, wherein the interconnect layer includes interconnect dies embedded in a molding compound and interposer through-holes. In some embodiments, an interconnect die electrically couples a first component substrate to a second component substrate. In some embodiments, a package component is electrically connected to the first component substrate and the second component substrate. In some embodiments, a method of forming a semiconductor device further includes forming a substrate core, wherein forming the substrate core includes: forming a glass through-hole through a glass core; forming an opening through the glass core; and placing a passive device within the opening of the glass core. In some embodiments, a passive device electrically couples a second redistribution structure to a third redistribution structure, and wherein the glass through-hole electrically couples the second redistribution structure to the third redistribution structure.

[0122] In other embodiments of this application, a method for forming a semiconductor device is provided, the method comprising: forming a first set of substrate through-holes (TSVs) and a second set of TSVs through a substrate core; forming a first redistribution structure over the first set of TSVs; forming a second redistribution structure over the second set of TSVs, the second redistribution structure being electrically isolated from the first redistribution structure and the first set of TSVs; performing a dicing process to form a first component substrate and a second component substrate, wherein the first component substrate includes a first portion of the substrate core, the first set of TSVs and the first redistribution structure, and wherein the second component substrate includes a second portion of the substrate core, the second set of TSVs and the second redistribution structure; attaching the first component substrate and the second component substrate to a carrier, the first component substrate and the second component substrate being laterally offset by a gap; filling the gap with a molding material; forming a third redistribution structure over the first component substrate and the second component substrate, wherein after forming the third redistribution structure, the first component substrate and the second component substrate are electrically connected; and attaching a package assembly to the third redistribution structure, wherein each of the package assembly includes a plurality of integrated circuit dies disposed over an interposer. In some embodiments, forming the semiconductor device further includes, prior to forming the third redistribution structure: directly forming metal pillars over the first and second redistribution structures; directly attaching the first interconnect die to the molding material, the first redistribution structure, and the second redistribution structure; and forming a molding compound around the metal pillars and the first interconnect die. In some embodiments, the first interconnect die is electrically coupled to the first, second, and third redistribution structures. In some embodiments, forming the semiconductor device further includes, prior to forming the first and second redistribution structures: forming a first cavity and a second cavity through a substrate die; attaching the substrate die to the redistribution layer; attaching a first passive device to the redistribution layer within the first cavity; and attaching a second passive device to the redistribution layer within the second cavity. In some embodiments, attaching the first passive device includes electrically coupling the first passive device to the redistribution layer, and attaching the second passive device includes bonding the non-active side of the second passive device to the redistribution layer. In some embodiments, forming the semiconductor device further includes forming a sealant around and between the package components, wherein the sealant is continuous.

[0123] In some embodiments of this application, a semiconductor device is provided, comprising: a packaging substrate including: a first component substrate including a first redistribution structure; a second component substrate including a second redistribution structure, the second component substrate being laterally offset from the first component substrate; a molding material disposed between the first component substrate and the second component substrate; and a third redistribution structure disposed above the first component substrate and the second component substrate, the third redistribution structure being electrically connected to both the first component substrate and the second component substrate; and a first packaging assembly attached to the third redistribution structure, the first packaging assembly including a first integrated circuit die disposed above a first interposer. In some embodiments, the first packaging assembly is electrically connected to both the first component substrate and the second component substrate. In some embodiments, the semiconductor device further includes a second packaging assembly attached to the third redistribution structure, wherein the second packaging assembly includes a second integrated circuit die disposed above a second interposer. In some embodiments, the third interposer is disposed between the molding material and the third redistribution structure, wherein the third interposer includes a third interconnect die, and wherein the third interconnect die is electrically coupled to the first redistribution structure, the second redistribution structure, and the third redistribution structure. In some embodiments, the first component substrate includes a first glass core, and wherein a first passive device is included within the first glass core. In some embodiments, the second component substrate includes a second glass core, and the second passive device is contained within the second glass core. In some embodiments, the first passive device includes two electrically active sides, and the second passive device includes a first side and a second side opposite to each other, wherein the first side is electrically active, and wherein the second side is electrically inactive.

[0124] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other operations and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Forming an encapsulation component, the encapsulation component comprising: The intermediary layer includes the first redistribution structure; Multiple integrated circuit dies are attached to the first side of the first redistribution structure; Forming a packaging substrate, wherein forming the packaging substrate includes: A second redistribution structure and a third redistribution structure are formed above the opposite sides of the substrate core; The substrate core is diced to form multiple component substrates; A first component substrate and a second component substrate are attached to a carrier, the first component substrate and the second component substrate being laterally offset from each other by a gap; and A bonding layer is formed over the first component substrate and the second component substrate; Attaching the packaging assembly to the packaging substrate; and An external connector is formed above the packaging substrate, the external connector being configured to electrically couple the signal wiring, power wiring, or ground wiring of the plurality of integrated circuit dies to an additional packaging assembly.

2. The method according to claim 1, wherein, Forming the bonding layer includes forming a fourth redistribution structure over the first component substrate and the second component substrate, wherein the fourth redistribution structure includes the bonding layer.

3. The method of claim 2, further comprising forming an interconnect layer over the first component substrate and the second component substrate prior to forming the fourth redistribution structure, wherein, The interconnect layer includes interconnect dies embedded in the molding compound and intermediate layer through-holes.

4. The method according to claim 3, wherein, The interconnect die electrically couples the first component substrate to the second component substrate.

5. The method according to claim 1, wherein, The packaging component is electrically connected to the first component substrate and the second component substrate.

6. The method of claim 1, further comprising forming the substrate core, wherein, Forming the substrate core includes: Forming a through-hole in the glass core; An opening is formed through the glass core; and The passive device is placed inside the opening of the glass core.

7. The method according to claim 6, wherein, The passive device electrically couples the second redistribution structure to the third redistribution structure, and wherein the glass through-hole electrically couples the second redistribution structure to the third redistribution structure.

8. A method of forming a semiconductor device, comprising: The first set of substrate through-holes and the second set of substrate through-holes are formed through the substrate core; A first redistribution structure is formed above the first set of substrate through-holes; A second redistribution structure is formed above the second set of substrate through-holes, and the second redistribution structure is electrically isolated from the first redistribution structure and the first set of substrate through-holes; A dicing process is performed to form a first component substrate and a second component substrate, wherein the first component substrate includes a first portion of the substrate core, a first set of substrate through-holes and a first redistribution structure, and wherein the second component substrate includes a second portion of the substrate core, a second set of substrate through-holes and a second redistribution structure; The first component substrate and the second component substrate are attached to the carrier, and the first component substrate and the second component substrate are laterally offset by a gap; Fill the gap with molding material; A third redistribution structure is formed over the first component substrate and the second component substrate, wherein, after the formation of the third redistribution structure, the first component substrate and the second component substrate are electrically connected; and The packaging components are attached to the third redistribution structure, wherein each of the packaging components includes a plurality of integrated circuit dies disposed above an interposer layer.

9. The method of claim 8, further comprising, before forming the third redistribution structure: Metal pillars are formed directly above the first redistribution structure and the second redistribution structure; The first interconnect die is directly attached to the molding material, the first redistribution structure, and the second redistribution structure; as well as A molding compound is formed around the metal pillar and the first interconnect die.

10. A semiconductor device, comprising: Packaging substrate, including: A first component substrate, including a first redistribution structure; The second component substrate includes a second redistribution structure, and the second component substrate is laterally offset from the first component substrate; Molding material, disposed between the first component substrate and the second component substrate; and A third redistribution structure is disposed above the first component substrate and the second component substrate, and the third redistribution structure is electrically connected to both the first component substrate and the second component substrate; and A first packaging component is attached to the third redistribution structure, the first packaging component including a first integrated circuit die disposed above a first interposer layer.

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