Inter-Layer Multiplexer Bypass Architecture for Fault-Tolerant Compute Arrays

Abstract

A compute array employs inter-layer multiplexers between stacked processing layers to maintain continuous signal paths when column segments become defective. Each processing column includes multiple processing elements that generate partial-sum signals transmitted vertically through the stack. The multiplexers dynamically route these signals through adjacent functional column segments, preserving connectivity from the top layer to the output-sum region. A controller identifies defective segments by comparing final output sums and reconfigures multiplexer states without halting computation. The architecture provides column-segment fault tolerance with minimal area and timing overhead.

Images