Read / write control method, storage circuit, and control system

Abstract

This application relates to a read / write control method, a storage circuit, and a control system. The read / write control circuit, applied in the storage circuit, identifies the read / write status of external read / write control signals received by the memory in the storage circuit to determine the current operation type of the memory. If the current operation type of the memory is a read operation, it performs address repeatability detection on the currently received external address information and generates a detection feedback signal. It acquires a reference clock signal and performs signal modulation processing on the reference clock signal according to the detection feedback signal to generate a modulated clock signal, which is then sent to the memory. This allows the memory to determine whether to perform a read operation on the external address information based on the clock state of the modulated clock signal. This avoids redundant internal operations caused by continuously accessing the same address for read operations, thereby reducing the internal power consumption of the memory and minimizing unnecessary resource consumption.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a read / write control method, a storage circuit, and a control system. Background Technology

[0002] In existing Random Access Memory (RAM), data read and write operations are typically performed synchronously, strictly relying on an externally provided clock signal. As the demand for access speeds continues to grow, systems often increase the clock frequency to achieve performance targets. However, high-frequency clock signal switching significantly exacerbates the dynamic power consumption within the memory. In practical applications, however, continuous access to the same address frequently occurs, causing the memory to perform unnecessary repeated read operations, thus incurring additional dynamic power consumption and resource overhead.

[0003] There is currently no effective solution to the problem of redundant operations in memory, resulting in additional dynamic power consumption and resource overhead caused by repeatedly making read requests to the same address in traditional technologies. Summary of the Invention

[0004] Therefore, it is necessary to provide a read / write control method, a storage circuit, and a control system to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a read / write control method applied to a read / write control circuit in a storage circuit; the method includes:

[0006] The external read / write control signals received by the memory in the storage circuit are used to identify the read / write status and determine the current operation type of the memory.

[0007] If the current operation type of the memory is a read operation, then address duplication detection is performed on the external address information currently received by the memory, and a detection feedback signal is generated.

[0008] A reference clock signal is acquired, and the reference clock signal is modulated according to the detection feedback signal to generate a modulated clock signal. The modulated clock signal is then sent to the memory so that the memory determines whether to perform a read operation on the external address information based on the clock state of the modulated clock signal.

[0009] In one embodiment, the read / write control circuit includes an address comparison circuit; the step of identifying the read / write status of the external read / write control signal received by the memory in the storage circuit and determining the current operation type of the memory includes:

[0010] The address comparison circuit receives and identifies the external read / write control signal.

[0011] If the level of the external read / write control signal is detected to be at the first level, then the current operation type of the memory is determined to be a read operation;

[0012] If the level of the external read / write control signal is detected to be the second level, then the current operation type of the memory is determined to be a write operation.

[0013] The first voltage level and the second voltage level are opposite to each other.

[0014] In one embodiment, the read / write control circuit includes an address decoding circuit and an address comparison circuit; the address comparison circuit includes an address buffer; if the current operation type of the memory is a read operation, then address duplication detection is performed on the external address information currently received by the memory, and a detection feedback signal is generated, including:

[0015] The external address information is decoded by the address decoding circuit to obtain decoded address information, and the decoded address information is sent to the address comparison circuit.

[0016] The address comparison circuit compares the decoded address information with the value of the address buffer to generate a detection feedback signal.

[0017] In one embodiment, the step of comparing the decoded address information with the value of the address buffer through the address comparison circuit to generate a detection feedback signal includes:

[0018] If the value of the address buffer is empty, a detection feedback signal for an invalid load level is generated;

[0019] If the value of the address buffer is the previous address information, then the decoded address information is compared with the previous address information; the previous address information is the decoded address information corresponding to the last read operation before the current read operation;

[0020] If the decoded address information is inconsistent with the previous address information, a detection feedback signal for loading an invalid level is generated;

[0021] If the decoded address information is consistent with the previous address information, a detection feedback signal with a valid load level is generated;

[0022] The invalid level and the valid level are opposite to each other.

[0023] In one embodiment, the read / write control circuit further includes a clock modulation circuit; the modulation clock signal includes a first modulation clock signal; the step of performing signal modulation processing on the reference clock signal according to the detection feedback signal to generate the modulation clock signal includes:

[0024] If the level loaded in the detection feedback signal is an invalid level, then the clock modulation circuit performs a logical conversion between the invalid level and the reference clock signal to generate a first modulation clock signal; the first modulation clock signal keeps clock synchronized with the reference clock signal during the current read operation cycle;

[0025] The first modulation clock signal is sent to the memory so that the memory performs a read operation on the external address information when the first modulation clock signal is in a clock valid state.

[0026] In one embodiment, the read / write control circuit further includes a clock modulation circuit; the modulation clock signal includes a second modulation clock signal; the step of performing signal modulation processing on the reference clock signal according to the detection feedback signal to generate the modulation clock signal includes:

[0027] If the level loaded in the detection feedback signal is an effective level, then the clock modulation circuit performs a logical conversion between the effective level and the reference clock signal to generate a second modulated clock signal; the second modulated clock signal remains in an invalid clock state during the current read operation cycle;

[0028] The second modulated clock signal is sent to the memory so that the memory does not perform a read operation on the external address information.

[0029] In one embodiment, the method further includes:

[0030] After the address duplication detection step is completed, the decoded address information is written into the address buffer as the previous address information, and the value of the address buffer is iteratively updated.

[0031] In one embodiment, the method further includes:

[0032] If the current operation type of the memory is a write operation, then the address cache is cleared.

[0033] Secondly, this application provides a storage circuit, which includes a read / write control circuit and a memory;

[0034] The read / write control circuit is used to execute the read / write control method described above;

[0035] The memory is configured to determine whether to perform a read operation on the currently received external address information based on the clock state of the modulated clock signal sent by the read / write control circuit when the current operation type is a read operation.

[0036] In one embodiment, the read / write control circuit includes an address input terminal, a control terminal, a clock input terminal, and a clock output terminal; wherein,

[0037] The address input terminal of the read / write control circuit and the address input terminal of the memory are both used to receive external address information; the control terminal of the read / write control circuit and the control terminal of the memory are both used to receive external read / write control signals; the clock input terminal of the read / write control circuit is used to receive a reference clock signal; the clock output terminal of the read / write control circuit is connected to the clock terminal of the memory.

[0038] In one embodiment, the read / write control circuit includes an address decoding circuit, an address comparison circuit, and a clock modulation circuit; the address decoding circuit has an address input terminal and an address output terminal; the address comparison circuit has a control terminal, an address input terminal, and an output terminal; the clock modulation circuit has a control terminal, a clock input terminal, and a clock output terminal; wherein,

[0039] The address input terminal of the address decoding circuit is used to receive the external address information; the address output terminal of the address decoding circuit is connected to the address input terminal of the address comparison circuit.

[0040] The control terminal of the address comparison circuit is used to receive the external read / write control signal, and the output terminal of the address comparison circuit is connected to the control terminal of the clock modulation circuit.

[0041] The clock input terminal of the clock modulation circuit is used to receive the reference clock signal, and the clock output terminal of the clock modulation circuit is connected to the clock terminal of the memory.

[0042] Thirdly, this application provides a control system, which includes a controller and a storage circuit as described above; the controller is connected to the storage circuit.

[0043] The controller is used to generate external read / write control signals, external address information, and a reference clock signal and send them to the storage circuit.

[0044] The storage circuit is used to execute the read / write control method described above.

[0045] The aforementioned read / write control method, storage circuit, and control system introduce a read / write control circuit into the storage circuit. This circuit identifies the read / write status of the memory by recognizing the external read / write control signals received by the memory, thus determining the current operation type of the memory. When the current operation type is determined to be a read operation, address duplication detection is performed on the currently received external address information, generating a detection feedback signal to indicate whether the currently received external address information is duplicated. Furthermore, based on the detection feedback signal, a reference clock signal is modulated to generate a modulated clock signal, controlling whether the memory performs a read operation on the external address information. This avoids redundant internal operations caused by continuously accessing the same address for read operations, thereby reducing the memory's internal power consumption and minimizing unnecessary resource consumption. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a flowchart illustrating a read / write control method in one embodiment;

[0048] Figure 2 This is a schematic diagram of the storage circuit in one embodiment;

[0049] Figure 3 This is a schematic diagram of the memory structure in one embodiment;

[0050] Figure 4 This is a flowchart illustrating the read / write state identification steps in one embodiment;

[0051] Figure 5 This is a schematic diagram of the storage circuit in one exemplary embodiment;

[0052] Figure 6 This is a flowchart illustrating the signal modulation steps in one embodiment;

[0053] Figure 7 This is a flowchart illustrating the signal modulation step in another embodiment;

[0054] Figure 8 This is a schematic diagram of read / write control timing in a specific embodiment. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0056] In one embodiment, such as Figure 1 As shown, Figure 1 This is a flowchart illustrating a read / write control method in one embodiment. This embodiment provides a read / write control method applied to a read / write control circuit in a storage circuit. The read / write control method includes the following steps:

[0057] Step S101: The read / write status of the memory received by the memory in the storage circuit is identified to determine the current operation type of the memory.

[0058] The read / write control circuit includes an address input terminal, a control terminal, a clock input terminal, and a clock output terminal. The storage circuit also includes a memory; the memory may be, but is not limited to, random access memory (RAM). The memory includes an address input terminal, a clock terminal, and a control terminal. In an exemplary embodiment, see [reference needed]. Figure 2 The address input terminals of both the read / write control circuit and the memory are used to receive external address information (ADD). The control terminals of both the read / write control circuit and the memory are used to receive external read / write control signals (WE). The clock input terminal of the read / write control circuit is used to receive the reference clock signal (CLK). The clock output terminal of the read / write control circuit is connected to the clock terminal of the memory, and its clock output provides a modulated clock signal (CK) to the clock terminal of the memory. In addition, the memory also has data input / output terminals for inputting data signals (DATA) corresponding to write operations, or outputting data signals (DATA) corresponding to read operations.

[0059] In one exemplary embodiment, see Figure 3 The memory includes an address decoder, input / output circuitry, and a storage matrix. The address decoder receives external address information (ADD), decodes it, and sends it to the storage matrix. The storage matrix comprises multiple storage cells for storing data. It should be noted that when the memory is large, external address information (ADD) can be transmitted in parallel using multiple address lines. For example, for a 1K memory, 10 address lines can be used to transmit external address information (ADD) in parallel.

[0060] The input / output circuit is used to receive the modulation clock signal CK, the external read / write control signal WE, and to input or output the data signal DATA. In an exemplary embodiment, under the control of the external read / write control signal WE, the input / output circuit performs the following operations when the modulation clock signal CK is in a clock-active state (e.g., an active clock edge): During a write operation, the input / output circuit writes the data loaded by the data signal DATA into the memory cell corresponding to the external address information ADD in the memory matrix; during a read operation, it reads the data stored in the memory cell corresponding to the external address information ADD from the memory matrix and loads it into the data signal DATA for output.

[0061] The external address information, provided by an external controller, points to a specific memory cell. The external read / write control signals, also provided by an external controller, indicate the current memory operation type; this type includes both read and write operations.

[0062] The external read / write control signal level includes a first level and a second level. The first level is used to instruct the memory to perform a read operation, and the second level is used to instruct the memory to perform a write operation. It should be noted that the first and second levels are inverses of each other; for example, if the first level is high, the second level is low; and if the first level is low, the second level is high.

[0063] Step S102: If the current operation type of the memory is a read operation, then the address duplication detection is performed on the external address information currently received by the memory, and a detection feedback signal is generated.

[0064] Address duplication detection refers to detecting whether the currently received external address information is duplicated with the external address information corresponding to the last read operation before the current read operation, in order to accurately identify whether there is a situation of continuous access to the same address. It can be understood that if the operation preceding the current read operation is also a read operation, then it can be determined that the preceding operation is the "last read operation before the current read operation" described above.

[0065] The detection feedback signal is used to indicate whether the currently received external address information is a duplicate address. The detection feedback signal includes a valid level and an invalid level; a valid level indicates that the currently received external address information is a duplicate address; an invalid level indicates that the currently received external address information is a non-duplicate address.

[0066] It should be noted that the valid and invalid levels are inverses of each other; for example, if the valid level is high, then the invalid level is low; if the valid level is low, then the invalid level is high.

[0067] Step S103: Obtain the reference clock signal, perform signal modulation processing on the reference clock signal according to the detection feedback signal to generate a modulated clock signal, and send the modulated clock signal to the memory so that the memory can determine whether to perform a read operation on the external address information according to the clock state of the modulated clock signal.

[0068] The reference clock signal is used to provide a clock reference for the storage circuit. In an exemplary embodiment, the reference clock signal may be provided by an external controller or an external clock source, but is not specifically limited thereto.

[0069] The modulated clock signal is used to provide a clock reference for the memory in the storage circuit to control the read and write behavior of the memory. In an exemplary embodiment, the memory performs a read or write operation when the modulated clock signal is in a clock-active state; wherein, the clock-active state may include, but is not limited to, an active clock edge (rising edge or falling edge), which needs to be set according to actual control requirements and is not specifically limited here; for example, when the clock-active state is a rising edge, the memory triggers a read or write operation at the rising edge of the modulated clock signal.

[0070] The modulation clock signal includes a first modulation clock signal and a second modulation clock signal; wherein the first modulation clock signal is kept synchronized with the reference clock signal during the current read operation cycle, and is used to control the memory to perform read operations on external address information; the second modulation clock signal is kept in an invalid state during the current read operation cycle, and is used to control the memory not to perform read operations on external address information.

[0071] It is understandable that the current read operation cycle refers to the time window from when the current external address signal is effectively received by the memory until the next new external address signal is effectively received by the memory, under the condition that the external read / write control signal indicates that the current operation type of the memory is a read operation.

[0072] In one exemplary embodiment, the process of modulating a reference clock signal based on a detection feedback signal to generate a modulated clock signal includes the following steps: modulating the reference clock signal according to the level type applied by the detection feedback signal to generate a corresponding modulated clock signal. Exemplarily, the level applied by the detection feedback signal and the reference clock signal are logically converted to generate the corresponding modulated clock signal.

[0073] In an exemplary embodiment, the read / write control circuit identifies the read / write status of the external read / write control signal received by the memory. If the current operation type of the memory is identified as a read operation, address duplication detection is performed on the external address information currently received by the memory. If the external address information currently received by the memory is detected as a duplicate address, a detection feedback signal with a valid level is generated. If the external address information currently received by the memory is detected as a non-duplicate address, a detection feedback signal with an invalid level is generated. Furthermore, based on the level type loaded in the detection feedback signal, the reference clock signal is modulated to generate a corresponding modulated clock signal, which is sent to the memory so that the memory can determine whether to perform a read operation on the external address information according to the clock state of the modulated clock signal.

[0074] In this embodiment, a read / write control circuit is introduced into the storage circuit, and the read / write control circuit identifies the read / write status of the memory by recognizing the external read / write control signals received by the memory, thereby determining the current operation type of the memory. When the current operation type of the memory is determined to be a read operation, address duplication detection is performed on the external address information currently received by the memory, and a detection feedback signal is generated to characterize whether the currently received external address information is duplicated. Furthermore, based on the detection feedback signal, the reference clock signal is modulated to generate a modulated clock signal to control whether the memory performs a read operation on the external address information. Thus, redundant internal operations caused by continuously accessing the same address for read operations can be avoided, thereby reducing the internal power consumption of the memory and reducing unnecessary resource occupation.

[0075] In one embodiment, such as Figure 4 As shown, Figure 4 This is a flowchart illustrating the read / write status identification step in one embodiment; the read / write status identification of the external read / write control signals received by the memory in the storage circuit to determine the current operation type of the memory includes the following steps:

[0076] Step S401: Receive and identify external read / write control signals through the address comparison circuit.

[0077] In one exemplary embodiment, see Figure 5The read / write control circuit includes an address decoding circuit, an address comparison circuit, and a clock modulation circuit. The address decoding circuit has an address input terminal and an address output terminal. The address comparison circuit has a control terminal, an address input terminal, and an output terminal. The clock modulation circuit has a control terminal, a clock input terminal, and a clock output terminal. Specifically, the address input terminal of the address decoding circuit receives external address information ADD; the address output terminal of the address decoding circuit is connected to the address input terminal of the address comparison circuit; the control terminal of the address comparison circuit receives external read / write control signal WE, and its output terminal is connected to the control terminal of the clock modulation circuit; the clock input terminal of the clock modulation circuit receives a reference clock signal CLK, and its clock output terminal is connected to the clock terminal of the memory; the clock output terminal of the clock modulation circuit provides a modulated clock signal CK to the clock terminal of the memory.

[0078] The address comparison circuit is used to synchronously receive and identify external read / write control signals sent to the memory to determine the current operation type of the memory, and then decide whether to perform address duplication detection on the currently received external address information based on the current operation type.

[0079] Understandably, when the address comparison circuit identifies the current operation type of the memory as a read operation, it performs address repeatability detection on the external address information currently received by the memory and generates a detection feedback signal to provide data basis for the modulation of the reference clock signal; when the address comparison circuit identifies the current operation type of the memory as a write operation, it does not perform address repeatability detection to ensure the timing determinism and execution efficiency of the write operation.

[0080] The external read / write control signal level includes a first level and a second level. The first level is used to instruct the memory to perform a read operation, and the second level is used to instruct the memory to perform a write operation. It should be noted that the first and second levels are inverses of each other; for example, if the first level is high, the second level is low; and if the first level is low, the second level is high.

[0081] Step S402: If the level of the external read / write control signal is detected to be the first level, then the current operation type of the memory is determined to be a read operation.

[0082] Step S403: If the level of the external read / write control signal is detected to be the second level, then the current operation type of the memory is determined to be a write operation.

[0083] In an exemplary embodiment, an external read / write control signal sent to the memory is received synchronously through an address comparison circuit, and the current operation type of the memory is determined by identifying the level state of the external read / write control signal. Specifically, if the level state of the external read / write control signal is identified as a first level, the current operation type of the memory is determined to be a read operation; if the level state of the external read / write control signal is identified as a second level, the current operation type of the memory is determined to be a write operation.

[0084] In this embodiment, by setting an address comparison circuit, the current operation type of the memory can be accurately sensed, laying the foundation for implementing read / write control logic based on operation type. Specifically, when the current operation type is identified as a read operation, address repeatability detection is performed and a detection feedback signal is generated to modulate the reference clock signal, thereby avoiding redundant access to duplicate addresses and reducing dynamic power consumption. When the current operation type is identified as a write operation, address repeatability detection is skipped to ensure the reliability of the write operation.

[0085] In one embodiment, if the current operation type of the memory is a read operation, then address duplication detection is performed on the external address information currently received by the memory, and a detection feedback signal is generated, including the following steps:

[0086] Step 1: The external address information is decoded by the address decoding circuit to obtain the decoded address information, and then the decoded address information is sent to the address comparison circuit.

[0087] In one exemplary embodiment, see Figure 5 The read / write control circuit includes an address decoding circuit; the address decoding circuit is used to convert the external address information ADD from the original encoding format into decoded address information that conforms to the preset address format, and send the decoded address information to the address comparison circuit.

[0088] The decoded address information refers to the binary address encoding that conforms to the preset address format. The preset address format needs to be set according to the actual decoding requirements, and is not specifically limited here.

[0089] Step 2: The decoded address information is compared with the value of the address buffer using the address comparison circuit to generate a detection feedback signal.

[0090] The address comparison circuit includes an address buffer; this buffer temporarily stores the decoded address information corresponding to the last valid read operation preceding the current read operation. Essentially, the address buffer provides a reference benchmark for address duplication detection, ensuring the accuracy and effectiveness of the detection.

[0091] In an exemplary embodiment, if the current operation type of the memory is a write operation, the address buffer is cleared. This effectively prevents the external address signal corresponding to the write operation from being mistakenly stored in the address buffer, thereby preventing it from participating in address duplication detection in subsequent read operations and ensuring the accuracy and reliability of the detection results.

[0092] In an exemplary embodiment, the method for comparing the decoded address information with the value of the address buffer may be: comparing the decoded address information bit by bit with the value of the address buffer to generate a detection feedback signal for characterizing address repetition.

[0093] In an exemplary embodiment, an address decoding circuit synchronously receives external address information sent to the memory, decodes the external address information to obtain decoded address information conforming to a preset address format, and sends the decoded address information to an address comparison circuit. Simultaneously, the address comparison circuit synchronously receives external read / write control signals sent to the memory and determines the current storage type of the memory by identifying the level state of the external read / write control signals. If the level state of the external read / write control signals is identified as the first level, the current operation type of the memory is determined to be a read operation. The decoded address information sent by the address decoding circuit is then received, compared with the value of the address buffer, and a detection feedback signal is generated. This detection feedback signal is sent to a clock modulation circuit, which modulates the received reference clock signal according to the detection feedback signal to generate a modulated clock signal. The modulated clock signal is then sent to the memory, allowing the memory to determine whether to perform a read operation on the external address information based on the clock state of the modulated clock signal.

[0094] In this embodiment, by setting an address decoding circuit, external address signals can be converted into decoded address information that conforms to a preset address format, laying the foundation for subsequent address repeatability detection. By setting an address comparison circuit, external read / write control signals can be parsed synchronously to identify the current operation type of the memory. When the current operation type is identified as a read operation, the decoded address information output by the address decoding circuit is compared with the value of the address buffer to generate a detection feedback signal that characterizes address repeatability, laying the foundation for subsequent clock signal modulation.

[0095] In one embodiment, an address comparison circuit compares the decoded address information with the value of the address buffer to generate a detection feedback signal, including the following steps:

[0096] Step 1: If the value of the address buffer is empty, generate a detection feedback signal for an invalid load level.

[0097] It should be noted that the value of the address register may be empty or may be the address information from the previous operation. The value of the address register depends on the circuit initialization state before the current read operation or the type of the previous operation.

[0098] In an exemplary embodiment, if the storage circuit was in an initialization state before the current read operation, or the previous operation type was a write operation, the value of the address buffer is empty; if the operation type before the current read operation was a read operation, the value of the address buffer is the previous address information.

[0099] The previous address information refers to the decoded address information corresponding to the last read operation before the current read operation. It can be understood that when the address buffer is not empty, it indicates that the previous operation was also a read operation. In this case, the address buffer value (i.e., the previous address information) is the decoded address information corresponding to the previous operation (i.e., the read operation).

[0100] Step 2: If the value of the address buffer is the previous address information, then compare the decoded address information with the previous address information.

[0101] Step 3: If the decoded address information is inconsistent with the previous address information, a detection feedback signal for loading an invalid level is generated.

[0102] The invalid level indicates that the currently received external address information is a non-repeating address.

[0103] Step 4: If the decoded address information is consistent with the previous address information, a detection feedback signal for loading a valid level is generated.

[0104] The valid level indicates that the currently received external address information is a duplicate address. It should be noted that the valid and invalid levels are inverses of each other; for example, if the valid level is high, the invalid level is low; if the valid level is low, the invalid level is high.

[0105] In an exemplary embodiment, when the current storage type of the memory is a read operation, the decoded address information is compared with the value of the address buffer using an address comparison circuit. Specifically, if the value of the address buffer is empty, a detection feedback signal with an invalid level is generated to indicate that the external address information currently received by the memory is a non-duplicate address. If the value of the address buffer is the previous address information, the decoded address information is compared with the previous address information. If the decoded address information and the previous address information are found to be inconsistent, a detection feedback signal with an invalid level is generated to indicate that the external address information currently received by the memory is a non-duplicate address. If the decoded address information and the previous address information are found to be consistent, a detection feedback signal with a valid level is generated to indicate that the currently received external address information is a duplicate address.

[0106] In an exemplary embodiment, the read-write control method further includes the following steps: after the address duplication detection step is completed, the decoded address information is written as the previous address information into the address buffer, and the value of the address buffer is iteratively updated.

[0107] Understandably, during continuous read operations, the value of the address buffer is not fixed, but dynamically updated with each read operation to cache the decoded address information corresponding to the most recent read operation. This ensures the accuracy and effectiveness of address duplication detection and avoids misjudgment of duplication detection due to the address buffer not being updated or being updated incorrectly, which would affect the memory read operation response performance.

[0108] In this embodiment, the decoded address information is compared with the value of the address buffer by the address comparison circuit. Based on whether the address buffer is empty and whether the decoded address information is consistent with the previous address information, a corresponding level detection feedback signal is generated, which lays the foundation for subsequent modulation of the reference clock signal to suppress redundant read operations and reduce the dynamic power consumption of the memory.

[0109] In one embodiment, such as Figure 6 As shown, Figure 6 This is a flowchart illustrating the signal modulation steps in one embodiment; the modulation clock signal includes a first modulation clock signal; the modulation clock signal is generated by modulating the reference clock signal according to the detection feedback signal, including the following steps:

[0110] Step 601: If the level loaded in the detection feedback signal is an invalid level, then the invalid level and the reference clock signal are logically converted by the clock modulation circuit to generate the first modulation clock signal.

[0111] The invalid level indicates that the currently received external address information is a non-repeating address. The first modulation clock signal remains synchronized with the reference clock signal during the current read operation cycle. The reference clock signal may be provided by an external controller or an external clock source, but is not specifically limited to this.

[0112] It is understandable that the first modulation clock signal keeps clock synchronized with the reference clock signal during the current read operation cycle. This means that during the current read operation cycle, the clock edge of the first modulation clock signal is aligned with the clock edge of the reference clock signal, and the clock pulse of the first modulation clock signal is completely consistent with the clock pulse of the reference clock signal, thereby ensuring the timing reliability and data access accuracy of the memory performing read operations.

[0113] In one exemplary embodiment, see Figure 5The read / write control circuit also includes a clock modulation circuit. This clock modulation circuit performs logical conversion between the level loaded in the detection feedback signal and the reference clock signal to generate a corresponding modulated clock signal. It can be understood that the clock modulation circuit can be used to suppress or enable the effective clock edge of the reference clock signal, ensuring that the memory performs read operations only when necessary.

[0114] In an exemplary embodiment, the clock modulation circuit includes a logic circuit whose inputs are a reference clock signal and a detection feedback signal; when the level of the detection feedback signal is invalid, the logic circuit outputs a first modulation clock signal synchronized with the reference clock signal to ensure that the memory triggers a read operation for external address information at the valid clock edge of the first modulation clock signal.

[0115] Step 602: Send the first modulation clock signal to the memory so that the memory can perform a read operation on the external address information when the first modulation clock signal is in a clock valid state.

[0116] The clock validity state of the first modulation clock signal may include, but is not limited to, valid clock edges (rising edge or falling edge), and needs to be set according to actual control requirements. No specific limitation is made here. For example, when the clock validity state is rising edge, if the current operation type is read operation, the memory triggers a read operation at the rising edge of the first modulation clock signal.

[0117] In this embodiment, by setting a clock modulation circuit, when the received detection feedback signal is invalid, a first modulation clock signal synchronized with the reference clock signal can be generated, so that the memory can perform a read operation on the external address signal when the first modulation clock signal is in an effective clock state, thereby ensuring the reliability and timing correctness of the memory read operation.

[0118] In one embodiment, such as Figure 7 As shown, Figure 7 This is a flowchart illustrating the signal modulation step in another embodiment; the modulation clock signal includes a second modulation clock signal; the modulation clock signal is generated by performing signal modulation processing on the reference clock signal based on the detection feedback signal, including the following steps:

[0119] Step S701: If the level loaded in the detection feedback signal is an effective level, then the effective level and the reference clock signal are logically converted by the clock modulation circuit to generate a second modulation clock signal.

[0120] Specifically, the second modulation clock signal remains in an invalid state during the current read operation cycle. This means that the second modulation clock signal is forced to remain at a constant and invalid level during the current read operation cycle, thereby completely preventing the occurrence of valid clock edges. This ensures that the memory cannot trigger a read operation for the current external address information, thus suppressing redundant reads.

[0121] In an exemplary embodiment, the clock modulation circuit includes a logic circuit whose inputs are a reference clock signal and a detection feedback signal; when the level of the detection feedback signal is active, the logic circuit outputs a second modulation clock signal to suppress the generation of active clock edges, thereby controlling the memory not to perform the current read operation.

[0122] Step S702: Send the second modulation clock signal to the memory so that the memory does not perform a read operation on external address information.

[0123] In this embodiment, by setting a clock modulation circuit, when the received detection feedback signal is at an effective level, the clock modulation circuit performs clock modulation on the reference clock signal to generate a second modulated clock signal, so as to completely suppress the generation of effective clock edges, thereby preventing redundant internal operations caused by continuous access to the same address in the memory, effectively reducing the internal power consumption of the memory, and reducing unnecessary resource occupation.

[0124] In one specific embodiment, taking the external read / write control signal WE with a first level high (indicating the memory to perform a read operation), a second level low (indicating the memory to perform a write operation), an invalid level low (indicating the currently received external address information is a non-duplicate address), and an active level high (indicating the currently received external address information is a duplicate address) as an example, combined with... Figure 5 The storage circuit shown and Figure 8 The read / write control timing diagram shown illustrates the read / write control method:

[0125] See Figure 8 WE is the external read / write control signal, AD is the value of the address buffer in the address comparison circuit (either empty or the previous address information), add is the decoded address information (i.e., the binary address code obtained after decoding the external address information ADD by the address decoder), CTRL is the detection feedback signal, CLK is the reference clock signal, and CK is the modulation clock signal (including the first modulation clock signal and the second modulation clock signal).

[0126] After the external controller begins sending external address information ADD and external read / write control signal WE to the memory, the address decoding circuit synchronously receives the external address information ADD sent to the memory and decodes it to obtain the decoded address information add1. The decoded address information add1 is then transmitted to the address comparison circuit. The address comparison circuit synchronously receives the external read / write control signal WE sent to the memory. By identifying the level of the external read / write control signal as the first level (i.e., high level), it determines that the current operation type of the memory is a read operation. At this point, it compares the received decoded address information add1 with the value of the address buffer (which is currently empty). Since the address buffer is empty at this time... Therefore, a detection feedback signal CTRL with an invalid level (i.e., low level) is generated, and the received decoded address information add1 is written into the address buffer as the previous address information to update the address buffer. The clock modulation circuit receives the reference clock signal CLK. Since the level loaded in the detection feedback signal CTRL is an invalid level (i.e., low level), the clock modulation circuit performs a logical conversion between the invalid level and the reference clock signal to generate a first modulation clock signal synchronized with the reference clock signal CLK. The first modulation clock signal is sent to the memory so that the memory can perform a read operation on the external address information ADD when the first modulation clock signal is at a valid clock edge (e.g., rising edge or falling edge).

[0127] The external controller continues to send the next external address information ADD and the external read / write control signal WE to the memory. The address decoding circuit synchronously receives the external address information ADD sent to the memory and decodes it to obtain the decoded address information add1. This decoded address information add1 is then transmitted to the address comparison circuit. The address comparison circuit synchronously receives the external read / write control signal WE sent to the memory. By identifying the level of the external read / write control signal as the first level (i.e., high level), it determines that the current operation type of the memory is a read operation. At this point, it compares the received decoded address information add1 with the value of the address buffer (which is now the previous address information add1). Since the value of the address buffer is now the previous address information add1, and the two are consistent, an increment is generated. The detection feedback signal CTRL carries an effective level (i.e., high level) and writes the received decoded address information add1 as the previous address information into the address buffer to update the address buffer; the clock modulation circuit receives the reference clock signal CLK. Since the level loaded in the detection feedback signal CTRL is an effective level (i.e., high level), the clock modulation circuit performs a logical conversion between the effective level and the reference clock signal to generate a second modulation clock signal (such as continuously outputting a high level) to suppress the generation of effective clock edges; the second modulation clock signal is sent to the memory so that the memory does not perform a read operation on the external address information ADD (i.e., decoded address add1). Based on this, redundant internal operations caused by continuous access to the same address can be avoided, thereby reducing the internal power consumption of the memory and reducing unnecessary resource occupation.

[0128] The external controller continues to send the next external address information ADD and the external read / write control signal WE to the memory. The address decoding circuit synchronously receives the external address information ADD sent to the memory and decodes it to obtain the decoded address information add2. This decoded address information add2 is then transmitted to the address comparison circuit. The address comparison circuit synchronously receives the external read / write control signal WE sent to the memory. By identifying the level of the external read / write control signal as the first level (i.e., high level), it determines that the current operation type of the memory is a read operation. At this point, it compares the received decoded address information add2 with the value of the address buffer (which is currently the previous address information add1). Since the value of the address buffer is now the previous address information... The information add2 is inconsistent with the previous address information, so a detection feedback signal CTRL with an invalid level (i.e., low level) is generated, and the received decoded address information add2 is written into the address buffer as the previous address information to update the address buffer; the clock modulation circuit receives the reference clock signal CLK. Since the level loaded in the detection feedback signal CTRL is an invalid level (i.e., low level), the clock modulation circuit performs a logical conversion between the invalid level and the reference clock signal to generate a first modulation clock signal synchronized with the reference clock signal CLK. The first modulation clock signal is sent to the memory so that the memory can perform a read operation on the external address information ADD when the first modulation clock signal is at a valid clock edge (e.g., rising edge or falling edge).

[0129] The external controller continues to send the next external address information ADD and the external read / write control signal WE to the memory. The address decoding circuit synchronously receives the external address information ADD sent to the memory and decodes it to obtain the decoded address information add3. The decoded address information add3 is then transmitted to the address comparison circuit. The address comparison circuit synchronously receives the external read / write control signal WE sent to the memory. By identifying that the level of the external read / write control signal is the second level (i.e., low level), it determines that the current operation type of the memory is a write operation. At this time, it does not receive the decoded address information add3 sent by the address decoding circuit, but instead clears the value of the address buffer and generates a detection feedback signal with an invalid level. The clock modulation circuit receives the reference clock signal CLK. Since the level loaded in the detection feedback signal is an invalid level (i.e., low level), it performs a logical conversion between the invalid level and the reference clock signal to generate a third modulation clock signal synchronized with the reference clock signal CLK. The third modulation clock signal is sent to the memory so that the memory performs a write operation on the external address information ADD when the third modulation clock signal is at a valid clock edge (e.g., rising edge or falling edge). Understandably, the third modulation clock signal keeps clock-synchronized with the reference clock signal during the current write operation cycle.

[0130] And so on, without further explanation.

[0131] In this embodiment, a read / write control circuit is introduced into the storage circuit, and the read / write control circuit identifies the read / write status of the memory by recognizing the external read / write control signals received by the memory, thereby determining the current operation type of the memory. When the current operation type of the memory is determined to be a read operation, address duplication detection is performed on the external address information currently received by the memory, and a detection feedback signal is generated to characterize whether the currently received external address information is duplicated. Furthermore, based on the detection feedback signal, the reference clock signal is modulated to generate a modulated clock signal to control whether the memory performs a read operation on the external address information. Thus, redundant internal operations caused by continuously accessing the same address for read operations can be avoided, thereby reducing the internal power consumption of the memory and reducing unnecessary resource occupation.

[0132] In one embodiment, see Figure 2 A storage circuit is provided, which includes a read / write control circuit and a memory.

[0133] The read / write control circuit is used to execute the read / write control method described in any of the above embodiments. It should be noted that the specific limitations of the read / write control circuit in executing the read / write control method can be found in the limitations of the read / write control method above, and will not be repeated here.

[0134] The memory is used to determine whether to perform a read operation on the currently received external address information based on the clock state of the modulated clock signal sent by the read / write control circuit when the current operation type is a read operation.

[0135] The memory is also used to perform a write operation on the currently received external address information according to the clock state of the third modulation clock signal sent by the read / write control circuit when the current operation type is a write operation; wherein the third modulation clock signal is kept clock synchronized with the reference clock signal during the current write operation cycle.

[0136] The memory may include, but is not limited to, RAM memory, without specific limitations.

[0137] In this embodiment, the storage circuit introduces a read / write control circuit. This circuit identifies the read / write status of the memory by recognizing the external read / write control signals received by the memory, thus determining the current operation type of the memory. When the current operation type is determined to be a read operation, address duplication detection is performed on the currently received external address information to generate a detection feedback signal, indicating whether the currently received external address information is duplicated. Furthermore, based on the detection feedback signal, a reference clock signal is modulated to generate a modulated clock signal to control whether the memory performs a read operation on the external address information. This avoids redundant internal operations caused by continuously accessing the same address for read operations, thereby reducing the internal power consumption of the memory and reducing unnecessary resource occupation.

[0138] In one embodiment, see Figure 5 The read / write control circuit includes an address decoding circuit, an address comparison circuit, and a clock modulation circuit; the address decoding circuit has an address input terminal and an address output terminal; the address comparison circuit has a control terminal, an address input terminal, and an output terminal; the clock modulation circuit has a control terminal, a clock input terminal, and a clock output terminal; wherein,

[0139] The address input terminal of the address decoding circuit is used to receive external address information (ADD); the address output terminal of the address decoding circuit is connected to the address input terminal of the address comparison circuit.

[0140] The control terminal of the address comparison circuit is used to receive the external read / write control signal WE, and the output terminal of the address comparison circuit is connected to the control terminal of the clock modulation circuit.

[0141] The clock input terminal of the clock modulation circuit is used to receive the reference clock signal CLK, and the clock output terminal of the clock modulation circuit is connected to the clock terminal of the memory.

[0142] The address comparison circuit may include, but is not limited to, a comparator, and no specific limitation is made here.

[0143] The clock modulation circuit may include, but is not limited to, logic circuits. In an exemplary embodiment, if the invalid level of the detection feedback signal CTRL is low (indicating that the currently received external address information is a non-repeating address) and the valid level of the detection feedback signal CTRL is high (indicating that the currently received external address information is a repeating address), then the logic circuit may be an OR gate; if the invalid level of the detection feedback signal CTRL is high (indicating that the currently received external address information is a non-repeating address) and the valid level of the detection feedback signal CTRL is low (indicating that the currently received external address information is a repeating address), then the logic circuit may be an AND gate.

[0144] It should be noted that the specific circuit structures corresponding to the address decoding circuit, address comparison circuit, and clock modulation circuit described in any of the above embodiments can be flexibly set according to actual design requirements, as long as they can respectively realize the functions of address decoding, address repeatability detection, and signal modulation, and are not limited here.

[0145] In this embodiment, by setting an address decoding circuit, the external address signal can be converted into decoded address information conforming to a preset address format, laying the foundation for subsequent address repetition detection. By setting an address comparison circuit, the current operation type of the memory can be accurately sensed. When the current operation type is identified as a read operation, the decoded address information output by the address decoding circuit is compared with the value of the address buffer to generate a detection feedback signal characterizing address repetition, laying the foundation for subsequent clock signal modulation. By setting a clock modulation circuit, when the received detection feedback signal is invalid, a first modulation clock signal synchronized with the reference clock signal can be generated, so that the memory performs a read operation on the external address signal when the first modulation clock signal is in an active clock state, thereby ensuring the reliability and timing correctness of the memory read operation. When the received detection feedback signal is active, the reference clock signal is clock modulated to generate a second modulation clock signal to completely suppress the generation of active clock edges, thereby preventing redundant internal operations caused by continuous access to the same address, effectively reducing the internal power consumption of the memory, and reducing unnecessary resource occupation.

[0146] In one embodiment, a control system is provided, including a controller and a storage circuit described in any of the above embodiments; the controller is connected to the storage circuit.

[0147] The controller is used to generate external read / write control signals, external address information, and reference clock signals to send to the storage circuit.

[0148] The storage circuit is used to execute the read / write control method described in any of the above embodiments.

[0149] The controller may be, but is not limited to, a microcontroller; no specific limitation is made here.

[0150] This embodiment of the control system introduces a read / write control circuit into the storage circuit. This circuit identifies the read / write status of the memory by recognizing the external read / write control signals received by the memory, thus determining the current operation type of the memory. When the current operation type is determined to be a read operation, address duplication detection is performed on the currently received external address information, generating a detection feedback signal to indicate whether the currently received external address information is duplicated. Furthermore, based on the detection feedback signal, a reference clock signal is modulated to generate a modulated clock signal to control whether the memory performs a read operation on the external address information. This avoids redundant internal operations caused by continuously accessing the same address for read operations, thereby reducing the memory's internal power consumption and minimizing unnecessary resource consumption.

[0151] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0152] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0153] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0154] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A read / write control method, characterized in that, The method is applied to a read / write control circuit in a storage circuit; the method includes: The external read / write control signals received by the memory in the storage circuit are used to identify the read / write status and determine the current operation type of the memory. If the current operation type of the memory is a read operation, then address duplication detection is performed on the external address information currently received by the memory, and a detection feedback signal is generated. A reference clock signal is acquired, and the reference clock signal is modulated according to the detection feedback signal to generate a modulated clock signal. The modulated clock signal is then sent to the memory so that the memory determines whether to perform a read operation on the external address information based on the clock state of the modulated clock signal.

2. The method according to claim 1, characterized in that, The read / write control circuit includes an address comparison circuit; the step of identifying the read / write status of the external read / write control signal received by the memory in the storage circuit and determining the current operation type of the memory includes: The address comparison circuit receives and identifies the external read / write control signal. If the level of the external read / write control signal is detected to be at the first level, then the current operation type of the memory is determined to be a read operation; If the level of the external read / write control signal is detected to be the second level, then the current operation type of the memory is determined to be a write operation. The first voltage level and the second voltage level are opposite to each other.

3. The method according to claim 1, characterized in that, The read / write control circuit includes an address decoding circuit and an address comparison circuit; the address comparison circuit includes an address buffer; if the current operation type of the memory is a read operation, then address duplication detection is performed on the external address information currently received by the memory, and a detection feedback signal is generated, including: The external address information is decoded by the address decoding circuit to obtain decoded address information, and the decoded address information is sent to the address comparison circuit. The address comparison circuit compares the decoded address information with the value of the address buffer to generate a detection feedback signal.

4. The method according to claim 3, characterized in that, The step of comparing the decoded address information with the value of the address buffer through the address comparison circuit to generate a detection feedback signal includes: If the value of the address buffer is empty, a detection feedback signal for an invalid load level is generated; If the value of the address buffer is the previous address information, then the decoded address information is compared with the previous address information; the previous address information is the decoded address information corresponding to the last read operation before the current read operation; If the decoded address information is inconsistent with the previous address information, a detection feedback signal for loading an invalid level is generated; If the decoded address information is consistent with the previous address information, a detection feedback signal with a valid load level is generated; The invalid level and the valid level are opposite to each other.

5. The method according to any one of claims 1 to 4, characterized in that, The read / write control circuit also includes a clock modulation circuit; The modulation clock signal includes a first modulation clock signal; The step of performing signal modulation processing on the reference clock signal based on the detection feedback signal to generate a modulated clock signal includes: If the level loaded in the detection feedback signal is an invalid level, then the clock modulation circuit performs a logical conversion between the invalid level and the reference clock signal to generate a first modulation clock signal; the first modulation clock signal keeps clock synchronized with the reference clock signal during the current read operation cycle; The first modulation clock signal is sent to the memory so that the memory performs a read operation on the external address information when the first modulation clock signal is in a clock valid state.

6. The method according to any one of claims 1 to 4, characterized in that, The read / write control circuit also includes a clock modulation circuit; The modulation clock signal includes a second modulation clock signal; The step of performing signal modulation processing on the reference clock signal based on the detection feedback signal to generate a modulated clock signal includes: If the level loaded in the detection feedback signal is an effective level, then the clock modulation circuit performs a logical conversion between the effective level and the reference clock signal to generate a second modulated clock signal; the second modulated clock signal remains in an invalid clock state during the current read operation cycle; The second modulated clock signal is sent to the memory so that the memory does not perform a read operation on the external address information.

7. The method according to claim 3, characterized in that, The method further includes: After the address duplication detection step is completed, the decoded address information is written into the address buffer as the previous address information, and the value of the address buffer is iteratively updated.

8. The method according to claim 3, characterized in that, The method further includes: If the current operation type of the memory is a write operation, then the address cache is cleared.

9. A storage circuit, characterized in that, The storage circuit includes a read / write control circuit and a memory. The read / write control circuit is used to execute the read / write control method according to any one of claims 1 to 8; The memory is configured to determine whether to perform a read operation on the currently received external address information based on the clock state of the modulated clock signal sent by the read / write control circuit when the current operation type is a read operation.

10. The storage circuit according to claim 9, characterized in that, The read / write control circuit includes an address input terminal, a control terminal, a clock input terminal, and a clock output terminal; wherein... The address input terminal of the read / write control circuit and the address input terminal of the memory are both used to receive external address information; the control terminal of the read / write control circuit and the control terminal of the memory are both used to receive external read / write control signals; the clock input terminal of the read / write control circuit is used to receive a reference clock signal; the clock output terminal of the read / write control circuit is connected to the clock terminal of the memory.

11. The storage circuit according to claim 10, characterized in that, The read / write control circuit includes an address decoding circuit, an address comparison circuit, and a clock modulation circuit; the address decoding circuit has an address input terminal and an address output terminal; the address comparison circuit has a control terminal, an address input terminal, and an output terminal; the clock modulation circuit has a control terminal, a clock input terminal, and a clock output terminal; wherein... The address input terminal of the address decoding circuit is used to receive the external address information; the address output terminal of the address decoding circuit is connected to the address input terminal of the address comparison circuit. The control terminal of the address comparison circuit is used to receive the external read / write control signal, and the output terminal of the address comparison circuit is connected to the control terminal of the clock modulation circuit. The clock input terminal of the clock modulation circuit is used to receive the reference clock signal, and the clock output terminal of the clock modulation circuit is connected to the clock terminal of the memory.

12. A control system, characterized in that, The control system includes a controller and a storage circuit as described in any one of claims 9 to 11; the controller is connected to the storage circuit. The controller is used to generate external read / write control signals, external address information, and a reference clock signal and send them to the storage circuit. The storage circuit is used to execute the read / write control method according to any one of claims 1 to 8.

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