A starting point control method based on twin logic

Abstract

This invention discloses a starting point control method based on twin logic, relating to the field of integrated circuit technology. The method includes: after the chip is powered on, the logic generation circuit begins to establish the state of the target logic channel, and the twin logic channel internally monitors the establishment of this state synchronously; when the twin logic channel determines that the target logic state has been established, it outputs a starting point latch signal and generates a starting point control signal, triggering a timing circuit to sequentially generate a logic lock signal and a shutdown signal; the logic lock signal securely locks the target logic to the latch matrix, and the shutdown signal subsequently shuts down the logic generation circuit. This invention uses "logic-driven timing" instead of the traditional "power-driven timing," truly binding the timing starting point to the physical establishment state of the module, fundamentally avoiding timing races and locking errors; and it can adapt to process and temperature fluctuations, significantly improving system reliability while precisely reducing additional power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a starting point control method based on twin logic. Background Technology

[0002] like Figure 1 As shown, the power-on sequence of chips using traditional fuse tuning technology typically consists of four stages: power-on to stabilization, fuse data reading, logic locking activation, and normal operation. However, these stages suffer from ineffective power consumption issues. That is, after the fuse logic reading is completed, the fuse logic decoding circuit and bias circuit continue to operate in both disabled and enabled states, leading to static power leakage. If the relevant modules are shut down after enabling, there is significant static power consumption before enabling; if the modules are shut down before enabling, the chip cannot correctly enter the initial logic state.

[0003] Existing patented technology (CN120223040B, a domino-style multi-level interlocking power management circuit) such as Figure 2 As shown, this method introduces a domino effect multi-stage interlocking module, relying on the power sensing front-end to generate timing signals, thus freeing itself from the constraints of enable signals and effectively reducing power consumption. However, this method still has limitations: because the power sensing front-end generates timing signals independently of the subsequent circuits, it ignores the actual setup state of downstream modules (such as fuse logic modules). For example, under extreme conditions such as low temperatures, device characteristics drift, and when the power supply voltage has stabilized, the fuse logic has not actually been fully established; at this time, the power sensing front-end has already triggered the timing signal, causing the logic to lock prematurely (catching an incorrect level), leading to a fatal lockout error. In addition, in order to adapt this independent timing circuit to different operating conditions (such as temperature, process angle, power supply fluctuations), it is often necessary to blindly increase the hardware overhead of the timing circuit (such as increasing resistors, capacitors, or cascading stages) to extend the fixed waiting time, which not only increases the area cost but also makes quantitative optimization difficult. Summary of the Invention

[0004] This invention provides a starting point control method based on twin logic to solve the technical problem in the power-on timing control of existing power management chips. Because the timing signal is generated independently by the power sensing front end, the timing starting point is disconnected from the actual establishment state of the downstream module. This leads to uncertain establishment state and logic locking errors in the downstream module when there are fluctuations in process, voltage, and temperature (especially in low-temperature slow establishment conditions). At the same time, it solves the problem that the traditional fixed timing method is difficult to accurately quantify the shutdown time, resulting in invalid static power leakage or system failure due to premature shutdown.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0006] A start-point control method based on twin logic is applied to a power management system comprising a logic generation circuit, a latch matrix, and a timing circuit. The start-point control method includes:

[0007] After the chip is powered on, the logic generation circuit starts working and establishes the logic state of the target logic channel;

[0008] The state establishment status of the target logic channel is monitored by a twin logic channel located inside the logic generation circuit; wherein the twin logic channel and the target logic channel have a twin-matched circuit structure.

[0009] Once the twin logic channel determines that the logic state of the target logic channel has been established, the twin logic channel outputs a start-point latch signal.

[0010] A start control signal is generated based on the start latch signal to trigger the timing circuit to start timing;

[0011] The timing circuit sequentially generates a logic lock signal and a shutdown signal; wherein, the logic lock signal is used to lock the logic state established by the target logic channel to the latch matrix, and the shutdown signal is used to turn off the logic generation circuit to reduce power consumption.

[0012] Furthermore, the target logic channel is a fuse logic channel, and the logic generation circuit is a fuse logic generation circuit; the logic locking signal is used to lock the established fuse logic state to the subsequent circuit.

[0013] Furthermore, the step of generating a start control signal based on the start latch signal includes: receiving the start latch signal through a start latch circuit; the start latch circuit latches the state of the start latch signal and generates a continuously valid start control signal; in order to avoid the timing circuit being repeatedly triggered or the logic generation circuit being repeatedly started due to the failure of the start latch signal after the shutdown signal turns off the logic generation circuit.

[0014] Furthermore, the logic generation circuit includes a self-starting bias circuit, and the fuse logic channel and the twin logic channel connected in parallel; the self-starting bias circuit is used to establish a bias voltage after the chip is powered on, and to provide bias current to the fuse logic channel and the twin logic channel through a current mirror structure.

[0015] Furthermore, the fuse logic channel includes a fuse element; the transistor size and structure inside the twin logic channel are completely identical to those of the fuse logic channel, the only difference being that the twin logic channel uses a reference resistor instead of the fuse element; the resistance value of the reference resistor is greater than the preset logic toggle threshold resistance value, so that after the self-starting bias circuit establishes the bias, the twin logic channel will necessarily output a high-level start-up latch signal, so as to physically represent that the logic states of the unblown fuse or the blown fuse in the fuse logic channel have been established.

[0016] Furthermore, the self-starting bias circuit includes a first PMOS transistor group and a first NMOS transistor group, the fuse logic channel includes a second PMOS transistor group and a second NMOS transistor group, and the twin logic channel includes a third PMOS transistor group and a third NMOS transistor group; the gate nodes of the first PMOS transistor group and the first NMOS transistor group serve as bias voltage output terminals, and are respectively connected to the gates of the second PMOS transistor group and the third PMOS transistor group, as well as the gates of the second NMOS transistor group and the third NMOS transistor group; thus, the self-starting bias circuit, the fuse logic channel, and the twin logic channel constitute a cascode current mirror structure.

[0017] Optionally, the starting point latch circuit includes a driving circuit and an RS flip-flop; the starting point latch signal is level-shaped by the driving circuit and then connected to the set terminal of the RS flip-flop; when the output level of the driving circuit goes high, the RS flip-flop pulls the output starting point control signal high and holds it.

[0018] Optionally, the starting point latch circuit includes a driving circuit and a D flip-flop; the starting point latch signal is level-shaped by the driving circuit and then connected to the clock terminal of the D flip-flop, and the input terminal of the D flip-flop is connected to a continuous high-level signal; when the output level of the driving circuit goes high, the D flip-flop pulls the output starting point control signal high and holds it.

[0019] The aforementioned twin logic-based start-up control method can also be used to import the working state control of other light decision-making modules or weak functional units after the chip is powered on; by configuring the twin logic channel that matches the module or unit for detection, the timing start point is adaptively generated step by step and the corresponding module is shut down, thus getting rid of the constraints of enable signal and power establishment.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] (1) The invention realizes the replacement of "power-driven timing" with "logic-driven timing", which fundamentally avoids timing races. The invention abandons the traditional power-sensing front end and innovatively introduces a twin logic channel with a twin-matching structure with the target logic inside the logic generation circuit. It directly extracts the state signal from the internal logic at the physical level. Only when the real logic is fully established will the twin logic channel output the starting point latch signal to trigger the timing circuit, so that the timing starting point is strongly bound to the actual physical state of the module. No matter how fast or slow the establishment is, it can ensure the absolute correctness of the locking timing and eliminate the risk of locking errors caused by timing races.

[0022] (2) Since the twin logic channel and the target logic channel (such as the fuse logic channel) share the bias voltage to form a Cascode current mirror, and the internal transistor size and structure are completely identical (only the reference resistor is used to replace the fuse), the twin logic can perfectly track the characteristic drift of the target logic under different process corners, voltages and temperatures. When the module build-up slows down under extreme conditions (such as low temperature), the twin start signal will be automatically delayed. Adaptive delay can be achieved without the need for the huge additional RC timing hardware overhead of existing technologies, which greatly simplifies the design and improves reliability.

[0023] (3) After ensuring the logic is established, the timing circuit generates a logic lock signal and a shutdown signal sequentially. The shutdown signal is generated on the premise that the logic is absolutely ready, so there will be no problem of incomplete logic establishment due to premature shutdown. Once the module is shut down and the power supply current drops to an extremely low level, the start-up latch circuit can firmly latch the valid state, avoiding the problem of loss of timing start signal and repeated triggering of timing circuit due to module power failure, and realizing accurate and safe zero-additional power consumption management.

[0024] (4) The “twin state perception + step-by-step interlocking shutdown” concept of the present invention is not only applicable to fuse logic scenarios, but can also be widely extended to the queuing control of other light decision modules or weak functional units after the chip is powered on. By adaptively shutting down idle modules step by step, the chip can get rid of the constraints of enable signals and comprehensively improve the overall energy efficiency ratio of the chip.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a timing diagram of the power-on stage of a chip using fuse trimming technology in the prior art;

[0028] Figure 2 This is a schematic diagram of a power management circuit module that uses a domino effect multi-level interlocking processing method in the prior art;

[0029] Figure 3 A schematic diagram of the overall architecture module of the starting point control method based on twin logic provided in the embodiments of the present invention;

[0030] Figure 4 This is a schematic diagram of the modular structure for signal interaction between the logic generation circuit and the timing circuit in an embodiment of the present invention;

[0031] Figure 5 The internal circuit schematic diagram of the logic generation circuit (including self-starting bias circuit, target logic channel and twin logic channel) provided in the embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of the starting point latch circuit implemented using an RS flip-flop in an embodiment of the present invention;

[0033] Figure 7 This is another schematic diagram of the starting point latch circuit implemented using a D flip-flop in an embodiment of the present invention;

[0034] Figure 8 The power-on simulation timing diagram for logic lock-in based on power sensing front-end control in the prior art under normal temperature conditions;

[0035] Figure 9 The simulation timing diagram shows the locking anomaly caused by the logic locking based on power sensing front-end control in the prior art under extreme low temperature conditions.

[0036] Figure 10 for Figure 9 Under the abnormal operating conditions shown, the simulation comparison timing diagram of the actual logic establishment delay is observed after decoupling the shutdown signal.

[0037] Figure 11 The timing diagram for power-on normal locking and shutdown simulation of the starting control method based on twin logic provided in the embodiments of the present invention under normal temperature (fast setup) conditions;

[0038] Figure 12 The simulation timing diagram of the adaptive delay locking and shutdown of the twin logic-based start-up control method provided in the embodiment of the present invention under the extreme conditions of low temperature (slow setup). Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0040] The core idea of ​​this invention is to provide a start-point control method based on twin logic. Building upon traditional domino effect multi-level interlocking technology (patent CN120223040B, a domino-style multi-level interlocking power management circuit), this invention abandons the traditional power sensing front-end (i.e., the method of generating timing signals based on power supply voltage thresholds) and innovatively introduces a monitoring and start-point control mechanism based on twin logic channels. Its core concept is to achieve logic-driven timing rather than power-driven timing; that is, subsequent timing and locking signals are only generated after the logic state of the target logic channel is fully established. Since the control start-point is directly related to the actual physical logic establishment state, rather than simply a power supply threshold or external enable signal, this invention is not only more adaptable but also fundamentally avoids timing race problems.

[0041] like Figure 3 and Figure 4 As shown, the twin logic-based starting point control method of this invention is applied to a power management system that includes a logic generation circuit, a latch matrix, and a timing circuit. In a specific embodiment, the target logic channel is a fuse logic channel, and correspondingly, the logic generation circuit is a fuse logic generation circuit.

[0042] After the chip is powered on, the logic generation circuit starts working and establishes the logic state of the target logic channel (such as a fuse logic channel). At this time, a twin logic channel located inside the logic generation circuit synchronously monitors the establishment of the target logic channel's state. The twin logic channel and the target logic channel have a twin-matched circuit structure. When the twin logic channel determines that the logic state of the target logic channel has been established, the twin logic channel outputs a start-point latch signal.

[0043] To prevent signal loss after the power management module shuts down the logic generation circuit, this invention further includes a start-point latch circuit. The start-point latch circuit receives the aforementioned start-point latch signal, latches its state, and then generates a continuously valid start-point control signal to trigger the timing circuit to start timing. Upon receiving the continuously valid start-point control signal, the timing circuit sequentially generates a logic lock signal and a shutdown signal. The logic lock signal securely and accurately locks the completed logic state of the target logic channel (such as the adjustment control word) to the subsequent latch matrix; while the shutdown signal, after locking, shuts off the power supply to the logic generation circuit to adaptively reduce additional power consumption.

[0044] I. Structure and Principle of Logic Generation Circuits

[0045] like Figure 5 As shown, the logic generation circuit (i.e., fuse logic generation circuit) in this embodiment consists of a self-starting bias circuit, a fuse logic channel serving as the target logic channel, and twin logic channels connected in parallel. The circuit includes components such as N-type transistors, P-type transistors, resistors, and fuses (polysilicon fuses are used in this example).

[0046] according to Figure 5 The circuit structure includes a self-starting bias circuit used to establish a bias voltage after the chip is powered on, and to provide bias current to the fuse logic channel and the twin logic channel through a current mirror structure.

[0047] Specifically, the self-starting bias circuit includes a first PMOS transistor group (MP1, MP2) and a first NMOS transistor group (MN1, MN2); the fuse logic channel includes a second PMOS transistor group (MP3, MP4) and a second NMOS transistor group (MN3, MN4); and the twin logic channel includes a third PMOS transistor group (MP5, MP6) and a third NMOS transistor group (MN5, MN6).

[0048] The gate nodes (Vbias1, Vbias2, Vbias3, Vbias4) of the first PMOS transistor group (MP1, MP2) and the first NMOS transistor group (MN1, MN2) serve as bias voltage output terminals, which are respectively connected to the gates of the second PMOS / NMOS transistor group (MP3, MP4, MN3, MN4) and the third PMOS / NMOS transistor group (MP5, MP6, MN5, MN6). Through this connection method, the self-starting bias circuit, the fuse logic channel, and the twin logic channel together constitute a cascode current mirror structure. Since each bias circuit can be used with multiple logic channels, this structure ensures that the current characteristics of the twin logic channel are highly consistent with those of the fuse logic channel.

[0049] In practical circuits, the current flowing through the fuse can be adjusted by configuring the bias voltage and the dimensions of the N and P type transistors. Since polysilicon fuses exhibit resistive characteristics, adjusting the current flowing through the fuse adjusts the voltage required to establish the fuse logic. In practical applications, the output node typically uses a driver circuit to increase the output amplitude to high / low levels. Typically, an unblowed fuse has a resistance below 100 ohms, while a blown fuse can have a resistance exceeding 10 kΩ, or even at the Mohm level. Through adjustment, the inverted level of the established fuse logic can correspond to a fuse resistance value at the kΩ level. For example, with a design threshold of 3 kΩ: when the fuse resistance is greater than 3 kΩ (i.e., blown, reaching above 10 kΩ), the output establishes a high level; when the fuse resistance is less than 3 kΩ (i.e., not blown, less than 100 ohms), the output establishes a low level.

[0050] The twin logic channel of this invention fully utilizes this characteristic. The transistor size and structure inside the twin logic channel are exactly the same as those of the fuse logic channel, the only difference being that the twin logic channel uses a reference resistor R1 instead of a fuse element. The value of R1 is set at the kohm level and is greater than a preset logic toggle threshold (for example, if the threshold is 3 kohm, then the value of R1 is 5 kohm).

[0051] When the chip powers on, since the twin logic channel and the fuse logic channel have completely identical structures, and R1 (5kohm) is necessarily greater than the toggle threshold (3kohm), the twin logic channel will inevitably output a high-level start-up latch signal after the bias circuit is established. When this start-up latch signal is high, it physically reflects that the twin fuse logic channel (regardless of whether its internal fuse is at a low level that has not been blown or at a high level that has been blown) has been established.

[0052] II. Specific Implementation of the Starting Point Latch Circuit

[0053] As mentioned earlier, since this invention prioritizes power consumption control, when the logic is locked to the subsequent circuit, the timing circuit generates a shutdown signal to turn off the logic generation circuit. At this time, the start-up latch signal output by the twin logic channel will become invalid. To prevent the timing circuit from repeatedly timing and the logic generation circuit from repeatedly starting, this state must be latched by the start-up latch circuit. The start-up latch circuit only needs to implement the function of this idea (the idea of ​​the start-up latch circuit is that once the start-up latch signal goes high, the signal level is shaped by the drive circuit of the latch circuit), without needing a complex circuit, but not limited to a specific circuit. This invention provides two implementations of the start-up latch circuit:

[0054] 1. Implement using the start-point latch of an RS flip-flop.

[0055] like Figure 6 As shown, the start-point latch circuit includes a driver circuit and an RS flip-flop. After the chip is powered on, the gate voltages of transistors MP7 and MN7 float in an intermediate state at the front end of the driver circuit (such as a cascaded inverter or a SMIT flip-flop), forming a TIELOW logic that keeps node NET0 continuously low. When the start-point latch signal output from the twin logic channel goes high, it is level-shaped by the driver circuit, which then outputs a high level to the set (SET, S) terminal of the RS flip-flop. The RS flip-flop responds immediately, pulling up and holding the start-point control signal at its output (Q), thus starting the subsequent timing circuit. Regardless of whether the output signal of the subsequent driver circuit jitters or the logic generation circuit is turned off, the pull-up of this start-point control signal is irreversible, thereby greatly improving the reliability of the timing.

[0056] 2. Implemented using the start-point latch of a D flip-flop.

[0057] like Figure 7 The diagram illustrates another form of the latch circuit. After the chip powers on, the gate voltages of MP8 and MN8 float in an intermediate state, forming the TIEHIGH logic, which keeps node NET1 continuously high and connected to the input (D) of the D flip-flop. When the start-up latch signal goes high, after being shaped by the driver circuit, it is used as a clock signal connected to the clock input of the D flip-flop. When the rising edge of the clock signal arrives, the D flip-flop latches the high level at its input, thereby pulling up and maintaining the start-up control signal at its output (Q). This starts the subsequent timing circuit, and regardless of whether the output signal of the driver circuit jitters, the start-up control remains continuously triggered at a high level, thus achieving both anti-jitter and continuous high-level triggering.

[0058] III. Timing Comparison of Linkage Control

[0059] To verify the reliability of this invention, we used XFAB 350nm CMOS process for comparative simulation (using two fuse channels):

[0060] 1. Deficiencies of existing technology (power drive timing):

[0061] like Figure 8 (Room temperature) and Figure 9 As shown in (low temperature), traditional technology (patent CN120223040B, a domino-style multi-level interlocking power management circuit) relies on the power supply sensing start signal.

[0062] like Figure 8As shown, "Power Supply" refers to the chip's power-on power supply; "Power Sensing Start Signal" is the timing start signal, enabling the lock-on timing and disabling the timing signal; "Lock Signal" is the fuse logic lock signal, used to lock the logic generated by the fuse module; "Fuse Establishment Logic" indicates the logic established by the fuse module that is not locked by the lock signal; the simulation shows that this signal has been established at 150µs; "Locked Logic" represents the fuse logic locked by the lock signal and transmitted to the subsequent circuit; "Supply Current" only represents the supply current of the fuse logic generation circuit during the simulation, which includes the bias circuit current when the fuse logic is established. The simulation shows that under normal circumstances, after the chip is powered on, the power supply senses and generates the start signal, sequentially generating the lock signal and the shutdown signal. The lock signal locks and outputs the fuse-established logic (high level), generating the locked logic (high level); the shutdown signal implements power management, causing the supply current to adaptively decrease, thus shutting down additional power consumption without the need for enable control.

[0063] like Figure 9 As shown, under low temperature conditions, after the chip is powered on, the power supply sense generates a start signal, and in time, it generates a lock signal and a turn-off signal. However, due to the low temperature environment, the fuse module establishment time is delayed. The simulation shows that the fuse establishment logic does not become high level, and the lock signal cannot lock the output high level, that is, the lock logic fails. This simulation case only discusses the temperature dimension. The deviation of the process corner also has similar potential anomalies.

[0064] Figure 9 Because the fuse module's setup time is delayed and the turn-off signal generation time is advanced, the fuse is turned off prematurely before the setup logic is generated. To observe the relationship between fuse setup and turn-off, the turn-off signal is disconnected from the fuse logic generation circuit to observe the signal state. Figure 10 As shown in the diagram, in this case, the fuse establishment logic is later than the lock and turn-off signals. Simulations show that the fuse logic establishment time is approximately 1.6ms, while under normal temperature conditions, it takes about 150us. Because this scheme relies on the power sensing front end to independently generate the timing start signal, but ignores the establishment status of the downstream module, in certain specific situations, even if the power supply is stable, the fuse logic may not be fully established, causing the timing lock signal to trigger prematurely, leading to a logic lock error. The diagram shows that the locked logic output is low, resulting in a lock failure.

[0065] 2. Advantages of this invention (logic-driven timing):

[0066] We simulated a twin logic-based starting point control method employing the concept of this patent, see [link / details]. Figure 11As shown. Under normal temperature conditions, "Power Supply" refers to the chip's power-on power supply, "Twin Logic Start Signal" is the timing start signal based on this patent, which enables and disables the timing lock, and "Lock Signal" is the fuse logic lock signal used to lock the logic generated by the fuse module. "Fuse Establishment Logic" refers to the logic established by the fuse module that is not locked by the lock signal, and "Locked Logic" refers to the fuse logic that is locked by the lock signal and transmitted to the subsequent circuit. "Power Supply Current" only represents the power supply current of the fuse logic generation circuit during simulation, which includes the bias circuit current when the fuse logic is established. Simulation shows that under normal conditions, after the chip is powered on, the twin logic detects and generates the start signal. Due to the twin relationship, the fuse establishment logic is already established at this time. Simulation shows that at 150us, the fuse establishment logic and the twin logic start signal synchronously become high level. The starting signal generates a lock signal and a turn-off signal sequentially. The lock signal locks and outputs the logic (high level) established by the fuse, generating the locked logic (high level). The turn-off signal realizes power consumption management, turns off the fuse logic generation module, and makes the power supply current adaptively decrease, so that additional power consumption can be turned off without enabling control.

[0067] Even at low temperatures, the concept of this patent can still guarantee the correctness of the logic locking, such as... Figure 12 As shown in the simulation, after the chip is powered on, both the fuse establishment logic and the twin logic start signal are established slowly, and synchronously complete the establishment and become high level around 1.6ms. The twin logic detects and generates the start signal, and the twin relationship ensures that the fuse establishment logic has been established. The start signal generates a lock signal and a turn-off signal sequentially. The lock signal locks the fuse establishment logic (high level) and outputs it, generating the locked logic (high level); the turn-off signal realizes power consumption management, turns off the fuse logic generation module, and makes the supply current adaptively decrease, thus shutting down additional power consumption without enabling control.

[0068] This invention does not overturn traditional design concepts and does not conflict with the existing chip's working mode of locking fuse logic after power-on. This invention aims to optimize the locking timing and method while retaining power management functions. It adopts a twin logic detection method to optimize and supplement the locking timing, abandoning the control role of power sensing signals. Through twin logic, it performs adaptive sequential control at the internal dimension of the module, which is a supplementary power-on timing management method. This approach binds the timing start point to the actual state of the module, realizing "logic-driven timing" rather than "power-driven timing". While ensuring adaptive power consumption reduction, it fundamentally avoids timing race problems and has positive practical significance and application value.

[0069] IV. Universality and Extensibility

[0070] The twin logic-based start-point control method described in this invention is not limited to the needs of fuse logic generation and locking, but is also applicable to other scenarios that require power consumption management and strict timing control.

[0071] For example, after a chip powers on, certain lightweight decision-making modules or weakly functional units need to queue up to import their operating states, and they do not need to participate in the main signal chain after the chip is operating normally. Using the control concept of this invention, detection can be performed by configuring twin logic channels that match these modules. Upon power-on, timing start points are adaptively generated step-by-step through twin detection, and these modules are shut down step-by-step after the state import is complete. This approach breaks free from the rigid constraints of traditional enable signals and power-up times, ensuring strict sequential relationships and avoiding errors in importing operating states caused by timing conflicts. It possesses extremely high scalability and practical significance.

[0072] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A starting point control method based on twin logic, applied to a power management system including a logic generation circuit, a latch matrix, and a timing circuit, characterized in that, The starting point control method includes: After the chip is powered on, the logic generation circuit starts working and establishes the logic state of the target logic channel; The state establishment status of the target logic channel is monitored by a twin logic channel located inside the logic generation circuit; wherein the twin logic channel and the target logic channel have a twin-matched circuit structure. Once the twin logic channel determines that the logic state of the target logic channel has been established, the twin logic channel outputs a start-point latch signal. A start control signal is generated based on the start latch signal to trigger the timing circuit to start timing; The timing circuit sequentially generates a logic lock signal and a shutdown signal; wherein, the logic lock signal is used to lock the logic state established by the target logic channel to the latch matrix, and the shutdown signal is used to turn off the logic generation circuit to reduce power consumption; The target logic channel is a fuse logic channel, and the logic generation circuit is a fuse logic generation circuit; the logic locking signal is used to lock the established fuse logic state to the subsequent circuit. The step of generating a start control signal based on the start latch signal includes: receiving the start latch signal through a start latch circuit; the start latch circuit latches the state of the start latch signal and generates a continuously valid start control signal; The logic generation circuit includes a self-starting bias circuit, and the fuse logic channel and the twin logic channel connected in parallel; the self-starting bias circuit is used to establish a bias voltage after the chip is powered on, and to provide bias current to the fuse logic channel and the twin logic channel through a current mirror structure; The fuse logic channel includes a fuse element; the transistor size and structure inside the twin logic channel are completely identical to those of the fuse logic channel, the only difference being that the twin logic channel uses a reference resistor instead of the fuse element; the resistance value of the reference resistor is greater than the preset logic toggle threshold resistance value, so that after the self-starting bias circuit establishes the bias, the twin logic channel outputs a high-level start-up latch signal, so as to physically represent that the logic states of the unblown fuse or the blown fuse in the fuse logic channel have been established.

2. The starting point control method based on twin logic according to claim 1, characterized in that, The self-starting bias circuit includes a first PMOS transistor group and a first NMOS transistor group; the fuse logic channel includes a second PMOS transistor group and a second NMOS transistor group; and the twin logic channel includes a third PMOS transistor group and a third NMOS transistor group. The gate nodes of the first PMOS transistor group and the first NMOS transistor group serve as bias voltage output terminals, respectively connected to the gates of the second PMOS transistor group and the third PMOS transistor group, as well as the gates of the second NMOS transistor group and the third NMOS transistor group. This allows the self-starting bias circuit, the fuse logic channel, and the twin logic channel to form a cascode current mirror structure.

3. The starting point control method based on twin logic according to claim 1, characterized in that, The starting point latch circuit includes a driving circuit and an RS flip-flop; the starting point latch signal is level-shaped by the driving circuit and then connected to the set terminal of the RS flip-flop; when the output level of the driving circuit goes high, the RS flip-flop pulls the output starting point control signal high and holds it.

4. The starting point control method based on twin logic according to claim 1, characterized in that, The starting point latch circuit includes a driving circuit and a D flip-flop; the starting point latch signal is level-shaped by the driving circuit and then connected to the clock terminal of the D flip-flop, and the input terminal of the D flip-flop is connected to a continuous high-level signal. When the output level of the driving circuit goes high, the D flip-flop pulls the output start-up control signal high and holds it.

5. The starting point control method based on twin logic according to claim 1, characterized in that, The starting point control method is also used to import the working status control of other light decision-making modules or weak functional units after the chip is powered on; by configuring the twin logic channel that matches the module or unit for detection, the timing starting point is adaptively generated step by step and the corresponding module is shut down, thus getting rid of the constraints of enable signal and power establishment.

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