Semiconductor structure, method of manufacturing the same and electronic device

Abstract

This application discloses a semiconductor structure, its fabrication method, and an electronic device, relating to the field of semiconductor technology. The semiconductor structure includes: a substrate; a first stacked structure including a first doped layer, a first semiconductor layer, and a second doped layer disposed along a first direction; a second stacked structure located on the first stacked structure and spaced apart from it, including a third doped layer, a second semiconductor layer, and a fourth doped layer disposed along the first direction; a first conductive structure located in and in contact with the third doped layer, extending at least through the first semiconductor layer along the first direction, and spaced apart from the second semiconductor layer; a first dielectric layer surrounding the first conductive structure; a second conductive structure surrounding the sidewalls of the second stacked structure; and a second dielectric layer located between the second conductive structure and the second stacked structure, in contact with both the second conductive structure and the second stacked structure. The structure is simple and has high integration.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and an electronic device. Background Technology

[0002] As semiconductor structure dimensions shrink, the manufacturing process becomes increasingly complex, and the power performance area (PPA) gain gradually decreases. Therefore, improving the integration density of semiconductor structures without changing performance has become an urgent problem to solve. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, a method for fabricating the same, and an electronic device, which can optimize device performance and improve device integration.

[0004] A semiconductor structure, comprising:

[0005] Base;

[0006] The first stacked structure includes a first doped layer, a first semiconductor layer and a second doped layer stacked along a first direction perpendicular to the substrate, wherein the first doped layer and the second doped layer have the same conductivity type.

[0007] The second stacked structure is located on the first stacked structure, corresponding to and spaced apart from the first stacked structure, and includes a third doped layer, a second semiconductor layer and a fourth doped layer stacked along the first direction, wherein the third doped layer and the fourth doped layer have the same conductivity type.

[0008] A first conductive structure is located in and in contact with the third doped layer, and extends at least through the first semiconductor layer along the first direction; the first conductive structure is spaced apart from the second semiconductor layer.

[0009] A first dielectric layer is disposed around the first conductive structure and is located between the first stacked structure and the first conductive structure;

[0010] A second conductive structure surrounds the sidewall of the second stacked structure;

[0011] The second dielectric layer is located between the second conductive structure and the second stacked structure, and is in contact with both the second conductive structure and the second stacked structure.

[0012] In one embodiment, the first conductive structure extends into the substrate along the first direction.

[0013] In one embodiment, the distance between the top surface of the first conductive structure away from the substrate and the substrate is less than the distance between the top surface of the third doped layer away from the substrate and the substrate.

[0014] In one embodiment, the first doped layer and the third doped layer have opposite conductivity types.

[0015] In one embodiment, the semiconductor structure includes a plurality of second stacked structures arranged in an array, and the second conductive structures of the plurality of second stacked structures are connected to form an integral structure.

[0016] In one embodiment, the semiconductor structure includes a plurality of first stacked structures arranged in an array, the semiconductor structure further including:

[0017] The first line extends along a second direction parallel to the substrate and contacts the first doped layer in each of the first stacked structures arranged along the second direction.

[0018] In one embodiment, the first bit line includes:

[0019] A first metal silicide layer extends along the second direction and is in contact with the first doped layer;

[0020] The first conductive layer is located on the side of the first metal silicide layer away from the first doped layer, and is in contact with the first metal silicide layer, and extends along the second direction.

[0021] In one embodiment, the semiconductor structure further includes:

[0022] The first word line extends along a third direction parallel to the substrate and contacts the second doped layer in each of the first stacked structures arranged along the third direction.

[0023] Wherein, the third direction intersects with the second direction, the first conductive structure passes through the first word line, and the first dielectric layer is disposed between the first word line and the first conductive structure; the first word line and the second conductive structure are spaced apart.

[0024] In one embodiment, the first doped layers of each of the first stacked structures arranged along the second direction are connected to form an integral structure.

[0025] In one embodiment, the semiconductor structure further includes:

[0026] The second bit line is disposed corresponding to the second stacked structure, located on the top surface of the fourth doped layer away from the substrate, and spaced apart from the second conductive structure.

[0027] In one embodiment, the orthographic projection of the second stacked structure onto the substrate coincides with the orthographic projection of the first stacked structure onto the substrate.

[0028] A method for fabricating a semiconductor structure, comprising:

[0029] Provide a base;

[0030] A first stacked structure is formed on the substrate, the first stacked structure including a first doped layer, a first semiconductor layer and a second doped layer stacked along a first direction perpendicular to the substrate;

[0031] A second stacked structure, a first dielectric layer, and a first conductive structure are formed on the first stacked structure. The second stacked structure corresponds to and is spaced apart from the first stacked structure. The second stacked structure includes a third doped layer, a second semiconductor layer, and a fourth doped layer stacked along the first direction. The first conductive structure is located in and in contact with the third doped layer, and extends at least through the first semiconductor layer along the first direction. The first conductive structure is spaced apart from the second semiconductor layer. The first dielectric layer surrounds the first conductive structure and is located between the first stacked structure and the first conductive structure.

[0032] A second dielectric layer and a second conductive structure are formed around the sidewall of the second stacked structure, respectively; the second dielectric layer is located between the second conductive structure and the second stacked structure, and is in contact with the second conductive structure and the second stacked structure, respectively;

[0033] The first doped layer and the second doped layer have the same conductivity type, and the third doped layer and the fourth doped layer have the same conductivity type.

[0034] In one embodiment, forming the first laminated structure on the substrate includes:

[0035] A first stacked material is formed on the surface of the substrate, the first stacked material comprising a first doped material layer, a first semiconductor material layer and a second doped material layer stacked along the first direction;

[0036] A first isolation groove is formed in the first laminated material to obtain a first initial laminated structure; the first isolation groove penetrates the first laminated material along the first direction and extends along a second direction parallel to the substrate;

[0037] A second isolation trench is formed in the first initial stacked structure to obtain the first stacked structure; the second isolation trench extends at least to the top surface of the first doped material layer along the first direction and extends along a third direction parallel to the substrate, the third direction intersecting the second direction.

[0038] In one embodiment, forming a first isolation groove in the first laminated material to obtain the first initial laminated structure includes:

[0039] A first initial isolation trench is formed in the first stacked material; the first initial isolation trench extends along the first direction into the first doped material layer and extends along the second direction;

[0040] A first isolation layer is formed on the sidewall of the first initial isolation groove;

[0041] The first doped material layer at the bottom of the first initial isolation trench is removed to form the first isolation trench.

[0042] In one embodiment, after forming the first isolation trench, the method for fabricating the semiconductor structure further includes:

[0043] A first bit line is formed at the bottom of the first isolation layer, the first bit line is in contact with the first doped material layer, and extends along the second direction.

[0044] In one embodiment, the material of the first doped layer includes doped polysilicon, and forming a first line at the bottom of the first isolation layer includes:

[0045] The surface of the first doped material layer exposed by the first isolation trench is subjected to metal silicide treatment to form a first metal silicide layer that extends along the second direction and contacts the first doped material layer.

[0046] A first conductive layer is formed at the bottom of the first isolation layer, the first conductive layer is in contact with the first metal silicide layer, and extends along the second direction;

[0047] The first bit line includes the first metal silicide layer and the first conductive layer.

[0048] In one embodiment, after forming the first stacked structure on the substrate, the method for fabricating the semiconductor structure further includes:

[0049] A first word line is formed on the first stacked structure. The first word line extends along a third direction parallel to the substrate and contacts the second doped layer in each of the first stacked structures arranged along the third direction.

[0050] In one embodiment, the material of the second doped layer includes doped polysilicon, and the formation of the first word line on the first stacked structure includes:

[0051] The surface of the second doped layer away from the substrate is subjected to metal silicide treatment to form a second metal silicide layer corresponding to the first stacked structure;

[0052] A second conductive layer is formed on the surface of the second metal silicide layer, the second conductive layer is in contact with the second metal silicide layer, and extends along the third direction;

[0053] The first word line includes a second metal silicide layer and a second conductive layer, and the first word line is connected to a plurality of first stacked structures arranged along the third direction.

[0054] In one embodiment, forming a second stacked structure, a first dielectric layer, and a first conductive structure on the first stacked structure includes:

[0055] A third doped material layer is formed on the first stacked structure, and the third doped material layer is spaced apart from the first stacked structure.

[0056] A first via is formed in the third doped material layer, extending at least through the first semiconductor layer along the first direction;

[0057] The first dielectric layer is formed on the inner wall of the first through hole, and the top surface of the first dielectric layer away from the substrate is lower than the top surface of the third doped material layer away from the substrate;

[0058] A first conductive structure is formed in the first through hole, and the top surface of the first conductive structure is lower than the top surface of the third doped material layer away from the substrate;

[0059] A second isolation layer is formed on the top surface of the first conductive structure, and the second isolation layer fills the first through hole;

[0060] A second semiconductor material layer and a fourth doped material layer are sequentially formed on the top surface of the third doped material layer to obtain a second stacked material including the third doped material layer, the second semiconductor material layer and the fourth doped material layer;

[0061] The second laminated material is patterned to obtain a second laminated structure located on the first laminated structure.

[0062] In one embodiment, the formation of a second dielectric layer and a second conductive structure surrounding the second stacked structure on the sidewalls of the second stacked structure includes:

[0063] A second dielectric layer is formed around the sidewall of the second stacked structure, and the second dielectric layers adjacent to the sidewall of the second stacked structure are spaced apart.

[0064] A second conductive structure is formed on the sidewall of the second dielectric layer away from the second stacked structure, and the second conductive structure surrounds the second stacked structure.

[0065] In one embodiment, a second conductive structure is formed on the sidewall of the second dielectric layer away from the second stacked structure, including:

[0066] The second conductive structure is formed on the periphery of the second stacked structure, and the second conductive structures of adjacent second stacked structures are connected to form an integral structure.

[0067] In one embodiment, the method for fabricating the semiconductor structure further includes:

[0068] A second bit line is formed on the top surface of the fourth doped layer. The second bit line is disposed corresponding to the second stacked structure and spaced apart from the second conductive structure.

[0069] An electronic device, or comprising the above-described semiconductor structure; and / or comprising a semiconductor structure made using the above-described semiconductor structure fabrication method.

[0070] In the aforementioned semiconductor structure, the second stacked structure is located on the first stacked structure, corresponding to and spaced apart from the first stacked structure. The first conductive structure is in contact with the third doped layer and extends at least through the first semiconductor layer along the first direction. The first dielectric layer is located between the first stacked structure and the first conductive structure. The second conductive structure surrounds the sidewall of the second stacked structure. The second dielectric layer is located between the second conductive structure and the second stacked structure, and is in contact with the second conductive structure and the second stacked structure respectively. The second stacked structure is located on the first stacked structure, which reduces the area of ​​the semiconductor structure, improves the integration of the semiconductor structure, simplifies the structure of the semiconductor structure, and reduces the manufacturing difficulty of the semiconductor structure.

[0071] In the above-mentioned method for fabricating a semiconductor structure, the second stacked structure is located on the first stacked structure, corresponding to and spaced apart from the first stacked structure. The first conductive structure is in contact with the third doped layer and extends at least through the first semiconductor layer along the first direction. The first dielectric layer is located between the first stacked structure and the first conductive structure. The second conductive structure surrounds the sidewall of the second stacked structure. The second dielectric layer is located between the second conductive structure and the second stacked structure, and is in contact with the second conductive structure and the second stacked structure respectively. This simplifies the fabrication process. The second stacked structure is located on the first stacked structure, which reduces the area of ​​the semiconductor structure and improves the integration density of the semiconductor structure. Attached Figure Description

[0072] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method in some embodiments;

[0074] Figure 2 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate in some embodiments;

[0075] Figure 3 for Figure 2 A schematic cross-sectional view of the corresponding semiconductor structure along a third direction perpendicular to the substrate.

[0076] Figure 4 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the formation of the first initial isolation trench in some embodiments;

[0077] Figure 5 for Figure 3 A schematic cross-sectional view of the corresponding semiconductor structure along a third direction perpendicular to the substrate.

[0078] Figure 6 This is a schematic cross-sectional view of the semiconductor structure along the second direction perpendicular to the substrate after the formation of the first isolation trench in some embodiments;

[0079] Figure 7 for Figure 6 A schematic cross-sectional view of the corresponding semiconductor structure along a third direction perpendicular to the substrate.

[0080] Figure 8 This is a schematic cross-sectional view of the semiconductor structure along the second direction perpendicular to the substrate after the first line is formed in some embodiments;

[0081] Figure 9 for Figure 6 A schematic cross-sectional view of the corresponding semiconductor structure along a third direction perpendicular to the substrate.

[0082] Figure 10 This is a schematic cross-sectional view of the semiconductor structure along the second direction perpendicular to the substrate after the second isolation trench is formed in some embodiments;

[0083] Figure 11 for Figure 10A schematic cross-sectional view of the semiconductor structure along a third direction perpendicular to the substrate in some corresponding embodiments;

[0084] Figure 12 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the first word line is formed in some embodiments;

[0085] Figure 13 for Figure 12 A schematic cross-sectional view of the semiconductor structure along a third direction perpendicular to the substrate in some corresponding embodiments;

[0086] Figure 14 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the formation of the second isolation layer in some embodiments;

[0087] Figure 15 for Figure 14 A schematic cross-sectional view of the semiconductor structure along a third direction perpendicular to the substrate in some corresponding embodiments;

[0088] Figure 16 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the second stacked structure is formed in some embodiments;

[0089] Figure 17 for Figure 16 A schematic cross-sectional view of the semiconductor structure along a third direction perpendicular to the substrate in some corresponding embodiments;

[0090] Figure 18 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the second bit line is formed in some embodiments;

[0091] Figure 19 for Figure 18 A schematic cross-sectional view of the semiconductor structure along a third direction perpendicular to the substrate in some corresponding embodiments.

[0092] Explanation of reference numerals in the attached figures:

[0093] Substrate 102; First stacked structure 104; First doped layer 106; First semiconductor layer 108; Second doped layer 110; Second stacked structure 112; Third doped layer 114; Second semiconductor layer 116; Fourth doped layer 118; First conductive structure 120; First dielectric layer 122; Second dielectric layer 124; Second conductive structure 126; First bit line 128; First word line 130; Second bit line 132; First doped material layer 202; First semiconductor material layer 204; Second doped material layer 206; First stacked material 208; First isolation trench 210 First initial stacked structure 212; first isolation layer 214; first initial isolation trench 302; first metal silicide layer 304; first conductive layer 306; second metal silicide material layer 308; first filler material layer 310; second isolation trench 312; second metal silicide layer 314; second filler material layer 316; second conductive layer 318; second isolation layer 320; third filler material layer 402; third doped material layer 404; first sub-conductive structure 406; second sub-conductive structure 408; third metal silicide layer 410; fourth filler material layer 412. Detailed Implementation

[0094] To facilitate understanding of the embodiments of this disclosure, a more complete description of the embodiments of this disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of this disclosure are shown in the drawings. However, the embodiments of this disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0095] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this disclosure belong. The terminology used herein in the description of embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0096] In the description of the embodiments of this disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0097] It is understood that the terms "first," "second," etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first stacked structure may be referred to as a second stacked structure, and similarly, a second stacked structure may be referred to as a first stacked structure. Both the first and second stacked structures are stacked structures, but they are not the same stacked structure.

[0098] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. In the description of this disclosure, "several" means at least one, such as one, two, etc., unless otherwise expressly specified.

[0099] As used herein, the terms “substrate” and “base” refer to and include the base material or structure of the transistor material described in this disclosure. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate comprising layers of semiconductor material.

[0100] In this disclosure, the upper surface of the substrate is the surface on which the substrate forms a stacked structure. The lower surface of the substrate is positioned opposite to the upper surface. The upper and lower surfaces of other structures or layers are relative to the upper surface of the substrate. For structures or layers located within the substrate, the surface parallel to the substrate surface is designated as the upper surface / top surface / top / top face, and the surface away from the upper surface is designated as the lower surface / bottom surface / bottom / bottom face. Conversely, for structures or layers on the substrate, the surface closer to the upper surface is designated as the lower surface / bottom surface / bottom / bottom face, and the surface away from the upper surface is designated as the upper surface / top surface / top / top face. For structures, trenches, holes, or layers formed in a semiconductor structure in a direction away from the substrate surface, the surface perpendicular to the substrate is designated as the sidewall of the structure, trench, hole, or layer, and the point where the trench or hole stops penetrating is designated as the bottom of the trench or hole. For trenches or holes formed in other directions in a semiconductor structure, the point where the trench or hole stops penetrating is designated as the bottom of the trench or hole, and the surface in the penetrating direction of the trench or hole is designated as the sidewall of the trench or hole.

[0101] Figure 1 This is a schematic flowchart of the semiconductor structure fabrication method in some embodiments. Figure 2This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate in some embodiments. Figure 3 for Figure 2 A schematic cross-sectional view of the corresponding semiconductor structure along a third direction perpendicular to the substrate. For example, the X direction can be... Figure 2 The first direction shown is perpendicular to the base 102, and the Y direction can be... Figure 2 The second direction shown is in a plane parallel to the base 102, and the Z direction can be... Figure 2 The third direction shown is in a plane parallel to the base 102, and the second direction intersects with the third direction.

[0102] like Figure 1 , Figure 2 , Figure 3 As shown, in this embodiment, a method for fabricating a semiconductor structure is provided, comprising:

[0103] S102 provides the substrate.

[0104] A substrate 102 is provided. In some embodiments, the constituent material of the substrate 102 includes undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. As an example, in this embodiment, the constituent material of the substrate 102 is selected as silicon-on-insulator (SOI).

[0105] S104, forming a first layered structure on the substrate.

[0106] A first stacked structure 104 is formed on a substrate 102. The first stacked structure 104 includes a first doped layer 106, a first semiconductor layer 108, and a second doped layer 110 stacked along a first direction X perpendicular to the substrate 102. The stacking direction is from the substrate 102 toward a direction away from the substrate 102. The surfaces of the first semiconductor layer 108 that are disposed opposite to each other in the first direction X are in contact with the top surface of the first doped layer 106 away from the substrate 102 and the bottom surface of the second doped layer 110 near the substrate 102, respectively.

[0107] The first doped layer 106 and the second doped layer 110 are disposed at intervals, and the first doped layer 106 and the second doped layer 110 have the same conductivity type, including N-type and P-type. The first stacked structure is used to form a first transistor, in which one of the first doped layer 106 and the second doped layer 110 serves as the source and the other as the drain, and the first semiconductor layer 108 serves as the channel region located between the first doped layer 106 and the second doped layer 110 in the first transistor.

[0108] S106, a second stacked structure, a first dielectric layer and a first conductive structure are formed on the first stacked structure.

[0109] First, a second stacked structure 112, a first dielectric layer 122, and a first conductive structure 120 are formed on the first stacked structure 104. The second stacked structure 112 corresponds to and is spaced apart from the first stacked structure 104. The second stacked structure 112 includes a third doped layer 114, a second semiconductor layer 116, and a fourth doped layer 118 stacked along the first direction X. The third doped layer 114 and the fourth doped layer 118 have the same conductivity type. The second stacked structure is used to form a second transistor. In the second transistor, one of the third doped layer 114 and the fourth doped layer 118 serves as the source and the other serves as the drain. The second semiconductor layer 116 serves as the channel region located between the third doped layer 114 and the fourth doped layer 118 in the second transistor. The first conductive structure 120 is located in and in contact with the third doped layer 114, and extends at least through the first semiconductor layer 108 along the first direction X. The first conductive structure 120 and the second semiconductor layer 116 are spaced apart. The first dielectric layer 122 is disposed around the first conductive structure 120 and is located between the first stacked structure 104 and the first conductive structure 120. The first conductive structure 120 and the first dielectric layer 122 serve as the gate and gate dielectric layers of a first transistor including the first doped layer 106 and the second doped layer 110, respectively.

[0110] S108, a second dielectric layer and a second conductive structure of the second stacked structure are formed on the sidewalls of the second stacked structure, respectively.

[0111] A second dielectric layer 124 and a second conductive structure 126 are sequentially formed on the sidewall of the second stacked structure 112. The second dielectric layer 124 is located between the second conductive structure 126 and the second stacked structure 112, and is in contact with the second conductive structure 126 and the second stacked structure 112, respectively. The second conductive structure 126 and the second dielectric layer 124 serve as the gate and gate dielectric layers of the second transistor, which includes a third doped layer 114 and a fourth doped layer 118, respectively.

[0112] In the above-described method for fabricating a semiconductor structure, the second stacked structure 112 is located on the first stacked structure 104, corresponding to and spaced apart from the first stacked structure 104. The first conductive structure 120 is in contact with the third doped layer 114 and extends at least through the first semiconductor layer 108 along the first direction X. The first dielectric layer 122 is located between the first stacked structure 104 and the first conductive structure 120. The second conductive structure 126 surrounds the sidewall of the second stacked structure 112. The second dielectric layer 124 is located between the second conductive structure 126 and the second stacked structure 112, and is in contact with the second conductive structure 126 and the second stacked structure 112 respectively. This simplifies the fabrication process. The second stacked structure 112 is located on the first stacked structure 104, which reduces the area of ​​the semiconductor structure and improves the integration density of the semiconductor structure.

[0113] Figure 4 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the formation of the first initial isolation trench in some embodiments. Figure 5 for Figure 3 A schematic cross-sectional view of the corresponding semiconductor structure along a third direction perpendicular to the substrate. Figure 6 This is a schematic cross-sectional view of the semiconductor structure along the second direction perpendicular to the substrate after the formation of the first isolation trench in some embodiments. Figure 7 for Figure 6 A schematic cross-sectional view of the corresponding semiconductor structure along a third direction perpendicular to the substrate. Figure 8 This is a schematic cross-sectional view of the semiconductor structure along the second direction perpendicular to the substrate after the first line is formed in some embodiments. Figure 9 for Figure 6 A schematic cross-sectional view of the corresponding semiconductor structure along a third direction perpendicular to the substrate. Figure 10 This is a schematic cross-sectional view of the semiconductor structure along the second direction perpendicular to the substrate after the second isolation trench is formed in some embodiments. Figure 11 for Figure 10 In some corresponding embodiments, the semiconductor structure is shown in a cross-sectional view along a third direction perpendicular to the substrate, such as... Figures 4-11 As shown, in one embodiment, forming a first stacked structure 104 on the substrate 102 includes steps S202-S206.

[0114] S202, a first stacked material is formed on the surface of the substrate, the first stacked material comprising a first doped material layer, a first semiconductor material layer and a second doped material layer stacked along the first direction.

[0115] Specifically, a film-forming process, such as epitaxy or chemical vapor deposition, is used to sequentially form a first doped material layer 202, a first semiconductor material layer 204, and a second doped material layer 206 on a substrate 102. The first doped material layer 202, the first semiconductor material layer 204, and the second doped material layer 206 are arranged sequentially in the first direction X away from the substrate 102 to form a first stacked material 208. The first doped material layer 202 and the second doped material layer 206 have the same conductivity type.

[0116] S204, a first isolation groove is formed in the first laminated material to obtain a first initial laminated structure.

[0117] like Figures 4-7 As shown, the first stacked material 208 is patterned to form a first isolation trench 210 in the first stacked material 208, resulting in a first initial stacked structure 212 composed of a remaining first doped material layer 202, a remaining first semiconductor material layer 204, and a remaining second doped material layer 206. The first isolation trench 210 penetrates the first stacked material 208 along the first direction X and extends along the second direction Y parallel to the substrate 102. The first initial stacked structure 212 extends along the second direction Y and is spaced along the third direction Z. In the third direction Z, the first isolation trench 210 is located on one side of the first initial stacked structure 212.

[0118] like Figures 4-7 As shown, in one embodiment, forming a first isolation groove 210 in the first laminated material 208 to obtain the first initial laminated structure 212 includes steps S302-S306.

[0119] S302, forming a first initial isolation groove in the first laminated material.

[0120] like Figure 4 , Figure 5 As shown, the first stacked material 208 is patterned to form a first initial isolation trench 302 in the first stacked material. The first initial isolation trench 302 extends along the first direction X into the first doped material layer 202 and extends along the second direction Y. The bottom of the first initial isolation trench 302 exposes the first doped material layer 202. The first initial isolation trench 302 defines the position and shape of the first bit line.

[0121] It is understood that extending the first initial isolation trench 302 along the first direction X into the first doped material layer 202 can avoid the influence of the residue of the first semiconductor material layer 204 on the semiconductor structure manufacturing process. The solution of this application also applies when the first initial isolation trench 302 extends along the first direction X to penetrate the first semiconductor material layer 204. When there are multiple first initial isolation trenches 302, the multiple first initial isolation trenches 302 are arranged at intervals along the third direction Z.

[0122] S304, a first isolation layer is formed on the sidewall of the first initial isolation groove.

[0123] like Figure 6 , Figure 7 As shown, a deposition process, such as atomic layer deposition, is used to form a first isolation material on the inner wall of the first initial isolation trench 302. Then, an etching process, such as dry etching, is used to remove the first isolation material at the bottom of the first initial isolation trench 302, forming a first isolation layer 214 composed of the first isolation material on the sidewall of the first initial isolation trench 302.

[0124] S306, Remove the first doped material layer at the bottom of the first initial isolation trench to form the first isolation trench.

[0125] like Figure 6 , Figure 7 As shown, based on the first initial isolation trench 302, the first doped material layer 202 at the bottom of the first initial isolation trench is etched away, and the first doped material layer 202 at the bottom of the first isolation layer 214 is etched away laterally to form the first isolation trench 210.

[0126] like Figure 8 , Figure 9 As shown, in one embodiment, after forming the first isolation trench 210, the method for fabricating the semiconductor structure further includes: forming a first bit line 128 at the bottom of the first isolation layer 214, the first bit line 128 contacting the first doped material layer 202 and extending along the second direction Y, and in the third direction Z, two adjacent first doped material layers 202 contacting different first bit lines 128.

[0127] like Figure 8 , Figure 9 As shown, in one embodiment, the material of the first doped layer 106 includes doped polysilicon, and a first line 128 is formed at the bottom of the first isolation layer 214, including steps S402-S404.

[0128] S402, the surface of the first doped material layer 202 exposed by the first isolation trench 210 is subjected to metal silicide treatment to form a first metal silicide layer 304 extending along the second direction Y and in contact with the first doped material layer 202.

[0129] S404, a first conductive layer 306 is formed at the bottom of the first isolation layer 214. The first conductive layer 306 is in contact with the first metal silicide layer 304 and extends along the second direction Y.

[0130] Steps S402 and S404 specifically involve: First, metallizing the first doped material layer 202 exposed in the first isolation trench 210 to form a first metal silicide layer 304 extending along the second direction Y and contacting the first doped material layer 202. Second, forming a first conductive layer 306 on one side of the first metal silicide layer 304, with the first conductive layer 306 in contact with the first metal silicide layer 304. The first bit line 128 includes the first metal silicide layer 304 and the first conductive layer 306. This arrangement improves the contact between the first conductive layer 306 and the first doped material layer 202 while reducing the resistance of the first bit line 128.

[0131] It is understandable that the step of forming the first metal silicide layer 304 can be omitted, and the first conductive layer 306 can be used as the first first line 128. In this case, the first conductive layer 306 is in contact with the first doped material layer 202, extends along the second direction Y, and is spaced apart along the third direction Z. The resistance of the first line 128 is low, and the step of forming the first line 128 is simple. Alternatively, the step of forming the first conductive layer 306 can be omitted, and the first metal silicide layer 304 can be used as the first line 128 to improve the contact between the first line 128 and the first doped material layer 202. The step of forming the first line 128 is also simple.

[0132] It is understood that when the material of the second doped layer 206 includes doped polysilicon, in step S402, the surface of the second doped material layer 206 away from the substrate 102 is subjected to metal silicide treatment to form a second metal silicide material layer 308. The second metal silicide material layer 308 extends along the second direction Y and is spaced along the third direction Z, corresponding to and contacting the second doped material layer 206.

[0133] S206, a second isolation groove is formed in the first initial stacked structure to obtain the first stacked structure.

[0134] like Figure 10 , Figure 11As shown, firstly, a deposition process, such as chemical vapor deposition or atomic layer deposition, is used to form a first filling material layer 310 in the first isolation trench 210. The first filling material layer 310 fills the first isolation trench 210 and extends to cover the first initial stacked structure 212 (the second metal silicide material layer 308). The first filling material layer 310 on top of the first initial stacked structure 212 can protect the second metal silicide material layer 308 located on the second doped layer 110. Secondly, the first initial stacked structure 212 is patterned to form a second isolation trench 312 in the first initial stacked structure 212, forming a first stacked structure 104. The second isolation trench 312 extends at least along the first direction X to the top surface of the first doped material layer 202 away from the substrate 102, and extends along a third direction Z parallel to the substrate 102. The third direction Z intersects the second direction Y, and the second isolation trenches 312 are spaced apart along the second direction Y.

[0135] Figure 2 , Figure 3 In the semiconductor structure shown, the second isolation trench 312 penetrates the first doped material layer 202 along the first direction X. At this time, a plurality of first stacked structures 104 are arranged in an array, and the second doped layers 110 in each first stacked structure 104 are spaced apart. Figure 10 , Figure 11 In the illustrated semiconductor structure, the second isolation trench 312 extends along the first direction X to the top surface of the first doped material layer 202. At this time, multiple first stacked structures 104 are spaced apart along the third direction Z, and the first doped layers 106 of the multiple first stacked structures 104 arranged in a row along the second direction Y are connected to form an integral structure. It can be understood that the second isolation trench 312 can also extend along the first direction X into the first doped material layer 106. In this case, multiple first stacked structures 104 are spaced apart along the third direction Z, and the first doped layers 106 of the multiple first stacked structures 104 arranged in a row along the second direction Y are connected to form an integral structure.

[0136] It is understandable that during the formation of the second isolation trench 312, the second isolation trench 312 penetrates the second metal silicide material layer 308 located on top of the second doped material layer 110 along the first direction X, forming a plurality of second metal silicide layers 314. The plurality of second metal silicide layers 314 are arranged at intervals and are respectively corresponding to a plurality of first stacked structures 104. At this time, in the second direction Y, the second metal silicide layers 314 corresponding to two adjacent first stacked structures 104 are arranged at intervals.

[0137] Figure 12 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the first word line is formed in some embodiments. Figure 13 for Figure 12 In some corresponding embodiments, the semiconductor structure is shown in a cross-sectional view along a third direction perpendicular to the substrate, such as... Figure 12 , Figure 13 As shown, in one embodiment, after forming a first stacked structure 104 on the substrate 102, the method for fabricating the semiconductor structure further includes: forming a first word line 130 on the first stacked structure 104. The first word line 130 extends along a third direction Z parallel to the substrate 102 and contacts a second doped layer 110 in a plurality of first stacked structures 104 arranged along the third direction Z. It is understood that the plurality of first word lines 130 are spaced apart along a second direction Y, and the first word lines 130 are connected to the plurality of first stacked structures 104 arranged in a row along the third direction Z.

[0138] like Figure 12 , Figure 13 As shown, in one embodiment, the material of the second doped layer 110 includes doped polysilicon, and the formation of the first word line 130 on the first stacked structure 104 includes steps S502-S504.

[0139] S502, the surface of the second doped layer 110 away from the substrate 102 is subjected to metal silicide treatment to form a second metal silicide layer 314 corresponding to the first stacked structure 104.

[0140] S504, a second conductive layer 318 is formed on the surface of the second metal silicide layer 314, the second conductive layer 318 is in contact with the second metal silicide layer 314 and extends along the third direction Z.

[0141] Steps S502-S504 specifically involve the following steps: First, after forming the first stacked structure 104, a second filler material layer 316 is formed in the second isolation trench 312. A chemical mechanical polishing process is then used to remove the first filler material layer 310 and the second filler material layer 316 that extend and cover the top surface of the first stacked structure 104 or the top surface of the second metal silicide material layer 308, thereby exposing the second doped layer 110 or the second metal silicide material layer 308 serving as the second metal silicide layer 314. With the second doped layer 110 exposed, the surface of the second doped layer 110 away from the substrate 102 is subjected to metal silicide treatment to form a second metal silicide layer 314 corresponding to the first stacked structure 104. Multiple second metal silicide layers 314 are arranged in an array. With the second metal silicide layer 314 exposed, the step of forming the second metal silicide layer 314 can be omitted. The second metal silicide layer 314 can be formed by first forming the second metal silicide material layer 308, eliminating the need for a separate step of forming the second metal silicide layer 314. This simplifies the process and makes it easier to operate. Next, a second conductive layer 318 is formed on the surface of the second metal silicide layer 314 away from the substrate 102. The second conductive layer 318 contacts the second metal silicide layer 314 and extends along the third direction Z, spaced apart along the second direction Y. The second conductive layer 318 is connected to a plurality of first stacked structures 104 arranged in a row along the third direction Z. The first letter 130 includes the second metal silicide layer 314 and the second conductive layer 318.

[0142] Figure 14 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the formation of the second isolation layer in some embodiments. Figure 15 for Figure 14 In some corresponding embodiments, the semiconductor structure is shown in a cross-sectional view along a third direction perpendicular to the substrate. Figure 16 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the second stacked structure has been formed in some embodiments. Figure 17 for Figure 16 In some corresponding embodiments, a schematic cross-sectional view of the semiconductor structure along a third direction perpendicular to the substrate is shown; such as... Figures 14-17 As shown, in one embodiment, forming a second stacked structure, a first dielectric layer, and a first conductive structure on the first stacked structure 104 includes steps S602-S614.

[0143] S602, a third doped material layer is formed on the first stacked structure, wherein the third doped material layer is spaced apart from the first stacked structure.

[0144] like Figure 14 , Figure 15As shown, firstly, a third filling material layer 402 is formed on the first word line 130. The third filling material layer 402 extends and covers the second filling material layer 316. The orthogonal projection of the third filling material layer 402 on the substrate 102 coincides with the surface of the substrate 102. The device structures located on both sides of the third filling material layer 402 in the first direction X are separated by the third filling material layer 402. Secondly, a third doped material layer 404 is formed on the first stacked structure 104. The third doped material layer 404 is spaced apart from the first stacked structure 104.

[0145] S604, a first via is formed in the third doped material layer, extending at least through the first semiconductor layer along the first direction.

[0146] Specifically, firstly, a mask material is formed on the top surface of the third doped material layer 404 away from the substrate 102. For example, the mask material includes an oxide layer and a silicon nitride layer formed sequentially along a direction away from the substrate 102. Secondly, a first via is formed in the third doped material layer 404, extending at least through the first semiconductor layer 108 along the first direction X. The first via penetrates the mask material. The first via and the first stacked structure 104 are respectively correspondingly disposed. The first via can extend through the first stacked structure 104 into the substrate 102. The greater the depth of the first via in the first direction X, the greater the capacitance in the semiconductor structure.

[0147] S606, the first dielectric layer is formed on the inner wall of the first through hole, and the top surface of the first dielectric layer away from the substrate is lower than the top surface of the third doped material layer away from the substrate.

[0148] Specifically, firstly, a first dielectric material layer and a first conductive material are sequentially formed on the inner wall of the first via, with the first conductive material filling the first via. Then, a chemical mechanical polishing process is used to remove the first dielectric material layer and the first conductive material filling the opening portion of the first via, exposing a third doped material layer on the sidewall of the first via. This forms a first dielectric layer 122 composed of the remaining first dielectric material layer and a first sub-conductive structure 406 composed of the remaining first conductive material. The top surface of the first dielectric layer 122 away from the substrate 102 is lower than the top surface of the third doped material layer 404 away from the substrate 102, and the top surface of the first dielectric layer 122 away from the substrate 102 is higher than the lower surface of the third doped material layer 404 near the substrate 102. Further, the top surface of the first sub-conductive structure 406 away from the substrate 102 is flush with the top surface of the first dielectric layer 122 away from the substrate 102. For example, the first dielectric layer 122 includes an oxide layer and a high-k gate dielectric layer sequentially formed on the sidewall of the first via.

[0149] S608, a first conductive structure is formed in the first through hole, the top surface of the first conductive structure being lower than the top surface of the third doped material layer away from the substrate.

[0150] Specifically, a second sub-conductive structure 408 is formed in the first through hole, which is in contact with the first sub-conductive structure 406. The top surface of the second sub-conductive structure 408 is lower than the top surface of the third doped material layer away from the substrate. The second sub-conductive structure is electrically connected to the third doped material layer 404. The first conductive structure 120 includes the first sub-conductive structure 406 and the second sub-conductive structure 408.

[0151] In some embodiments, before forming a second sub-conductive structure 408 in contact with the first sub-conductive structure 406 in the first via, the method for fabricating the semiconductor structure further includes: performing metal silicide treatment on the surface of the third doped material layer 404 exposed in the first via to form a third metal silicide material; after forming the second sub-conductive structure 408 in contact with the first sub-conductive structure 406 in the first via, the method for fabricating the semiconductor structure further includes: removing the third metal silicide material exposed at the opening of the first via, and retaining the third metal silicide material located between the second sub-conductive structure 408 and the third doped material layer 404 as a third metal silicide layer 410; wherein the second sub-conductive structure 408 and the third doped material layer 404 are electrically connected through the third metal silicide layer 410, and the contact resistance between the second sub-conductive structure 408 and the third doped material layer 404 can be reduced by providing the third metal silicide layer 410.

[0152] S610, a second isolation layer is formed on the top surface of the first conductive structure, and the second isolation layer fills the first through hole.

[0153] Specifically, firstly, a second isolation layer 320 is formed by filling the first via with the second isolation layer 320. The second isolation layer 320 completely fills the first via and is respectively disposed correspondingly to the first via. The second isolation layer 320 is in contact with the top surface of the first conductive structure 120 away from the substrate 102 (the top surface of the third metal silicide layer 410 away from the substrate 102). The top surface of the second isolation layer 320 away from the substrate 102 is higher than the top surface of the third doped material layer 404. Secondly, the mask material on the top surface of the third doped material layer 404 is removed.

[0154] S612, a second semiconductor material layer and a fourth doped material layer are sequentially formed on the top surface of the third doped material layer to obtain a second stacked material including the third doped material layer, the second semiconductor material layer and the fourth doped material layer.

[0155] Specifically, a deposition process is used to sequentially form a second semiconductor material layer and a fourth doped material layer on the top surface of the third doped material layer 404. In the first direction X, the opposite surfaces of the second semiconductor material layer are in contact with the third doped material layer 404 and the fourth doped material layer, respectively. The third doped material layer 404 and the fourth doped material layer have the same conductivity type, resulting in a second stacked material including the third doped material layer 404, the second semiconductor material layer and the fourth doped material layer.

[0156] S614, the second laminated material is patterned to obtain a second laminated structure located on the first laminated structure.

[0157] like Figure 16 , Figure 17 As shown, the second stacked material is patterned to form a second stacked structure 112 located on the first stacked structure 104. The second stacked structure includes a fourth doped layer 118 composed of the remaining fourth doped material layer, a second semiconductor layer 116 composed of the remaining second semiconductor material layer, and a third doped layer 114 composed of the remaining third doped material layer 404. Furthermore, the orthographic projection of the second stacked structure 112 on the substrate 102 coincides with the orthographic projection of the first stacked structure 104 on the substrate 102, allowing the same mask to be used to form the first stacked structure 104 and the second stacked structure 112, thus reducing fabrication costs.

[0158] Figure 18 This is a schematic cross-sectional view of the semiconductor structure along a second direction perpendicular to the substrate after the second bit line is formed in some embodiments. Figure 19 for Figure 18 In some corresponding embodiments, the semiconductor structure is shown in a cross-sectional view along a third direction perpendicular to the substrate, such as... Figure 18 , Figure 19 As shown, in one embodiment, a second dielectric layer 124 and a second conductive structure 126 are formed around the sidewall of the second stacked structure 112, including steps S702-S704.

[0159] S702, a second dielectric layer 124 is formed around the sidewall of the second stacked structure 112, and the second dielectric layers 124 adjacent to the sidewall of the second stacked structure 112 are spaced apart.

[0160] S704, a second conductive structure 126 is formed on the sidewall of the second dielectric layer 124 away from the second stacked structure 112, and the second conductive structure 126 surrounds the second stacked structure 112.

[0161] For example, the second dielectric layer 124 includes an oxide layer and a high-k gate dielectric layer formed sequentially in a direction away from the second stacked structure 112.

[0162] In one embodiment, a second conductive structure 126 is formed on the sidewall of the second dielectric layer 124 away from the second stacked structure 112, including: forming the second conductive structure 126 on the periphery of the second stacked structure 112, and connecting the second conductive structures 126 of adjacent second stacked structures 112 to form an integral structure, so as to facilitate the lead-out of the second conductive structure 126.

[0163] In another embodiment, a second conductive structure 126 is formed on the sidewall of the second dielectric layer 124 away from the second stacked structure 112, including: forming the second conductive structure 126 on the periphery of the second stacked structure 112, with the second conductive structures 126 corresponding to adjacent second stacked structures 112 spaced apart, thereby reducing the fabrication cost of the semiconductor structure.

[0164] like Figure 18 , Figure 19 As shown, in one embodiment, the method for fabricating the semiconductor structure further includes:

[0165] A second bit line 132 is formed on the top surface of the fourth doped layer 118. The second bit line 132 is correspondingly disposed with respect to the second stacked structure 112 and spaced apart from the second conductive structure 126. For example, the second bit line 132 is disposed in the fourth filler material layer 412, that is, the second bit line 132 and the second conductive structure 126 are separated by the fourth filler material layer 412.

[0166] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0167] This disclosure provides a semiconductor structure, the parts of which are the same as or corresponding to those in the embodiments of the above-described semiconductor structure preparation method, and will not be repeated below. Figure 2 , Figure 3 , Figure 18 , Figure 19 As shown, in this embodiment, a semiconductor structure is provided, including: a substrate 102, a first stacked structure 104, a second stacked structure 112, a first conductive structure 120, a first dielectric layer 122, a second conductive structure 126, and a second dielectric layer 124.

[0168] The first stacked structure 104 includes a first doped layer 106, a first semiconductor layer 108, and a second doped layer 110 stacked along a first direction X perpendicular to the substrate 102, wherein the first doped layer 106 and the second doped layer 110 have the same conductivity type. A second stacked structure 112 is located on the first stacked structure 104, corresponding to and spaced apart from the first stacked structure 104, and includes a third doped layer 114, a second semiconductor layer 116, and a fourth doped layer 118 stacked along the first direction X, wherein the third doped layer 114 and the fourth doped layer 118 have the same conductivity type. A first conductive structure 120 is located in and in contact with the third doped layer 114, and extends at least through the first semiconductor layer 108 along the first direction X, wherein the first conductive structure 120 is spaced apart from the second semiconductor layer 116. A first dielectric layer 122 is disposed around the first conductive structure 120, located between the first stacked structure 104 and the first conductive structure 120. The second conductive structure 126 surrounds the sidewall of the second stacked structure 112; the second dielectric layer 124 is located between the second conductive structure 126 and the second stacked structure 112, and is in contact with the second conductive structure 126 and the second stacked structure 112 respectively.

[0169] In the above semiconductor structure, the second stacked structure 112 is located on the first stacked structure 104, corresponding to and spaced apart from the first stacked structure 104. The first conductive structure 120 is in contact with the third doped layer 114 and extends at least through the first semiconductor layer 108 along the first direction X. The first dielectric layer 122 is located between the first stacked structure 104 and the first conductive structure 120. The second conductive structure 126 surrounds the sidewall of the second stacked structure 112. The second dielectric layer 124 is located between the second conductive structure 126 and the second stacked structure 112, and is in contact with the second conductive structure 126 and the second stacked structure 112 respectively. The second stacked structure 112 is located on the first stacked structure 104. This reduces the area of ​​the semiconductor structure, improves the integration of the semiconductor structure, simplifies the structure of the semiconductor structure, and reduces the manufacturing difficulty of the semiconductor structure.

[0170] In one embodiment, the first conductive structure 120 extends into the substrate 102 along the first direction X, thereby increasing the capacitance in the semiconductor structure.

[0171] In one embodiment, the distance between the top surface of the first conductive structure 120 away from the substrate 102 and the substrate 102 is less than the distance between the top surface of the third doped layer 114 away from the substrate 102 and the substrate 102.

[0172] In one embodiment, the first doped layer 106 and the third doped layer 114 have opposite conductivity types.

[0173] In one embodiment, the semiconductor structure includes a plurality of second stacked structures 112 arranged in an array, and the second conductive structures 126 of the plurality of second stacked structures 112 are connected to form an integral structure to facilitate the lead-out of the second conductive structures 126.

[0174] In other embodiments, the semiconductor structure includes a plurality of second stacked structures 112 arranged in an array, with the plurality of second stacked structures 112 spaced apart from the second conductive structure 126, thereby reducing the fabrication cost of the semiconductor structure.

[0175] In one embodiment, the semiconductor structure includes a plurality of first stacked structures 104 arranged in an array, and the semiconductor structure further includes a first line 128 extending along a second direction Y parallel to the substrate 102 and contacting the first doped layer 106 in each of the first stacked structures 104 arranged along the second direction Y.

[0176] In one embodiment, the first bit line 128 includes: a first metal silicide layer 304 and a first conductive layer 306; the first metal silicide layer 304 extends along the second direction Y and contacts the first doped layer 106; the first conductive layer 306 is located on the side of the first metal silicide layer 304 away from the first doped layer 106, contacts the first metal silicide layer 304, and extends along the second direction Y.

[0177] In one embodiment, the semiconductor structure further includes: a first word line 130 extending along a third direction Z parallel to the substrate 102 and contacting the second doped layer 110 in each of the first stacked structures 104 arranged along the third direction Z;

[0178] Wherein, the third direction Z intersects with the second direction Y, the first conductive structure 120 passes through the first word line 130, and the first dielectric layer 122 is disposed between the first word line 130 and the first conductive structure 120; the first word line 130 and the second conductive structure 126 are disposed at intervals.

[0179] In one embodiment, the first word line 130 includes: a plurality of second metal silicide layers 314 and a second conductive layer 318; the second metal silicide layers 314 are arranged in an array, and the plurality of second metal silicide layers 314 and the plurality of first stacked structures 104 are respectively disposed correspondingly, and the second metal silicide layers 314 are in contact with the corresponding second doped layer 110; the second conductive layer 318 is located on the side of the second metal silicide layer 314 away from the second doped layer 110, and is in contact with the second doped layer 110, and extends along the third direction Z, and is arranged at intervals along the second direction Y, and the second conductive layer 318 is connected to the plurality of first stacked structures 104 arranged in a row along the third direction Z.

[0180] In one embodiment, the first doped layers 106 of each of the first stacked structures 104 arranged along the second direction Y are connected to form an integral structure.

[0181] In one embodiment, the semiconductor structure further includes a second bit line 132, which is disposed corresponding to the second stacked structure 112, located on the top surface of the fourth doped layer 118 away from the substrate 102, and spaced apart from the second conductive structure 126.

[0182] In one embodiment, the orthographic projection of the second stacked structure 112 on the substrate 102 coincides with the orthographic projection of the first stacked structure 104 on the substrate 102, thereby reducing the area of ​​the semiconductor structure and improving the integration of the semiconductor structure.

[0183] In some embodiments, the semiconductor structure includes a memory, which includes: read word lines, read bit lines, write word lines, write bit lines, and memory cells; the memory cells include read transistors and write transistors; the read transistors include a memory gate, a first source-drain, and a second source-drain; the write transistors include a control gate, a third source-drain, and a fourth source-drain; wherein the memory gate is connected to the third source-drain, the first source-drain is connected to the read bit line, the second source-drain is connected to the read word line, the control gate is connected to the write word line, and the fourth source-drain is connected to the write bit line.

[0184] It is understandable that the first word line 130 corresponds to the read word line, the first bit line 128 corresponds to the read bit line, the second conductive structure 126 corresponds to the write word line, and the second bit line 132 corresponds to the write bit line. The capacitor formed by the first word line 130 (electrode), the first dielectric layer 122, and the first conductive structure 120 (electrode) corresponds to the memory structure. The portion of the first conductive structure 120 corresponding to the first semiconductor layer 108 corresponds to the memory gate. One of the first doped layer 106 and the second doped layer 110 corresponds to the first source / drain, and the other corresponds to the second source / drain. The portion of the second conductive structure 126 corresponding to the second semiconductor layer 116 corresponds to the control gate. One of the third doped layer 114 and the fourth doped layer 118 corresponds to the third source / drain, and the other corresponds to the fourth source / drain.

[0185] In one embodiment, the projection of the write transistor in the memory onto the read transistor covers the read transistor.

[0186] This disclosure also provides an electronic device including the above-described semiconductor structure; and / or including a semiconductor structure fabricated using the above-described semiconductor structure fabrication method. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. The embodiments of this application do not impose special limitations on the specific form of the above-described electronic device.

[0187] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0188] The above-described embodiments are merely illustrative of several implementation methods of the present disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present disclosure embodiments, and these modifications and improvements all fall within the protection scope of the present disclosure embodiments.

Claims

1. A semiconductor structure, characterized in that, include: Base; The first stacked structure includes a first doped layer, a first semiconductor layer and a second doped layer stacked along a first direction perpendicular to the substrate, wherein the first doped layer and the second doped layer have the same conductivity type. The second stacked structure is located on the first stacked structure, corresponding to and spaced apart from the first stacked structure, and includes a third doped layer, a second semiconductor layer and a fourth doped layer stacked along the first direction, wherein the third doped layer and the fourth doped layer have the same conductivity type. A first conductive structure is located in and in contact with the third doped layer, and extends at least through the first semiconductor layer along the first direction; the first conductive structure is spaced apart from the second semiconductor layer. A first dielectric layer is disposed around the first conductive structure and is located between the first stacked structure and the first conductive structure; A second conductive structure surrounds the sidewall of the second stacked structure; The second dielectric layer is located between the second conductive structure and the second stacked structure, and is in contact with both the second conductive structure and the second stacked structure.

2. The semiconductor structure according to claim 1, characterized in that, The first conductive structure extends into the substrate along the first direction.

3. The semiconductor structure according to claim 1, characterized in that, The distance between the top surface of the first conductive structure away from the substrate and the substrate is less than the distance between the top surface of the third doped layer away from the substrate and the substrate.

4. The semiconductor structure according to claim 1, characterized in that, The first doped layer and the third doped layer have opposite conductivity types.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes multiple second stacked structures arranged in an array, and the second conductive structures of the multiple second stacked structures are connected to form an integral structure.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes multiple first stacked structures arranged in an array, and the semiconductor structure further includes: The first line extends along a second direction parallel to the substrate and contacts the first doped layer in each of the first stacked structures arranged along the second direction.

7. The semiconductor structure according to claim 6, characterized in that, The first bit line includes: A first metal silicide layer extends along the second direction and is in contact with the first doped layer; The first conductive layer is located on the side of the first metal silicide layer away from the first doped layer, and is in contact with the first metal silicide layer, and extends along the second direction.

8. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: The first word line extends along a third direction parallel to the substrate and contacts the second doped layer in each of the first stacked structures arranged along the third direction. Wherein, the third direction intersects with the second direction, the first conductive structure passes through the first word line, and the first dielectric layer is disposed between the first word line and the first conductive structure; the first word line and the second conductive structure are spaced apart.

9. The semiconductor structure according to claim 6, characterized in that, The first doped layers of each of the first stacked structures arranged along the second direction are connected to form an integral structure.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The second bit line is disposed corresponding to the second stacked structure, located on the top surface of the fourth doped layer away from the substrate, and spaced apart from the second conductive structure.

11. The semiconductor structure according to claim 1, characterized in that, The orthographic projection of the second stacked structure onto the substrate coincides with the orthographic projection of the first stacked structure onto the substrate.

12. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A first stacked structure is formed on the substrate, the first stacked structure including a first doped layer, a first semiconductor layer and a second doped layer stacked along a first direction perpendicular to the substrate; A second stacked structure, a first dielectric layer, and a first conductive structure are formed on the first stacked structure. The second stacked structure corresponds to and is spaced apart from the first stacked structure. The second stacked structure includes a third doped layer, a second semiconductor layer, and a fourth doped layer stacked along the first direction. The first conductive structure is located in and in contact with the third doped layer, and extends at least through the first semiconductor layer along the first direction. The first conductive structure is spaced apart from the second semiconductor layer. The first dielectric layer surrounds the first conductive structure and is located between the first stacked structure and the first conductive structure. A second dielectric layer and a second conductive structure are respectively formed around the sidewalls of the second stacked structure; The second dielectric layer is located between the second conductive structure and the second stacked structure, and is in contact with both the second conductive structure and the second stacked structure. The first doped layer and the second doped layer have the same conductivity type, and the third doped layer and the fourth doped layer have the same conductivity type.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The formation of the first laminated structure on the substrate includes: A first stacked material is formed on the surface of the substrate, the first stacked material comprising a first doped material layer, a first semiconductor material layer and a second doped material layer stacked along the first direction; A first isolation groove is formed in the first laminated material to obtain a first initial laminated structure; the first isolation groove penetrates the first laminated material along the first direction and extends along a second direction parallel to the substrate; A second isolation trench is formed in the first initial stacked structure to obtain the first stacked structure; the second isolation trench extends at least to the top surface of the first doped material layer along the first direction and extends along a third direction parallel to the substrate, the third direction intersecting the second direction.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The step of forming a first isolation groove in the first laminated material to obtain the first initial laminated structure includes: A first initial isolation trench is formed in the first stacked material; the first initial isolation trench extends along the first direction into the first doped material layer and extends along the second direction; A first isolation layer is formed on the sidewall of the first initial isolation groove; The first doped material layer at the bottom of the first initial isolation trench is removed to form the first isolation trench.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The method for fabricating a semiconductor structure after forming the first isolation trench further includes: A first bit line is formed at the bottom of the first isolation layer, the first bit line is in contact with the first doped material layer, and extends along the second direction.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The material of the first doped layer includes doped polysilicon, and the formation of the first line at the bottom of the first isolation layer includes: The surface of the first doped material layer exposed by the first isolation trench is subjected to metal silicide treatment to form a first metal silicide layer that extends along the second direction and contacts the first doped material layer. A first conductive layer is formed at the bottom of the first isolation layer, the first conductive layer is in contact with the first metal silicide layer, and extends along the second direction; The first bit line includes the first metal silicide layer and the first conductive layer.

17. The method for preparing a semiconductor structure according to claim 12, characterized in that, After forming the first stacked structure on the substrate, the method for fabricating the semiconductor structure further includes: A first word line is formed on the first stacked structure. The first word line extends along a third direction parallel to the substrate and contacts the second doped layer in each of the first stacked structures arranged along the third direction.

18. The method for preparing a semiconductor structure according to claim 17, characterized in that, The material of the second doped layer includes doped polysilicon, and the formation of the first word line on the first stacked structure includes: The surface of the second doped layer away from the substrate is subjected to metal silicide treatment to form a second metal silicide layer corresponding to the first stacked structure; A second conductive layer is formed on the surface of the second metal silicide layer, the second conductive layer is in contact with the second metal silicide layer, and extends along the third direction; The first word line includes a second metal silicide layer and a second conductive layer, and the first word line is connected to a plurality of first stacked structures arranged along the third direction.

19. The method for preparing a semiconductor structure according to claim 12, characterized in that, The formation of a second stacked structure, a first dielectric layer, and a first conductive structure on the first stacked structure includes: A third doped material layer is formed on the first stacked structure, and the third doped material layer is spaced apart from the first stacked structure. A first via is formed in the third doped material layer, extending at least through the first semiconductor layer along the first direction; The first dielectric layer is formed on the inner wall of the first through hole, and the top surface of the first dielectric layer away from the substrate is lower than the top surface of the third doped material layer away from the substrate; A first conductive structure is formed in the first through hole, and the top surface of the first conductive structure is lower than the top surface of the third doped material layer away from the substrate; A second isolation layer is formed on the top surface of the first conductive structure, and the second isolation layer fills the first through hole; A second semiconductor material layer and a fourth doped material layer are sequentially formed on the top surface of the third doped material layer to obtain a second stacked material including the third doped material layer, the second semiconductor material layer and the fourth doped material layer; The second laminated material is patterned to obtain a second laminated structure located on the first laminated structure.

20. The method for preparing a semiconductor structure according to claim 12, characterized in that, The second dielectric layer and the second conductive structure are respectively formed around the sidewalls of the second stacked structure, including: A second dielectric layer is formed around the sidewall of the second stacked structure, and the second dielectric layers adjacent to the sidewall of the second stacked structure are spaced apart. A second conductive structure is formed on the sidewall of the second dielectric layer away from the second stacked structure, and the second conductive structure surrounds the second stacked structure.

21. The method for preparing a semiconductor structure according to claim 20, characterized in that, A second conductive structure is formed on the sidewall of the second dielectric layer away from the second stacked structure, including: The second conductive structure is formed on the periphery of the second stacked structure, and the second conductive structures of adjacent second stacked structures are connected to form an integral structure.

22. The method for preparing a semiconductor structure according to claim 12, characterized in that, Other methods for fabricating semiconductor structures include: A second bit line is formed on the top surface of the fourth doped layer. The second bit line is disposed corresponding to the second stacked structure and spaced apart from the second conductive structure.

23. An electronic device, characterized in that, Includes the semiconductor structure according to any one of claims 1-11; and / or includes a semiconductor structure made using the preparation method of the semiconductor structure according to any one of claims 12-22.

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