A chip packaging structure integrating in-situ radiative heat dissipation and its fabrication method

Abstract

This invention discloses a chip packaging structure with integrated in-situ radiative heat dissipation and its fabrication method, belonging to the field of semiconductor chip heat dissipation technology. The packaging structure includes a silicon carbide wafer, a device layer, a molding compound layer, a high-emissivity cone-tip array structure, a redistribution layer, pads, and metal bumps. The high-emissivity cone-tip array structure is formed directly on the back side of the silicon carbide wafer using femtosecond laser direct writing technology, exhibiting a micro-nano composite structure with an average emissivity exceeding 97% in the 2.5-16μm wavelength range. This invention directly integrates the high-radiative heat dissipation structure onto the back side of the chip substrate, allowing chip heat to be directly dissipated to the external environment in the form of infrared radiation. This bypasses the complex multi-layered heat conduction paths of traditional packaging, significantly reducing thermal resistance and improving heat dissipation efficiency. This structure offers advantages such as small size, low thermal resistance, good mechanical stability, and high process compatibility, making it suitable for high-performance computing chips, power devices, and other applications with high heat dissipation requirements.

Description

Technical Field

[0001] This invention belongs to the field of heat dissipation technology for semiconductor chips, specifically relating to a chip packaging structure with integrated in-situ radiative heat dissipation and its fabrication method. Background Technology

[0002] With the rapid development of next-generation information technologies such as 5G communication, cloud computing, and autonomous vehicles, the power consumption and power density of semiconductor chips are constantly increasing, and the heat dissipation problem of chips is becoming increasingly serious. Excessively high operating temperatures not only affect the performance and stability of chip operation, but also cause the probability of chip failure to increase exponentially with rising temperature. Therefore, efficient thermal management of semiconductor chips is of paramount importance.

[0003] Flip-chip packaging is widely used due to its superior electrical performance and high-density interconnects. Traditional heat dissipation solutions for flip-chips involve attaching a metal heat sink to the back of the chip package, relying on solid-state thermal conduction to transfer heat and ensure continuous and stable chip operation. This method of attaching a heat dissipation structure externally to the chip occupies additional space, increases thermal resistance, and may even be incompatible with semiconductor processes. Micro-thermal channels typically involve fabricating micrometer-scale channels on the chip or package surface, using forced flow of coolant to remove heat. While offering significant heat dissipation capabilities, this requires additional piping and heat exchange systems, greatly increasing package complexity and size, which is detrimental to the development requirements of chip integration. In chip-level packaging, depositing a graphene thermal layer on the back of the wafer can improve the chip's heat dissipation efficiency. However, the heat dissipation structure prepared by this deposition coating method is susceptible to environmental influences, exhibiting problems such as low adhesion and poor uniformity, limiting its application in actual mass production.

[0004] Existing mainstream chip heat dissipation technologies, including external metal heat sinks, integrated microchannels, or additional heat dissipation layers, generally suffer from problems such as large package size, long heat dissipation paths, high thermal resistance, poor mechanical stability, and insufficient long-term reliability. Summary of the Invention

[0005] This invention aims to address the problems of large heat sink volume, long heat dissipation paths, and high thermal resistance in traditional chip heat dissipation technologies. It proposes a packaging structure that directly integrates a high-emissivity micro-cone array on the back side of the chip substrate, utilizing the principle of thermal radiation to achieve in-situ heat dissipation. Through multi-level micro / nano structure morphology design and the selection of high thermal conductivity semiconductor materials, this structure significantly enhances the infrared radiation capability of the chip's back side, allowing some heat to be directly radiated to the external environment in the form of electromagnetic waves. This bypasses the complex heat conduction paths of traditional packaging, significantly reducing overall thermal resistance and improving heat dissipation efficiency. This technology is applicable to high-performance computing chips, optoelectronic devices, power semiconductors, and other fields with stringent heat dissipation requirements. It can significantly improve chip heat dissipation efficiency while simplifying the packaging structure, improving system integration and reliability, and achieving long-term, efficient, and stable radiative heat dissipation, demonstrating promising application prospects.

[0006] This invention is achieved through the following technical solution:

[0007] A chip packaging structure integrating in-situ radiative heat dissipation includes: a silicon carbide wafer 1 with high thermal conductivity, a device layer 2, a molding compound layer 3, a high emissivity cone-shaped array structure 4, a redistribution layer 5, pads 6, and metal bumps 7; the upper surface of the silicon carbide wafer 1 is integrated with a pre-fabricated device layer 2; the lower surface has a high emissivity cone-shaped array structure 4; the molding compound layer 3 covers the side surface and part of the lower surface of the silicon carbide wafer 1, exposing the central region of the lower surface of the silicon carbide wafer 1; the high emissivity cone-shaped array structure 4 is formed in the exposed region of the lower surface of the silicon carbide wafer; the redistribution layer 5 is constructed on the upper surface of the device layer 2; the pads 6 are disposed between the lower surface of the redistribution layer 5 and the upper surface of the device layer 2, for realizing electrical communication between the device layer 2 and the redistribution layer 5; the metal bumps 7 are disposed on the upper surface of the redistribution layer 5 for connecting to an external circuit board, and realizing electrical communication between the redistribution layer 5 and the external circuit board.

[0008] Furthermore, the silicon carbide wafer 1 is made of 4H-SiC, 6H-SiC or N-doped SiC, and has a size of 0.1cm-10cm and a thickness of 0.15mm-3mm.

[0009] Furthermore, the high emissivity cone-tip array structure 4 is a two-level micro-nano composite structure, including a micron-scale cone-tip array and nano-scale particles and clusters. The cone height of the micron-scale cone-tip array is 60μm-120μm; the nano-scale particles and clusters are attached to the surface of the micron-scale cone-tip array, and the size of the nano-scale particles and clusters is 200nm-1μm.

[0010] Furthermore, the high emissivity cone-tip array structure 4 has an average emissivity of over 97% in the 2.5-16μm range.

[0011] Furthermore, the high-emissivity cone-tip array structure 4 is fabricated using femtosecond laser direct writing technology. The specific processing steps are as follows: First, the sample is ultrasonically treated in acetone, ethanol, and deionized water for 10-30 minutes in sequence. Second, the sample is fixed on a two-dimensional moving platform, which consists of two one-dimensional moving displacement stages to ensure precise movement of the sample in the XY plane. Subsequently, the laser focus is focused on the sample surface through a field lens, and a pre-set processing program is used to scan line by line to rapidly fabricate a layered micro-nano composite structure on the sample surface. The fundamental wavelength of the femtosecond laser is 1030nm, which is doubled to 515nm. The laser repetition frequency is 50kHz-1000kHz, the laser pulse width is 280fs-10ps, the laser single pulse energy is 1-100μJ, the laser scanning speed is 1-1000mm / s, and the scanning interval is 20-100μm.

[0012] On the other hand, the present invention also provides a method for fabricating a chip packaging structure with integrated in-situ radiation heat dissipation, comprising the following steps:

[0013] S1. Provide a silicon carbide wafer with the device layer fabricated, and mount it on the upper surface of the temporary bonding layer with the device layer facing down.

[0014] S2. Use encapsulation material for injection molding to form a molding compound that completely covers the back and sides of the silicon carbide wafer; mechanically grind the lower surface of the molding compound to expose the central area of ​​the lower surface of the silicon carbide wafer.

[0015] S3. A high emissivity cone-tip array structure is fabricated on the exposed lower surface region of a silicon carbide wafer using femtosecond laser direct writing technology, serving as an in-situ radiation heat dissipation surface;

[0016] S4. A redistribution layer is formed by photolithography. Pads are provided on the lower surface of the redistribution layer and metal bumps are provided on the upper surface. Electrical connection with the device layer is achieved through the pads, and electrical connection with the redistribution layer is achieved through the metal bumps.

[0017] S5. The device layer of the silicon carbide wafer is attached to the lower surface of the redistribution layer with the device layer facing down. The device layer is soldered and fixed to the pads, and the gap between the silicon carbide wafer and the pads is filled to obtain a wafer-level silicon carbide chip packaging structure that integrates a high emissivity microstructure to achieve in-situ radiation heat dissipation.

[0018] Further, in step (3), the processing parameters of the femtosecond laser direct writing technology are as follows: the laser fundamental wavelength is 1030nm, which becomes 515nm after frequency doubling; the laser repetition frequency is 50kHz-1000kHz; the laser pulse width is 280fs-10ps; the laser single pulse energy is 1-100μJ; the laser scanning speed is 1-1000mm / s; and the scanning spacing is 20-100μm.

[0019] Compared with the prior art, the advantages of the present invention are as follows:

[0020] 1. Unlike traditional methods of mounting heat sinks or depositing thermal coatings, this invention offers advantages such as high heat dissipation efficiency, strong mechanical stability, and low thermal resistance. In the 8-14μm infrared band, the emissivity of SiC wafers is increased from 55% to over 97%. Within the broadband infrared spectral band of 2.5-16μm, the radiative power density is increased by 107.89 W / m². 2 The power density is increased by 66.5%, significantly enhancing the radiative heat dissipation effect. By integrating a high-emissivity cone-tip array structure on the back of the chip, the heat generated during chip operation can be directly dissipated to the external environment in the form of infrared radiation. This bypasses the complex multi-layer heat dissipation path in traditional packaging, significantly reducing overall thermal resistance. Traditional packaging with multiple TIM layers leads to greater series thermal resistance; the packaging structure designed in this invention is an integrated structure, eliminating the thermal resistance issues between different materials. This improves heat dissipation efficiency from a physical layout perspective. Simultaneously, it effectively avoids problems such as uneven thickness, incomplete coverage, easy coating peeling, cracking, or aging over time and with the environment that are common in coating processes, thus ensuring the consistency and reliability of heat dissipation performance. Its mechanical strength, structural stability, and environmental tolerance are significantly superior to coating structures.

[0021] 2. Compared with traditional chip packaging structures, this invention achieves miniaturization and thinning of the chip heat dissipation structure, while remaining compatible with wafer-level chip packaging processes. By fabricating a cone-tip array structure using femtosecond laser processing, chip radiative heat dissipation is achieved, eliminating the need for bulky external components such as heat sinks or vapor chambers. This results in miniaturization and thinning of the chip package, better meeting the thermal management requirements of high-power silicon carbide devices in compact packaging environments. This structure perfectly fits the wafer-level packaging process flow, allowing for direct back-side micro-cone structure processing and front-side molding after front-end fabrication, facilitating mass production with high consistency. Attached Figure Description

[0022] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0023] Figure 1 A schematic diagram of heat dissipation for the chip;

[0024] Wherein, a is a schematic diagram of traditional chip heat dissipation, where TIM is the thermal interface material; b is a schematic diagram of the chip packaging structure with integrated in-situ radiation heat dissipation of the present invention. Figure 2 a is a schematic diagram of the heat dissipation path of a traditional heat sink (chip → package housing → heat sink).

[0025] Figure 2 This is a schematic diagram of the heat transfer path and thermal resistance of the chip.

[0026] Wherein, a represents the heat dissipation path of a traditional heat sink, which is chip → package housing → heat sink; b represents the heat dissipation path of the present invention, which is chip → heat sink;

[0027] Figure 3 This is a schematic diagram of a chip packaging structure with integrated in-situ radiative heat dissipation according to the present invention.

[0028] Figure 4 This is a schematic diagram of a high-emissivity microcone array structure.

[0029] Wherein, a is a three-dimensional cross-sectional profile of the cone-tip array structure, and b is a cold field scanning electron microscope image of the cone-tip array structure;

[0030] Figure 5 The diagram above is a schematic diagram of the fabrication process of the chip packaging structure with integrated in-situ radiation heat dissipation of the present invention.

[0031] Figure 6 This is a test diagram of a cone-shaped array structure;

[0032] Where a is the reflectance test curve of the sample, emissivity = 1 - reflectance, and b is the spectral radiance diagram of the sample.

[0033] In the figure: 1. Silicon carbide wafer; 2. Device layer; 3. Molding layer; 4. High emissivity microcone array structure; 5. Redistribution layer; 6. Pad; 7. Metal bump. Detailed Implementation

[0034] To clearly and completely describe the technical solution and its specific working process of the present invention, the specific embodiments of the present invention are as follows, in conjunction with the accompanying drawings:

[0035] Example 1

[0036] like Figure 3 As shown, this invention provides a chip packaging structure with integrated in-situ radiative heat dissipation. This structure includes a silicon carbide wafer 1, a device layer 2, a molding compound 3, a high-emissivity cone-shaped array structure 4, a redistribution layer 5, pads 6, and metal bumps 7. The upper surface of the silicon carbide wafer 1 has a pre-fabricated device layer 2 integrated thereon; the lower surface has the high-emissivity cone-shaped array structure 4; the molding compound 3 covers the sides and part of the lower surface of the silicon carbide wafer 1, exposing the central region of the lower surface of the silicon carbide wafer 1; the high-emissivity cone-shaped array structure 4 is formed in the exposed region of the lower surface of the silicon carbide wafer; the redistribution layer 5 is constructed on the upper surface of the device layer 2; the pads 6 are disposed on the lower surface of the redistribution layer 5 to achieve electrical communication between the device layer 2 and the redistribution layer 5; the metal bumps 7 are disposed on the upper surface of the redistribution layer 5 for connection to an external circuit board. The side away from the metal bumps is the lower surface, and the side closer to the metal bumps is the upper surface. The redistribution layer 5 is on the upper surface of the device layer 2.

[0037] The main principle behind this structure for chip heat dissipation is that a high emissivity cone-shaped array structure is directly integrated onto the back of the chip wafer substrate. This allows the heat generated during chip operation to be dissipated to the external environment in the form of infrared radiation, thereby shortening the high thermal resistance caused by the complex heat dissipation path in traditional packaging, improving heat dissipation efficiency, and simplifying the chip packaging structure to increase system integration.

[0038] In this embodiment, the silicon carbide wafer 1 serves as the core of the entire packaging structure, possessing excellent thermal conductivity and high hardness. It provides mechanical support and thermal conduction path for the device layer 2 on its upper surface and the high emissivity microcone array structure 4 on its lower surface. The thickness of the silicon carbide wafer 1 can be 0.15mm-3mm.

[0039] The device layer 2 is fabricated on the upper surface of the silicon carbide wafer 1. This layer integrates active and passive devices such as transistors, resistors, capacitors, and PN junctions through semiconductor manufacturing processes, forming the functional core of the chip. During chip operation, this area is the main source of power consumption and constitutes a heat concentration area.

[0040] The molding compound 3, formed by transfer molding, covers the sides and part of the lower surface of the silicon carbide wafer 1, providing robust mechanical support, physical protection, and environmental protection (moisture resistance, contamination prevention, and mechanical damage prevention) for the entire chip structure. Its material is typically an epoxy molding compound filled with fillers such as silicon dioxide. After polishing, the lower surface of the molding compound 3 is flush with the lower surface of the silicon carbide wafer 1, together forming the bottom plane of the package. This provides favorable conditions for the subsequent fabrication of the high-emissivity microcone array structure 4 and ensures the structural stability and standardization of the package during installation.

[0041] like Figure 4 As shown in a and b, the high emissivity cone-tip array structure 4 is a two-level micro-nano composite structure, comprising a micrometer-scale cone-tip array and nano-scale particles and clusters. The cone tip height is approximately 80 μm, and the nanoparticle size is 200 nm - 1 μm. This structure is formed directly on the back side of the wafer by femtosecond laser direct writing technology through etching or induction. During this process, a large number of micro-nano-scale particles and clusters are attached to the surface of the cone-tip array, forming a micro-nano composite structure. The micrometer-scale cone tip structure is a key factor in enhancing light absorption; the higher the cone tip height, the stronger the geometric light-trapping effect and the higher the emissivity. At the same time, the high aspect ratio cone tip structure significantly increases the specific surface area, enhances the heat exchange effect between the chip heat source and the air, and improves the heat dissipation efficiency. The high emissivity cone-tip array structure 4, as an in-situ radiative heat sink, can emit the heat conducted from the device layer 2 into the surrounding environment in the form of electromagnetic waves, reducing the chip temperature.

[0042] The redistribution layer 5 is fabricated on the device layer 2 and is typically composed of alternating layers of polymer dielectric layers and metal conductor layers. The core function of the redistribution layer 5 is to distribute signals and power through different layers of lines, redistributing the I / O (input / output) signals in the device layer 2 to a wider, more spaced area to accommodate the interconnection requirements with external circuits after packaging, optimize signal transmission paths, and enable the chip to achieve higher data transmission efficiency within a limited area.

[0043] The pads 6 are formed on the lower surface of the redistribution layer 5. The pads 6 serve as electrical connection points between the device layer 2 and the redistribution layer 5, enabling electrical communication between the device layer 2 and the redistribution layer 5.

[0044] The metal bump 7 is formed on the upper surface of the redistribution layer 5 and is typically manufactured using processes such as reflow soldering. Its material is a conductive metal. The metal bump 7 is electrically connected to the redistribution layer 5 and, through the redistribution layer 5, to the device layer 2. The metal bump 7 serves as an electrical and mechanical connection interface between the packaged chip and the external printed circuit board.

[0045] The chip heat dissipation structure of this embodiment can significantly increase the effective heat dissipation surface area, enhance the thermal radiation effect, and improve the convective heat transfer capacity. It effectively avoids problems such as uneven thickness and incomplete coverage that are prone to occur in the coating process, thereby ensuring the consistency and reliability of heat dissipation performance. Its mechanical strength, structural stability, and environmental tolerance are significantly better than coating structures. It is not prone to peeling or cracking due to thermal stress or mechanical impact, and is more suitable for thermal management of semiconductor devices in harsh working environments.

[0046] Compared to traditional heat dissipation solutions that rely on heat conduction and convection, this method eliminates the need for surface-mounted metal heat sinks and complex thermal interface materials, simplifying the heat flow path from the chip's heat source to the external environment. It efficiently converts the heat generated by the chip into infrared radiation energy, directly dissipating it into space, thus achieving higher thermal radiation efficiency. Simultaneously, from Figure 2 As can be seen, the high emissivity microcone array structure is integrally formed with the chip substrate, eliminating the additional interfacial thermal resistance caused by the bonding of different materials in the traditional solution, and ensuring that heat can be quickly dissipated.

[0047] Example 2

[0048] like Figure 5 As shown in Figure ae, this embodiment details a method for fabricating a chip packaging structure with integrated in-situ radiative heat dissipation. The method specifically includes the following steps:

[0049] (1) Implement a temporary bonding process on the surface of silicon carbide wafer 1:

[0050] A temporary carrier (such as a glass carrier or a silicon-based carrier) with good mechanical rigidity and thermal stability is provided. A temporary bonding layer is formed on the upper surface of the carrier by coating or lamination. Then, a silicon carbide wafer 1 with front-end device fabrication completed is prepared, which has a device layer 2 on its upper surface. The device layer 2 is precisely mounted on the upper surface of the temporary bonding layer with its upper surface facing down. This step provides solid mechanical support for subsequent back-side processing and effectively protects the device layer 2 on the upper surface of the silicon carbide wafer.

[0051] (2) Transfer molding is performed on the upper surface of the bonded substrate:

[0052] High thermal conductivity epoxy molding compound is used for injection molding to form a molding compound 3 that completely covers the back and sides of the silicon carbide wafer 1; after curing, the molding compound 3 provides preliminary mechanical integration and environmental protection for the entire chip structure.

[0053] (3) After the molding compound 3 has cured and stabilized, perform the debonding operation:

[0054] Based on the material properties of the temporary bonding layer, an appropriate debonding method is adopted. The temporary substrate and temporary bonding layer on the upper surface of the molding compound 3 are removed sequentially; after this step, the device layer 2 of the silicon carbide wafer is re-exposed.

[0055] (4) The lower surface of the molding layer 3 is subjected to a thinning treatment combining mechanical grinding and chemical mechanical polishing:

[0056] By precisely controlling the grinding depth and flatness, the lower surface of the silicon carbide wafer 1 is exposed, and the lower surface of the molding layer 3 is ensured to be on the same reference plane as the lower surface of the silicon carbide wafer 1, so as to prepare a flat substrate for subsequent microstructure processing.

[0057] (5) Fabrication of high emissivity microcone array structure:

[0058] On the exposed lower surface of silicon carbide wafer 1, a femtosecond laser processing system was used for scanning. By precisely controlling the laser power, scanning speed, repetition frequency, and scanning path, a uniformly distributed high-emissivity microcone array structure 4 with a height of 60-120 μm was induced on the wafer surface. During this process, the interaction between the laser and the material also generated a large number of micro- and nano-sized particles and clusters in situ on the surface of the microcones. These microscopic features collectively endow the microcone structure with broadband high emissivity characteristics in the infrared band (especially the 8-13 μm atmospheric window band). Figure 6 As shown, the 80 μm high cone-shaped structure exhibits an average emissivity of ≥97% in the infrared band of 2.5–16 μm, demonstrating broad-spectrum high emissivity characteristics. The spectral radiance of the cone-shaped structure approaches that of an ideal blackbody, thus forming a highly efficient in-situ radiative heat dissipation layer. Within the 2.5–16 μm range, the radiative power density at 300 K increases by 107.89 W / m². 2 This significantly enhances the radiative heat dissipation effect.

[0059] (6) On the upper surface of the molding layer 3, the following steps are performed to complete the electrical interconnection:

[0060] Fabrication of redistribution layer 5: A polymer dielectric layer (such as polyimide) is sequentially deposited and patterned using processes such as spin coating, exposure, and development, and a patterned metal conductor layer (such as copper) is formed using processes such as sputtering and electroplating. This alternating stacking process constitutes a multilayer redistribution layer 5. This layer is used to redistribute the I / O (input / output) signals in device layer 2 to a wider, more spaced area to accommodate the interconnection requirements with external circuits after packaging.

[0061] Fabrication of pad 6: On the bottom layer of redistribution layer 5, pad 6 is formed to connect with the electrode of device layer 2 through photolithography and electroplating processes, so as to achieve electrical connection with device layer 2.

[0062] Fabrication of metal bumps 7: On the top layer of the completed redistribution layer 5, metal bumps 7 (such as solder balls) are formed by balling, electroplating or printing solder and reflow soldering. These bumps are electrically connected to the redistribution layer 5 and ultimately serve as the interface for electrical connection and mechanical fixation between the package and the external circuit board.

[0063] (7) Complete flip-chip bonding and underfill to achieve encapsulation:

[0064] The silicon carbide wafer is attached to the lower surface of the redistribution layer with the device layer facing down. The device layer is soldered and fixed to the pads, and the gap between the silicon carbide wafer and the pads is filled. This results in a wafer-level silicon carbide chip packaging structure that integrates a high-emissivity microstructure to achieve in-situ radiative heat dissipation.

[0065] The results show that the chip heat dissipation packaging structure provided by the present invention allows heat to be directly transferred from the active area of ​​the chip through the substrate to the microcone array for radiation, shortening the conduction path, significantly reducing thermal resistance, and ensuring that heat can be quickly dissipated. Figure 6 Figure 'a' shows a comparison curve of the reflectivity of an untreated silicon carbide wafer in the 2.5-16 μm range with that after femtosecond laser direct writing. According to Kirchhoff's law, emissivity = 1 - reflectivity. It can be seen that silicon carbide exhibits very high reflectivity in the 10.3-12.6 μm range, meaning its emissivity is almost zero. This wavelength range falls within the atmospheric transmission window (8-13 μm), which is unfavorable for infrared radiation heat dissipation of the chip. However, after laser processing, the emissivity of silicon carbide reaches over 97% across the entire 2.5-16 μm wavelength range, exhibiting broad-spectrum high emissivity characteristics. Figure 6 Let b represent the spectral irradiance of an ideal blackbody (emissivity = 1), untreated silicon carbide, and silicon carbide after femtosecond laser direct writing at 300 K. An ideal blackbody possesses the strongest spectral irradiance; the closer the spectral irradiance is to that of a blackbody, the stronger the object's infrared radiation capability. It can be seen that there is a significant difference in the irradiance of silicon carbide before and after femtosecond laser treatment; the irradiance of silicon carbide is significantly enhanced after laser treatment, approaching that of an ideal blackbody. Through analysis of… Figure 6 The radiant power density can be obtained by integrating the irradiance curve in region b. Calculations show that in the 2.5-16 μm band, the blackbody radiant power density is 277.79 W / m², the silicon carbide wafer's radiant power density is 162.25 W / m², and the laser-treated silicon carbide wafer's radiant power density is 270.14 W / m². Compared to the untreated silicon carbide wafer, the laser-treated wafer shows an increase in radiant power density of 107.89 W / m². 2 The power density was increased by 66.5%, significantly enhancing the radiative heat dissipation effect.

[0066] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0067] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0068] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A chip packaging structure integrating in-situ radiative heat dissipation, characterized in that, include: The silicon carbide wafer (1) has high thermal conductivity, a device layer (2), a molding compound (3), a high emissivity cone array structure (4), a redistribution layer (5), pads (6), and metal bumps (7). The upper surface of the silicon carbide wafer (1) is integrated with a pre-fabricated device layer (2); the lower surface has a high emissivity cone array structure (4). The molding compound (3) covers the sides and part of the lower surface of the silicon carbide wafer (1), exposing the central region of the lower surface of the silicon carbide wafer (1). The high emissivity cone array structure (4)... The spike array structure (4) is formed in the exposed area on the lower surface of the silicon carbide wafer; the redistribution layer (5) is constructed on the upper surface of the device layer (2); the pad (6) is disposed between the lower surface of the redistribution layer (5) and the upper surface of the device layer (2) to realize the electrical connection between the device layer (2) and the redistribution layer (5); the metal bump (7) is disposed on the upper surface of the redistribution layer (5) to connect with the external circuit board and realize the electrical connection between the redistribution layer (5) and the external circuit board.

2. The chip packaging structure with integrated in-situ radiative heat dissipation as described in claim 1, characterized in that, The silicon carbide wafer (1) is made of 4H-SiC, 6H-SiC or N-doped SiC, and has a size of 0.1cm-10cm and a thickness of 0.15mm-3mm.

3. The chip packaging structure with integrated in-situ radiative heat dissipation as described in claim 1, characterized in that, The high emissivity cone-tip array structure (4) is a two-level micro-nano composite structure, including a micron-level cone-tip array and nano-level particles and clusters. The cone-tip height of the micron-level cone-tip array is 60μm-120μm. The nano-level particles and clusters are attached to the surface of the micron-level cone-tip array, and the size of the nano-level particles and clusters is 200nm-1μm.

4. The chip packaging structure with integrated in-situ radiative heat dissipation as described in claim 1, characterized in that, The high emissivity cone-shaped array structure (4) has an average emissivity of over 97% at 2.5-16 μm.

5. The chip packaging structure with integrated in-situ radiative heat dissipation as described in claim 1, characterized in that, The high emissivity cone-tip array structure (4) is prepared by femtosecond laser direct writing technology. The specific processing steps are as follows: First, the sample is ultrasonically treated in acetone, ethanol and deionized water for 10-30 minutes in sequence; second, the sample is fixed on a two-dimensional moving platform, which consists of two one-dimensional moving displacement stages to meet the precise movement of the sample in the XY plane; then, the laser focus is focused on the sample surface through a field lens, and the layered micro-nano composite structure is rapidly prepared on the sample surface by scanning line by line through a pre-set processing program; the fundamental wavelength of the femtosecond laser is 1030nm, which becomes 515nm after frequency doubling, the repetition frequency of the laser is 50kHz-1000kHz, the laser pulse width is 280fs-10ps, the laser single pulse energy is 1-100μJ, the laser scanning speed is 1-1000mm / s, and the scanning interval is 20-100μm.

6. The method for fabricating a chip packaging structure with integrated in-situ radiative heat dissipation as described in claim 1, characterized in that, Includes the following steps: S1. Provide a silicon carbide wafer with the device layer fabricated, and mount it on the upper surface of the temporary bonding layer with the device layer facing down. S2. Use encapsulation material for injection molding to form a molding compound that completely covers the back and sides of the silicon carbide wafer; mechanically grind the lower surface of the molding compound to expose the central area of ​​the lower surface of the silicon carbide wafer. S3. A high emissivity cone-tip array structure is fabricated on the exposed lower surface region of a silicon carbide wafer using femtosecond laser direct writing technology, serving as an in-situ radiation heat dissipation surface; S4. A redistribution layer is formed by photolithography. Pads are provided on the lower surface of the redistribution layer and metal bumps are provided on the upper surface. Electrical connection with the device layer is achieved through the pads, and electrical connection with the redistribution layer is achieved through the metal bumps. S5. The device layer of the silicon carbide wafer is attached to the lower surface of the redistribution layer with the device layer facing down. The device layer is soldered and fixed to the pads, and the gap between the silicon carbide wafer and the pads is filled to obtain a wafer-level silicon carbide chip packaging structure that integrates a high emissivity microstructure to achieve in-situ radiation heat dissipation.

7. The method for fabricating a chip packaging structure with integrated in-situ radiative heat dissipation as described in claim 6, characterized in that, In step (3), the processing parameters of the femtosecond laser direct writing technology are as follows: the laser fundamental wavelength is 1030nm, which becomes 515nm after frequency doubling; the laser repetition frequency is 50kHz-1000kHz; the laser pulse width is 280fs-10ps; the laser single pulse energy is 1-100μJ; the laser scanning speed is 1-1000mm / s; and the scanning spacing is 20-100μm.

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