Single-phase t-type three-level power module based on embedded package and electronic equipment

Abstract

The application discloses a single-phase T-type three-level power module based on embedded packaging and electronic equipment, and the power module comprises a power copper foil layer, a chip layer, a control and auxiliary power layer and a rewiring power layer; the power copper foil layer comprises a substrate and a vertical through hole arranged at the outer periphery and electrically connected to the rewiring power layer through the vertical through hole; the chip layer is arranged on the power copper foil layer, is provided with a cavity, and four power semiconductor chips are embedded into the cavity to form a single-phase T-type three-level circuit; the control and auxiliary power layer is arranged on the chip layer and comprises a non-driving wiring area of a midpoint compensation plane; the rewiring power layer is arranged on the control and auxiliary power layer and forms a main power circuit; and a projection part of the midpoint compensation plane in the direction perpendicular to the rewiring power layer covers the main power circuit. The application realizes the improvement of parasitic parameters through layout optimization, is favorable for reducing the switching voltage overshoot and improving the electrical performance of the power module under high-frequency working conditions.

Description

Technical Field

[0001] This invention relates to the field of power electronic systems, and more particularly to a single-phase T-type three-level power module and electronic device based on embedded packaging. Background Technology

[0002] As power electronic systems evolve towards higher power density and higher frequency, the T-type three-level topology, while becoming a core solution in the inverter field due to its low switching losses and high waveform quality, suffers from severe parasitic effects under traditional wire bonding packaging due to its complex commutation path. This not only causes severe voltage spikes due to excessive loop inductance, threatening the safety of SiC / IGBT chips and exacerbating electromagnetic interference, but also limits system compactness due to its split layout and single-sided heat dissipation structure. Furthermore, the aluminum bonding wires relied upon in traditional packaging are prone to fatigue fracture during long-term cycling, and the excessively long thermal management path has become a physical bottleneck restricting further breakthroughs in high-reliability, high-power applications of the T-type topology.

[0003] With the development of power electronics technology, high-power-density, high-switching-frequency power electronic converters are widely used in new energy vehicles, motor drive systems, and renewable energy power generation systems. As a core component of power electronic systems, the packaging structure of power modules has a significant impact on the system's electrical performance, thermal performance, and reliability.

[0004] In recent years, PCB embedded packaging technology has been increasingly applied to power module design. This technology embeds power semiconductor chips within multilayer printed circuit boards and utilizes multilayer metal conductors for electrical interconnection, which can shorten current paths and improve structural integration to some extent. However, in existing embedded packaging structures, a large current loop area is easily formed during commutation, resulting in significant parasitic inductance and affecting the operating accuracy and lifespan of electronic devices. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a single-phase T-type three-level power module and electronic device based on embedded packaging, so as to improve the above-mentioned problems.

[0006] This invention provides a single-phase T-type three-level power module based on embedded packaging, which includes, from bottom to top, a power copper foil layer, a chip layer, a control and auxiliary power layer, and a redistribution power layer; wherein:

[0007] The power copper foil layer includes a substrate and a vertical through-hole disposed on the outer periphery of the substrate, and is electrically connected to the redistribution power layer through the vertical through-hole;

[0008] A chip layer is disposed above the power copper foil layer and has a cavity. Four power semiconductor chips are coplanarly embedded in the cavity and electrically connected to form a single-phase T-type three-level circuit.

[0009] A control and auxiliary power layer is disposed above the chip layer and includes a driving wiring area and a non-driving wiring area. The non-driving wiring area forms a midpoint compensation plane, which is electrically connected to the midpoint terminal of the single-phase T-type three-level circuit.

[0010] A redistribution power layer is disposed above the control and auxiliary power layer, and a main power line is formed on its surface;

[0011] Wherein, the projection of the midpoint compensation plane in the direction perpendicular to the redistribution power layer at least partially covers the main power line, so that the main power line and the midpoint compensation plane form a spatial coupling structure.

[0012] Preferably, the midpoint compensation plane is a continuous copper foil plane disposed in the non-driving wiring area.

[0013] Preferably, the projection of the midpoint compensation plane in the direction perpendicular to the redistribution power layer covers 60%-95% of the main power line.

[0014] Preferably, the power semiconductor chip, the control and auxiliary power layer, and the redistribution power layer are vertically electrically interconnected through an array of electroplated micropores.

[0015] Preferably, it also includes a housing and an external electrical interface disposed on the housing, the external electrical interface being electrically connected to the redistribution power layer.

[0016] Preferably, the redistribution power layer further includes a metallized protection buffer structure formed by the main power lines extending downward through a micro-via array, the metallized protection buffer structure covering the electrodes of the power semiconductor chip.

[0017] Preferably, it further includes a copper base plate layer and an insulating layer, wherein the insulating layer is disposed between the copper base plate layer and the power copper foil layer.

[0018] Preferably, the vertical distance between the control and auxiliary power layer and the chip layer is 0.05mm to 0.08mm; the vertical distance between the redistribution power layer and the control and auxiliary power layer is 0.08mm to 0.15mm.

[0019] This invention also provides an electronic device comprising a single-phase T-type three-level power module based on embedded packaging as described above.

[0020] Compared with the prior art, the present invention has at least the following improvements:

[0021] 1. This invention optimizes the spatial layout between the main power line and the midpoint compensation plane, so that the two form an overlapping area in the vertical direction, thereby improving the electromagnetic coupling between them, increasing the mutual inductance value, and ultimately achieving an effective reduction in the parasitic inductance of the power module converter circuit.

[0022] 2. The present invention adopts a PCB embedded packaging structure, which enables the power semiconductor chip to form a compact vertical interconnect structure with other layers, further shortening the current path and reducing the loop area, thereby improving the power density of the entire power module. Attached Figure Description

[0023] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is an overall structural diagram of a single-phase T-type three-level power module based on embedded packaging provided in the first embodiment of the present invention;

[0025] Figure 2 An exploded view of the single-phase T-type three-level power module based on embedded packaging provided in the first embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a single-phase T-type three-level circuit;

[0027] Figure 4 This is a schematic diagram of the structure of the control and auxiliary power layer and the midpoint compensation plane provided in an embodiment of the present invention;

[0028] Figure 5 This is a side view of the control and auxiliary power layer and midpoint compensation plane provided in an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the rewiring power layer provided in an embodiment of the present invention;

[0030] Figure 7 This is a side view of the redistribution power layer provided in an embodiment of the present invention;

[0031] Figure 8 This is a schematic diagram showing the vertical projection overlap relationship between the midpoint compensation plane of the rewiring power layer and the control and auxiliary power layer, provided in an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Please see Figure 1 and Figure 2 The first embodiment of the present invention provides a single-phase T-type three-level power module based on embedded packaging, which includes, from bottom to top, a power copper foil layer L5, a chip layer L3, a control and auxiliary power layer L2, and a redistribution power layer L1; wherein:

[0034] The power copper foil layer L5 includes a substrate and a vertical through-hole disposed on the outer periphery of the substrate. It is electrically connected to the redistribution power layer L1 through the vertical through-hole, thereby completing the commutation loop closure of the single-phase T-type three-level circuit in the vertical dimension, while also having the ability to dissipate heat and support the chip layer L3.

[0035] In this embodiment, in particular, a copper base plate layer L6 and an insulating layer L7 are also included. The copper base plate layer L6 is disposed below the power copper foil layer L5 and is isolated from the back side of the chip layer L3 by the insulating layer L7.

[0036] In this embodiment, the chip layer L3 is disposed above the power copper foil layer L5 and has a cavity, housing four power semiconductor chips (i.e., Figure 3 The G1-G4 components are coplanarly embedded in the cavity and electrically connected to form a single-phase T-type three-level circuit.

[0037] The electrical connection method of the four power semiconductor chips and the final single-phase T-type three-level circuit are as follows: Figure 3 As shown.

[0038] In this embodiment, the outer periphery of the chip layer L3 is provided with a plurality of vertical copper pillar terminals with a diameter of 0.3mm to 1.0mm. The vertical copper pillar terminals are coupled in parallel at multiple points with the redistribution power layer L1 and the control and auxiliary power layer L2 through the electroplating layer of the vertical through hole wall, so as to reduce the parasitic inductance at the interface.

[0039] The control and auxiliary power layer L2 is disposed above the chip layer L3 and includes a driving wiring area and a non-driving wiring area. The non-driving wiring area forms a midpoint compensation plane 7, which is electrically connected to the midpoint of the single-phase T-type three-level circuit.

[0040] In this embodiment, as Figure 4 and Figure 5 As shown, the control and auxiliary power layer L2 is pressed onto the chip layer L3, and the vertical distance between the control and auxiliary power layer L2 and the chip layer L3 is 0.05mm~0.08mm, preferably 0.06mm.

[0041] In this embodiment, the control and auxiliary power layer L2 includes a drive wiring area and a midpoint compensation plane 7 filled in the non-wiring area. The midpoint compensation plane 7 is electrically connected to the midpoint terminal 0 (Neutral) of the single-phase T-type three-level circuit.

[0042] Specifically, the drive wiring area is provided with lines and various electronic devices, such as signal lines 8, etc. The midpoint compensation plane 7 is a large area continuous copper foil plane set in the non-wiring area, which is provided with connecting through holes 9. The hole walls of the connecting through holes 9 are formed with an electroplated layer to realize the connection with the rewiring power layer L1.

[0043] The thickness of the continuous copper foil is 0.015mm to 0.2mm, preferably 0.02mm.

[0044] A redistribution power layer L1 is disposed above the control and auxiliary power layer L2, and a main power line is formed on its surface.

[0045] In this embodiment, the redistribution power layer L1 is pressed onto the control and auxiliary power layer L2, and the vertical distance between the redistribution power layer L1 and the control and auxiliary power layer L2 is 0.08mm~0.15mm.

[0046] In this embodiment, as Figure 6 As shown, a main power line 3 is formed on the front side of the redistribution power layer L1, and the main power line 3 includes a DC positive path and a DC negative path. The projection of the midpoint compensation plane 7 in the direction perpendicular to the redistribution power layer L1 covers the main power line 3, thus forming a spatial coupling structure between the main power line 3 and the midpoint compensation plane 7.

[0047] In this embodiment, as Figure 7 As shown, copper pillars 5 and a protective copper layer 6 are also formed on the back side of the redistribution power layer L1. The copper pillars 5 are used to connect and fix with the connection through holes 9 on the control and auxiliary power layer L2. The protective copper layer 6 is used to protect the surface of the control and auxiliary power layer L2.

[0048] In this embodiment, the electrodes of the power semiconductor chip in the redistribution power layer L1, the control and auxiliary power layer L2, and the chip layer L3 are vertically electrically interconnected through a micro-via array 4 filled with electroplating. Specifically, using precision depth-controlled laser drilling technology, a micro-via array 4 is formed between the redistribution power layer L1, the control and auxiliary power layer L2, and the electrodes of the power semiconductor chip. High-density electroplating is used to fill the micro-via array 4, thereby achieving vertical electrical interconnection between the source / drain electrodes of the redistribution power layer L1 and the power semiconductor chip.

[0049] In this embodiment, as Figure 8 As shown, Figure 8 This is a schematic diagram showing the vertical projection overlap between the midpoint compensation plane 7 of the rewiring power layer L1 and the control and auxiliary power layer L2. Figure 8 In the diagram, the dashed box represents the overlapping portion of the projection of the midpoint compensation plane 7 onto the direction perpendicular to the redistribution power layer L1 and the main power line 3. It can be seen that this projection partially covers the main power line 3, and specifically, the coverage ratio is 60%-95%.

[0050] In this embodiment, during operation, current flows in from the DC+ terminal 1 of the rewiring power layer L1, passes vertically downward through the high-density electroplated micro-hole array 4, and enters the electrode of the power semiconductor chip through the metallized protective buffer structure of the rewiring power layer L1. After passing through the chip layer L3, the current is collected by the power copper foil layer L5 on the back of the chip layer L3. The current is then transversely transmitted along the power copper foil layer L5 to the edge of the substrate, and flows upward through the vertical copper pillar terminals at the edge of the substrate back to the DC negative path of the top rewiring power layer L1. This "top-bottom-top" vertical stack-up design minimizes the area enclosed by the commutation loop, thereby significantly reducing parasitic inductance.

[0051] In addition, by setting an internal midpoint compensation plane 7 and optimizing the spatial relationship between the main power line 3 and the midpoint compensation plane 7, the midpoint return path of the main power line 3 and the midpoint compensation plane 7 forms a tightly coupled structure in space, which can generate a magnetic flux cancellation effect during the three-level commutation process, thereby effectively reducing the parasitic inductance of the module commutation circuit.

[0052] Specifically, during the high-frequency switching process of the entire power module, the parasitic inductance of the commutation circuit is mainly determined by the area of ​​the current loop formed between the power current path of the main power line 3 and its return path. According to electromagnetic field theory, the parasitic inductance of a conductor loop can be approximately expressed as:

[0053]

[0054] Where: L is the parasitic inductance of the loop; μ0 is the permeability of free space; A is the equivalent area enclosed by the current loop; and l is the equivalent length of the current path.

[0055] As can be seen from the above relationship, the larger the loop area, the greater the parasitic inductance.

[0056] In traditional power module structures, the power current path and the midpoint return path are usually located in different planar structures with a large spatial distance between them. This results in a large current loop area during the commutation process, leading to a large parasitic inductance.

[0057] In this embodiment, by setting a midpoint compensation conductor region inside the power module and making the projection of the main power line 3 in the vertical direction overlap with the midpoint compensation plane 7, the power current path and the midpoint return path form a tightly coupled planar loop structure in space.

[0058] When two conductors carrying currents in opposite directions approach each other in space, according to electromagnetic theory, their magnetic fields will partially cancel each other out. For two parallel conductors, their mutual inductance per unit length can be expressed as:

[0059]

[0060] Where: M is mutual inductance; d is the distance between the two conductors; r is the conductor radius or equivalent size.

[0061] When a tight coupling structure is formed between the power current path and the midpoint return path, the mutual inductance between them increases, and the system's equivalent inductance can be expressed as:

[0062] L eq= L 1+ L 2-2 M

[0063] Where: L1 is the self-inductance of the main power line 3; L2 is the self-inductance of the midpoint return path; M is the mutual inductance between the two paths.

[0064] From the above formula, it can be seen that when the mutual inductance M increases, the equivalent parasitic inductance L... eq It will be significantly reduced.

[0065] This embodiment optimizes the spatial layout between the main power line 3 and the midpoint compensation plane 7, so that the two form an overlapping area in the vertical direction, thereby improving the electromagnetic coupling between them, increasing the mutual inductance value, and ultimately achieving an effective reduction in the parasitic inductance of the module converter circuit.

[0066] Therefore, this embodiment can improve parasitic parameters through conductor layer layout optimization without adding additional components, which is beneficial for reducing switching voltage overshoot and improving the electrical performance of the power module under high-frequency operating conditions.

[0067] Meanwhile, the use of a PCB embedded packaging structure enables a compact vertical interconnect structure between the power semiconductor chip and the conductor layer, which can further shorten the current path and reduce the loop area, thereby improving the power density of the module.

[0068] In summary, this embodiment not only optimizes the current loop structure in the T-type three-level circuit, but also enables effective control of parasitic parameters through conductor layer layout, making it suitable for high-frequency, high-power-density power electronics applications.

[0069] The following provides a further description of some preferred embodiments of the present invention and its process flow.

[0070] Preferably, it further includes an outer shell layer L4, which includes an outer shell 2 and an external electrical interface disposed on the outer shell 2, the external electrical interface being electrically connected to the redistribution power layer L1.

[0071] In this embodiment, as Figure 1 and Figure 2 As shown, the outer casing 2 can be made of plastic and is used to house the power module, providing support and protection. The external electrical interface adopts a vertical copper pillar terminal structure that penetrates the substrate and is electrically connected to the redistribution power layer L1 through an electroplated layer on the hole wall.

[0072] Preferably, the redistribution power layer L1 further includes a metallization protection buffer structure that covers the electrodes of the power semiconductor chip.

[0073] In this embodiment, the main power line 3 extends downward through a micro-hole array 4 to form a metallized protective buffer structure that directly covers the electrode surface of the power semiconductor chip. The copper thickness of the metallized protective buffer structure is 0.005 mm to 0.02 mm, preferably 0.01 mm. By directly covering the electrodes of the power semiconductor chip with the metallized protective buffer structure, not only is the mechanical strength of the electrodes enhanced, but a reliable soldering / electroplation substrate is also provided for subsequent high-power copper pillar interconnects.

[0074] In this embodiment, in particular, in addition to the multi-layer structure described above, each layer of the power module is filled with an insulating medium, such as glass fiber reinforced resin material, which serves to fix and support the structure and provide physical isolation.

[0075] The process flow of this embodiment is described in detail below:

[0076] S1: Substrate Preparation and Chip Implantation: A cavity is formed on a pre-designed PCB core board using laser or mechanical milling. Four power semiconductor chips G1~G4 are implanted into the cavity in parallel and coplanar manner. The back of the power semiconductor chips is fixed to the power copper foil layer L5 to ensure good heat conduction.

[0077] S2: Construction of the Integrated Metallized Protective Buffer Structure: A 0.01 mm thick integrated metallized protective buffer structure is first deposited on the electrodes of the power semiconductor chip. This metallized protective buffer structure directly covers the electrodes of the power semiconductor chip, which not only enhances the mechanical strength of the electrodes, but also provides a reliable soldering / electroplating substrate for subsequent high-power copper pillar interconnects.

[0078] S3: Vacuum Lamination and Insulation Filling: Glass fiber reinforced resin materials (such as FR4 or BT resin) are selected as the filling medium. Multilayer lamination is performed in a vacuum environment to ensure that the resin completely fills the gap between the chip and the substrate cavity. The presence of glass fiber effectively improves the structural stability of the module and matches the coefficient of thermal expansion (CTE) between the chip and the PCB.

[0079] S4: Microvia Fabrication and Vertical Interconnection: Utilizing precision depth-controlled laser drilling technology, a microvia array is created between the redistribution power layer L1, the control and auxiliary power layer L2, and the chip electrodes. High-density electroplating is used to fill the microvia array to achieve vertical electrical interconnection between the electrodes (such as source or drain) of the redistribution power layer L1 and the chip layer L3. Vertical copper pillar terminals with a diameter of 1.0 mm (range 0.3 mm~1.0 mm) are fabricated on the outer periphery of the substrate. Multi-point parallel coupling between the redistribution power layer L1 and the control and auxiliary power layer L2 is achieved through the electroplating layer on the hole walls, minimizing interface parasitic inductance.

[0080] S5: Surface Finishing and Terminal Integration: The main power circuitry is routed on the redistribution power layer L1. Then, the outer shell layer L4 is added, bringing the external electrical interfaces out through vertical vias in the substrate. Finally, a plastic shell is used for encapsulation to protect the internal architecture.

[0081] This embodiment eliminates the gold wire leads in traditional packaging by using embedded PCB technology, greatly reducing the commutation loop inductance of the T-type three-level circuit. Through the spatial overlap design of the main power lines of the rewiring power layer L1 with the midpoint compensation plane of the control and auxiliary power layers L2, spatial decoupling of the power loop and control loop is achieved, effectively suppressing voltage spikes and dv / dt noise coupling under high-frequency switching, and significantly improving the module's power density.

[0082] This invention also provides an electronic device comprising a single-phase T-type three-level power module based on embedded packaging as described above.

[0083] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An embedded package-based single-phase T-type three-level power module, characterized by, It includes, from bottom to top, a power copper foil layer, a chip layer, a control and auxiliary power layer, and a redistribution power layer; wherein: The power copper foil layer includes a substrate and a vertical through-hole disposed on the outer periphery of the substrate, and is electrically connected to the redistribution power layer through the vertical through-hole; A chip layer is disposed above the power copper foil layer and has a cavity. Four power semiconductor chips are coplanarly embedded in the cavity and electrically connected to form a single-phase T-type three-level circuit. A control and auxiliary power layer is disposed above the chip layer. It includes a driving wiring area and a non-driving wiring area. The non-driving wiring area forms a midpoint compensation plane. The midpoint compensation plane is electrically connected to the midpoint terminal of the single-phase T-type three-level circuit. The midpoint compensation plane is a continuous copper foil plane disposed in the non-driving wiring area. A redistribution power layer is disposed above the control and auxiliary power layer, and a main power line is formed on its surface; the power semiconductor chip, the control and auxiliary power layer, and the redistribution power layer are vertically electrically interconnected through an array of electroplated microvias; the redistribution power layer also includes a metallized protective buffer structure formed by the main power lines extending downward through the microvia array, and the metallized protective buffer structure covers the electrodes of the power semiconductor chip; Wherein, the projection of the midpoint compensation plane in the direction perpendicular to the redistribution power layer at least partially covers the main power line, so that the main power line and the midpoint compensation plane are spatially coupled.

2. The embedded package-based single-phase T-type three-level power module of claim 1, wherein: The projection of the midpoint compensation plane in the direction perpendicular to the redistribution power layer covers 60%-95% of the main power line.

3. The embedded package-based single-phase T-type three-level power module of claim 1, wherein: It also includes an outer shell layer, which includes an outer shell and an external electrical interface disposed on the outer shell, the external electrical interface being electrically connected to the redistribution power layer.

4. The embedded package-based single-phase T-type three-level power module of claim 1, wherein, It also includes a copper base plate layer and an insulating layer, wherein the insulating layer is disposed between the copper base plate layer and the power copper foil layer.

5. The embedded package-based single-phase T-type three-level power module of claim 1, wherein, The vertical distance between the control and auxiliary power layer and the chip layer is 0.05mm~0.08mm; the vertical distance between the redistribution power layer and the control and auxiliary power layer is 0.08mm~0.15mm.

6. An electronic device, comprising: Includes the single-phase T-type three-level power module based on embedded packaging as described in any one of claims 1 to 5.

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