Characterizing path margin monitoring without using scan chains

Abstract

An integrated circuit device includes a scan chain and a path margin monitoring unit (PMU) on a single die. The scan chain tests a signal path in the integrated circuit device. The PMU includes path monitoring circuitry and self-test circuitry. Path monitoring circuitry monitors a delay in propagation of a signal along a signal path. The self-test circuitry tests the path monitoring circuitry and reports test results via a communication path other than the scan chain.

Description

Technical Field

[0001] This disclosure generally relates to silicon lifecycle management (SLM) systems. Specifically, this disclosure relates to characterization path margin monitoring. Background Technology

[0002] As technology nodes shrink and device complexity and gate count increase, some methods for characterizing circuits during manufacturing may become insufficient to optimize their performance. With the emergence of mission-critical applications such as automotive electronics or health monitoring devices, fault avoidance and prediction are increasingly important requirements for control electronics in these applications. Summary of the Invention

[0003] In some aspects, an integrated circuit device includes a path margin monitoring unit (PMU), which comprises a path monitoring circuitry and a self-test circuitry. The path monitoring circuitry monitors the delay in signal propagation along the signal path within the integrated circuit device. The self-test circuitry tests the path monitoring circuitry and reports the test results via a communication path other than the scan chain used to test the signal path within the integrated circuit device.

[0004] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other technologies related to any of the foregoing aspects. Attached Figure Description

[0005] This disclosure will be more fully understood from the following detailed description and the accompanying drawings illustrating embodiments of the present disclosure. The drawings are provided to give knowledge and understanding of embodiments of the present disclosure and are not intended to limit the scope of the disclosure to these particular embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0006] Figure 1 This is a block diagram of an integrated circuit with a built-in path margin monitoring system according to some embodiments of the present disclosure.

[0007] Figure 2A This is a block diagram of a path margin monitoring unit (PMU) according to some embodiments of the present disclosure.

[0008] Figure 2B It is shown Figure 2A The timing diagram of the operation of the path monitoring circuit system.

[0009] Figure 3A This is a block diagram of a PMU operating in monitoring mode according to some embodiments of the present disclosure.

[0010] Figure 3B This is a flowchart of a PMU operating in monitoring mode according to some embodiments of the present disclosure.

[0011] Figure 3C This is a timing diagram illustrating the operation of multiple PMUs in response to multiple test modes according to some embodiments of the present disclosure.

[0012] Figure 3D This is a delay table for different signal paths according to some embodiments of this disclosure.

[0013] Figure 4 This is a block diagram of a PMU having a self-test circuit system with internal circuitry for testing path monitoring circuitry, according to some embodiments of the present disclosure.

[0014] Figure 5 This is a block diagram of a PMU with a self-test circuit system having external circuitry for testing path monitoring circuitry, according to some embodiments of the present disclosure.

[0015] Figure 6 Flowcharts depicting various processes used during the design and manufacture of integrated circuits according to some embodiments of the present invention.

[0016] Figure 7 A diagram depicts an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0017] Various aspects of this disclosure relate to characterizing path margin monitoring without using a scan chain. In digital circuits, signals propagate between sequential circuits such as flip-flops and registers according to a timing sequence determined by a clock. For a digital circuit to operate correctly, these signals must arrive at the next sequential circuit at least a certain amount of time before the relevant clock signal. The difference between the time a signal arrives and the nearest possible arrival time is called timing margin or path margin, or simply margin.

[0018] During integrated circuit design, the timing of analog circuitry ensures sufficient margin (e.g., greater than a minimum threshold margin) along different signal paths within the integrated circuit. However, the actual margin in the manufactured chip may differ from the analog margin, and the margin can vary as a function of temperature and voltage. Furthermore, the margin can also change over time as the chip ages. Therefore, the ability to characterize and monitor the actual margin of different signal paths in operating a chip is beneficial.

[0019] Path margin monitoring units (PMUs) can be distributed throughout an integrated circuit. A PMU is a circuit that measures the delay along different signal paths within an integrated circuit. Because they are part of the circuitry within the integrated circuit, it is useful to be able to test that the PMUs operate as needed and do not exhibit manufacturing or other defects.

[0020] Scan chains are a method for testing circuit systems within integrated circuits. Scan chains provide access to the internal workings of an integrated circuit. This allows values ​​to be set and read from internal circuits via the scan chain. In this way, a test pattern can be applied at one internal point within the chip, and the corresponding response at another internal point can be read. This simplifies testing because more signal values ​​and signal paths are accessible. Furthermore, multiple test points can be connected in series to form a scan chain. This allows for the parallel testing of multiple signal paths. Automated Test Pattern Generation (ATPG) is an automated process for generating test patterns, and test patterns for different circuits can be compressed as part of this process.

[0021] Scan chains can be used to test PMUs. However, this has several drawbacks. First, including PMU testing within a scan chain architecture means that PMU testing is integrated with the testing of other circuits in the scan chain architecture. However, since the PMU monitors conditions on the circuitry while other circuits implement the actual functionality, it may be desirable to test the PMU system separately from or at different times from the functional circuitry on the device. Furthermore, to be included in a scan chain architecture, the PMU system must be inserted into the design early enough to be included in the scan chain. However, in a standard design flow, monitoring functions and the PMU can be added later in the design phase. Designers can design the functional circuitry and insert the corresponding scan chain first, then insert the PMU later. Additionally, later changes to the PMU will also require updates to the scan chain architecture.

[0022] In some respects, the PMU includes a path monitoring circuitry and a self-test circuitry. When the PMU operates in monitoring mode, the path monitoring circuitry monitors the delay of signal propagation along the signal path in the integrated circuit. When the PMU operates in self-test mode, the self-test circuitry tests the path monitoring circuitry. The results of the self-test mode are reported via a communication path different from the scan chain. For example, the PMU can be connected to the chain according to IEEE 1687. The IEEE 1687 interface is a network standard for accessing internal chip data over a serial network. To accommodate this self-test approach, some hardware changes are made to the PMU compared to a PMU connected as part of a scan chain, and some changes are also made to the test mode. Examples of these changes will be described in more detail below.

[0023] The technical advantages of this disclosure include, but are not limited to, the following: Separating the PMU system from the scan chain architecture allows it to be designed and operated separately from the scan chain. The PMU can be inserted after the scan chain has been designed and inserted, and the PMU system can be modified later during the design phase. Furthermore, the PMU can be tested and operated separately from the scan chain architecture used to test the functional circuitry system.

[0024] As an example, Figure 1 This is a block diagram of an integrated circuit with a built-in path margin monitoring system according to some embodiments of the present disclosure. In this particular example, the integrated circuit 100 is divided into four sectors, each sector having four processor cores 110 and associated logic 112. The integrated circuit also includes a main central processing unit (CPU) 114, on-chip memory 116, and input / output (I / O) functions 118, such as serializer / deserializers (Serdes), high-speed peripheral component interconnect (PCIe), high-definition multimedia interface (HDMI), and dual data rate (DDR).

[0025] The PMU system includes instances of PMU circuitry, shown as black squares, some of which are labeled 130, and a PMU controller 150. Instances of PMU circuitry 130 are distributed throughout the integrated circuit to monitor path margins at different points across the integrated circuit. Figure 1 For convenience, the PMU circuit 130 is not shown in every block. In an alternative embodiment, the PMU circuit 130 may also be inserted into other blocks. The PMU circuit 130 is integrated side-by-side with the monitored signal path. As a result, the integrated circuit can be monitored in real time.

[0026] The PMU controller 150 is also integrated on the chip. Figure 1 In this diagram, it is shown as a single block, but it can be implemented in a distributed manner. The PMU controller 150 communicates with the PMU circuitry 130. The controller 150 sends control signals 140 to the PMU circuitry 130. For example, the PMU system can have different operating modes, including a self-test mode and a monitoring mode. In self-test mode, the PMU system performs tests on the PMU circuitry itself to ensure it operates correctly. In monitoring mode, the PMU system measures the delay along the signal path, thus providing real-time information about chip operation. The PMU controller 150 sends control signals 140 to the PMU circuitry to configure them for the current operating mode.

[0027] The PMU controller 150 also receives data 160 from the PMU circuitry. In monitoring mode, this data 160 can indicate the delay of the monitored signal. The controller 150 can analyze these signals to provide path margin monitoring capabilities across integrated circuits. For example, it can combine data from individual PMU circuits to provide a chip-level model of path margin.

[0028] In self-test mode, this data 160 can indicate which PMU circuits 130 are defective. Data 160 is transmitted via a communication path rather than through a scan chain used to test functional circuit systems. For example, PMU circuits 130 can be chained together according to IEEE 1687.

[0029] Because both the PMU circuit 130 and the PMU controller 150 are on-chip, the PMU system can provide real-time monitoring of path headroom across the integrated circuit. The data generated by the PMU system can be used on-chip. For example, path headroom is affected by operating voltage, temperature, and clock speed. Path headroom measurements can be used as feedback to other circuitry on the chip, which can then modify their operation accordingly. For instance, if path headroom begins to degrade in one part of the chip, the clock speed can be reduced, or heat buildup can be reduced by increasing cooling or decreasing power consumption. On the other hand, if excessive path headroom exists in one part of the chip, the clock speed can be increased, or increased heat buildup can be allowed by reducing cooling or increasing power consumption. The collected PMU data can be used to explore operational limitations such as clock speed and voltage.

[0030] Monitoring data generated by the PMU system can also be used to monitor changes in path headroom during chip lifespan. Current path headroom data can be compared with historical data to identify trends and predict future problems. Monitoring data can also be analyzed off-chip. For example, more complex analyses may require computing resources unavailable on-chip, and storing long-term captured PMU data may require more space than is available on-chip. Analysis can also combine PMU data with other data unavailable on-chip, such as external measurements of temperature or power consumption. As another example, monitoring data from multiple chips can be analyzed together to provide a view larger than a single chip on a board, a rack-mounted device, or other environments.

[0031] Figure 2A This is a block diagram of a path margin monitoring unit (PMU) 200 according to some embodiments of the present disclosure. The block diagram illustrates the operation of the path monitoring circuitry 205 within the PMU during monitoring mode. Figure 2B This is a timing diagram showing the operation of the path monitoring circuit system 205. Figure 2A Signal path 264, monitored by PMU 200, is shown. Signal path 264 begins with sequential circuit 261, propagates through combinational circuit system 262, and terminates with sequential circuit 263. In this example, sequential circuits 261 and 263 are flip-flops (also referred to herein as "flops"), and both the initiating flip-flop 261 and the terminating flip-flop 263 are timed by a common clock signal. For clarity, this example shows one initiating flip-flop 261, but multiple initiating flip-flops can be used to generate the functional signal received by the terminating flip-flop 263.

[0032] Signal path 264 is tapped at point 266, and PMU 200 monitors the signal delay at this point. This signal is one of the inputs to multiplexer 260, and... Figure 2AThe path is marked as path 1. P.Sel (Path Selection) is the selection signal for the multiplexer, which can be provided by the PMU controller. When multiplexer 260 is set to select path 1, the monitored signal 266 is selected and routed to multiplexer output 265. Path monitoring circuitry 205 monitors the delay of this signal. Path monitoring circuitry 205 receives the signal propagating along the monitored path 1 and also receives the corresponding clock signal. The monitored signal is compared with a delayed version of the signal to determine the amount of delay that would cause a mismatch between the monitored signal and the corresponding delayed version of the signal. The amount of delay is a measure of the path margin of the signal path. Path monitoring circuitry 205 outputs a monitoring signal 255 representing the path margin and / or delay along signal path 264.

[0033] The path monitoring circuitry system 205 includes two flip-flops 210 and 230, both timed by the same clock signal as flip-flop 263. For convenience, they are referred to as shadow flip-flop 210 and capture flip-flop 230. Shadow flip-flop 210 receives the monitored signal 265 without any additional delay. Capture flip-flop 230 receives a delayed version of the monitored signal 265. Here, the monitored signal 265 is input to a configurable delay circuit 220, which adds an adjustable amount of delay. A delay selection signal D.Sel determines the amount of delay, which in this example is a multiple of a certain basic delay Δ. The D.Sel signal can be determined directly or indirectly by the PMU controller. For example, the controller can set the operating mode of PMU 200, and then PMU 200 can determine the sequence of P.Sel values ​​applied over time. Alternatively, the controller can send the P.Sel signal directly to the PMU.

[0034] Comparator 240 (e.g., XOR or XNOR) compares a reference version 215 from shaded flip-flop 210 with a delayed version 235 from capture flip-flop 230. If the two versions 215 and 235 are the same, the output is indicated as pass (P), or if the two versions 215 and 235 are different, the output is indicated as fail (F). Monitor flip-flop 250 captures P or F using the same clock signal as the other flip-flops.

[0035] Figure 2B This is a timing diagram illustrating the operation. In this example, signal path 264 is timed by clock signal CLK. The monitored signal 265 toggles between 0 and 1 and has a certain propagation delay δ. Figure 2B The top row shows the input 213 of the shadow trigger 210, which is simply a toggle signal with a delay δ. Figure 2BThe dashed line shows the point in time when the CLK signal causes flip-flops 210 and 230 to capture their input values ​​(e.g., at the rising edge of the clock). The shaded flip-flop 210 receives signal 213 and captures logic 1. It outputs signal 215, which is a reference version of the monitored signal. For clarity, Figure 2B The value of output signal 215 is considered only after the second CLK is triggered.

[0036] Below, the timing diagram of the shaded flip-flop 210 shows five delayed versions 233A-233E from the input to the capture flip-flop 230, where the delay ranges from 0 for 235A to 4 Δ for 235E. Here, Δ is the base delay of the configurable delay circuit 220. The base delay depends on the technology node. For example, at more advanced nodes, the base delay could be approximately 15 ps. The timing of flip-flops 210 and 230 is determined by the CLK signal.

[0037] Version 233A has zero delay, and if the configurable delay is set to that delay, the capture trigger 230 will also capture logic 1 as output 235A. Versions 233B and 233C have an increased delay, but the logic 1 value still arrives within sufficient time to be captured by trigger 230, resulting in output signals 235B and 235C. In versions 233D and 233E, the delay exceeds the available path margin, so the capture trigger 230 will capture the next bit, which is logic 0, as output signals 235D and 235E.

[0038] The corresponding output 245 of comparator 240 is shown in the right column. P stands for pass, meaning the signal path has sufficient path margin to continue operating correctly, even with additional time delay. F stands for fail, meaning the path margin is insufficient to accommodate the additional delay. In this example, comparator 240 is an XOR gate. When the two inputs are the same, the XOR gate produces logic 0, which is pass P in this case. An XOR output of logic 1 means the two inputs are different, which is fail F. Versions 233A-233C pass, and versions 233D-233E fail. From this, it can be inferred that the actual path margin is between 2Δ and 3Δ.

[0039] exist Figure 2A In the example circuit shown, not all delay versions 233A-233E are compared in every clock cycle. Instead, the configurable delay 220 produces only one delay version per clock cycle. Other delay versions are compared in other clock cycles. In alternative versions, multiple values ​​can be compared in a single clock cycle if additional flip-flops are added to capture the different versions. However, this increases the area of ​​the PMU, which will be multiplied by the number of PMUs on the integrated circuit.

[0040] This explanation pertains to monitoring a single signal path 264 by a single PMU. Multiplexer 260 allows multiple signal paths to be monitored by a single PMU. Figure 2A In the system, there are multiple signal paths 1 to Path K. The selection input P.Sel of the multiplexer 260 selects which signal is connected to the path monitoring circuitry system 205.

[0041] Now consider the situation where multiple PMUs operate concurrently to monitor different signal paths, such as Figure 3A and Figure 3B As shown. Figure 3A yes Figure 2A The PMUs are individually configured, but with additional circuitry for parallel monitoring. Specifically, the monitoring triggers 250 of different PMUs are chained together via TDI and TDO ports. TDI / TDO are serial input / outputs of the IEEE 1687 interface. TDI is the input connection from the previous PMU in the chain to this PMU, while TDO is the output connection from this PMU to the next PMU in the chain. Figure 3A It also includes an additional AND gate 374 and an OR gate 372, with the AND gate 374 taking the inversion of the scan enable (~SE) as input and the OR gate 372 looping back from the output of the monitoring trigger 250. Figure 3B This is a flowchart of parallel monitoring.

[0042] Suppose there are N PMUs connected in the chain. The output TDO of one PMU is connected to the input TDI of the next PMU in the chain, and vice versa. In this way, the contents of the monitoring triggers 250 in the chain can be read out through the chain. If there are N PMUs in the chain, each PMU can monitor K possible paths via P. Sel, and each PMU can be set for L different delays via D. Sel. Then, if each possible combination of (PMU, P. Sel, D. Sel) is tested individually and the result P / F is read out individually, then all possible signal paths will be monitored using N×K×L readouts of the chain.

[0043] However, because they are separate circuits and monitor separate signal paths, the N PMUs can operate in parallel. For example, all N PMUs can monitor the path specified by P. Sel for a delay specified by D. Sel, and cycle through multiple test modes used to execute that path. At the end, the P / F stored in all the monitoring flip-flops 250 can be read out via a chain. However, the output 255 of the monitoring flip-flops 250 follows the output 245 of the XOR gate 240. When output 245 rises to logic 1, output 255 will rise to logic 1 (failure), and when output 245 falls to logic 0, output 255 will fall to logic 0 (pass). If the monitoring flip-flops 250 are not read out in every cycle, F may be missed. If output 255 produces F on a cycle that is not read out, such as for an earlier test mode, and then changes to P on a read out cycle for a later test mode, F will be missed. In one embodiment, the output of the monitoring trigger 250 is fed back to the input of the OR gate 372, and the output of the OR gate 372 is input to the monitoring trigger 250, such as... Figure 3A As shown. This loop, which feeds the output of the monitoring trigger 250 back to the "OR" gate 372, is used to freeze any failure (logic 1). If the output 255 has ever reached logic 1, it will remain at logic 1.

[0044] All PMU cycles through different test modes. If a fault occurs for any test mode, the monitoring trigger 250 will output F during the chain readout. When considering the next combination of path and delay, the monitoring trigger 250 is first reset. This is achieved by adding an AND gate 374 and a scan enable SE. SE is a signal that controls the scan chain that provides test modes to signal path 264. When SE is logic 1, the test mode is shifted into signal path 264. When SE is logic 0, signal path 264 operates in response to the loaded test mode. This is when signal monitoring occurs. Figure 3A In the XOR 240, when SE is logic 1, then ~SE (not SE) is logic 0, and logic 0 propagates to the input of XOR 240, meaning that output 245 is logic 0. This resets the shadow flip-flops and capture flip-flops 210 and 230, so that the value of the watch flip-flop 250 is unaffected during the shift.

[0045] Once the test mode is loaded for the new signal path, it is ready to be monitored. The scan enable SE is logic 0, and ~SE is logic 1, which effectively allows AND gate 374 to pass. Signal 265 will pass through AND gate 374. The path monitoring circuit 205 receives the signal from the new signal path being monitored as signal 265 and operates as previously described.

[0046] Figure 3B This is a flowchart of the process. At 380, the signal path (P. Sel) selection is set for the PMUs in the chain. Each PMU then monitors the selected signal path. At 382, ​​the delay (D. Sel) selection is also set for the PMUs in the chain. At 384, different test modes are shifted in and applied to the signal paths. As a result of the freeze loop, if a fault is encountered for any test mode, the monitoring trigger 250 captures F. At 386, P / F stored in the monitoring trigger 250 is read out. This process is then repeated for other delays and other signal paths. Figure 3B In this diagram, it is shown as two loops. For a given path k, the inner loop 388 cycles through different delays, while the outer loop 389 cycles through different paths k.

[0047] exist Figures 3C-3D An example of this is shown in the figure. Figure 3C It shows in Figure 3B The timing diagram for loop passing the test mode at position 384. Figure 3C Loops 380 or 382 are not shown. Figure 3C The scan enable (SE) and clock are shown. Figure 3C The outputs of the shadow flip-flop, capture flip-flop, and monitor flip-flop for the two PMUs (PMU1 and PMU2) are also shown. When the scan enable SE is logic 1, a test mode is shifted in to test the signal path of the PMU. Not all test modes need to be applied to all PMUs. When the scan enable SE is logic 0, the signal path is operated and produces results in response to the test mode.

[0048] For test mode 1, the outputs of shadow flip-flops 311(1), 312(1) and capture flip-flops 321(1), 322(2) are the same for PMU1 and PMU2, so the test passes as indicated by the monitoring flip-flops 331(1), 332(2) which store logic 0 for both PMUs. For test mode 2, PMU1 fails because shadow flip-flops 311(2) and capture flip-flops 321(2) have different logic levels. The value of monitoring flip-flop 331(2) of PMU1 will be recorded as logic 1 for failure. PMU2 passes mode 2, so its monitoring flip-flop 332(2) remains at logic 0. For mode 3, PMU1 passes, but monitoring flip-flop 331(3) fails due to logic 1. Figure 3AThe feedback loop shown remains in failure (logic 1). This is the expected result. Otherwise, the failure of mode 2 would be lost. PMU2 causes mode 3 to fail, so its monitoring trigger 332 (3) records logic 1 (failure). For any subsequent test modes asserted by P. Sel and D. Sel in this iteration, the monitoring triggers of PMU1 and PMU2 will remain in the failure state (logic 1). At the end of the test mode sequence, the output response of the monitoring triggers is transmitted through the 1687 interface (in Figure 3B 386 locations were serially scanned out.

[0049] This applies to the different values ​​of P. Sel and D. Sel via Figure 3B Loops 380 and 382 repeat. The final result is as follows: Figure 3D The table shown illustrates the pass / fail results for each P. Sel and each D. Sel. Each row represents a different signal path (P. Sel). Each column represents a different delay (D. Sel). The path margin for each signal path can be determined from this table. For example, the path margin for path 1 (P. Sel=1) is equal to the delay corresponding to D. Sel=6.

[0050] Figures 4-5 The PMU's self-test mode is shown. Figure 4 It shows Figure 3A The PMU has an additional self-test circuitry for testing the circuitry within the path monitoring circuitry system 205. The self-test circuitry system includes a feedback loop from the output of the shadow flip-flop 210 to the input of the shadow flip-flop. This loop includes an inverter 472 connected between the input of the shadow flip-flop 210 and the input of the multiplexer 260. When the multiplexer 260 selects the loop, the loop operates as an oscillator to generate a toggle signal and apply it to the path monitoring circuitry system 205. The toggle signal has a near-zero propagation delay because it is generated internally to the PMU. Therefore, the path monitoring circuitry system 205 should generate a path P (logic 0) for all delay values ​​within the configurable delay 220. If an error exists in one of the delay branches, the value may be fixed instead of toggled. This will result in a failure F when the branch is active. In self-test mode, the configurable delay circuitry 220 tests all signal paths within the configurable delay circuitry. The freeze loop circuitry 255-372 preserves the occurrence of any failure F.

[0051] Figure 5 It shows Figure 3AThe PMU has additional self-test circuitry for testing circuitry outside the test path monitoring circuitry system 205. These are primarily through different paths k of the multiplexer 260. The additional test circuitry system includes a comparator 582 and a corresponding flip-flop 584, referred to as a toggle flip-flop. Using path 1 as an example, a toggle signal is generated on path 1, for example, by loading the corresponding test mode onto signal path 264 using a scan chain. Comparator 582 compares the input 213 and output 215 of the shaded flip-flop 210. Since the inputs are toggled, the inputs and outputs should always be complementary, and XOR gate 582 should produce logic 1, which is captured by the toggle flip-flop 584. However, if an error exists along path 1 to the shaded flip-flop, input 213 and output 215 can be the same, and XOR gate 582 will produce logic 0. The self-test can be looped through different paths k to test different circuitry within the PMU.

[0052] The toggle trigger 584 is part of a chain with a monitoring trigger 250. The self-test results stored in the two triggers 584 and 250 can be read out through the chain.

[0053] Figure 6 A set of exemplary processes 600 used during the design, verification, and manufacturing of an article of art, such as an integrated circuit, are illustrated to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be constructed and implemented as multiple modules or operations. The term "EDA" stands for "Electronic Design Automation." These processes begin with the creation of a product idea 610 with information provided by a designer, which is transformed to create an article of art using a set of EDA processes 612. When the design is completed, it is tape-out 634, which occurs when the pattern (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing facility to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, a semiconductor die is manufactured 636, and a packaging and assembly process 638 is performed to produce a finished integrated circuit 640.

[0054] The specifications of circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ​​(“HDLs”) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be transformed into logic-level register-transfer-level (“RTL”) descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of representation, as a more detailed description, adds more useful details to the design description, such as including more details of the described modules. These more detailed lower-level representations can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language used to specify lower-level representations that provide more detailed descriptions is SPICE, used for detailed descriptions of circuits with multiple analog components. Descriptions at each representation level are permitted to be used by the corresponding system at that layer (e.g., a formal verification system). The design process can use… Figure 6 The sequence is shown. The described process is implemented by an EDA product (or EDA system).

[0055] During system design phase 614, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0056] During logic design and functional verification 616, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of a circuit can be verified to generate outputs that match the specification requirements of the designed circuit or system. Functional verification can use simulators and other programs, such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, a specific system of components, referred to as a “simulator” or “prototype system,” is used to accelerate functional verification.

[0057] During the synthesis and design of the 618 test circuit, HDL code is transformed into a netlist. In some embodiments, the netlist can be a graph structure, where edges represent components of the circuit and nodes represent how the components are interconnected. Both HDL code and netlist are tiered artifacts that can be used by EDA products to verify that the integrated circuit performs as specified during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Furthermore, the completed integrated circuit can be tested to verify that it meets specification requirements.

[0058] During netlist verification (620), the netlist is checked to ensure it conforms to timing constraints and HDL code. During design planning (622), the overall planar diagram of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0059] During layout or physical implementation 624, physical placement (location of circuit components such as transistors or capacitors) and routing (connecting circuit components via multiple conductors) occur, and cells can be selected from a library to enable specific logic functions. As used herein, the term "cell" can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are implemented as physical structures and simulations. Parameters, such as dimensions, are specified for selected cells (based on "standard cells"), and they are made accessible in a database for use in EDA products.

[0060] During the analysis and extraction phase 626, circuit functionality is verified at the layout level, allowing for refinement of the layout design. During physical verification 628, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and that the circuit functionality matches the HDL design specifications. During resolution enhancement 630, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0061] During the tape-out process, data is created for producing a photomask (if appropriate, after applying photolithographic enhancement). During mask data preparation 632, the "tape-out" data is used to generate a photomask that is used to produce the finished integrated circuit.

[0062] Computer systems (such as) Figure 7 The storage subsystem of the computer system (700) can be used to store some or all of the EDA products described herein, as well as the programs and data structures used by the units for developing libraries and by the physical and logical designs of the products that use the libraries.

[0063] Figure 7 An example machine of computer system 700 is shown, in which a set of instructions can be executed to cause the machine to perform any or more methods discussed herein. In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate with the capabilities of a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0064] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) specifying the actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein.

[0065] Example computer system 700 includes processing devices 702 that communicate with each other via bus 730, main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage device 718.

[0066] Processing device 702 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor that implements other instruction sets or combinations of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 may be configured to execute instructions 726 for performing the operations and steps described herein.

[0067] The computer system 700 may also include a network interface device 708 that communicates via a network 720. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), a graphics processing unit 722, a signal generation device 716 (e.g., a speaker), a graphics processing unit 722, a video processing unit 728, and an audio processing unit 732.

[0068] Data storage device 718 may include machine-readable storage medium 724 (also referred to as non-transitory computer-readable medium) on which one or more instruction sets 726 or software implementing any one or more methods or functions described herein are stored. During the execution of instruction 726 by computer system 700, instruction 726 may also reside wholly or at least partially in main memory 704 and / or processing device 702, which also constitute machine-readable storage medium.

[0069] In some implementations, instruction 726 includes instructions that implement the functions corresponding to this disclosure. Although machine-readable storage medium 724 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine and processing device 702 to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0070] Certain parts of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most efficient way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. These operations are those that require the physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0071] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. Unless otherwise stated, as is apparent from this disclosure, it should be understood that throughout the specification, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities within the registers and memories of the computer system into other data representing physical quantities similarly represented within the computer system's memory or registers or other such information storage devices.

[0072] This disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specifically constructed for its intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0073] The algorithms and demonstrations presented herein do not inherently relate to any particular computer or other device. Various other systems can be used with the program based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the method. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of the invention described herein can be implemented using a variety of programming languages.

[0074] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0075] In the foregoing disclosure, implementations of this disclosure have been described with reference to specific example implementations thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the implementations of this disclosure as set forth in the following claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the drawings, and the same elements are labeled with the same numerals. Therefore, this disclosure and the drawings are to be considered illustrative rather than restrictive.

Claims

1. An integrated circuit device comprising multiple path margin monitoring units (PMUs), including: A path monitoring circuit system that monitors the delay of a signal propagating along a signal path in the integrated circuit device; as well as A self-test circuit system tests the path monitoring circuit system and reports test results via a communication path other than the scan chain used to test the signal path in the test integrated circuit device.

2. The integrated circuit device according to claim 1, wherein the path monitoring circuit system comprises: A shadow trigger that captures a reference version of the monitored signal; Delay circuit, the delay circuit being connected to a capture trigger, wherein the capture trigger captures a delayed version of the monitored signal; and A first comparator compares the reference version and the delayed version of the monitored signal.

3. The integrated circuit device of claim 2, wherein the self-test circuit system includes a feedback loop from the output of the shadow trigger to the input of the shadow trigger, the feedback loop including an inverter, and the feedback loop operates to generate a toggle signal and apply the toggle signal to the path monitoring circuit system.

4. The integrated circuit device of claim 2, wherein the path monitoring circuit system tests all signal paths in the delay circuit.

5. The integrated circuit device of claim 2, wherein the self-test circuit system further comprises a second comparator that compares the input of the shadow trigger with the output of the shadow trigger.

6. The integrated circuit device according to claim 2, wherein the path monitoring circuit system further comprises: A monitoring trigger is provided, which captures the result of the comparison; as well as The freeze loop circuit system freezes the state of the monitoring trigger once the comparison indicates that the reference version and the delayed version of the monitored signal are different.

7. The integrated circuit device according to claim 1, wherein the PMU further comprises: A multiplexer that multiplexes multiple signal paths into the path monitoring circuitry system, and the self-test circuitry system is configured to test the PMU in response to a flip signal propagating along the monitored signal path.

8. The integrated circuit device of claim 1, wherein the self-test circuit system is configured to generate a flip signal and apply the flip signal to the path monitoring circuit system to test the path monitoring circuit system.

9. The integrated circuit device of claim 1, wherein the self-test circuit is configured to test the PMU in response to a flip signal propagating along the monitored signal path.

10. The integrated circuit device according to claim 1, further comprising: A controller that controls the PMU; wherein the PMU is capable of operating in a monitoring mode using the path monitoring circuitry system and a self-test mode using the self-test circuitry system, and the controller configures the operating mode of the PMU.

11. A method comprising: Control signals are sent to multiple path margin monitoring unit (PMU) circuits to control the operation of the PMUs; The PMU is capable of operating in a monitoring mode and a self-test mode. In the monitoring mode, the PMU monitors the delay of signal propagation along the signal path in the integrated circuit device, and in the self-test mode, the PMU performs a self-test. as well as The monitoring results of the monitoring mode are received, and the test results are received from the self-test mode, wherein the monitoring results and test results are received via a communication path other than the scan chain used to test the signal path on the integrated circuit device.

12. The method of claim 11, wherein the communication path comprises a PMU chain.

13. The method of claim 12, wherein in the self-test mode, all PMUs in the chain concurrently run self-tests, and receiving test results includes receiving test results from all PMUs in the chain.

14. The method of claim 12, wherein in the monitoring mode, all PMUs in the chain concurrently monitor latency, and receiving monitoring results includes receiving monitoring results from all PMUs in the chain.

15. The method of claim 12, wherein the PMU is connected to the chain according to IEEE 1687.

16. The method of claim 12, further comprising: For the monitoring mode, The scan chain is used to shift the test mode into the signal path; as well as In response to the test mode, a control signal is sent to configure the PMU to monitor the latency.

17. The method of claim 12, wherein the delay of the monitoring signal comprises: The test is repeated through different test modes to determine whether the signal does not meet the path margin requirements. as well as If the signal does not meet any of the different test modes, a fault is reported.

18. A non-transient computer-readable medium comprising stored instructions, which, when executed by a processing device, cause the processing device to: Multiple path margin monitoring units (PMUs) are inserted into an integrated circuit design, wherein the PMUs are capable of operating in a monitoring mode that monitors the delay of signal propagation along the signal path in the integrated circuit and in a self-test mode that tests the PMUs; and A communication path is inserted into the PMU to report the results of the self-test mode, wherein the communication path is separate from the scan chain used to test the signal paths in the integrated circuit.

19. The non-transient computer-readable medium of claim 18, wherein the PMU and communication path are inserted separately from the scan chain.

20. The non-transient computer-readable medium of claim 18, further comprising: Generate scan chain instructions for setting the signal path during the self-test mode.

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