current sensor

Abstract

The present disclosure relates to a current sensor. A current sensor for measuring an alternating current in a conductor comprises an inductor having first and second connection points whose potentials correspond to first and second measurement voltages Va, Vb, respectively; a processing unit connected to the first and second connection points for converting an induced voltage of the inductor into an output signal representing an alternating current measurement. The processing unit comprises a linear compensation network and first and second analog-to-digital converters connected to the first and second connection points, respectively. The linear compensation network comprises a voltage divider connected between the first and second connection points, wherein a point is at a mid-point potential between the first and second potentials; a subtractor connected to outputs of the first and second analog-to-digital converters; a mid-point voltage adjustment unit connected to the subtractor or to outputs of the first and second analog-to-digital converters for adjusting the mid-point potential based on an output thereof to maintain absolute values of Va and Vb greater than an error threshold for an alternating current having a peak amplitude less than a small amplitude current threshold.

Description

Technical Field

[0001] This invention relates to a current sensor for measuring alternating current in a conductor, and more particularly, to a current sensor based on a Rogowski coil. Background Technology

[0002] Current sensors for measuring alternating current in a conductor based on magnetic induction are known in the prior art (see [link]). Figures 1 to 3 This type of current sensor 1' includes: an inductor 2' for providing an induced voltage generated by a time-varying magnetic field produced by an alternating current in conductor 3'; and a processing unit 10' configured to convert the induced voltage into an output signal representing the alternating current by integrating the induced voltage over time and calibrating the gain of the coil. For the example Rogowski coil, the induced voltage e(t) in inductor 2' is given by the following equation.

[0003] ,

[0004] S is the cross-section of the Rogowski coil, that is, the area of ​​a small loop.

[0005] n is the number of turns.

[0006] l is the average closed path of the Rogowski coil surrounding the primary conductor 3'.

[0007] µ0 is the vacuum permeability.

[0008] I p It is the primary current in the primary conductor 3'.

[0009] M is the obtained proportionality constant.

[0010] Typically, these current sensors are based on a fully analog solution if an analog output signal is desired. In these devices, the processing unit 10' includes an analog integrator 110', which comprises an operational amplifier 111' and passive components, such as... Figure 2 and Figure 3 As shown in the image.

[0011] Although seemingly simple, this method requires expensive, high-quality components. Furthermore, in most cases, gain calibration of the coil needs to be performed manually by adjusting potentiometer 44'.

[0012] The market trend is towards achieving higher accuracy over an extended temperature range. A drawback of fully analog solutions is that passive components are sensitive to temperature variations, meaning that temperature compensation is often required.

[0013] Another problem with purely analog integrators is that they integrate even the slightest parasitic offset (e.g., due to operational amplifiers), resulting in an output that will always be unstable and will eventually drift, causing either the upper or lower level to saturate. Therefore, a static gain or active compensation stage must be used to limit this drift. Offset suppression circuits have the disadvantage of introducing phase errors of varying degrees, which poses a major problem for power measurements. Therefore, in this type of application, it is necessary to add a phase shift compensation stage, typically composed of a low-pass filter. Unfortunately, the correction will not be constant but will depend on the frequency, meaning that the design will need to be optimized to minimize the phase difference at the fundamental frequency (typically 16 2 / 3, 50, 60, or 400 Hz).

[0014] TEDS (Electronic Data Sheets for Sensors, IEEE 1457.4) are being used more and more: key parameters of these sensors are stored in memory, and customers read this memory to adjust their front end and measurements (see [link to documentation]). Figure 3 ). Summary of the Invention

[0015] In view of the above, the object of the present invention is to provide an accurate and low-cost current sensor for measuring alternating current.

[0016] Advantageously, it provides an accurate current sensor over a wide measurement range of current amplitude.

[0017] The advantage is that it provides an accurate current sensor over a wide temperature range.

[0018] Advantageously, it provides a current sensor that can be easily and quickly calibrated.

[0019] Advantageously, it provides a current sensor with small phase error.

[0020] Advantageously, it provides current sensors capable of providing TEDS data.

[0021] The object of the present invention is achieved by providing the system according to claim 1.

[0022] The dependent claims set forth various advantageous features of embodiments of the invention.

[0023] This document discloses a current sensor for measuring alternating current in a conductor. The current sensor includes: an inductor having a first connection point at a first potential corresponding to a first measurement voltage Va relative to ground and a second connection point at a second potential corresponding to a second measurement voltage Vb relative to ground; and a processing unit connected to the first and second connection points and configured to convert an induced voltage induced in the inductor by the alternating current into an output signal of the current sensor representing a measured value of the alternating current.

[0024] The processing unit includes a first analog-to-digital converter connected to a first connection point, a second analog-to-digital converter connected to a second connection point, and a linear compensation network.

[0025] Linear compensation networks include:

[0026] A voltage divider is connected between a first connection point and a second connection point, and has a midpoint potential located between the first potential and the second potential.

[0027] The subtractor is connected to the output of the first analog-to-digital converter and the output of the second analog-to-digital converter.

[0028] A midpoint voltage regulation unit, connected to the output of a subtractor or the output of a first analog-to-digital converter and a second analog-to-digital converter, is configured to regulate the midpoint potential based on the output of the subtractor or the output of the first analog-to-digital converter and the second analog-to-digital converter, so as to keep the absolute values ​​of the first measured voltage Va and the second measured voltage Vb greater than the error threshold Th for AC currents with peak amplitudes less than the small amplitude current threshold Th1.

[0029] In an advantageous embodiment, the midpoint voltage adjustment unit is configured to adjust the midpoint potential based on the output of the subtractor or the output of the first analog-to-digital converter and the second analog-to-digital converter, so as to keep the absolute values ​​of the first measured voltage Va and the second measured voltage Vb greater than the error threshold Th for a voltage less than twice the small amplitude voltage threshold Th2 between the first connection point and the second connection point, wherein an AC current having a peak amplitude equal to the small amplitude current threshold Th1 induces a peak induced voltage, which generates a voltage between the first connection point and the second connection point that is twice the small amplitude voltage threshold Th2.

[0030] In an advantageous embodiment, the midpoint voltage adjustment unit is configured to detect that the absolute values ​​of the measured voltages Va and Vb at the input terminals of the first and second analog-to-digital converters relative to ground are both greater than a small-amplitude voltage threshold Th2, and thereby set the midpoint potential to ground.

[0031] In an advantageous embodiment, the midpoint voltage adjustment unit is configured to detect that the absolute value of at least one of the measured voltages Va and Vb at the input terminals of the first analog-to-digital converter and the second analog-to-digital converter is lower than a small-amplitude voltage threshold Th2, and thereby set the midpoint potential to an adjustment voltage ΔV that is higher or lower than ground.

[0032] In an advantageous embodiment, the regulating voltage ΔV is selected within the range of 0.25 to 0.75 of the small-amplitude voltage threshold Th2, for example, the regulating voltage ΔV is approximately half of the small-amplitude voltage threshold Th2.

[0033] In an advantageous embodiment, the midpoint voltage regulation unit includes a decimation filter connected to the output of the subtractor, configured to regulate the midpoint potential (φmid) based on the output of the decimation filter so as to keep the absolute values ​​of the measured voltages Va and Vb at the inputs of the first analog-to-digital converter and the second analog-to-digital converter greater than the error threshold Th for AC currents with peak amplitudes less than the small amplitude current threshold Th1.

[0034] In an advantageous embodiment, the midpoint voltage regulation unit further includes an absolute value unit and a comparator.

[0035] The absolute value unit can be configured to provide the absolute value of the output of the decimation filter, and the midpoint voltage adjustment unit can be configured to detect, via a comparator, that the absolute value of the output of the decimation filter is less than a predefined comparator voltage Vcomp, and thereby set the midpoint potential (φmid) to an adjustment voltage ΔV that is higher or lower than ground. The midpoint voltage adjustment unit can also be configured to detect, via a comparator, that the absolute value of the output of the decimation filter is greater than a predefined comparator voltage Vcomp, and thereby set the midpoint potential to ground.

[0036] In an advantageous embodiment, the inductor is a Rogowski coil.

[0037] In an advantageous embodiment, the linear compensation network and at least a portion of the first analog-to-digital converter and the second analog-to-digital converter are implemented in a field-programmable gate array (FPGA).

[0038] In an advantageous embodiment, the first analog-to-digital converter and the first analog-to-digital converter are ΣΔ modulators.

[0039] In an advantageous embodiment, the processing unit further includes an output signal processing circuit for generating an output signal of a current sensor representing an alternating current, wherein the output signal processing circuit is connected to the output of the subtractor and includes a digital low-pass filter for integrating the output signal of the subtractor.

[0040] In an advantageous embodiment, the digital low-pass filter has The transfer function is of the form α, where the coefficient α is preferably the reciprocal of a power of 2.

[0041] In an advantageous embodiment, the output signal processing circuit further includes a gain calibration unit for calibrating the gain of the inductor and / or compensating for the gain of the digital low-pass filter.

[0042] In an advantageous embodiment, the gain calibration unit includes a multiplier and a third ΣΔ modulator having a constant input corresponding to the gain of the inductor and / or the gain of the digital low-pass filter, wherein the output of the third ΣΔ modulator is connected to the input of the multiplier, wherein another input of the multiplier is connected to the output of the subtractor, and the output of the multiplier is connected to the input of the digital low-pass filter.

[0043] In an advantageous embodiment, the output signal processing circuit further includes a fourth ΣΔ modulator connected to the output of the digital low-pass filter.

[0044] In an advantageous embodiment, the output signal processing circuit further includes an analog low-pass filter connected to the output of the fourth ΣΔ modulator.

[0045] Other advantageous features of the invention will become apparent from the following detailed description of embodiments of the invention and the accompanying drawings. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a Rogowski coil;

[0047] Figure 2 This is a schematic diagram of a current sensor including a Rogowski coil and an analog integrator;

[0048] Figure 3 This is a schematic diagram of a current sensor that includes a Rogowski coil, an analog integrator, and a TEDS memory.

[0049] Figure 4 The diagram above shows a ΣΔ modulator implemented using a field-programmable gate array and passive components according to an embodiment of the present invention, and a typical output signal of the ΣΔ modulator (bottom).

[0050] Figure 5 yes Figure 4 A schematic diagram showing the relationship between the analog input and the ΣΔ equivalent output signal of the ΣΔ modulator illustrates the linear relationship at large signals (left) and in the unreliable region near zero (right).

[0051] Figure 6 This is a schematic diagram of a current sensor according to an embodiment of the present invention;

[0052] Figure 7This is a schematic diagram of the output signal processing circuit of a current sensor according to an embodiment of the present invention;

[0053] Figure 8 yes Figure 7 The low-pass filter in the image is plotted as a log-log graph of filter gain versus frequency.

[0054] Figure 9 This is a schematic diagram of a portion of the output signal processing circuit of a current sensor according to an embodiment of the present invention, used to generate an analog output signal. Detailed Implementation

[0055] Referring to the accompanying drawings, the current sensor 1 according to an embodiment of the present invention includes a primary current I supplied by the primary conductor 3. p Inductor 2, which generates an induced voltage e(t) from the time-varying magnetic field.

[0056] The inductor 2 has a first connection point 4a at a first potential φa and a second connection point 4b at a second potential φb for measuring the induced voltage e(t). Typically, the inductor 2 has a non-zero resistance during operation as a current sensor at the operating temperature (e.g., at room temperature). The circuit for measuring the induced voltage e(t) may further include one or more series resistors 22a, 22b between the first connection point 4a and the inductor 2 and / or between the second connection point 4b and the inductor 2.

[0057] The current sensor 1 also includes a processing unit 10 connected to the first connection point 4a and the second connection point 4b, the processing unit being configured to convert the induced voltage e(t) into an output signal of the current sensor representing an AC current measurement. In a preferred embodiment, the inductor 2 is a Rogowski coil. In a variant, the inductor 2 is a pickup coil.

[0058] The processing unit 10 of the current sensor 1 of the present invention is implemented at least partially using digital electronics, which replace the analog electronics of the purely analog solutions of the prior art. In a preferred embodiment, the processing unit 10 is implemented at least partially using a field-programmable gate array (FPGA) 11.

[0059] The use of digital electronic devices enables high precision stability over a wide temperature range because the accuracy of digital signal processing depends only on its clock frequency, which remains stable (with a frequency variation of a few parts per million per degree Celsius (ppm / ℃)).

[0060] The processing unit 10 includes an analog-to-digital converter, which is preferably a ΣΔ modulator. Figure 4The upper figure illustrates an exemplary implementation of a ΣΔ modulator 30 using FPGA 11 and passive components. The ΣΔ modulator 30 includes an analog comparator 31 and a D-type flip-flop 34 implemented in FPGA 11, as well as a passive integrator network including resistor 32 and capacitor 33. The comparator 31 may be part of FPGA 11 or external to FPGA, depending on the requirements. The comparator 31 may be implemented using an operational amplifier. The positive input of comparator 31 is used as the analog signal input of the ΣΔ modulator 30. The output of comparator 31 is connected to the data input D of the D-type flip-flop 34. The digital signal output of the ΣΔ modulator 30 is connected to the data output Q of the D-type flip-flop 34. The data output Q of the D-type flip-flop 34 is also connected to the negative input of comparator 31 via resistor 32. The negative input of comparator 31 is connected to ground via capacitor 33. The D-type flip-flop 34 is connected to the clock 35 of FPGA 11. Figure 4 The figure below shows a typical output signal s2 of a ΣΔ modulator compared to a linear analog input signal s1.

[0061] The equivalent output of a ΣΔ modulator is essentially linear with respect to the analog input (see [link]). Figure 5 (Left figure in the image). However, the linearity of the analog-to-digital converter (especially the linearity of the ΣΔ modulator) is affected by comparator errors (such as hysteresis or propagation time) at low input values. Figure 5 Compared to the left image, Figure 5 The right-hand image is magnified near zero. For analog input amplitudes below the error threshold (Th), the equivalent output signal of the ΣΔ modulator is zero. Therefore, in the near-zero region r0, roughly between -Th and +Th, the measurement is unreliable. For analog input amplitudes greater than Th in regions r1 and r2, the measurement is reliable, and in these regions the equivalent output signal is linear with respect to the analog input.

[0062] In practice, the alternating current to be measured mostly has a periodic waveform, especially a sinusoidal waveform. If the peak amplitude of the alternating current is large compared to the error threshold Th, then the relative error during the zero-crossing period is insignificant compared to the peak amplitude, and the measurement is reliable. If the peak amplitude of the alternating current is not much larger than the error threshold Th, then the relative error during the zero-crossing period is significant compared to the peak amplitude, and the measurement is unreliable.

[0063] Processing unit 10 includes a first analog-to-digital converter 30a connected to a first connection point 4a, a second analog-to-digital converter 30b connected to a second connection point 4b, and a linear compensation network 20.

[0064] The input terminal of the first analog-to-digital converter 30a is connected to the first measurement potential φa, and the input terminal of the second analog-to-digital converter 30b is connected to the second measurement potential φb.

[0065] In a preferred embodiment, the first analog-to-digital converter 30a and the second analog-to-digital converter 30b are ΣΔ modulators. The output of the ΣΔ modulator is a bit stream. Single-bit links are indicated by thin lines in the diagram.

[0066] The linear compensation network 20 is configured to correct the aforementioned errors for alternating currents with periodic waveforms whose peak amplitude is not significantly larger than the error threshold Th (e.g., the peak amplitude is less than 10 times, 100 times, or 1000 times the error threshold Th), based on the requirement regarding the relative error of the measured value with respect to the peak amplitude. For alternating currents with periodic waveforms whose peak amplitude is significantly larger than the error threshold Th (e.g., greater than 10 times, 100 times, or 1000 times the error threshold Th), the linear compensation network 20 maintains the aforementioned relative errors to a negligible small size during zero-crossing periods, thereby achieving the desired requirement regarding the relative error with respect to the peak amplitude.

[0067] The linear compensation network 20 includes a voltage divider 21 connected between a first connection point 4a and a second connection point 4b, and has a midpoint 4c at a midpoint potential φmid between the first potential φa and the second potential φb.

[0068] Voltage divider 21 includes a first measuring resistor 21a between the first connection point 4a and the midpoint 4c, and a second measuring resistor 21b between the midpoint 4c and the second connection point 4b. Voltage divider 21 may include additional series resistors 21a and 21b between the first connection point 4a and the second connection point 4b and the connection terminals of inductor 2.

[0069] The linear compensation network 20 also includes a subtractor 27 and a midpoint voltage regulation unit 23. The outputs of the first analog-to-digital converter 30a and the second analog-to-digital converter 30b are connected to the input of the subtractor 27.

[0070] Subtractor 4 subtracts the bit stream s2 from the two ΣΔ modulators 30a and 30b from the two-level digital output voltages {-V0, +V0} or {0, +V0}, generating a three-level digital output signal s3 represented by a multi-bit vector stream. The multi-bit link is indicated by a thick arrow in the diagram.

[0071] Direct arithmetic operations on ΣΔ bitstreams are feasible in FPGAs and have the following advantages:

[0072] Relatively inexpensive FPGAs can be used for these arithmetic operations. Developing alternative solutions such as silicon-based DSP slices or multipliers is more expensive.

[0073] These operations are performed without interrupting the data stream, thus improving the real-time nature of the application.

[0074] - It saves internal FPGA resources and increases speed because these calculations only involve bits or very small bit vectors.

[0075] The midpoint voltage adjustment unit 23 is configured to adjust the midpoint potential φmid based on the outputs of the first analog-to-digital converter 30a and the second analog-to-digital converter 30b, so that for AC currents with peak amplitudes smaller than the small-amplitude current threshold Th1, the absolute values ​​of the measured voltages Va and Vb at the input terminals of the first and second analog-to-digital converters relative to ground are maintained to be greater than the error threshold Th. The corresponding small-amplitude voltage threshold Th2 for the measured voltages Va and Vb is defined as follows: An AC current with a peak amplitude equal to the small-amplitude current threshold Th1 induces a peak induced voltage, which generates a voltage between the first connection point 4a and the second connection point 4b that is twice the small-amplitude voltage threshold Th2.

[0076] For example, without error compensation (i.e., with the midpoint potential φmid set to ground), the small-amplitude voltage threshold Th2 can be defined as 10 times, 100 times, or 1000 times the error threshold Th, depending on the acceptable relative error of the measurement during the zero crossing.

[0077] The measurement voltages Va and Vb measured by the processing unit 10 are the potential differences between the first measurement potential φa and the second measurement potential φb and ground. The midpoint voltage Vmid adjusted by the midpoint voltage adjustment unit 23 is the potential difference between the midpoint potential φmid and ground.

[0078] The adjustment of the midpoint voltage Vmid does not significantly change the effective output signal of the current sensor representing the alternating current, which is attributed to differential measurement: a certain voltage difference is applied to one branch connected to subtractor 27, and the same voltage difference is subtracted from the other branch connected to subtractor 27.

[0079] exist Figure 6 In one embodiment, the midpoint voltage adjustment unit 23 is connected to the output of the subtractor and is configured to adjust the midpoint potential φmid based on the output of the subtractor so that, for AC currents with peak amplitudes less than the small amplitude current threshold Th1, the absolute value of the potential difference between the first and second potentials Va and Vb relative to ground is greater than the error threshold Th.

[0080] In a variant (not shown in the figure), the midpoint voltage adjustment unit 23 is connected to the outputs of the first analog-to-digital converter (ADC) and the second ADC 30a, 30b, and is configured to adjust the midpoint potential φmid based on the outputs of the first ADC and the second ADC 30a, 30b, so as to maintain the absolute value of the potential difference between the first and second potentials Va, Vb relative to ground greater than the error threshold Th for AC currents with peak amplitudes less than the small amplitude current threshold Th1. In this variant, the midpoint voltage Vmid can be adjusted as a function of the outputs of the first ADC and the second ADC 30a, 30b as a separate input parameter of that function.

[0081] In a preferred embodiment, the midpoint voltage adjustment unit 23 is configured to detect that the absolute values ​​of the measured voltages Va and Vb relative to ground at the inputs of the first and second analog-to-digital converters are both greater than a small-amplitude voltage threshold Th2, and thereby set the midpoint potential φmid to ground. This detection is based on the output of the subtractor 27 or on the outputs of the first and second analog-to-digital converters 30a and 30b. In these embodiments, the linear compensation network 20 does not sacrifice a large measurement range for the accuracy of weak current measurements.

[0082] In a preferred embodiment, the midpoint voltage adjustment unit 23 is configured to detect that the absolute value of at least one of the measured voltages Va and Vb relative to ground at the first analog-to-digital converter and the second analog-to-digital converter is lower than a small-amplitude voltage threshold Th2, and thereby set the midpoint potential φmid to an adjustment voltage ΔV that is higher or lower than ground. Figure 6 In this embodiment, the adjustment voltage ΔV is the voltage corresponding to the logic "true" of the output of comparator 26. However, the logic "true" voltage of a standard comparator can be converted to any other constant voltage using circuitry known to those skilled in the art. Preferably, the adjustment voltage ΔV is selected within a range of 0.25 to 0.75 of the small-amplitude voltage threshold Th2. For example, the adjustment voltage ΔV is approximately half of the small-amplitude voltage threshold Th2. This detection is based on the outputs of the first analog-to-digital converter and the second analog-to-digital converters 30a, 30b, for example, the detection is based on the output of subtractor 27.

[0083] In a preferred embodiment, the midpoint voltage adjustment unit 23 includes a decimation filter 24 connected to the output of the subtractor 27, and the midpoint voltage adjustment unit 23 is configured to adjust the midpoint potential φmid based on the output of the decimation filter 24, so as to keep the absolute values ​​of the measured voltages Va and Vb at the inputs of the first analog-to-digital converter and the second analog-to-digital converter relative to ground greater than the error threshold Th for AC currents with peak amplitudes less than the small amplitude current threshold Th1.

[0084] In a preferred embodiment, the midpoint voltage adjustment unit 23 further includes an absolute value unit 25 and a digital comparator 26. The absolute value unit 25 is configured to provide the absolute value of the output of the decimation filter 24. The midpoint voltage adjustment unit 23 is configured to detect, via comparator 26, that the absolute value of the output of the decimation filter 24 is less than a predefined comparator voltage Vcomp, and thereby set the midpoint potential φmid to an adjustment voltage ΔV above or below ground. The midpoint voltage adjustment unit 23 is also configured to detect, via comparator, that the absolute value of the output of the decimation filter 24 is greater than a predefined comparator voltage Vcomp, and thereby set the midpoint potential φmid to ground. Vcomp is a multi-bit representation of the small current amplitude threshold Th1 or the small amplitude voltage threshold Th2. In this embodiment, small AC currents are completely shifted out of the unreliable region r0 and can therefore be reliably measured. Large AC currents can also be reliably measured because the relative error during the zero-crossing period is negligible compared to the peak amplitude.

[0085] In a variant (not shown in the figure), the regulating voltage ΔV is a non-constant function of the output of the decimation filter; that is, the regulating voltage ΔV has more than one value or a quasi-continuous set of values. For example, the regulating voltage ΔV increases with the peak amplitude of the alternating current. In particular, the regulating voltage ΔV can increase linearly from a minimum to a maximum value with respect to the peak amplitude of the alternating current.

[0086] The processing unit 10 also includes an output signal processing circuit 40 for generating an output signal representing the alternating current. The output signal processing circuit 40 is connected to the output of the subtractor 27 and includes a digital low-pass filter 45 for integrating the output signal of the subtractor 27. The signal is integrated in the digital low-pass filter 45 because the induced voltage e(t) is related to the measured alternating current I. p The time derivative is proportional to the value. In a preferred embodiment, the digital low-pass filter 45 is implemented in FPGA 11. Preferably, the digital low-pass filter 45 has... The transfer function is of the form [formula missing]. This is a pure first-order transfer function, guaranteeing the -20dB / decade frequency required for integration over the Rogowski coil output (see [reference missing]). Figure 8 Furthermore, the phase remains constant at 90°. By choosing a coefficient α as the reciprocal of a power of 2, the use of a multiplier can be eliminated by applying a shift only within the vector.

[0087] In a preferred embodiment, the output signal processing circuit 40 further includes a gain calibration unit 41 for calibrating the gain of the inductor 2 and / or compensating for the gain of the digital low-pass filter 45. Preferably, the gain calibration unit 41 performs gain calibration before integration by the low-pass filter 45.

[0088] The gain calibration unit 41 includes a multiplier 43 and a third ΣΔ modulator 42, which has a constant input (i.e., a digital multi-bit number) corresponding to the gain of the inductor and / or the gain of the digital low-pass filter. The output of the third ΣΔ modulator 42 is connected to the input of the multiplier. Another input of the multiplier is connected to the output of the subtractor 27, and the output of the multiplier 43 is connected to the input of the digital low-pass filter 45. The output signal of the multiplier 43 is a multi-bit vector stream.

[0089] The implementation of a ΣΔ modulator (digital multi-bit input, single-bit ΣΔ bit stream output) in an FPGA is well known, therefore this article will not describe the implementation.

[0090] The output signal of a current sensor representing alternating current can have any desired format. FPGAs can generate a wide variety of outputs, either alone or in combination with additional components (e.g., passive components). Current sensors can also provide multiple output signals with different formats, such as analog output signals and one or more digital output signals.

[0091] For example, an analog output signal can be provided as follows. In one embodiment, the output signal processing circuit 40 further includes a fourth ΣΔ modulator 46 connected to the output of the digital low-pass filter 45 and an external analog low-pass filter 47 connected to the output of the fourth ΣΔ modulator 46 (see [link to original text]). Figure 9 ).

[0092] For example, the following digital output signals can be implemented in an FPGA:

[0093] -SPI

[0094] -ΣΔ

[0095] - Single bus

[0096] -I2C

[0097] -MODBUS (External components added)

[0098] -PROFIBUS (external components added)

[0099] - Ethernet (external components added)

[0100] Because it is entirely digital, this invention enables the integration of TEDS data in an FPGA without requiring additional memory integrated circuits.

[0101] The current sensor 1 also includes an output interface 50 for providing an output signal.

[0102] List of reference numerals in the attached figures

[0103] Current sensor 1, 1'

[0104] Inductors, such as Rogowski coils 2 and 2'

[0105] Connect points 4a and 4b

[0106] Number of windings n

[0107] Average closed path l

[0108] Cross section S

[0109] Magnetic field B(t)

[0110] Induced voltage e(t)

[0111] Primary conductor 3

[0112] Primary current I p

[0113] Processing units 10, 10'

[0114] FPGA 11

[0115] Linear compensation network 20

[0116] Voltage divider 21

[0117] Midpoint 4c

[0118] Measuring resistors 21a, 21b

[0119] Measuring potentials φa and φb

[0120] Measure voltages Va and Vb

[0121] Midpoint potential φmid

[0122] Midpoint voltage Vmid

[0123] Series resistors 22a and 22b

[0124] Midpoint voltage regulation unit 23

[0125] Decimation filter 24

[0126] Absolute value unit 25

[0127] Comparator 26

[0128] Comparator voltage Vcomp

[0129] Subtractor 27

[0130] Analog-to-digital converter

[0131] ΣΔ modulators 30, 30a, 30b

[0132] Comparator 31

[0133] Passive Integrated Network

[0134] Resistor 32

[0135] Capacitor 33

[0136] D-type trigger 34

[0137] Clock 35

[0138] Unreliable measurement area r0

[0139] Reliable measurement areas r1, r2

[0140] Output signal processing circuit 40

[0141] Gain calibration unit 41

[0142] ΣΔ modulator 42

[0143] Digital multiplier 43

[0144] Potentiometer 44'

[0145] Digital low-pass filter 45

[0146] ΣΔ modulator 46

[0147] Low-pass filter 47

[0148] Output interface 50

[0149] Simulated input s1

[0150] Bitstream S2

[0151] Subtract bitstream s3

[0152] Constant bitstream s4

[0153] Gain-calibrated waveform s5

[0154] Output signal s6

[0155] Filtered output signal s7

[0156] TEDS memory 100, 100'

[0157] Single-bus communication 101, 101'

[0158] Analog Integrator 110'

[0159] Operational amplifier 111'

Claims

1. A current sensor (1) for measuring alternating current in a conductor, the current sensor comprising: Inductor (2), the inductor having a first connection point (4a) at a first potential corresponding to a first measured voltage Va relative to ground and a second connection point (4b) at a second potential corresponding to a second measured voltage Vb relative to ground, and A processing unit (10), connected to the first connection point and the second connection point (4a, 4b), is configured to convert the induced voltage induced in the inductor by the alternating current into an output signal of the current sensor representing a measured value of the alternating current. The processing unit (10) includes a first analog-to-digital converter (30a) connected to the first connection point (4a), a second analog-to-digital converter (30b) connected to the second connection point (4b), and a linear compensation network (20). Its features are, The linear compensation network (20) includes: A voltage divider (21) is connected between the first connection point and the second connection point (4a, 4b) and has a midpoint (4c) at a midpoint potential (φmid) between the first potential and the second potential. Subtractor (27), the subtractor being connected to the output of the first analog-to-digital converter (30a) and the output of the second analog-to-digital converter (30b), and A midpoint voltage adjustment unit (23) is connected to the output of the subtractor or the outputs of the first analog-to-digital converter and the second analog-to-digital converter (30a, 30b), and is configured to adjust the midpoint potential (φmid) based on the output of the subtractor or the outputs of the first analog-to-digital converter and the second analog-to-digital converter (30a, 30b) to keep the absolute values ​​of the first measured voltage Va and the second measured voltage Vb greater than the error threshold Th for AC currents with peak amplitudes less than the small amplitude current threshold Th1.

2. The current sensor according to claim 1, wherein, The midpoint voltage adjustment unit (23) is configured to adjust the midpoint potential (φmid) based on the output of the subtractor or the output of the first analog-to-digital converter and the second analog-to-digital converter (30a, 30b) to keep the absolute values ​​of the first measured voltage Va and the second measured voltage Vb greater than the error threshold Th for a voltage less than twice the small amplitude voltage threshold Th2 between the first connection point 4a and the second connection point 4b, wherein an AC current having a peak amplitude equal to the small amplitude current threshold Th1 induces a peak induced voltage, which generates a voltage between the first connection point and the second connection point (4a, 4b) that is twice the small amplitude voltage threshold Th2.

3. The current sensor according to claim 1, wherein, The midpoint voltage adjustment unit (23) is configured to detect that the absolute values ​​of the measured voltages Va and Vb at the input terminals of the first analog-to-digital converter and the second analog-to-digital converter relative to ground are both greater than the small amplitude voltage threshold Th2, and thereby set the midpoint potential (φmid) to ground.

4. The current sensor according to claim 1, wherein, The midpoint voltage adjustment unit (23) is configured to detect that the absolute value of at least one of the measured voltages Va and Vb at the input terminals of the first analog-to-digital converter and the second analog-to-digital converter relative to ground is lower than a small-amplitude voltage threshold Th2, and thereby set the midpoint potential (φmid) to an adjustment voltage ΔV that is higher or lower than ground.

5. The current sensor according to claim 4, wherein, The regulating voltage ΔV is selected within the range of 0.25 to 0.75 of the small amplitude voltage threshold Th2. For example, the regulating voltage ΔV is approximately half of the small amplitude voltage threshold Th2.

6. The current sensor according to claim 4, wherein, The midpoint voltage adjustment unit (23) includes a decimation filter (24) connected to the output of the subtractor (27), and the midpoint voltage adjustment unit (23) is configured to adjust the midpoint potential (φmid) based on the output of the decimation filter (24) so ​​that for AC currents with peak amplitudes less than the small amplitude threshold Th1, the absolute values ​​of the measured voltages Va and Vb at the inputs of the first analog-to-digital converter and the second analog-to-digital converter relative to ground are kept greater than the error threshold Th.

7. The current sensor according to claim 6, wherein, The midpoint voltage adjustment unit (23) further includes an absolute value unit (25) and a comparator (26). The absolute value unit (25) is configured to provide the absolute value of the output of the decimation filter (24), and the midpoint voltage adjustment unit (23) is configured to detect by the comparator that the absolute value of the output of the decimation filter (24) is less than a predefined comparator voltage Vcomp, and thereby set the midpoint potential (φmid) to the adjustment voltage ΔV above or below ground. The midpoint voltage adjustment unit (23) is also configured to detect by the comparator that the absolute value of the output of the decimation filter (24) is greater than the predefined comparator voltage Vcomp, and thereby set the midpoint potential (φmid) to ground.

8. The current sensor according to claim 1, wherein, The inductor (2) is a Rogowski coil.

9. The current sensor according to claim 1, wherein, The linear compensation network (20) and at least a portion of the first analog-to-digital converter and the second analog-to-digital converter (30a, 30b) are implemented in a field-programmable gate array.

10. The current sensor according to claim 1, wherein, The first analog-to-digital converter and the second analog-to-digital converter (30a, 30b) are ΣΔ modulators.

11. The current sensor according to claim 1, wherein, The processing unit (10) further includes an output signal processing circuit (40) for generating an output signal representing the alternating current of the current sensor, wherein the output signal processing circuit (40) is connected to the output of the subtractor (27) and includes a digital low-pass filter (45) for integrating the output signal of the subtractor (27).

12. The current sensor according to claim 1, wherein, The digital low-pass filter (45) has The transfer function is of the form α, where the coefficient α is preferably the reciprocal of a power of 2.

13. The current sensor according to claim 1, wherein, The output signal processing circuit (40) further includes a gain calibration unit (41) for calibrating the gain of the inductor (2) and / or compensating for the gain of the digital low-pass filter (45).

14. The current sensor according to claim 13, wherein, The gain calibration unit (41) includes a multiplier (43) and a third ΣΔ modulator (42), the third ΣΔ modulator having a constant input corresponding to the gain of the inductor and / or the gain of the digital low-pass filter, wherein the output of the third ΣΔ modulator (42) is connected to the input of the multiplier, wherein another input of the multiplier is connected to the output of the subtractor (27), and the output of the multiplier (43) is connected to the input of the digital low-pass filter (45).

15. The current sensor according to claim 11, wherein, The output signal processing circuit (40) also includes a fourth ΣΔ modulator (46) connected to the output of the digital low-pass filter (45).

Images