A DC function test method based on a digital board card ATE power supply

Abstract

The application relates to the technical field of function test, and particularly discloses a DC function test method based on a digital board card ATE power supply, which generates a virtual Patern same as a digital board card instruction sequence for a power supply board card, and embeds DC measurement information in a specific vector line in the virtual Patern. Clocks of the two are synchronized through a unified test platform, and the power supply board card and the digital board card are started at the same time, so that when the power supply board card runs to a mark position, the DC index measurement can be triggered at the moment when the specific digital function of the measured chip is executed. The DC measurement and the digital function state are accurately time-aligned, and multi-point dynamic measurement can be completed in a single test process.

Description

Technical Field

[0001] This invention relates to the field of functional testing technology, and specifically to a DC functional testing method based on a digital board ATE power supply. Background Technology

[0002] During the functional and electrical performance testing of a chip under test (DUT) using an automated test equipment (ATE), the digital circuit board typically drives the chip to enter different operating states at different times according to a preset test pattern, while the power supply board is responsible for monitoring the chip's power supply status and DC parameters. Since the chip's DC characteristics are highly dependent on its instantaneous operating state, whether the timing of DC parameter measurements precisely corresponds to the execution sequence of the digital functional tests directly affects the authenticity of the test results and the accuracy of the judgment.

[0003] However, in existing testing procedures, DC measurements often cannot be completed at precise points in time during the continuous execution of the digital pattern. Instead, they rely on interruptions or phased switching of the testing process, resulting in a significant time discrepancy between the DC measurement moment and the target functional state. In high-speed, high-precision chip testing scenarios, this timing mismatch can easily lead to measurement results that fail to accurately reflect the chip's DC behavior under specific functional vectors, thus affecting the reliability of test judgments. Furthermore, when DC parameters need to be acquired at multiple different functional moments during testing, the timing coordination between the measurement process and functional testing becomes more complex, increasing the difficulty of test procedure design and the uncertainty of results. Summary of the Invention

[0004] The purpose of this invention is to provide a DC function testing method based on a digital board ATE power supply, thereby solving the above-mentioned technical problems.

[0005] The objective of this invention can be achieved through the following technical solutions: A DC function testing method based on a digital board ATE power supply includes the following steps: A virtual pattern is written to the power supply board. The instruction sequence of the virtual pattern is the same as the instruction sequence of the test pattern to be run on the digital board. At least one vector row of the virtual pattern contains DC measurement information. The clock synchronization between the power supply board and the digital board is controlled by the unified test platform UTP board. The unified test platform UTP board simultaneously sends a Pattern start signal to both the power board and the digital board; After receiving the Pattern start signal, the power board and the digital board each run their respective Patterns. During the continuous operation of the digital board test pattern, when the power board runs to the vector row in the virtual pattern that contains the DC measurement information, it performs DC index measurement on the chip under test (DUT).

[0006] As a further aspect of the present invention: writing a virtual pattern to the power supply board includes: Obtain the same instruction sequence as the test pattern to be run on the digital board; The instruction sequence is compressed, and duplicate vector instructions are merged; In the compressed instruction sequence, DC measurement information is added to the specified vector rows according to the test requirements to generate the virtual pattern.

[0007] As a further aspect of the present invention: before synchronizing the clocks of the power supply board and the digital board by controlling the unified test platform UTP board, the time difference between the power supply board and the digital board when receiving and responding to instructions from the unified test platform UTP board is measured.

[0008] As a further aspect of the present invention: during the operation of their respective Patterns by the power supply board and the digital board: The power supply board adjusts the startup time of its virtual pattern according to the time difference, so that the virtual pattern runs synchronously with the test pattern of the digital board.

[0009] As a further aspect of the present invention: adding DC measurement information to a specified vector row according to test requirements includes: Read the configuration file, which records the correspondence between vector row numbers and DC measurement information; Based on the correspondence, the DC measurement information is written into the vector row with the corresponding number.

[0010] As a further aspect of the present invention: performing DC index measurement on the chip under test (DUT) includes: The power board triggers the measurement action based on the measurement mode, measurement channel, and current range defined in the DC measurement information.

[0011] As a further aspect of the present invention: DC measurement information is set in multiple different vector rows of the virtual pattern; During the running of the virtual pattern, the power supply board performs DC index measurements at different times corresponding to the multiple different vector rows.

[0012] As a further aspect of the present invention: after the digital board completes the test pattern operation, the DC index measurement data is read from the power board.

[0013] The beneficial effects of this invention are as follows: By designing the overall DC function test process, this invention ensures that the measurement of DC parameters is highly consistent with the execution timing of digital function tests, thereby significantly improving the test results' ability to reflect the actual operating state of the chip. This method allows for the acquisition of DC parameters corresponding to the chip under test at multiple different functional moments during continuous digital function testing, avoiding deviations in measurement results from the target functional state due to test process interruptions or timing misalignments, thus enhancing the reliability and consistency of DC test conclusions. Simultaneously, this invention allows the DC measurement process to be naturally embedded into the overall test process without additional intervention in the execution of digital function tests, which helps maintain the continuity and stability of the test process. When test requirements involve acquiring multiple sets of DC parameters at different functional stages, this invention can complete the corresponding measurements in a single test, reducing repetitive operations and process adjustments during testing, and improving the controllability and repeatability of the test process. Based on the above effects, this invention helps improve the timing consistency, test stability, and test result reliability of DC function testing based on digital boards and ATE power supplies, meeting the requirements for accuracy and process rationality in complex chip testing scenarios. Attached Figure Description

[0014] The invention will now be further described with reference to the accompanying drawings.

[0015] Figure 1 This is a flowchart illustrating a DC function testing method based on a digital board ATE power supply according to the present invention. Figure 2 This is a schematic diagram of DC measurement according to the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Please see Figures 1-2 As shown, this invention is a DC function testing method based on a digital board ATE power supply, comprising the following steps: A virtual pattern is written to the power supply board. The instruction sequence of the virtual pattern is the same as the instruction sequence of the test pattern to be run on the digital board. At least one vector row of the virtual pattern contains DC measurement information. In a preferred embodiment of the present invention, writing a virtual pattern to a power supply board includes: Obtain the same instruction sequence as the test pattern to be run on the digital board; The instruction sequence is compressed, and duplicate vector instructions are merged; In the compressed instruction sequence, DC measurement information is added to the specified vector rows according to the test requirements to generate the virtual pattern.

[0018] Specifically, the process of writing a virtual pattern to the power supply board uses the test pattern that the digital board is about to execute as the basic input. This assumes that the instruction sequence used by the digital board during testing and the corresponding time sequence information of each vector row are already known. Based on this, the complete instruction sequence of the test pattern is obtained from the digital board side. This instruction sequence describes the execution structure of the digital functional test in the time dimension and serves as the raw data source for subsequent virtual pattern construction. After the obtained instruction sequence is introduced to the power supply board side, it is not written directly as a whole. Instead, duplicate vector instructions are identified and processed. By merging vector instructions that are equivalent in time structure, a compressed instruction sequence is formed, thereby reducing the redundancy of the virtual pattern while maintaining the time correspondence of each vector row.

[0019] It should be noted that time-structure equivalent vector instructions refer to multiple vector instructions within the time execution framework of the test pattern that, although differing in storage location or frequency of occurrence, maintain consistency in temporal order, duration, and relative temporal relationship with preceding and following vectors, and do not cause changes to the test state within their corresponding time periods. These vector instructions occupy the same temporal position during pattern execution, and their execution does not alter the critical nodes of digital functional testing or power-related operations on the timeline; they are solely used to maintain the continuous execution of the pattern. When multiple vector instructions serve the same occupancy role on the timeline and do not affect subsequent functional or measurement moments requiring attention, these vector instructions can be considered time-structure equivalent. During the construction of a virtual pattern, this equivalence allows these vector instructions to be merged without altering the overall temporal correspondence and distribution of critical measurement moments, thus preserving the original pattern's temporal structure characteristics while reducing the storage and execution process overhead of redundant instructions.

[0020] After compression, based on predetermined test requirements, for the function time requiring DC parameter measurement, the vector row number corresponding to that function time is located in the compressed instruction sequence, and DC measurement-related information is written into that vector row. This ensures that when the virtual pattern reaches the corresponding time position, the vector row can trigger the corresponding measurement action. The DC measurement information describes the measurement attributes corresponding to that vector row and, together with the time sequence information of the instruction sequence itself, constitutes the complete virtual pattern content. The final generated virtual pattern maintains a structural correspondence with the digital board test pattern in terms of instruction sequence, while carrying DC measurement information in the designated vector rows. This serves as the target data for writing to the power supply board and enabling it to perform corresponding operations based on the time structure of the virtual pattern during subsequent testing.

[0021] The clock synchronization between the power supply board and the digital board is controlled by the unified test platform UTP board. The unified test platform UTP board simultaneously sends a Pattern start signal to both the power board and the digital board; After receiving the Pattern start signal, the power board and the digital board each run their respective Patterns. In a preferred embodiment of the present invention, before the clock synchronization between the power supply board and the digital board is controlled by the unified test platform UTP board, the time difference between the power supply board and the digital board when receiving and responding to instructions from the unified test platform UTP board is measured.

[0022] In a preferred embodiment, during the execution of their respective Patterns by the power supply board and the digital board: The power supply board adjusts the startup time of its virtual pattern according to the time difference, so that the virtual pattern runs synchronously with the test pattern of the digital board.

[0023] In another preferred embodiment, adding DC measurement information to a specified vector row according to test requirements includes: Read the configuration file, which records the correspondence between vector row numbers and DC measurement information; Based on the correspondence, the DC measurement information is written into the vector row with the corresponding number.

[0024] Specifically, during the test preparation phase, the Unified Test Platform (UTP) board acts as a control source, receiving control commands to coordinate the test process. These commands trigger the management of the timing relationship between the power supply board and the digital board. Before performing clock synchronization, a command trigger signal is sent to both the power supply board and the digital board from the same control source, causing them to respond to the command. During this process, the time information between the power supply board receiving the command and the digital board generating a valid response is acquired, thus forming time difference data reflecting the order of their responses. This time difference data is recorded as an input condition for subsequent timing adjustments.

[0025] After acquiring the time difference, the unified test platform UTP board simultaneously sends a pattern start signal to both the power supply board and the digital board. This start signal instructs both types of boards to enter their respective pattern execution states. Upon receiving the start signal, the power supply board enters the virtual pattern execution process, while the digital board enters the test pattern execution process. During the actual pattern execution, the power supply board does not directly execute the virtual pattern at the arrival time of the start signal. Instead, it adjusts the start time of the virtual pattern based on the acquired time difference data, ensuring that the virtual pattern's position on the timeline corresponds to the position of the digital board's test pattern. This guarantees that both patterns unfold under the same time reference.

[0026] During the virtual pattern construction phase, a configuration file is pre-formed based on the test requirements. This configuration file, as input data, records the vector row numbers that need to be performed for DC measurements and the corresponding DC measurement information. When generating the virtual pattern, the contents of this configuration file are read, and the DC measurement information is written into the virtual pattern vector row corresponding to the vector row number. This ensures that the virtual pattern has clear measurement indication information when it reaches the time position corresponding to the vector row, thus providing a direct basis for the measurement behavior of the power board during the subsequent synchronous operation of the pattern.

[0027] It is worth noting that after the virtual pattern is constructed and written to the power board, the virtual pattern contains corresponding DC measurement information in multiple different vector rows according to the test requirements. This DC measurement information serves as input data and corresponds one-to-one with each vector row in time sequence, indicating the measurement action to be performed when the virtual pattern reaches that vector row. The positions of these multiple vector rows in the virtual pattern maintain a time correspondence with the corresponding vector rows in the digital board test pattern. Therefore, the DC measurement information carried by different vector rows actually corresponds to the working state of the chip under test at different functional moments. For example, the first vector row set in the virtual pattern is used to correspond to the DC measurement requirements when the chip enters a certain functional excitation state, while another vector row is used to correspond to the DC measurement requirements after the chip switches to a subsequent function. These vector rows are arranged in time sequence in the virtual pattern and executed sequentially.

[0028] During the execution of the virtual pattern, the power supply board parses the virtual pattern content line by line according to the order of the vector rows. When it reaches a vector row without DC measurement information, it only maintains the time progression of the pattern. When it reaches a vector row with DC measurement information, it reads the measurement-related information already written in that vector row and triggers a DC performance measurement action for the chip under test based on this information. As the virtual pattern continues to run to the next vector row with DC measurement information, the power supply board performs the corresponding DC performance measurement again at the time position corresponding to that vector row. Thus, during one virtual pattern execution, multiple DC performance measurements are completed at different times corresponding to multiple different vector rows, generating measurement data outputs corresponding to the time positions of each vector row.

[0029] During the continuous operation of the digital board test pattern, when the power board runs to the vector row in the virtual pattern that contains the DC measurement information, it performs DC index measurement on the chip under test (DUT).

[0030] In another preferred embodiment of the present invention, performing DC index measurement on the chip under test (DUT) includes: The power board triggers the measurement action based on the measurement mode, measurement channel, and current range defined in the DC measurement information.

[0031] Understandably, after the digital board completes the test pattern run, it reads the DC index measurement data from the power board.

[0032] Specifically, during the virtual pattern operation, when the power supply board executes to the vector row with DC measurement information set, the power supply board reads the written DC measurement information from the vector row as the input condition for the measurement action. The DC measurement information is used to clarify the measurement mode to be used in this measurement, the power supply channel involved in the measurement, and the corresponding current range parameters.

[0033] Based on the read measurement mode information, the power board determines whether the measurement targets the voltage or current index of the chip under test and selects the corresponding measurement path accordingly. Based on the measurement channel information, the power board determines which power supply channel of the chip under test needs to be measured. Based on the current range information, the power board completes internal range matching before triggering the measurement to ensure that the measurement conditions are consistent with the test requirements corresponding to the current vector row.

[0034] After completing the above information parsing, the power supply board triggers a DC parameter measurement at the time position corresponding to the vector row, and stores the measured DC parameters in the data buffer area inside the board after associating them with the identification information of the vector row. As the virtual pattern continues to run, the power supply board repeats the above process at subsequent vector rows with DC measurement information, thereby generating multiple sets of DC parameter measurement data corresponding to different vector row time positions during one pattern run. When the digital board completes the overall run of the test pattern, the test process enters the data acquisition stage. By reading the DC parameter measurement data stored in the power supply board, the measurement results corresponding to each vector row are output for subsequent analysis and judgment, so that the acquired data can fully reflect the DC characteristics of the chip under test at different times during the digital function test.

[0035] This solution establishes a stable, direct, and repeatable correspondence between DC functional test results and the chip's actual operating state. This transforms DC metrics from independent measurements detached from functional behavior into indicators that reflect the chip's actual electrical characteristics at different points in the functional test process. In this way, DC measurements no longer rely on manually defined test phases or process switching nodes but are naturally embedded within the functional test timeline. This allows multiple sets of DC data acquired during the same test to correspond to the chip's operating state under different functional vectors. This effect ensures continuity and consistency of test results over time, avoiding distortion caused by measurement time offsets and eliminating the need to break down multi-step DC testing into multiple independent processes.

[0036] This invention controls the power supply and digital board clock synchronization via a UTP board. When the digital board issues a Pattern start command, the UTP simultaneously sends Pattern start signals to both the power supply and digital boards. Upon receiving this start signal, both boards run their respective Patterns. Considering the different environments of the different boards, there may be slight time differences in the received signals. This time difference can be measured first and compensated during the operation of the power board's Pattern to ensure that the Patterns of the two boards remain synchronized in time. Under this condition, the accuracy of DC measurement is maximized.

[0037] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A DC function testing method based on a digital board ATE power supply, characterized in that, Includes the following steps: A virtual pattern is written to the power supply board. The instruction sequence of the virtual pattern is the same as the instruction sequence of the test pattern to be run on the digital board. At least one vector row of the virtual pattern contains DC measurement information. The clock synchronization between the power supply board and the digital board is controlled by the unified test platform UTP board. The unified test platform UTP board simultaneously sends a Pattern start signal to both the power board and the digital board; After receiving the Pattern start signal, the power board and the digital board each run their respective Patterns. During the continuous operation of the digital board test pattern, when the power board runs to the vector row in the virtual pattern that contains the DC measurement information, it performs DC index measurement on the chip under test (DUT).

2. The DC function testing method based on a digital board ATE power supply according to claim 1, characterized in that, Writing a virtual pattern to the power supply board includes: Obtain the same instruction sequence as the test pattern to be run on the digital board; The instruction sequence is compressed, and duplicate vector instructions are merged; In the compressed instruction sequence, DC measurement information is added to the specified vector rows according to the test requirements to generate the virtual pattern.

3. The DC function testing method based on a digital board ATE power supply according to claim 2, characterized in that, Before synchronizing the clocks of the power supply board and the digital board using the unified test platform UTP board, measure the time difference between the power supply board and the digital board when they receive and respond to commands from the unified test platform UTP board.

4. The DC function testing method based on a digital board ATE power supply according to claim 3, characterized in that, During the process of the power supply board and digital board running their respective patterns: The power supply board adjusts the startup time of its virtual pattern according to the time difference, so that the virtual pattern runs synchronously with the test pattern of the digital board.

5. The DC function testing method based on a digital board ATE power supply according to claim 4, characterized in that, Add DC measurement information to the specified vector rows according to the test requirements, including: Read the configuration file, which records the correspondence between vector row numbers and DC measurement information; Based on the correspondence, the DC measurement information is written into the vector row with the corresponding number.

6. The DC function testing method based on a digital board ATE power supply according to claim 1, characterized in that, Performing DC performance measurements on the chip under test (DUT) includes: The power board triggers the measurement action based on the measurement mode, measurement channel, and current range defined in the DC measurement information.

7. The DC function test method based on a digital board ATE power supply according to claim 1, characterized in that, DC measurement information is set in multiple different vector rows of the virtual pattern; During the running of the virtual pattern, the power supply board performs DC index measurements at different times corresponding to the multiple different vector rows.

8. The DC function test method based on a digital board ATE power supply according to claim 1, characterized in that, After the digital board completes the test pattern, the DC index measurement data is read from the power board.

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