A noise suppression method for high PSRR low dropout linear regulator

Abstract

The embodiment of the present application relates to the field of integrated circuits and analog power management technology, and particularly relates to a noise suppression method of a high-PSRR low-dropout linear regulator, which comprises inserting an enhancement unit formed by a diode-connected MOS tube and a common-source common-gate structure in series between an error amplifier of the low-dropout linear regulator and a power input end; a small signal voltage proportional to the voltage of the power input end is generated by the diode-connected MOS tube and transmitted to the input end of the common-source common-gate structure; the ratio of the small signal voltage between the output end of the error amplifier and the power input end is controlled by the common-source common-gate structure; and the transmission of the noise of the power input end to the output end of the error amplifier is suppressed based on the ratio of the small signal voltage. The present application realizes a high and stable power supply rejection ratio by inserting the enhancement unit formed by the diode-connected MOS tube and the common-source common-gate structure in series.

Description

Technical Field

[0001] This application relates to the fields of integrated circuits and analog power management technology, and in particular to a noise suppression method for a high PSRR low dropout linear regulator. Background Technology

[0002] With the increasing prevalence of portable electronic devices, medical instruments, and high-precision System-on-Chip (SoC), the performance requirements for their internal power management circuits are becoming increasingly stringent. Low-dropout linear regulators (LDOs), due to their advantages such as low output voltage ripple and relatively simple structure, are often used to provide clean and stable power to noise-sensitive modules (such as RF front-ends, phase-locked loops, and high-precision analog-to-digital converters). Power supply rejection ratio (PSRR) is a key indicator measuring the ability of an LDO to suppress input noise and ripple propagation to the output. A high PSRR is crucial for ensuring the signal-to-noise ratio and stability of the entire system. To improve the PSRR performance of LDOs, existing technologies mainly focus on two directions: one is to use power isolation technology, such as inserting a charge pump or capacitive coupling circuit in the power supply path of the LDO's error amplifier, to isolate noise by increasing the power supply voltage or blocking the AC path. While this method can improve the PSRR in specific frequency bands, it often requires additional pump circuits and capacitors, significantly increasing chip area, static power consumption, and design complexity, and may introduce new switching noise. Secondly, feedforward or feedback cancellation techniques are employed. For example, by constructing a feedforward path parallel to the main path, the input ripple signal is amplified inverted or in-phase, and then superimposed and canceled with the original noise signal at key nodes (such as the gate of the power transistor); or the gain characteristics are affected by adjusting the body potential of the MOS transistor inside the error amplifier. These methods improve PSRR to some extent, but their performance is highly dependent on precise parameter matching and gain adjustment, making the design difficult, and they are not robust to process deviations, temperature changes, and load current fluctuations. Especially in some relatively simple improvement schemes, the PSRR improvement effect will significantly decrease with the increase of load current, and it is impossible to maintain stable and excellent noise suppression capability across the entire load range.

[0003] In summary, there is a common contradiction in existing technologies for improving the PSRR of LDOs: high-performance solutions often come with complex circuits, high power consumption, and large area; while simple solutions suffer from unstable performance and poor load adaptability. Therefore, there is an urgent need for an LDO circuit method that can achieve high and stable PSRR across the entire load current range while ensuring low power consumption and small area. Summary of the Invention

[0004] To address this, the present invention provides a noise suppression method for a high PSRR low dropout linear regulator, which overcomes the problems of complex circuits and high power consumption in existing high-performance solutions, while the performance of simple solutions degrades with load changes and is difficult to balance.

[0005] To achieve the above objectives, this invention provides a noise suppression method for a high PSRR, low dropout linear regulator. It includes:

[0006] Step S1: Insert an enhancement unit consisting of a diode-connected MOS transistor and a common-source cascode structure connected in series between the error amplifier and the power input terminal of the low-dropout linear regulator.

[0007] Step S2: A small signal voltage proportional to the power input voltage is generated by the diode-connected MOS transistor and transmitted to the input terminal of the cascode structure.

[0008] Step S3: Using the common source cascode structure, control the small signal voltage ratio between the output terminal and the power supply input terminal of the error amplifier;

[0009] Step S4: Based on the small signal voltage ratio, suppress the transmission of noise from the power input terminal to the error amplifier output terminal.

[0010] Further, in step S1, an enhancement unit consisting of a diode-connected MOS transistor connected in series with a cascode structure is inserted, including:

[0011] Between the output node of the error amplifier and the power input terminal, a first MOSFET, a second MOSFET, and a third MOSFET are connected in series in sequence.

[0012] The source of the first MOS transistor is connected to the power input terminal, and the gate and drain of the first MOS transistor are shorted.

[0013] The source of the second MOS transistor is connected to the drain of the first MOS transistor, and its gate is connected to a fixed bias voltage.

[0014] The source of the third MOS transistor is connected to the drain of the second MOS transistor, its drain is connected to the output terminal of the error amplifier, and its gate is connected to the output terminal of the error amplifier.

[0015] The second MOS transistor and the third MOS transistor form a common source and common gate structure.

[0016] Further, in step S2, a small signal voltage proportional to the power input voltage is generated by the diode-connected MOS transistor and transmitted to the input terminal of the cascode structure, including:

[0017] The AC disturbance signal in the power input voltage directly acts on the source of the first MOS transistor;

[0018] The first MOS transistor generates a first small-signal voltage at its gate and drain nodes that is proportional to the AC disturbance signal.

[0019] The first small-signal voltage is applied to the source of the second MOS transistor as the input signal of the common-source common-gate structure.

[0020] Further, in step S3, using the cascode structure, controlling the small-signal voltage ratio between the output terminal and the power supply input terminal of the error amplifier includes:

[0021] Step S31: Based on the common source cascode structure, generate an equivalent small-signal resistance gain and transmit the small-signal voltage to the output of the error amplifier;

[0022] Step S32: Through the common source cascode structure, the change in the output voltage of the error amplifier caused by the first small signal voltage is controlled to be approximately equal to the AC disturbance voltage at the power input terminal.

[0023] Furthermore, in step S31, the equivalent small-signal resistance gain generated by the common-source cascode structure is determined by the transconductance and output resistance of the second MOS transistor and the third MOS transistor.

[0024] Furthermore, the product of the transconductance of the first MOSFET and the output resistance of the third MOSFET satisfies the following condition:

[0025] ;

[0026] Where gm1 is the transconductance of the first MOSFET and Ro3 is the output resistance of the third MOSFET.

[0027] Further, in step S4, based on the small-signal voltage ratio, suppressing the transmission of noise from the power supply input terminal to the error amplifier output terminal includes:

[0028] The first small-signal voltage is transmitted to the output of the error amplifier through the common source cascode structure, so that the voltage ripple at the output of the error amplifier is approximately equal to the voltage ripple at the power input.

[0029] By utilizing the voltage follower relationship established between the output of the error amplifier and the power input, noise at the power input is blocked at this critical node.

[0030] Furthermore, it also includes a bias circuit for providing the fixed bias voltage, wherein the power supply terminal of the bias circuit is independent of the power supply input terminal.

[0031] Furthermore, the first MOSFET, the second MOSFET, and the third MOSFET all operate in the saturation region.

[0032] Furthermore, the product of the transconductance and output resistance of the second MOSFET and the output resistance of the third MOSFET is greater than the output resistance of the first MOSFET.

[0033] Compared with existing technologies, the beneficial effect of this invention lies in its utilization of the huge equivalent impedance gain generated by the cascode structure formed by MN2 and MN3. This characteristic results in extremely low impedance from node VX, ensuring that VX can be transmitted to node VG with almost no attenuation, thereby achieving vg / vin≈1 at the output of the error amplifier. Most importantly, this gain effect is maintained over a wide operating current range. Therefore, even if the load current (IL) changes from light load to heavy load, causing a drift in the gate voltage VG of the power transistor and the operating points of each MOSFET, the relationship vg / vin≈1 remains stable. This fundamentally overcomes the limitations of traditional simple boost structures (such as...). Figure 3 The inherent problem of a sharp deterioration in PSRR improvement due to the sudden drop in the on-resistance of MN2 under heavy load (as shown) is addressed by achieving a complex performance improvement with minimal circuit modifications. The structure is compact and easy to integrate. The enhancement unit consists of only three MOS transistors (MN1, MN2, MN3) connected in series, eliminating the need for complex charge pumps, additional amplification stages, or precisely matched feedforward / feedback networks. This structure is directly embedded between the error amplifier output node and the power supply, without altering the basic architecture of the LDO main loop. Therefore, the design complexity is low, the increase in layout area is minimal, and it is highly advantageous for implementation in highly integrated chips.

[0034] Furthermore, this invention directly connects the source of the diode-connected first MOSFET MN1 to the power input terminal VIN, enabling any AC disturbance signal vin on the input voltage to act directly on the sensing element without attenuation or delay. The diode connection of MN1 allows the potential change of its gate-drain node VX to naturally and linearly follow the source disturbance, thereby directly converting power supply noise into a proportional voltage signal vx. This sensing mechanism is simple and direct, with a clear signal path, avoiding the signal attenuation, phase delay, or need for additional amplification stages common in traditional feedforward or feedback structures, laying an accurate signal foundation for subsequent precise cancellation. Utilizing the characteristics of mature devices, high linearity and high reliability signal transmission are achieved. The diode-connected MOSFET is in one of its most basic and stable operating states, and its small-signal characteristics (transconductance gm1) have good predictability and consistency in the saturation region. This invention utilizes this mature characteristic to achieve a linear conversion of noise voltage to current and then back to voltage (vin->vx). This method does not rely on special device models, complex linearization circuits, or precise bias conditions, thus exhibiting stronger robustness to process fluctuations and temperature variations, ensuring the stability and consistency of sensing signals under different operating environments. It provides an ideal and strongly driven input signal for the cascode processing unit. The generated vx signal is directly applied to the source of the second MOSFET MN2. For MN2, its gate is fixed biased (AC ground), so the change in the source signal vx is equivalent to the change in its gate-source voltage v_gs (v_gs = -vx), thereby efficiently converting the voltage signal vx into modulation of the drain current of MN2. This connection method utilizes the high input impedance characteristic of the MOSFET source as input, ensuring minimal load effect on the preceding stage (MN1), allowing vx to be transmitted with almost no loss. Simultaneously, it provides a low-impedance, strongly driven current signal source for the subsequent cascode structure (MN2-MN3), maximizing the gain and bandwidth of the entire noise processing path, ensuring that high-frequency noise can also be effectively tracked and processed.

[0035] Furthermore, this invention creatively enables the power transistor gate voltage (VG) to accurately follow the noise changes of the power input (VIN) (i.e., vg / vin≈1) by introducing an enhancement unit at the output node of the error amplifier, consisting of a diode-connected MOSFET (MN1) and a cascode structure (MN2, MN3) connected in series. Most importantly, the large and stable impedance gain provided by the cascode structure ensures that this following relationship does not significantly change with drastic variations in load current. Therefore, this invention overcomes the fundamental defect of traditional simple PSRR boosting circuits, which suffer from drastic performance degradation under heavy load conditions, and achieves and maintains near-theoretical PSRR performance across the entire operating range from light to heavy load. Achieving complex performance enhancement with a minimalist circuit structure, it combines low power consumption and a small area: the enhancement unit consists of only three MOSFETs, requiring no additional operational amplifiers, precision matching networks, charge pumps, or large-capacitance capacitors. This structure is directly embedded in the existing LDO architecture, adding almost no additional quiescent current branches, thus having a negligible impact on the chip's total quiescent power consumption. Meanwhile, very few new components are added, and the increase in layout area is also very limited. This invention provides a solution that achieves maximum PSRR performance gains with near-minimum circuit complexity, power consumption, and area overhead, making it highly practical and economical.

[0036] Furthermore, this invention does not passively attenuate noise through filtering or isolation, but instead constructs a precise active feedforward path through steps S1 to S3. This path "copyes" the power supply noise vin and feeds it forward to the output node VG of the error amplifier, forming a voltage follower relationship where vg≈vin. Finally, in step S4, the natural suppression of common-mode signals (vg and vin) by the gate-source port of the power transistor is utilized to effectively cancel the noise at the control terminal (v_gs≈0), thereby blocking the noise transmission path from the power transistor to the core output from the source, achieving a high power supply rejection ratio (PSRR) with a clear principle and significant effect. This ensures the stability and robustness of the high PSRR performance across the entire load range. The entire noise suppression mechanism is achieved by adding an enhancement unit consisting of three MOSFETs (MN1, MN2, MN3). This unit requires no additional bias current branch, complex control loop, or large passive components, and adds almost no static power consumption or chip area. This invention provides an elegant solution that achieves the highest performance gain with the lowest complexity, power consumption, and area cost, demonstrating outstanding economy and practicality.

[0037] Furthermore, this invention creatively enables the power transistor gate voltage to precisely follow the power input noise by introducing a simple yet efficient enhancement unit at a critical node, thereby achieving active cancellation on the core path of noise propagation. Crucially, thanks to the large and stable impedance gain provided by the cascode structure, this excellent noise suppression effect remains stable across the entire operating range from light to heavy loads, completely overcoming the fundamental defect of traditional simple solutions where performance degrades sharply with increasing load current. The enhancement unit consists of only three MOS transistors, eliminating the need for charge pumps, complex feedforward networks, or additional amplification stages. This design achieves a significant leap in PSRR performance with almost no increase in quiescent current consumption and chip layout area, perfectly balancing the often contradictory design goals of high performance, low power consumption, and small area, providing a highly cost-effective solution. The performance improvement mechanism of this invention mainly relies on the intrinsic characteristics of the classic cascode structure and the defined transistor operating state (saturation region). It has low dependence on the absolute accuracy of device parameters and special process modules, and is more adaptable to process fluctuations, temperature changes and power supply disturbances, ensuring the reliability and consistency of performance under different manufacturing processes and actual working environments, and reducing design risks and manufacturing costs. Attached Figure Description

[0038] Figure 1 This is a typical LDO circuit using PMOS as the power transistor;

[0039] Figure 2 shows the PMOS power transistor and its small-signal model;

[0040] Figure 3 This is a circuit for improving PSRR;

[0041] Figure 4 shows the improved enhanced PSRR structure and its small-signal model;

[0042] Figure 5 This is a flowchart illustrating the noise suppression method for the high PSRR low dropout linear regulator of the present invention. Detailed Implementation

[0043] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0044] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0045] Please see Figures 1-5 As shown, Figure 1Figure 2 shows a typical LDO circuit using PMOS as the power transistor; Figure 3 shows the PMOS power transistor and its small-signal model. Figure 3 Figure 4 shows an improved PSRR circuit and its small-signal model. Figure 5 This is a flowchart illustrating the noise suppression method for the high PSRR low dropout linear regulator of the present invention.

[0046] The noise suppression method for a high PSRR low dropout linear regulator of the present invention includes:

[0047] Step S1: Insert an enhancement unit consisting of a diode-connected MOS transistor and a common-source cascode structure connected in series between the error amplifier and the power input terminal of the low-dropout linear regulator.

[0048] Step S2: A small signal voltage proportional to the power input voltage is generated by the diode-connected MOS transistor and transmitted to the input terminal of the cascode structure.

[0049] Step S3: Using the common source cascode structure, control the small signal voltage ratio between the output terminal and the power supply input terminal of the error amplifier;

[0050] Step S4: Based on the small signal voltage ratio, suppress the transmission of noise from the power input terminal to the error amplifier output terminal.

[0051] Specifically, in step S1, an enhancement unit consisting of a diode-connected MOS transistor connected in series with a common-source, common-gate structure is inserted, including:

[0052] Between the output node of the error amplifier and the power input terminal, a first MOSFET, a second MOSFET, and a third MOSFET are connected in series in sequence.

[0053] The source of the first MOS transistor is connected to the power input terminal, and the gate and drain of the first MOS transistor are shorted.

[0054] The source of the second MOS transistor is connected to the drain of the first MOS transistor, and its gate is connected to a fixed bias voltage.

[0055] The source of the third MOS transistor is connected to the drain of the second MOS transistor, its drain is connected to the output terminal of the error amplifier, and its gate is connected to the output terminal of the error amplifier.

[0056] The second MOS transistor and the third MOS transistor form a common source and common gate structure.

[0057] In this embodiment of the invention, the first MOSFET (MN1) is configured as a diode. Its source is directly connected to the power input terminal VIN to receive the input voltage and accompanying noise disturbances. The gate and drain of the first MOSFET are shorted, forming a diode-connected load structure, so that the DC potential of its drain (i.e., node VX) is lower than VIN by a threshold voltage, while simultaneously sensing small AC signal changes on VIN. The second MOSFET (MN2) has its source connected to the drain (node ​​VX) of the first MOSFET MN1, and its gate connected to an independent fixed bias voltage VB. This bias voltage VB is generated by a simple bias circuit (e.g., a current mirror bias source with a startup circuit) independent of the main power supply VIN noise to ensure its stability. MN2 works together with the subsequent MN3. The third MOSFET (MN3) has its source connected to the drain (node ​​VY) of the second MOSFET MN2. Its drain is directly connected to the output node VG of the error amplifier. Its gate is also connected to the same node VG, therefore MN3 operates as a diode-connected load. The second MOSFET MN2 and the third MOSFET MN3 together form a cascode structure. MN2 acts as a common-source amplifier (with its input at the gate VB, but small-signal paths are injected from the source VX), and MN3 serves as its common-gate load.

[0058] In this embodiment, through reasonable size design and bias voltage VB setting, it is ensured that the first MOSFET MN1, the second MOSFET MN2, and the third MOSFET MN3 all operate in the saturation region. This is the basis for the circuit to achieve its intended function. When there is AC noise or ripple (small signal vin) on the power input terminal VIN, the noise directly acts on the source of MN1. Since MN1 is a diode connection, a small signal voltage vx proportional to and in phase with vin will be generated on its gate-drain node VX; this small signal vx appears at the source of MN2. For MN2, its gate voltage VB is a fixed DC, so the change of vx is equivalent to injecting a small signal input into its source. This input signal is amplified and transmitted through the common-source, common-gate structure composed of MN2 and MN3. Because the cascode structure can generate extremely high output impedance (equivalent to amplifying the output resistance Ro3 of MN3 by approximately (gm2×Ro2) times), the impedance seen from node VX is extremely low, while the signal transmission efficiency to node VG is extremely high. Ultimately, a small signal voltage change vg is generated at the error amplifier output node VG that is approximately equal to the input noise vin, thus achieving vg / vin≈1.

[0059] This invention utilizes the significant equivalent impedance gain generated by the cascode structure formed by MN2 and MN3. This characteristic results in extremely low impedance from node VX, ensuring that VX is transmitted to node VG with almost no attenuation, thus achieving vg / vin≈1 at the error amplifier output. Most importantly, this gain effect is maintained over a wide operating current range. Therefore, even if the load current (IL) changes from light to heavy load, causing a drift in the power transistor gate voltage VG and the operating points of each MOSFET, the relationship vg / vin≈1 remains stable. This fundamentally overcomes the limitations of traditional simple boost structures (such as...). Figure 3 The inherent problem of a sharp deterioration in PSRR improvement due to the sudden drop in the on-resistance of MN2 under heavy load (as shown) is addressed by achieving a complex performance improvement with minimal circuit modifications. The structure is compact and easy to integrate. The enhancement unit consists of only three MOS transistors (MN1, MN2, MN3) connected in series, eliminating the need for complex charge pumps, additional amplification stages, or precisely matched feedforward / feedback networks. This structure is directly embedded between the error amplifier output node and the power supply, without altering the basic architecture of the LDO main loop. Therefore, the design complexity is low, the increase in layout area is minimal, and it is highly advantageous for implementation in highly integrated chips.

[0060] Specifically, in step S2, a small signal voltage proportional to the power input voltage is generated by the diode-connected MOS transistor and transmitted to the input of the cascode structure, including:

[0061] The AC disturbance signal in the power input voltage directly acts on the source of the first MOS transistor;

[0062] The first MOS transistor generates a first small-signal voltage at its gate and drain nodes that is proportional to the AC disturbance signal.

[0063] The first small-signal voltage is applied to the source of the second MOS transistor as the input signal of the common-source common-gate structure.

[0064] In this embodiment of the invention, the "diode-connected MOS transistor" refers to the first MOS transistor MN1. Its source is directly connected to the power input terminal VIN, and the gate and drain of the first MOS transistor are shorted at node VX. When the low dropout linear regulator (LDO) is operating, the power input terminal VIN is not an ideal DC voltage and is usually coupled with noise or ripple from the preceding circuitry (such as a switching power supply or battery connector). These unwanted AC disturbance signals (small-signal component vin) are directly applied to the source of MN1. Since MN1 is connected in diode form (gate-drain shorted), its gate-source voltage V_GS and drain-source voltage V_DS are always equal and together determine its conduction current. When an AC disturbance vin appears on VIN, the disturbance will directly and almost without attenuation change the source potential of MN1. For a MOS transistor operating in the saturation region with its gate and drain shorted, its drain current I_D has a square-law relationship with V_GS (approximately equal to VIN-V_X). Therefore, a small change in the source voltage vin will cause a synchronous change in V_GS, thereby modulating its drain current. To maintain current balance (the current in this branch is constrained by the subsequent cascode structure and the error amplifier output stage), the potential of node VX (i.e., the drain and gate of MN1) must be adjusted accordingly. As a result, a first small-signal voltage vx is generated at node VX that is proportional to and in phase (or highly correlated) with the input AC disturbance signal vin. This vx can be approximated as vx≈vin×A, where A is a proportionality coefficient close to 1, the specific value of which is determined by the small-signal transconductance gm1 and output resistance Ro1 of MN1 at this operating point, as well as the impedance looking down from node VX. Under the parameters designed in this invention, vx can "replicate" or "sense" the noise waveform on VIN with high precision. Node VX is directly connected to the source of the second MOS transistor MN2. Therefore, this first small-signal voltage vx is directly applied to the source terminal of the MOS transistor MN2, which constitutes the input stage of the cascode structure. For MN2, its gate is driven by a fixed, pure bias voltage VB, which can be considered AC ground in the small-signal model. Therefore, the voltage change vx applied to its source is completely equivalent to applying an input signal of magnitude -vx to its gate-source port (because v_gs=v_g-v_s=0-vx=-vx). Thus, the noise disturbance vin from the power supply input is converted into a proportional voltage signal vx via the diode-connected MN1 and successfully injected into the input of the cascode amplifier composed of MN2 and MN3 (specifically, the source terminal of MN2). This process is the crucial first step in the entire PSRR enhancement mechanism, ensuring that power supply noise information can be accurately picked up and fed into the subsequent high-gain, high-rejection-ratio processing unit (cascode structure), laying the signal foundation for finally achieving noise cancellation (vg follows vin) at the error amplifier output.

[0065] This invention connects the source of a diode-connected first MOSFET MN1 directly to the power input terminal VIN, allowing any AC disturbance signal vin on the input voltage to act directly on the sensing element without attenuation or delay. The diode connection of MN1 ensures that the potential change of its gate-drain node VX naturally and linearly follows the source disturbance, thus directly converting power supply noise into a proportional voltage signal vx. This sensing mechanism is simple, direct, and has a clear signal path, avoiding the signal attenuation, phase delay, or need for additional amplification stages common in traditional feedforward or feedback structures, laying an accurate signal foundation for subsequent precise cancellation. Utilizing the characteristics of mature devices, it achieves high linearity and high reliability signal transmission. The diode-connected MOSFET is in one of its most basic and stable operating states, and its small-signal characteristics (transconductance gm1) have good predictability and consistency in the saturation region. This invention utilizes this mature characteristic to achieve a linear conversion of noise voltage to current and then back to voltage (vin->vx). This method does not rely on special device models, complex linearization circuits, or precise bias conditions, thus exhibiting stronger robustness to process fluctuations and temperature variations, ensuring the stability and consistency of sensing signals under different operating environments. It provides an ideal and strongly driven input signal for the cascode processing unit. The generated vx signal is directly applied to the source of the second MOSFET MN2. For MN2, its gate is fixed biased (AC ground), so the change in the source signal vx is equivalent to the change in its gate-source voltage v_gs (v_gs = -vx), thereby efficiently converting the voltage signal vx into modulation of the drain current of MN2. This connection method utilizes the high input impedance characteristic of the MOSFET source as input, ensuring minimal load effect on the preceding stage (MN1), allowing vx to be transmitted with almost no loss. Simultaneously, it provides a low-impedance, strongly driven current signal source for the subsequent cascode structure (MN2-MN3), maximizing the gain and bandwidth of the entire noise processing path, ensuring that high-frequency noise can also be effectively tracked and processed.

[0066] Specifically, in step S3, the small-signal voltage ratio between the output terminal and the power supply input terminal of the error amplifier is controlled using the common-source cascode structure, including:

[0067] Step S31: Based on the common source cascode structure, generate an equivalent small-signal resistance gain and transmit the small-signal voltage to the output of the error amplifier;

[0068] Step S32: Through the common source cascode structure, the change in the output voltage of the error amplifier caused by the first small signal voltage is controlled to be approximately equal to the AC disturbance voltage at the power input terminal.

[0069] Specifically, in step S31, the equivalent small-signal resistance gain generated by the common-source cascode structure is determined by the transconductance and output resistance of the second and third MOS transistors.

[0070] Specifically, the product of the transconductance of the first MOSFET and the output resistance of the third MOSFET satisfies the following condition:

[0071] ;

[0072] Where gm1 is the transconductance of the first MOSFET and Ro3 is the output resistance of the third MOSFET.

[0073] In this embodiment of the invention, the common-source common-gate structure is composed of a second MOSFET MN2 and a third MOSFET MN3. The source of MN2 receives a noise sensing signal vx from the first MOSFET MN1, and its gate is driven by a fixed bias voltage VB. The source of MN3 is connected to the drain of MN2 (node ​​VY), and its gate and drain are connected together to the output node VG of the error amplifier. Therefore, MN3 operates in an active diode connection state, serving as the load of MN2. The small-signal voltage vx applied to the source of MN2 (originating from power supply noise vin) first generates an equivalent input voltage v_gs2 = -vx at the gate-source port of MN2. This voltage is converted into a controlled small-signal drain current i_d2 ≈ gm2 × (-vx) through the transconductance gm2 of MN2. This is the first voltage-to-current conversion and amplification; the small-signal current i_d2 attempts to flow out from the drain of MN2 (node ​​VY). However, MN3 here constitutes a common-gate amplifier. For MN3, its gate is connected to VG (which can be considered a virtual ground or a fixed reference point for small-signal transmission path analysis), and its source (node ​​VY) receives current i_d2. The key characteristic of the cascode structure is that it "boosts" the output resistance Ro2 of MN2 by approximately (gm3 × Ro3), where gm3 and Ro3 are the transconductance and output resistance of MN3, respectively. Therefore, the equivalent output resistance of MN2 looking upwards from node VY becomes extremely high, approximating as (gm3 × Ro3) × Ro2; due to the extremely high impedance looking upwards from VY, almost all of the current i_d2 flows through MN3 (towards node VG). MN3 acts as a diode-connected load with a small-signal resistance of approximately 1 / gm3. The current i_d2 flowing through MN3 generates a voltage drop across its terminals (i.e., between nodes VY and VG). Due to the extremely high impedance provided by the cascode structure, the current i_d2 can be "pushed" to the output node VG with almost no loss, resulting in a significant voltage change vg across VG. This process achieves extremely high equivalent small-signal resistance gain, meaning that a small voltage vx controls the current across a large impedance, ultimately producing a large voltage vg proportional to vx.

[0074] In this embodiment of the invention, the small-signal current equations of the network composed of MN1, MN2, and MN3 can be solved simultaneously. The core is that the gate of MN3 is connected to VG, and its v_gs3 = vg - vy. Through analysis, the ratio relationship between vg and vin (represented by vx) can be obtained. This invention, through design and biasing, ensures that the product of the transconductance gm1 of the first MOS transistor MN1 and the output resistance Ro3 of the third MOS transistor MN3 is much greater than 1, that is, gm1 × Ro3 >> 1. This is one of the key conditions for achieving ideal tracking. Under the above design conditions, combined with the huge impedance gain generated by the common source and common gate structure (MN2-MN3) (proportional to gm2 × Ro2 × Ro3), it can be finally deduced that the ratio between the small-signal change vg on the output voltage VG of the error amplifier and the small-signal disturbance vin at the power input terminal approximately satisfies: vg / vin ≈ 1 / (1 + (Ro1) / (gm2 × Ro2 × Ro3 + Ro2 + Ro3));

[0075] Since gm2×Ro2×Ro3 is much larger than Ro1, Ro2, and Ro3, the second term in the denominator approaches 0, therefore vg / vin≈1. This means that the voltage fluctuation vg at the output node of the error amplifier caused by the power supply noise vin is highly consistent with vin in both amplitude and phase. The gate voltage VG of the power transistor (PMOS) "follows" the noise variation of the power supply VIN. Because the source of the power transistor is directly connected to VIN, the noise component (vg-vin) in its gate-source voltage V_GS=VG-VIN becomes extremely small, thus greatly suppressing the transmission of noise to the output terminal from the source.

[0076] This invention creatively enables the power transistor gate voltage (VG) to accurately follow the noise changes of the power input (VIN) (i.e., vg / vin≈1) by introducing an enhancement unit at the output node of the error amplifier, consisting of a diode-connected MOSFET (MN1) and a cascode structure (MN2, MN3) in series. Crucially, the large and stable impedance gain provided by the cascode structure ensures that this following relationship does not significantly change with drastic variations in load current. Therefore, this invention overcomes the fundamental defect of traditional simple PSRR boosting circuits, which suffer from drastic performance degradation under heavy load conditions, achieving and maintaining near-theoretical PSRR performance across the entire operating range from light to heavy load. It achieves complex performance enhancements with a minimalist circuit structure, combining low power consumption and a small area: the enhancement unit consists of only three MOSFETs, requiring no additional operational amplifiers, precision matching networks, charge pumps, or large-capacitance capacitors. This structure is directly embedded in the existing LDO architecture, adding almost no additional quiescent current branches, thus having a negligible impact on the chip's total quiescent power consumption. Simultaneously, the number of new components is minimal, resulting in a very limited increase in the layout area. This invention provides a solution that achieves maximum PSRR performance gains with near-minimum circuit complexity, power consumption, and area overhead, making it highly practical and economical.

[0077] Specifically, in step S4, based on the small-signal voltage ratio, suppressing the transmission of noise from the power supply input terminal to the error amplifier output terminal includes:

[0078] The first small-signal voltage is transmitted to the output of the error amplifier through the common source cascode structure, so that the voltage ripple at the output of the error amplifier is approximately equal to the voltage ripple at the power input.

[0079] By utilizing the voltage follower relationship established between the output of the error amplifier and the power input, noise at the power input is blocked at this critical node.

[0080] In this embodiment of the invention, the power supply noise vin is converted into a proportional voltage vx via the first MOS transistor MN1 and applied as an input signal to the input terminal (source of MN2) of the cascode structure (MN2-MN3). This cascode structure, with its extremely high equivalent output impedance and precise current-to-voltage conversion capability, transmits the signal vx to the output node VG of the error amplifier (EA) with almost no distortion or attenuation. As a result, a voltage ripple vg is generated at node VG that is highly consistent with the power supply input noise vin in both amplitude and phase, i.e., vg≈vin is achieved. A noise "virtual ground" is established at the gate of the power transistor: this vg≈vin relationship is the core of the entire suppression mechanism. The source of the power transistor (typically a PMOS transistor) is directly connected to the power supply VIN, while its gate is connected to the output node VG of the error amplifier. Therefore, the gate-source voltage V_GS of the power transistor can be expressed as: V_GS = VG - VIN; its small-signal component is: v_gs = vg - vin. Since vg ≈ vin, substituting, we get: v_gs ≈ vin - vin = 0. Both the power supply VIN and the power transistor's gate VG have voltage fluctuations almost equal to vin, but the noise component in the potential difference (v_gs) between the power transistor's gate and source is nearly zero. For the power transistor, its drive signal (v_gs) is crucial in determining its conduction state and output current. When v_gs is not modulated by power supply noise, the power supply noise cannot be transmitted to its drain (transconductance gm_power) through the power transistor's amplification effect (transconductance gm_power), i.e., the LDO's output terminal VOUT.

[0081] This invention does not passively attenuate noise through filtering or isolation, but instead constructs a precise active feedforward path through steps S1 to S3. This path "copyes" the power supply noise vin and feeds it forward to the output node VG of the error amplifier, forming a voltage follower relationship where vg≈vin. Finally, in step S4, the natural suppression of common-mode signals (vg and vin) by the gate-source port of the power transistor is utilized to effectively cancel the noise at the control terminal (v_gs≈0), thereby blocking the noise transmission path from the power transistor to the core output at the source. This achieves a high power supply rejection ratio (PSRR) with a clear principle and significant effect, ensuring the stability and robustness of the high PSRR performance across the entire load range. The entire noise suppression mechanism is achieved by adding an enhancement unit consisting of three MOSFETs (MN1, MN2, MN3). This unit requires no additional bias current branch, complex control loop, or large passive components, and adds almost no static power consumption or chip area. This invention provides an elegant solution that achieves the highest performance gains with minimal complexity, power consumption, and area costs, demonstrating outstanding economic efficiency and practicality.

[0082] Specifically, it also includes a bias circuit for providing the fixed bias voltage, wherein the power supply terminal of the bias circuit is independent of the power supply input terminal.

[0083] Specifically, the first MOSFET, the second MOSFET, and the third MOSFET all operate in the saturation region.

[0084] Specifically, the product of the transconductance and output resistance of the second MOSFET and the output resistance of the third MOSFET is greater than the output resistance of the first MOSFET.

[0085] In this embodiment of the invention, the bias circuit providing a fixed gate bias voltage VB for the second MOSFET MN2 is not directly connected to the main power input VIN of the low-dropout linear regulator. Instead, it is connected to an independent, cleaner power domain (e.g., an on-chip power rail that has undergone preliminary voltage regulation, or a power supply with weaker noise coupling to VIN). This design ensures that the bias voltage VB itself is not directly affected by noise and ripple on the main power supply VIN, thus providing a stable DC voltage. In small-signal analysis, the gate of MN2 can be considered a clean AC ground. This power isolation design blocks the possibility of power supply noise interfering with the operating point of the cascode structure through the bias path, ensuring the accuracy and stability of the feedforward noise cancellation path, and is an important auxiliary measure for achieving a high PSRR target. The bias circuit can be a simple current mirror structure with a startup function, the design and implementation of which are well known in the art.

[0086] In the circuit design of this invention embodiment, through precise device size (W / L) planning and reasonable setting of the aforementioned independent bias voltage VB, it is ensured that the first MOSFET MN1, the second MOSFET MN2, and the third MOSFET MN3 operate stably in the saturation region under all expected operating conditions (including process corner, temperature, and load current variations). This is the foundation for realizing the small-signal model and performance prediction upon which the theoretical analysis of this invention relies. MOSFETs operating in the saturation region have high output impedance and stable transconductance characteristics, which allows MN1 to accurately and linearly convert vin to vx. Only then can the cascode structure formed by MN2 and MN3 exhibit its core characteristic of extremely high output impedance, thereby generating a huge equivalent small-signal resistance gain. If any MOSFET enters the linear region, its output impedance will drop sharply, causing a severe degradation of the gain effect of the cascode structure, making it impossible to achieve vg / vin≈1, and greatly reducing the PSRR improvement effect. Therefore, ensuring that all three MOSFETs are in the saturation region is a key prerequisite for the normal functioning of the circuit in this embodiment.

[0087] In this embodiment of the invention, the design requirements for device parameters satisfy the following: the product of the transconductance gm2 of the second MOS transistor MN2 and its output resistance Ro2, multiplied by the output resistance Ro3 of the third MOS transistor MN3, results in a value much larger than the output resistance Ro1 of the first MOS transistor MN1. That is, (gm2×Ro2×Ro3)>>Ro1. This condition directly guarantees the ideal following relationship of vg / vin≈1. From the provided small-signal transmission expression vg / vin≈1 / (1+Ro1 / (gm2×Ro2×Ro3+Ro2+Ro3)), it can be seen that only when (gm2×Ro2×Ro3) is much larger than Ro1 does the fractional term Ro1 / (gm2×Ro2×Ro3+...) approach 0, thus making the entire ratio approach 1. (gm2×Ro2×Ro3) essentially represents the huge impedance gain provided by the cascode structure. Therefore, this condition quantifies the minimum requirement for the gain of the cascode structure to overcome the influence of the MN1 output impedance, and is the core criterion for guiding circuit design and iterative optimization of transistor size.

[0088] This invention creatively enables the power transistor gate voltage to precisely follow the power input noise by introducing a simple yet efficient enhancement unit at a critical node, thereby achieving active cancellation on the core noise propagation path. Crucially, thanks to the large and stable impedance gain provided by the cascode structure, this excellent noise suppression effect remains stable across the entire operating range from light to heavy loads, completely overcoming the fundamental defect of traditional simple solutions where performance degrades sharply with increasing load current. The enhancement unit consists of only three MOSFETs, eliminating the need for charge pumps, complex feedforward networks, or additional amplification stages. This design achieves a significant leap in PSRR performance with almost no increase in quiescent current consumption and chip layout area, perfectly balancing the often contradictory design goals of high performance, low power consumption, and small area, providing a highly cost-effective solution. The performance improvement mechanism of this invention mainly relies on the intrinsic characteristics of the classic cascode structure and the defined transistor operating state (saturation region). It has low dependence on the absolute accuracy of device parameters and special process modules, and is more adaptable to process fluctuations, temperature changes and power supply disturbances, ensuring the reliability and consistency of performance under different manufacturing processes and actual working environments, and reducing design risks and manufacturing costs.

[0089] Figure 1This is a typical LDO circuit using a PMOS transistor as the power transistor, where BGR, EA, and Ppower represent the bandgap reference circuit, error amplifier, and power transistor, respectively. Δvin, Δvref, Δvg, and Δvout represent the ripple in the input voltage, the reference voltage, the gate voltage of the power transistor, and the output voltage, respectively. Let the PSRR of the error amplifier, power transistor, and bandgap reference circuit be P1, P2, and P3, respectively, and the open-loop gains of the error amplifier and power transistor be A1 and A2, respectively. Let P represent the overall PSRR of the LDO circuit, and β represent the resistor feedback network coefficient. Δvref is...

[0090]

[0091] Δvg is the sum of the small-signal ripple at the differential input of EA and the small-signal ripple at the power supply of EA, amplified by EA and corresponding to the small-signal output of EA.

[0092]

[0093] Δvout is the sum of the small-signal ripple at the Ppower gate and the small-signal ripple at the Ppower source, amplified by Ppower and corresponding to the small-signal output.

[0094]

[0095] Combining equations (1) and (3), the PSRR of the overall LDO circuit is:

[0096]

[0097] Next, we will derive the formulas for P2 and A2 of the PMOS power transistor separately. The PMOS power transistor and its small-signal model are shown in Figure 2. Figure 2(b) is the small-signal model of Figure 2(a), where 1 / geaout represents the output impedance of the first stage of the power transistor, i.e., the error amplifier. CGS and CGD represent the gate-source parasitic capacitance and gate-drain parasitic capacitance of the PMOS power transistor, respectively. gm and Ro represent the transconductance and on-resistance of the power transistor, respectively. vg represents the small-signal voltage of the gate of the power transistor. vout represents the small-signal voltage of the output stage. s is the Laplace variation factor. Req represents the total equivalent resistance of the output node. Req=(R1+R2) / / RL.

[0098] Based on this small-signal model, the node KCL equations for nodes vg and vout are listed respectively, and the following can be obtained:

[0099]

[0100]

[0101] Combining equations (5) and (6), and eliminating vg, we can obtain the DC PSRR of the PMOS power transistor as follows:

[0102]

[0103] Setting vin equal to 0 in equations (5) and (6) and combining them again, we can obtain the DC open-loop gain of the PMOS power transistor as follows:

[0104]

[0105] Substituting equations (7) and (8) into equation (4), we can obtain the DC PSRR of the overall LDO circuit as follows:

[0106]

[0107] In equation (9), once the error amplifier and bandgap reference circuit are determined, the only term that can be changed is 1-P1. To improve the power supply rejection performance of the LDO, the value of equation (9) needs to be made smaller. Therefore, if 1-P1≈0, i.e., P1≈1, the numerator in equation (9) can be reduced, thereby improving the PSRR of the LDO.

[0108] The above analysis shows that P1≈1 can improve the power supply rejection performance of the LDO. Based on this idea, a method can be derived, the circuit of which is as follows. Figure 3 As shown in the diagram, the yellow portion represents one structure that makes P1 approximately equal to 1. MN1 is a diode-connected metal-oxide-semiconductor field-effect transistor (MOS), so its on-resistance is 1 / gmp1, where gmp1 is the transconductance of MN1. MN2 is a common-source amplifier with an on-resistance of Rdsn2. Therefore, P1 can be expressed as...

[0109]

[0110] According to equation (10), as long as gmp1Rdsn2 is much greater than 1, P1 can be approximately equal to 1, thereby achieving the goal of improving PSRR.

[0111] This structure improves the PSRR of the circuit, but it has a drawback: the increase in load current IL leads to a decrease in the gate voltage vg of the power transistor, which increases the gate-source voltage vGS1 of MN1. Since MN1 is always operating in the saturation region due to its diode connection, the drain-source current IDS of MN1 will increase. MN1 and MN2 are on the same branch, so the drain-source current of MN2 will also increase. Note that vg is also the drain-source voltage of MN2. The decrease in MN2's drain-source voltage and the increase in its drain-source current work together to cause Rdsn2 of MN2 to decrease significantly with increasing IL, resulting in a decrease in P1, which is no longer approximately equal to 1. Therefore, as IL increases, the improvement effect of this structure on PSRR becomes less significant. To address this problem, this invention improves the structure, and the improved circuit structure exhibits good PSRR improvement under different IL conditions.

[0112] As is well known, the cascode structure can generate a gain on the small-signal resistance of a MOSFET, making the small-signal resistance the product of the gain and the small-signal resistance. Inspired by the cascode structure, the improved boosted PSRR structure is shown in Figure 4(a). Here, vb is the bias voltage, and voea is the voltage at the output of the error amplifier. A DC-biased NMOS transistor is connected in series with the original cascode amplifier, forming a cascode structure. The small-signal model of Figure 4(a) is shown in Figure 4(b). Since this is a PSRR derivation, vb and voea can both be considered grounded in the small-signal model. gm1 and gm2 are the transconductances of MN1 and MN2, respectively, and Ro1, Ro2, and Ro3 are the on-resistances of MN1, MN2, and MN3, respectively. Based on the fact that the current flowing through the three MOSFETs is equal, the following can be listed:

[0113]

[0114] Eliminating vx from the equation yields

[0115]

[0116] Comparing equations (12) and (10), it can be found that the condition for equation (10) to be approximately equal to 1 is that gmp1Rdsn2 is much greater than 1, but this condition gradually becomes invalid as the load current increases. In equation (12), due to the gain effect of the cascode structure on Ro3, the magnitude of gm2Ro2Ro3 is much greater than that of Ro1. Therefore, Ro1 / (gm2Ro2Ro3+Ro2+Ro3) in the denominator of equation (12) is approximately equal to 0, so vg / vin is approximately equal to 1 under different load currents. Therefore, the improved structure has a better effect on improving PSRR.

[0117] The above embodiments are merely illustrative examples and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A noise suppression method for a high PSRR, low dropout linear regulator, characterized in that, include: Step S1: Insert an enhancement unit consisting of a diode-connected MOS transistor and a common-source cascode structure connected in series between the error amplifier and the power input terminal of the low-dropout linear regulator. Step S2: A small signal voltage proportional to the power input voltage is generated by the diode-connected MOS transistor and transmitted to the input terminal of the cascode structure. Step S3: Using the common source cascode structure, control the small signal voltage ratio between the output terminal and the power supply input terminal of the error amplifier; Step S4: Based on the small signal voltage ratio, suppress the transmission of noise from the power input terminal to the error amplifier output terminal.

2. The noise suppression method for a high PSRR low dropout linear regulator according to claim 1, characterized in that, In step S1, an enhancement unit consisting of a diode-connected MOS transistor connected in series with a cascode structure is inserted, including: Between the output node of the error amplifier and the power input terminal, a first MOSFET, a second MOSFET, and a third MOSFET are connected in series in sequence. The source of the first MOS transistor is connected to the power input terminal, and the gate and drain of the first MOS transistor are shorted. The source of the second MOS transistor is connected to the drain of the first MOS transistor, and its gate is connected to a fixed bias voltage. The source of the third MOS transistor is connected to the drain of the second MOS transistor, its drain is connected to the output terminal of the error amplifier, and its gate is connected to the output terminal of the error amplifier. The second MOS transistor and the third MOS transistor form a common source and common gate structure.

3. The noise suppression method for a high PSRR low dropout linear regulator according to claim 1, characterized in that, In step S2, a small signal voltage proportional to the power input voltage is generated by the diode-connected MOS transistor and transmitted to the input terminal of the cascode structure, including: The AC disturbance signal in the power input voltage directly acts on the source of the first MOS transistor; The first MOS transistor generates a first small-signal voltage at its gate and drain nodes that is proportional to the AC disturbance signal. The first small-signal voltage is applied to the source of the second MOS transistor as the input signal of the common-source common-gate structure.

4. The noise suppression method for a high PSRR low dropout linear regulator according to claim 1, characterized in that, In step S3, the small-signal voltage ratio between the output terminal and the power supply input terminal of the error amplifier is controlled using the common-source cascode structure, including: Step S31: Based on the common source cascode structure, generate an equivalent small-signal resistance gain and transmit the small-signal voltage to the output of the error amplifier; Step S32: Through the common source cascode structure, the change in the output voltage of the error amplifier caused by the first small signal voltage is controlled to be approximately equal to the AC disturbance voltage at the power input terminal.

5. The noise suppression method for a high PSRR low dropout linear regulator according to claim 4, characterized in that, In step S31, the equivalent small-signal resistance gain generated by the common-source cascode structure is determined by the transconductance and output resistance of the second MOS transistor and the third MOS transistor.

6. The noise suppression method for a high PSRR low dropout linear regulator according to claim 1, characterized in that, The product of the transconductance of the first MOSFET and the output resistance of the third MOSFET satisfies the following condition: ； Where gm1 is the transconductance of the first MOSFET and Ro3 is the output resistance of the third MOSFET.

7. The noise suppression method for a high PSRR low dropout linear regulator according to claim 1, characterized in that, In step S4, based on the small-signal voltage ratio, the transmission of noise from the power supply input terminal to the error amplifier output terminal is suppressed, including: The first small-signal voltage is transmitted to the output of the error amplifier through the common source cascode structure, so that the voltage ripple at the output of the error amplifier is approximately equal to the voltage ripple at the power input. By utilizing the voltage follower relationship established between the output of the error amplifier and the power input, noise at the power input is blocked at this critical node.

8. The noise suppression method for a high PSRR low dropout linear regulator according to claim 1, characterized in that, It also includes a bias circuit for providing the fixed bias voltage, wherein the power supply terminal of the bias circuit is independent of the power supply input terminal.

9. The noise suppression method for a high PSRR low dropout linear regulator according to claim 1, characterized in that, The first MOSFET, the second MOSFET, and the third MOSFET all operate in the saturation region.

10. The noise suppression method for a high PSRR low dropout linear regulator according to claim 1, characterized in that, The product of the transconductance and output resistance of the second MOSFET and the output resistance of the third MOSFET is greater than the output resistance of the first MOSFET.

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