Low power consumption low voltage differential linear regulator with enable control function

Abstract

The application belongs to the technical field of integrated circuits, and discloses a low-power consumption LDO without external capacitor with an enabling control function. A FVF structure is used as a bias current source of a differential input pair in an improved FC circuit, and a local common-mode negative feedback loop is introduced, so that a high-swing error amplifier working in AB class is formed. Through compensation circuit design, the transient response of the LDO circuit under the condition of no capacitor load is realized, the overshoot voltage and undershoot voltage are not more than 300 mV, and the whole circuit can stably output 1.8 V voltage under 3.3 V voltage. Through coupling of the compensation circuit and the improved high-swing error amplifier, the power consumption is reduced, and the chip area is saved. The enabling circuit design enables the circuit to work normally when the enabling signal SEL is high, and the circuit is turned off when SEL is low, so that the power consumption of the circuit is extremely low when it is turned off, thereby improving the reliability of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a low-power, capacitor-free, low-dropout linear regulator with enable control function. Background Technology

[0002] Low dropout linear regulators (LDOs) are widely used in various electronic devices due to their simple structure, low noise, and low cost, providing stable and clean power to core chips. With the rapid development of the Internet of Things (IoT), wearable devices, and portable medical electronics, higher demands are being placed on LDOs: 1) Eliminating the need for large external capacitors to save PCB area and system cost (i.e., "capacitor-free" or "small-capacitor" LDOs); 2) Low quiescent current to extend battery life; 3) High power supply rejection ratio (PSRR) to resist noise interference on power lines; 4) Integrated enable control for easy power domain management and reduced system standby power consumption; 5) Maintaining stability over a wide load current range and under zero-load capacitor conditions.

[0003] Traditional LDOs typically require an off-chip capacitor in the microfarad (μF) range at their output to ensure loop stability, which increases system size and cost. While some capacitor-free LDO designs exist, they generally face the following challenges:

[0004] 1. The trade-off between stability and transient response speed: To maintain stability without external capacitors, the loop bandwidth is usually narrow, resulting in slow load transient response and excessive undershoot and overshoot in the output voltage. 2. Performance trade-off under light and heavy load conditions: Under extremely light load conditions (e.g., 1μA), to reduce power consumption, the circuit bias current is very small, leading to a sharp drop in the gain-bandwidth product (GBW) and performance degradation; while under heavy load conditions (e.g., 100mA), sufficient bandwidth and slew rate are needed to ensure fast response. 3. The performance trade-off between light and heavy load conditions: Under extremely light load conditions (e.g., 1μA), to reduce power consumption, the circuit bias current is very small, leading to a sharp drop in the gain-bandwidth product (GBW) and performance degradation; while under heavy load conditions (e.g., 100mA), sufficient bandwidth and slew rate are needed to ensure fast response.

[0005] Therefore, there is an urgent need in this field for a new type of capacitorless LDO solution that can simultaneously achieve high stability, fast transient response, high power supply rejection ratio, and low quiescent current.

[0006] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0007] (1) The contradiction between stability and transient response speed: In order to maintain stability without external capacitors, the loop bandwidth is usually narrow, which leads to slow load transient response speed and excessive undershoot and overshoot of output voltage.

[0008] (2) Performance trade-offs under light and heavy load conditions: Under extremely light load conditions (such as 1μA), in order to reduce power consumption, the circuit bias current is very small, which leads to a sharp drop in the gain-bandwidth product (GBW) and performance degradation; while under heavy load conditions (such as 100mA), sufficient bandwidth and slew rate are required to ensure fast response.

[0009] (3) Performance trade-offs under light and heavy load conditions: Under extremely light load conditions (such as 1μA), in order to reduce power consumption, the circuit bias current is very small, which leads to a sharp drop in the gain-bandwidth product (GBW) and performance degradation; while under heavy load conditions (such as 100mA), sufficient bandwidth and slew rate are required to ensure fast response. Summary of the Invention

[0010] To address the problems existing in the prior art, this invention provides a low-power LDO with enable control function and no external capacitor.

[0011] This invention is implemented as follows: a low-power, capacitor-free, low-dropout linear regulator with enable control function, comprising:

[0012] High slew rate error amplifier, enable control circuit, adaptive bias circuit, transient response compensation circuit;

[0013] High slew rate error amplifier: Its non-inverting input is connected to the reference voltage VREF, and its inverting input is connected to the output feedback voltage VFB of the LDO.

[0014] Transient response compensation circuit: Couple the transient compensation circuit to the improved high slew rate error amplifier;

[0015] Enable control circuit: Combining logic control and analog circuit shutdown, it provides safe power management and enables high-level activation and low-level shutdown.

[0016] Furthermore, the high slew rate error amplifier:

[0017] Its non-inverting input is connected to the reference voltage VREF, and its inverting input is connected to the output feedback voltage VFB of the LDO; the high slew rate error amplifier is an improvement on the structure of the traditional folded common-source amplifier (FC);

[0018] Improvement 1: To improve efficiency by using M3 and M4 as driver transistors, the input driver transistors M1 and M2 are first split into two sets of transistors: Ma1 and Mb2, and Ma2 and Mb2. These split CMOS transistors need to carry a fixed and equal current. Then... Figure 2 The current mirrors M3 and M4 are split proportionally to form Ma3, Mb3 and Ma4, Mb4; the cross-coupling connection between the current mirrors (Mb3, Ma4) and the input transistors (Mb1, Ma2) ensures that the small signal current is in phase with the source; the other transistors remain unchanged and continue to use the traditional FC structure.

[0019] Improvement 2: An Flipped Voltage Follower (FVF) structure is used to bias the input differential pair transistors. Alternatively, two matching resistors can be added to the input stage to make the op-amp operate in Class AB. The first method is improved as follows: In the traditional Folded Cascode (FC) circuit, the tail current source of the input differential pair is a fixed value. This means that the sum of the source currents of the input differential pair transistors is clamped. Therefore, the maximum current at the output terminal is also limited to As in formula (1):

[0020] (1)

[0021] (K is the mirror factor from the input stage to the output stage), and its slew rate formula is (2):

[0022] (2)

[0023] The output impedance formula (3) for FVF is approximately:

[0024] (3)

[0025] in , This is the transconductance of the corresponding MOSFET, and roB is the output impedance of MB. This value is very small, meaning that FVF is an ideal voltage source, capable of quickly providing or sinking current to the load; thus, the source current of the input differential pair is no longer limited by... This generates a large current, which is then mirrored to the output stage via a current mirror, resulting in a large output current IOUT; the corresponding slew rate SR is no longer determined by... The decision is made by the following formula (4).

[0026] (4)

[0027] Assuming a large input signal causes VIN to be much greater than VIP, the drain current Ib3 of Mb3 will increase sharply, while the drain current Ib4 of Ma4 will decrease sharply. Ib3 will generate a significant voltage drop across the gate resistor RCM1 of Mb3, as shown in formula (5).

[0028] (5)

[0029] Formula (6) for the gate voltage of Mb3

[0030] (6)

[0031] Enlargement leads to Decrease; because the current Ia4 flowing through Ma4 is very small, ≈0, its gate voltage of Ma4 is approximately equal to its drain voltage; the drain voltages of Mb3 and Ma4 are approximately equal, and thus formula (7) can be obtained:

[0032]

[0033] (7)

[0034] Furthermore, the transient response compensation circuit:

[0035] The transient compensation circuit design significantly improves the transient response of the circuit, effectively ensuring the realization of an LDO circuit without external capacitors; the transient compensation circuit is coupled with an improved high slew rate error amplifier.

[0036] Furthermore, the enable control circuit:

[0037] The key control section consists of a three-stage inverter chain of Mp1-Mp3 and Mn1-Mn3, with each stage typically having a larger width-to-length ratio than the previous stage, acting as a buffer to enhance signal drive and rapidly charge and discharge the gate capacitance of subsequent MOS transistors, thereby accelerating switching speed and reducing state transition delays. In the bias circuit section, Mp4 and Mp5, along with the PMOS switches Mp6, Mp7, Mn4, and Mn5 for bias tail current, are connected in series in the current path of the bias circuit, eliminating power consumption of the internal analog module at its source and reducing the quiescent current of the entire LDO to almost zero, maximizing power savings. Mp8 controls the gate of the power transistor, ensuring complete turn-off and eliminating leakage current. The Mn6 switch, output to ground, eliminates any possibility of leakage current caused by a floating gate, achieving "complete turn-off".

[0038] Another objective of this invention is to provide a low-power, capacitor-free LDO control method with enable control functionality, comprising:

[0039] Step 1: Connect the non-inverting input of the high slew rate error amplifier to the reference voltage VREF, and connect the inverting input to the output feedback voltage VFB of the LDO.

[0040] Step 2: Couple the transient compensation circuit with the improved high slew rate error amplifier through the transient response compensation circuit;

[0041] Step 3: By combining the enable control circuit with logic control and analog circuit shutdown, safe power management is achieved, enabling high-level activation and low-level shutdown.

[0042] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0043] For existing capacitorless LDOs, especially low-power LDOs integrated into on-chip power management scenarios, there are generally three key technical contradictions: First, transient performance and static power consumption are difficult to balance. Traditionally, to ensure recovery speed during load surges, the error amplifier tail current or the power transistor drive capability is often increased. However, this directly raises the static current, leading to increased standby power consumption and thermal design pressure. Conversely, if the bias current is lowered to pursue low power consumption, the error amplifier slew rate is limited, the gate drive node charging and discharging speed is insufficient, resulting in significant output voltage undershoot during load surges and significant overshoot during load shedding, even inducing loop stability deterioration. Second, without external capacitors, the output pole damping is insufficient, the loop compensation window is narrower, and the "Gate node" between the error amplifier and the power transistor becomes a dynamic bottleneck. Simply relying on slow negative feedback is insufficient to suppress rapid disturbances in VOUT in a timely manner. Third, enable control is an essential function in low-power chips, but existing solutions often only perform logic shutdown or single-point isolation. Residual leakage current in the bias branch and gate floating issues in the shutdown state can still cause quiescent current and reliability risks. Simultaneously, slow node recovery during start-up and shutdown also prolongs output setup time and affects the system's power-on sequence control. The challenge in solving these problems lies in simultaneously improving large-signal driving capability and transient suppression capability without significantly increasing quiescent current, introducing external capacitors, or compromising loop stability and reliable shutdown.

[0044] This invention addresses the core challenge of "rapid gate node control" by proposing a synergistic solution involving error amplifier slew rate, transient compensation, and enable / disable switching, thus simultaneously resolving the aforementioned difficulties at the mechanistic level. First, on the error amplifier side, the input stage and current mirror of the traditional folded cascode structure are separated and cross-coupled, ensuring that small-signal currents remain in phase at the folded node, improving equivalent transconductance and current utilization. Furthermore, a matching resistor is added to the input stage to form a local common-mode feedback loop, ensuring that the potentials across the resistor are the same at the DC operating point, resulting in no DC current and thus no increase in static power consumption. Under large-signal conditions, the gate voltage difference generates feedback through the resistor, increasing the output drive current as the product of the input stage dynamic current and the resistor value. This causes the error amplifier to exhibit Class AB drive characteristics, significantly improving the charging and discharging capability of the gate node and overcoming the bottleneck of output slew rate limitation imposed by the traditional fixed tail current. Secondly, on the transient compensation side, by coupling the output voltage change to the source node of the key transistor via capacitors, a fast net injection current or net extraction current path to the gate node is constructed. This allows for rapid extraction of gate charge when the load suddenly increases to enhance power transistor conduction and suppress VOUT undershoot, and rapid injection of gate charge when the load suddenly decreases to weaken power transistor conduction and suppress VOUT overshoot. This achieves first-time clamping of output disturbances before the feedback loop is fully established, enabling rapid recovery without external capacitors. Finally, on the enable control side, a three-stage inverter chain enhances the drive capability, and a switch is connected in series on the bias current path to cut off the analog module's power consumption at the current source. Simultaneously, strong pull-up and pull-down and discharge are applied to the power transistor gate and key nodes to prevent gate floating and residual leakage, ensuring that the static current in the off state approaches zero and that start-stop transitions are rapid and reliable. Based on the synergy of the above mechanisms, this invention achieves a comprehensive and innovative technical effect under low power consumption constraints, including improved slew rate, significant suppression of transient undershoot and overshoot, substantial reduction of turn-off leakage current, and enhanced feasibility of LDO without external capacitors. This solves the inherent contradiction in the prior art that "high transient performance must come at the cost of high static power consumption or external capacitors".

[0045] This invention significantly reduces system BOM cost and size: Traditional LDOs typically require external 1μF or larger ceramic capacitors to maintain transient stability. This invention allows for direct power supply to the digital core, analog modules, or RF circuits without external capacitors or other components. This not only saves on the material cost per chip, but more importantly, it saves valuable PCB area. This is of immeasurable value for consumer electronics that pursue ultra-thin and compact designs (such as wearable devices, mobile phones, and tablets) and communication modules and IoT terminals that require high-density integration.

[0046] This invention redefines the battery life and application scenarios of battery-powered devices with its groundbreaking low-power characteristics. The distributed enable switch architecture proposed in this invention suppresses the off-state leakage current to 8.129 μA even at worst-case process corners and a high temperature of 125°C. Figure 9 ), and combined with a static current ≤30μA under full load ( Figure 10 The superior performance of this technology systematically solves the power consumption problem under advanced processes. This brings orders of magnitude improvement potential to battery-powered devices and expands the application boundaries of power management chips to cutting-edge fields that are extremely sensitive to power consumption, such as energy harvesting and passive IoT, thereby opening up new high-value markets.

[0047] Does the technical solution of this invention overcome technical bias? In this technical field, there has long been a prevalent and deeply ingrained bias: "To obtain a good load transient response, an LDO must rely on an external output capacitor of a certain capacitance to provide instantaneous charge buffering; completely removing the external capacitor inevitably leads to a severe deterioration in transient performance, failing to meet the requirements of high-performance applications." This bias stems from the stability theory of traditional LDO design, leading those skilled in the art to generally view reliance on external capacitors as an unavoidable technical choice, and to be forced to bear the resulting systemic costs and design complexity. This invention fundamentally challenges and successfully overcomes this technical bias. Completely different from existing technical paths, this solution, through an original circuit architecture and design method—especially the synergistic design of a specific internal frequency compensation network and a high slew rate error amplifier—eliminates dependence on any external compensation capacitor. Detailed post-simulation data (verification closest to the fabrication results) strongly demonstrates its breakthrough effect: under extreme conditions without external capacitors, the circuit's output voltage transient deviation is strictly constrained to within ±300mV when handling a drastic full-range load step of 100μA to 100mA within 1μS (e.g., Figure 8 As shown: the actual overshoot voltage is 123mV, and the undershoot voltage is 293mV. Meanwhile, the solution also achieves excellent overall performance with a static current not exceeding 30μA across the entire process angle and a turn-off leakage current as low as μA.

[0048] This achievement demonstrates that, through ingenious internal circuit design, sufficient transient response and stability can be provided entirely by the chip itself, thus physically eliminating the need for external capacitors. This invention not only achieves high-performance specifications previously considered impossible to attain under "no external capacitor" conditions, but even surpasses traditional designs that rely on external capacitors in some aspects. Therefore, this solution breaks through long-standing industry norms and design taboos, opening a completely new technical path for hyper-integrated, high-reliability power management, fully demonstrating its outstanding substantive features and significant progress. Attached Figure Description

[0049] Figure 1 This is a block diagram of a low-power LDO structure with enable control function provided in an embodiment of the present invention.

[0050] Figure 2 This is a schematic diagram of a conventional common-source cascode amplifier circuit provided in an embodiment of the present invention.

[0051] Figure 3 The present invention provides (1) an improved FC amplifier circuit using FVF as a bias voltage source and (2) an improved FC amplifier circuit.

[0052] Figure 4 This is a high slew rate error amplifier operating in Class AB after combining FVF+R, as provided in the embodiments of the present invention.

[0053] Figure 5 This is a circuit diagram of the transient response compensation circuit provided in an embodiment of the present invention.

[0054] Figure 6 This is a schematic diagram of an LDO circuit with enable control function without external capacitors provided in an embodiment of the present invention.

[0055] Figure 7 This is a flowchart of a low-power, capacitor-free LDO with enable control function provided in an embodiment of the present invention.

[0056] Figure 8 Simulation diagram of transient response of LDO circuit without load capacitor.

[0057] Figure 9 Simulation of leakage current at different process angles under 125℃ conditions.

[0058] Figure 10 The curves showing the variation of static current with load current at different process angles.

[0059] In the diagram: 1. High slew rate error amplifier; 2. Enable control circuit; 3. Adaptive bias circuit; 4. Transient response compensation circuit. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0061] like Figure 1 As shown, an embodiment of the present invention provides a low-power capacitorless LDO with enable control function, comprising:

[0062] 1. High slew rate error amplifier; 2. Enable control circuit; 3. Adaptive bias circuit; 4. Transient response compensation circuit;

[0063] High slew rate error amplifier 1: Its non-inverting input is connected to the reference voltage VREF, and its inverting input is connected to the output feedback voltage VFB of the LDO.

[0064] Transient response compensation circuit 4: Couple the transient compensation circuit to the improved high slew rate error amplifier;

[0065] Enable control circuit 2: Combines logic control and analog circuit shutdown for safe power management, enabling high-level activation and low-level shutdown.

[0066] This invention provides a low-power, capacitor-free LDO with enable control functionality, comprising a high slew rate error amplifier 1, an enable control circuit 2, an adaptive bias circuit 3, and a transient response compensation circuit 4. The non-inverting input of the high slew rate error amplifier 1 is connected to a reference voltage VREF, and the inverting input is connected to an output feedback voltage VFB. Its output drives the gate of the power transistor Mpass through the adaptive bias circuit 3, achieving linear voltage regulation control of the output voltage VOUT. The output is fed back to the inverting input via a voltage divider network composed of resistors R1 and R2, thus forming a stable closed-loop negative feedback regulation structure.

[0067] Enable control circuit 2 is located in the bias path of the error amplifier's pre-amplifier stage. It manages the internal analog bias current through logic control signals, enabling the LDO to enter normal voltage regulation when the enable signal is high and to shut down the core analog module when the enable signal is low, thus preventing static leakage current. Transient response compensation circuit 4 is coupled to a key node of the high slew rate error amplifier, providing additional dynamic adjustment capability when the load current changes rapidly, thereby improving the system's transient response performance.

[0068] like Figure 2 As shown, the traditional folded cascode error amplifier uses a PMOS input differential pair and a folded current mirror structure. M1 and M2 are used as input transistors, while M3 and M4 are mainly used for current folding and current mirror replication. Most of their current is used only for structural support, resulting in low current utilization.

[0069] To address the above problems, the present invention is as follows: Figure 3The diagram shows an improvement on the traditional FC (current-driven) structure: the original input transistors M1 and M2 are split into two sets of parallel input transistors Ma1, Mb1 and Ma2, Mb2, each carrying a fixed and equal bias current; simultaneously, the original folded current mirror transistors M3 and M4 are proportionally split into Ma3, Mb3 and Ma4, Mb4, thus constructing a cross-coupled current-driven structure. The remaining bias transistors and output stage structure remain consistent with the traditional FC structure to ensure the stability and feasibility of the overall topology.

[0070] Under normal operating conditions, after the enable control circuit 2 receives a high-level enable signal, it turns on the error amplifier and its bias branch, enabling the high-slew rate error amplifier 1 to enter the working state. The reference voltage VREF and the output feedback voltage VFB are compared at the input terminal. When VOUT deviates, the error amplifier outputs a corresponding control signal, which, after being modulated by the adaptive bias circuit 3, drives the gate voltage of the power transistor Mpass, thereby adjusting the conduction level of Mpass and restoring the output voltage to the set value.

[0071] Inside the error amplifier, the small-signal voltage difference is first sensed and converted into a differential current signal by the PMOS input transistors Ma1, Mb1 and Ma2, Mb2. Since the input transistors are split into two groups carrying equal quiescent currents, the current changes generated under small-signal conditions can be superimposed in phase through the cross-coupled current mirror structure in the subsequent stage. Specifically, the cross-connection relationship between the current mirrors Mb3, Ma4 and the input transistors Mb1, Ma2 ensures that the current changes generated by the differential inputs no longer cancel each other out, but are effectively superimposed at the drive node, thereby significantly improving the equivalent transconductance of the error amplifier.

[0072] Meanwhile, M3 and M4, which originally only served a folding function, were reused to drive small-signal current paths, allowing their operating current to directly participate in the signal amplification process, thus improving the overall current utilization rate. Under the same static power consumption conditions, this structure can achieve a higher output current swing and faster charging and discharging capability, thereby significantly improving the slew rate performance of the error amplifier.

[0073] When the load current changes abruptly, the transient response compensation circuit 4 rapidly injects or extracts charge into the control node through dynamic coupling of the key node, and in conjunction with the enhanced driving capability of the high slew rate error amplifier, accelerates the adjustment speed of the gate voltage of the power transistor Mpass, suppresses the overshoot or undershoot of the output voltage, and thus maintains good transient stability even without external capacitors.

[0074] Through the above structure and working method, the present invention achieves a low-power LDO regulator with high slew rate, high efficiency, and enableable controllability without significantly increasing static power consumption.

[0075] The high slew rate error amplifier provided in this embodiment of the invention has its non-inverting input connected to the reference voltage VREF, and its inverting input connected to the output feedback voltage VFB of the LDO; specifically, the high slew rate error amplifier in this invention adopts the structure of a traditional folded common-source amplifier (FC) (such as...). Figure 2 Improvements were made to the circuit (as shown) to enhance its efficiency and overall performance;

[0076] Traditional FC circuits use either PMOS or NMOS transistors for the input section. This design prioritizes PMOS as the input transistor due to its higher non-dominant pole, lower flicker noise, and lower input common-mode level. Figure 2 (As shown) The current flowing through M3 and M4 is the largest; however, their function is limited to providing folding nodes for the input drive transistor and the generated small signal current. Now, an improvement is made to the traditional FC circuit:

[0077] Improvement 1: To improve efficiency by using M3 and M4 as driver transistors, the input driver transistors M1 and M2 are first split into two sets of transistors: Ma1 and Mb2, and Ma2 and Mb2. These split CMOS transistors need to carry a fixed and equal current. Then... Figure 2 The current mirrors M3 and M4 are split proportionally to form Figure 3 The cross-coupling connection between Ma3, Mb3 and Ma4, Mb4, and the current mirrors (Mb3, Ma4) and the input transistors (Mb1, Ma2) ensures that the small signal current remains in phase with the source; the other transistors remain unchanged and continue to use the traditional FC structure.

[0078] Improvement 2: An FVF (Flipped Voltage Follower) structure is used to bias the input differential pair transistors. Alternatively, two matching resistors can be added to the input stage to make the op-amp operate in Class AB. The first method is improved as follows: In a traditional FC circuit, the tail current source of the input differential pair is a fixed value. This means that the sum of the source currents of the input differential pair transistors is clamped. Therefore, the maximum current at the output terminal is also limited to As in formula (1):

[0079] (1)

[0080] (K is the mirror factor from the input stage to the output stage), and its slew rate formula is (2):

[0081] (2)

[0082] ( (It is the load capacitor) Therefore, in the traditional FC structure, to improve The only way is to increase or However, this would directly increase the overall power consumption of the circuit; therefore, to address the above problem, a flip-flop voltage follower (FVF) is introduced, such as... Figure 3 (1) shows that MB is a common-source amplifier, MA is a source follower, and the source node VX of MA is the output terminal of FVF, which is used to provide bias for the differential input pair; FVF is a local negative feedback mechanism composed of MA and MB; this mechanism greatly reduces the AC small-signal output impedance seen from node VX; the output impedance formula (3) of FVF is approximately:

[0083] (3)

[0084] in , This is the transconductance of the corresponding MOSFET, and roB is the output impedance of MB. This value is very small, meaning that FVF is an ideal voltage source, capable of quickly providing or sinking current to the load; thus, the source current of the input differential pair is no longer limited by... This creates a large current, which is then mirrored to the output stage through a current mirror, resulting in a huge output current IOUT; the corresponding slew rate SR is no longer determined by... The decision is made by the following formula (4).

[0085] (4)

[0086] Therefore, introducing an FVF as a bias source essentially transforms a Class A input stage into a Class AB input stage, thereby improving the slew rate of the op-amp without significantly increasing power consumption.

[0087] Another way to increase the slew rate is to add two matching resistors between the drain and gate of the input pair transistors, respectively. Figure 4 The local common-mode feedback loop shown (RCM1 and RCM2) also enables the op-amp to operate in class AB; the common-mode voltages of the drains of Mb3 and Ma4 are fed back to their common terminal. At the DC operating point, the two ends of resistors RCM1 and RCM2 have the same voltage and no DC flows through them, so the static power consumption does not increase.

[0088] Assuming a large input signal causes VIN to be much greater than VIP, the drain current Ib3 of Mb3 will increase sharply, while the drain current Ib4 of Ma4 will decrease sharply. Ib3 will generate a significant voltage drop across the gate resistor RCM1 of Mb3, as shown in formula (5).

[0089] (5)

[0090] Formula (6) for the gate voltage of Mb3

[0091] (6)

[0092] Enlargement leads to Decrease; because the current Ia4 flowing through Ma4 is very small, ≈0, its gate voltage of Ma4 is approximately equal to its drain voltage; the drain voltages of Mb3 and Ma4 are approximately equal, and thus formula (7) can be obtained:

[0093]

[0094] (7)

[0095] Gate voltage difference This will result in a larger output current. Output current The current is independent of the quiescent current but proportional to the product of the input stage's dynamic current Ib3 and RCM1. By appropriately setting the resistance values ​​of RCM1 and RCM2, the output current can be multiplied, thereby improving SR. This is achieved through the combination of FVF and R enhancement technologies. Figure 5 The improved FC circuit shown implements a high slew rate error amplifier operating in Class AB.

[0096] The transient response compensation circuit provided in this embodiment of the invention:

[0097] as follows Figure 5 Capacitors C1 and C2 are connected between the LDO output and the source terminals of transistors M11 and Mb3, respectively. During steady-state operation, the source potentials of these MOSFETs are set by the voltage drop across resistors Rm1 and RK1. This voltage drop is caused by the bias current Idc generated between the cascaded current mirrors M6, M7, Ma3, Mb3, Rk1, Rk2 and M8-M11, Rm1, Rm2. If, during steady-state operation, the load current suddenly increases, the output voltage will drop rapidly. The feedback loop EA needs time to react, but the output voltage change is immediately transmitted to the source terminal of Mb3 by capacitor C2. The potential at node K is rapidly reduced, thus lowering the gate-source voltage of Mb3. The rapid increase leads to a huge leakage current. Simultaneously, as the output voltage decreases, node M is also pulled down, causing the source voltage of M11 to drop, thereby affecting the absolute value of the gate-source voltage of M11. The current injected into the Gate terminal of M11 decreases as the load current decreases. As a result, a large net current is rapidly drawn from the Gate terminal, quickly pulling down the gate voltage of the power transistor Mpass and injecting more current into the load, thus preventing the output voltage from dropping. Conversely, when the load current suddenly decreases, the output voltage increases. The rapid rise of VOUT is coupled to the source of M11 through C1, causing the source voltage of M11 to rise rapidly, leading to… The voltage increases, resulting in a large source current; simultaneously, the rise in VOUT affects Mb3 through C2, causing the source voltage of Mb3 to increase and VGS_Mb3 to decrease. This reduces the current flow to the load and suppresses the rise of VOUT.

[0098] The transient compensation circuit design significantly improves the transient response of the circuit, effectively ensuring the realization of an LDO circuit without external capacitors. The transient compensation circuit is coupled with the improved high slew rate error amplifier, as shown in the figure. The transistors are rationally allocated for dual utilization, thereby reducing chip power consumption and chip area.

[0099] The enable control circuit provided in this embodiment of the invention:

[0100] The enable control circuit design of this project combines logic control and analog circuit shutdown to achieve efficient and safe power management, enabling high-level activation and low-level shutdown.

[0101] The enable control circuit is as follows: Figure 6As shown, the key control section consists of a three-stage inverter chain of Mp1-Mp3 and Mn1-Mn3, with each stage typically having a larger width-to-length ratio than the previous stage, acting as a buffer to enhance signal drive and rapidly charge and discharge the gate capacitance of subsequent MOS transistors, thereby accelerating switching speed and reducing state transition delays. In the bias circuit section, Mp4 and Mp5, along with the PMOS switches Mp6 and Mp7, and Mn4 and Mn5 for bias tail current, are connected in series in the current path of the bias circuit. This eliminates the power consumption of the internal analog module at its source, reducing the quiescent current of the entire LDO to a minimum. The power consumption is almost zero, maximizing power saving; the Mp8 gate of the power transistor ensures complete power transistor turn-off, eliminating leakage current; the Mn6 switch output to ground eliminates any possibility of leakage current caused by gate floating, achieving "complete turn-off"; through the above-mentioned specific enable circuit design, the circuit is turned on when the enable signal SEL is high and turned off when SEL is low; and the LDO circuit has almost no quiescent current and extremely low power consumption when turned off; strong pull-down and pull-up ensure fast turn-on and turn-off speeds; at the same time, it avoids node floating, improving circuit reliability.

[0102] like Figures 4 to 6 As shown, this embodiment of the invention, based on the aforementioned improved folded cascode error amplifier, further achieves a high slew rate, low power consumption, and turn-off capacitorless LDO regulator structure through the coordinated design of local common-mode feedback, transient response compensation, and enable control circuit. The overall circuit mainly includes: an improved high slew rate error amplifier, a local common-mode feedback enhancement structure, a transient response compensation circuit, and an enable control circuit.

[0103] The input stage of the improved high slew rate error amplifier consists of split input transistors Ma1, Mb1, Ma2, and Mb2, while the folded current mirror consists of Ma3, Mb3, Ma4, and Mb4, maintaining the DC bias and gain characteristics of the traditional folded structure. Based on this, as... Figure 4 As shown, matching resistors RCM1 and RCM2 are introduced between the relevant nodes of the input pair to form a local common-mode feedback path, which is used to enhance the driving capability under large signal conditions.

[0104] like Figure 5 As shown, the transient response compensation circuit achieves rapid charging and discharging regulation of the power transistor gate drive node by setting capacitors C1 and C2 between the LDO output terminal and the source of the internal key transistor, and cooperating with the bias branch formed by the cascaded current mirror and resistor network.

[0105] like Figure 6As shown, the enable control circuit consists of a three-stage inverter chain, a bias circuit switch, and power transistor gates and output node forced pull-up and pull-down transistors, realizing unified management of logic control and analog shutdown of the entire LDO circuit.

[0106] Under steady-state operating conditions, the voltages across RCM1 and RCM2 are equal, and no DC current flows through the resistor, thus no additional static power consumption is introduced. At this time, the common-mode voltage at the drains of Mb3 and Ma4 is fed back to the common node through the resistor, and the error amplifier maintains the same DC operating point and small-signal gain characteristics as the traditional FC structure.

[0107] When the input stage generates a differential signal, a voltage difference ΔV_G is formed between the two gates. This voltage difference introduces local common-mode feedback through RCM1 and RCM2, resulting in a large drive current I_OUT in the output stage. This output current is proportional to the dynamic current Ib3 of the input stage and is related to the resistance values ​​of RCM1 and RCM2, but does not depend on the magnitude of the static bias current. By properly setting the resistance values ​​of RCM1 and RCM2, the output drive capability can be multiplied without increasing the static power consumption, enabling the error amplifier to exhibit Class AB operating characteristics under large-signal conditions, thereby significantly improving the slew rate.

[0108] During transient response, if the load current suddenly increases, the output voltage VOUT drops rapidly. Before the feedback loop establishes regulation, the change in VOUT is directly coupled to the source of Mb3 through capacitor C2, causing the potential at node K to drop rapidly. This leads to a rapid increase in the gate-source voltage of Mb3, generating a large drain current. Simultaneously, the drop in VOUT acts on the source of M11 through capacitor C1, reducing the absolute value of its gate-source voltage and decreasing the current injected into the gate node. The combined effect of these two effects rapidly extracts charge from the gate node, causing a rapid decrease in the gate voltage of the power transistor Mpass. This increases the current supplied to the load and suppresses the output voltage drop.

[0109] When the load current suddenly decreases, VOUT rises rapidly. C1 increases the source voltage of M11, increasing |VGS_M11| and injecting a larger current into the Gate node. Simultaneously, C2 increases the source voltage of Mb3, decreasing VGS_Mb3 and its drain current. Under these combined effects, the Gate node is rapidly charged, and the power transistor Mpass is quickly turned off, reducing the current output to the load and thus suppressing output voltage surges. This achieves a fast and stable transient response without external capacitors.

[0110] In terms of enable control, when SEL is high, the three-stage inverter chain quickly transmits the enable signal to each control node, the bias circuit and error amplifier are turned on, and the LDO enters normal operation. When SEL is low, the bias current path is completely cut off, the power transistor gate and output node are forced to a certain potential, avoiding node floating and achieving almost zero static current consumption, thereby completing a safe and reliable power-off.

[0111] like Figure 7 As shown, an embodiment of the present invention provides a low-power, capacitor-free LDO control method with enable control function, comprising:

[0112] Step 1: Connect the non-inverting input of the high slew rate error amplifier to the reference voltage VREF, and connect the inverting input to the output feedback voltage VFB of the LDO.

[0113] Step 2: Couple the transient compensation circuit with the improved high slew rate error amplifier through the transient response compensation circuit;

[0114] Step 3: By combining the enable control circuit with logic control and analog circuit shutdown, safe power management is achieved, enabling high-level activation and low-level shutdown.

[0115] Example 1: Basic LDO Closed-Loop and Enable / Shutdown Synergy

[0116] This embodiment constructs a low-dropout linear regulator without external capacitors, including an error amplifier, a power transistor, an output voltage divider feedback network, a transient response compensation circuit, and an enable control circuit. The non-inverting input of the error amplifier receives a reference voltage, and the inverting input receives a feedback voltage sampled by the output voltage divider feedback network. The output of the error amplifier is connected to the gate of the power transistor to form a gate control node. The first terminal of the power transistor is connected to the input power supply, and the second terminal is connected to the regulated output. The enable control circuit consists of a three-stage inverter chain and a bias switch group. Each stage of the three-stage inverter chain has a stronger driving capability than the previous stage, used for rapid charging and discharging of the gate capacitor of the subsequent control node, reducing the enable switching delay. The bias switch group is connected in series in the bias current path between the error amplifier and the transient compensation circuit. The enable signal controls the switching transistor to turn on or off through the inverter chain. Additionally, pull-up or pull-down transistors are provided for the power transistor gate, as well as bleeder transistors for relevant nodes, to achieve a determined potential clamping.

[0117] When the enable signal is high, the enable control circuit connects the bias current path, the error amplifier compares the reference voltage with the feedback voltage and adjusts the gate control node potential to drive the power transistor's conduction level, causing the output voltage to converge to the voltage divider network's set value. When the enable signal is low, the enable control circuit cuts off the bias current path and pulls the gate control node to a predetermined potential that turns off the power transistor, eliminating the static current of the analog module inside the regulator, thereby achieving low-power shutdown and reliable state switching.

[0118] Example 2: Fast Transient Response Compensation Circuit

[0119] This embodiment adds a transient response compensation circuit based on Embodiment 1. The compensation circuit includes a first capacitor, a second capacitor, and corresponding bias and active amplification branches. One end of the first capacitor is connected to the regulated output terminal, and the other end is connected to the first source node; one end of the second capacitor is connected to the regulated output terminal, and the other end is connected to the second source node. The first and second source nodes are set to a defined DC potential in steady state through the bias establishment branch, and are electrically connected to the gate control node through the active branches respectively, so that the two coupled paths can provide transient currents in opposite directions to the gate control node.

[0120] In steady state, the bias current provided by the bias establishment branch creates a voltage drop on the relevant resistor network, keeping the first and second source nodes at a preset operating potential. The first and second capacitors only carry AC coupling and do not introduce additional DC power consumption. When a load change causes a sudden change in the output voltage, the rapid change in output voltage is coupled to the corresponding source node through the first and second capacitors, causing the corresponding active branch to instantaneously increase the injection or extraction current, thereby rapidly charging and discharging the gate control node, shortening the closed-loop regulation setup time and improving transient response capability.

[0121] Example 3: Cross-coupled split input stage and folded current mirror

[0122] This embodiment provides a high slew rate error amplifier, whose input stage includes two sets of input transistors: a first input transistor group and a second input transistor group; the folded current mirror stage includes a first folded current mirror group and a second folded current mirror group. The first and second input transistor groups are configured to carry a fixed and equal DC current; the folded current mirror stage is composed of split folded transistors and maintains a bias path consistent with the conventional folded structure, allowing the DC gain and operating point to be set in a conventional manner. The first folded current mirror group and the second input transistor group, as well as the second folded current mirror group and the first input transistor group, are cross-coupled to form a small-signal current in-phase superposition path.

[0123] When the error amplifier is operating, the differential signal at the input terminal is converted into a differential current change by two sets of input transistors. This current change is superimposed in phase through a cross-coupled folded current mirror path and sent to the output driver stage, enabling the output driver stage to obtain a larger effective drive current. Since the two sets of input transistors carry a fixed and equal DC current, the steady-state bias of the circuit does not drift with signal fluctuations. At the same time, the in-phase superposition of small-signal currents at the folded nodes enhances the equivalent transconductance and driving capability, thus providing a structural basis for improving the slew rate.

[0124] Example 4: Matching resistors to achieve local common-mode feedback

[0125] This embodiment, based on the high slew rate error amplifier of Embodiment 5, sets a first matching resistor and a second matching resistor between the relevant nodes of the input stage. These resistors are connected between the drain node and gate node corresponding to the first folded current mirror group, and between the drain node and gate node corresponding to the second folded current mirror group, respectively, forming a local common-mode feedback resistor pair. The resistance values ​​of the two resistors are matched to maintain symmetry, ensuring that the potentials at both ends are consistent at the DC operating point, thereby avoiding the generation of a DC current path and preventing an increase in static power consumption.

[0126] Under large-signal input conditions, the dynamic current of the input stage generates a voltage drop across the corresponding matching resistor. This voltage drop is fed back to the gate node and changes the gate-source voltage of the output branch, thereby generating an enhanced drive current related to the dynamic current. Since this enhanced drive current is determined by both the dynamic current and the resistor value, rather than by the upper limit of the static bias current, it can significantly increase the transient output current without increasing the static bias current, thus exhibiting Class AB drive characteristics and improving the slew rate.

[0127] Example 5: Reversing voltage follower bias branch releases tail current clamping

[0128] This embodiment, based on Embodiment 3, provides the bias of the input differential pair transistors using a flip-flop voltage follower bias branch. This bias branch provides a low-output-impedance equivalent voltage source to the input stage source node, enabling the input stage source potential to respond quickly to input signal changes under transient conditions and preventing the input stage source current from being strictly clamped by a fixed tail current source. The large transient current of the input stage is mirrored to the output driver stage through a folded current mirror stage, thereby forming a greater transient output current capability.

[0129] When rapid changes occur at the input, the switching voltage-following bias branch can quickly provide or absorb transient current, causing the input stage source current to briefly exceed the steady-state bias current limit. This current is then amplified by the current mirror stage and transmitted to the output driver stage, increasing the charging and discharging speed of the output stage for subsequent stages or the gate control node. This mechanism changes the determining factor of slew rate from the "static bias current limit" to the "dynamic current capability that can be provided transiently," thereby achieving a high slew rate without significantly increasing static power consumption.

[0130] Evidence related to the technical effects obtained by the embodiments of the present invention.

[0131] Post-simulation (a crucial step after circuit layout design, extracting parasitic resistance, capacitance, and inductance effects of all interconnects and performing simulations, yielding results closer to the actual chip fabrication performance than pre-simulation (schematic simulation)) is employed in this invention. Through a frequency compensation network and high slew rate error amplifier design, this invention effectively constrains the transient fluctuations of the output voltage (overshoot 123mV, undershoot 293mV) in post-simulation, even under extreme conditions without any external compensation capacitors, and facing a load current change rate approaching 100mA / μs. Figure 8 (As shown). This demonstrates the robustness of the circuit from a design verification perspective, significantly reducing the reliance on large off-chip capacitors, making it particularly suitable for advanced process systems-on-chips (SoCs) with stringent requirements for power quality and integration.

[0132] In traditional LDO shutdown architectures, leakage current, especially at high temperatures and fast process angles (FF), accumulates significantly through multiple parallel paths, often reaching tens or even hundreds of microamperes. This severely limits its application in battery-powered devices. For example... Figure 9 As shown, the distributed enable switch architecture introduced in this invention successfully suppresses the total off-state leakage current to an extremely low level of 8.129 μA under extreme post-simulation conditions of worst-case process corner (FF) and high temperature of 125°C. This data conclusively proves that this architecture does not simply perform single-point turn-off at the power input, but rather achieves effective point-to-point isolation of the internal leakage paths of key modules such as error amplifiers, voltage references, and power transistors through precisely laid-out distributed switch units, thereby achieving an order-of-magnitude reduction in leakage current.

[0133] Post-simulation results show that the static current of this circuit at various process corners under a load condition from 0 to 50mA is as follows: Figure 10 As shown, the maximum current is no more than 30 μA.

[0134] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A low-power, capacitor-free, low-dropout linear regulator with enable control function, characterized in that, include: Error amplifier, power transistor, output voltage divider feedback network, transient response compensation circuit, and enable control circuit; The error amplifier has a non-inverting input and an inverting input. The non-inverting input receives a reference voltage, and the inverting input receives a feedback voltage sampled from the output by the output voltage divider feedback network. The output terminal of the error amplifier is connected to the gate of the power transistor to form a gate control node. The first terminal of the power transistor is connected to the input power supply terminal, and the second terminal of the power transistor is connected to the regulated output terminal. The transient response compensation circuit is connected to both the regulated output terminal and the gate control node, and is used to couple the voltage change of the regulated output terminal into a fast charging current or discharging current for the gate control node. The enable control circuit receives an enable signal, and when the enable signal is high, it turns on the bias current path of the error amplifier and turns off the bias current path when the enable signal is low, and applies a certain potential to the gate control node to turn off the power transistor.

2. The low-dropout linear regulator as described in claim 1, characterized in that, The transient response compensation circuit includes a first capacitor and a second capacitor. One end of the first capacitor is connected to the regulated output terminal, and the other end is connected to the first source node; One end of the second capacitor is connected to the regulated output terminal, and the other end is connected to the second source node; The first source node and the second source node are respectively established with a bias current branch to establish a DC working potential in steady state, and the first source node and the second source node are respectively electrically connected to the gate control node through an active branch, so as to form a net injection current or a net extraction current to the gate control node when the regulated output terminal rises or falls.

3. The low-dropout linear regulator as described in claim 1, characterized in that, The enable control circuit includes a three-stage inverter chain and a bias switch group. The interstage driving capability of the three-stage inverter chain increases progressively along the signal transmission direction to enable rapid charging and discharging of the gate capacitor of the subsequent control node. The bias switch group is connected in series in the bias current path of the error amplifier and the transient response compensation circuit to eliminate the static current of the internal analog module from the current source terminal in the off state.

4. A high slew rate error amplifier, characterized in that, This includes the input stage, the folded current mirror stage, and the output drive stage. The input stage includes a first input transistor group and a second input transistor group. The first input transistor group is composed of a first input transistor and a third input transistor, and the second input transistor group is composed of a second input transistor and a fourth input transistor. The first input transistor group and the second input transistor group each carry a fixed and equal DC current. The folded current mirror stage includes a first folded current mirror group and a second folded current mirror group. The first folded current mirror group is composed of a first folded transistor and a third folded transistor, and the second folded current mirror group is composed of a second folded transistor and a fourth folded transistor. The first folded current mirror group and the second input transistor group, as well as the second folded current mirror group and the first input transistor group, are respectively cross-coupled to ensure that the small signal current generated by the input stage remains in phase and superimposed at the folded node, and provides enhanced drive current to the output drive stage.

5. The high slew rate error amplifier as described in claim 4, characterized in that, It also includes local common-mode feedback resistor pairs, The local common-mode feedback resistor pair includes a first matching resistor and a second matching resistor. The first matching resistor is connected between the drain node and the gate node corresponding to the first folded current mirror group, and the second matching resistor is connected between the drain node and the gate node corresponding to the second folded current mirror group. At the DC operating point, the first matching resistor and the second matching resistor are at the same potential and no DC current flows through them, so that the static power consumption does not increase. Under a large signal input, the first matching resistor and the second matching resistor form a local common-mode feedback loop, which increases the output drive current as the product of the input stage dynamic current and the resistance value of the matching resistor, thereby improving the slew rate.

6. The high slew rate error amplifier as described in claim 4, characterized in that, It also includes a switching voltage follower bias branch. The flip voltage follower bias branch provides a low output impedance equivalent voltage source to the source node of the input stage, so that the source current of the input stage is not clamped by the fixed tail current source, and the transient large current generated by the input stage is mirrored to the output drive stage through the folded current mirror stage to obtain a larger transient output current, thereby improving the slew rate.

7. A transient response compensation circuit for a low-dropout linear regulator without external capacitors, characterized in that, This includes the first coupling branch, the second coupling branch, and the bias establishment branch. The first coupling branch includes a first capacitor and a first active device. One end of the first capacitor is connected to the regulated output terminal, and the other end is connected to the first source node. The first active device is electrically connected to the gate control node and is controlled by the potential change of the first source node to provide injection current to the gate control node. The second coupling branch includes a second capacitor and a second active device. One end of the second capacitor is connected to the regulated output terminal, and the other end is connected to the second source node. The second active device is electrically connected to the gate control node and is controlled by the potential change of the second source node to draw current from the gate control node. The bias establishment branch connects the input power supply terminal and the ground terminal, providing a steady-state bias current to the first source node and the second source node, so as to establish the potential of the first source node and the potential of the second source node respectively under steady state.

8. The transient response compensation circuit as described in claim 7, characterized in that, When the load current increases, causing the voltage at the regulated output terminal to drop, the voltage drop at the regulated output terminal causes the potential of the second source node to drop rapidly through the second capacitor, thereby increasing the gate-source voltage of the second active device and increasing its drawdown current. At the same time, the voltage drop at the regulated output terminal causes the potential of the first source node to change through the first capacitor, thereby reducing the injection current of the first coupling branch to the gate control node. This results in a net drawdown current at the gate control node and a reduction in the gate voltage of the power transistor, thus enhancing the ability to supply power to the load.

9. The transient response compensation circuit as described in claim 7, characterized in that, When the load current decreases, causing the voltage at the regulated output terminal to rise, the voltage rise at the regulated output terminal causes the potential of the first source node to rise rapidly through the first capacitor, thereby increasing the injection current of the first active device to the gate control node. At the same time, the voltage rise at the regulated output terminal causes the potential of the second source node to rise through the second capacitor, thereby reducing the draw current of the second active device. This results in a net injection current at the gate control node and raises the gate voltage of the power transistor to reduce the current supplied to the load.

10. The transient response compensation circuit as described in claim 7, characterized in that, The bias establishment branch includes a cascaded current mirror and a resistor network. The cascaded current mirror and the resistor network together generate a bias current and form a corresponding voltage drop on the first source node and the second source node, so that the first coupling branch and the second coupling branch are in a preset conduction state under steady state, and convert the voltage change of the regulated output terminal into a fast charging and discharging current for the gate control node in transient state.

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