Chip clock control method and device, chip, electronic equipment and storage medium

Abstract

The application provides a chip clock control method and device, a chip, an electronic device and a storage medium, and relates to the technical field of chips. The method comprises the following steps: acquiring a clock output state of a phase-locked element; if the clock output state represents that the phase-locked element is not locked, providing a clock signal for a load module of the chip according to an input clock signal of the phase-locked element. According to the application, the clock output state of the phase-locked element represents that the phase-locked element is not locked, the supply of the clock signal for the load module is determined according to the input clock signal of the phase-locked element, so that the load module can generate a load at the power-on moment of the chip, and the voltage division obtained by the chip in the series power supply structure is optimized.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip clock control method and apparatus, chip, electronic device and storage medium. Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes, the operating power supply voltage of integrated circuit chips is gradually decreasing, while the operating current is correspondingly increasing. To further improve power conversion efficiency, existing technologies are beginning to adopt a chip-series power supply method on printed circuit boards (PCBs). This method optimizes the power supply architecture by connecting multiple chips in series, forming a multi-stage series voltage domain between the power input and ground terminals. Compared to traditional parallel power supply methods, the series power supply structure can effectively reduce the overall supply current, improve power conversion efficiency, and reduce the cost of power conversion circuit components. Therefore, this chip-series power supply method is increasingly widely used in high-performance, low-power systems.

[0003] In computing chip applications, the primary load is typically the algorithm core module, which requires a high-frequency clock to achieve high computing power. When computing chips employ a series power supply structure, voltage division is necessary between the chips based on the input power. Generally, chips with heavier loads have higher voltage division values, while those with lighter loads have lower voltage division values. However, uneven voltage division in the system can cause chips with higher voltage divisions to function normally, while chips with insufficient voltage divisions may experience communication or computing power anomalies. In severe cases, some chips may even fail to receive sufficient voltage and malfunction. These problems are particularly prominent in computing chip systems with series power supply architectures, necessitating the development of improvement solutions. Summary of the Invention

[0004] This application provides a chip clock control method and apparatus, a chip, an electronic device, and a storage medium to solve one or more of the above-mentioned technical problems.

[0005] In a first aspect, embodiments of this application provide a chip clock control method, the method comprising: acquiring the clock output state of a phase-locked element; if the clock output state indicates that the phase-locked element is not locked, then providing a clock signal to the load module of the chip according to the input clock signal of the phase-locked element.

[0006] Secondly, embodiments of this application provide a chip clock control device, the device comprising: an acquisition module for acquiring the clock output state of a phase-locked element; and a first control module for providing a clock signal to the load module of the chip based on the input clock signal of the phase-locked element if the clock output state indicates that the phase-locked element is not locked.

[0007] Thirdly, embodiments of this application provide a chip including the aforementioned chip clock control device.

[0008] Fourthly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor, when executing the computer program, implements the method described in any of the above-mentioned embodiments.

[0009] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in any of the preceding claims.

[0010] Sixthly, embodiments of this application provide a computer program product, wherein the computer program product includes a computer program that, when executed by a processor, implements the method described in any of the above-mentioned embodiments.

[0011] Compared with related technologies, this application has the following advantages:

[0012] This application provides a chip clock control method and apparatus, a chip, an electronic device, and a storage medium. The method includes: acquiring the clock output state of a phase-locked element (PLI); if the clock output state indicates that the PLI is not locked, then providing a clock signal to the load module of the chip based on the input clock signal of the PLI. According to the embodiments of this application, based on the clock output state of the PLI indicating that the PLI is not locked, the supply of a clock signal to the load module is determined according to the input clock signal of the PLI, thereby enabling the load module to generate a load at the moment the chip is powered on, thereby optimizing the voltage division obtained by the chip in the series power supply structure.

[0013] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0014] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this application and should not be construed as limiting the scope of this application.

[0015] Figure 1 A flowchart of a chip clock control method provided in an embodiment of this application is shown;

[0016] Figure 2A schematic diagram of a phase-locked loop structure provided in an embodiment of this application is shown;

[0017] Figure 3 A schematic diagram of a clock processing structure provided in an embodiment of this application is shown;

[0018] Figure 4 A timing diagram provided in an embodiment of this application is shown;

[0019] Figure 5 This illustration shows another clock processing structure provided in an embodiment of this application;

[0020] Figure 6 Another timing diagram provided in an embodiment of this application is shown;

[0021] Figure 7 Another timing diagram provided in an embodiment of this application is shown;

[0022] Figure 8 This paper shows a block diagram of a chip clock control device provided in an embodiment of this application;

[0023] Figure 9 A block diagram of an electronic device used to implement embodiments of this application is shown;

[0024] Figure 10 This illustration shows a schematic diagram of clock signal control for a load module provided in an embodiment of this application. Detailed Implementation

[0025] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the concept or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0026] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and all of them fall within the protection scope of the embodiments of this application.

[0027] First, let's explain the terms involved.

[0028] Voltage division: In a series circuit, the current through each resistor is equal, and the sum of the voltages across each resistor equals the total voltage of the circuit. Therefore, the voltage across each individual resistor is less than the total voltage of the circuit, hence the voltage division occurs when resistors are connected in series.

[0029] Load: The power generated, converted, and consumed by power equipment (such as a chip) during operation. It refers to an electronic component connected in a circuit with a certain potential difference between its two ends, used to convert electrical energy into other forms of energy.

[0030] PLL (Phase Locked Loop): A feedback control circuit that generates clock signals, including a phase detector, loop filter, voltage-controlled oscillator, latch, frequency divider, etc.

[0031] Crystal oscillator: A crystal that can convert electrical energy and mechanical energy into each other. When it operates in a resonant state, it can provide stable and accurate single-frequency oscillation to generate clock signals.

[0032] With the continuous advancement of semiconductor manufacturing processes, the operating power supply voltage of integrated circuit chips is gradually decreasing, while the operating current is correspondingly increasing. To maximize power conversion efficiency, existing technologies in printed circuit board (PCB) systems have begun to adopt a series-connected power supply method, where multiple chips are connected in series to form a multi-stage series voltage domain between the power input and ground terminals. This power supply architecture can effectively reduce the overall supply current, improve power conversion efficiency, and reduce the cost of power conversion modules and related components. However, existing integrated circuit chips still have several problems when using a series power supply architecture. For example, known series power supply circuits typically convert the external power supply voltage VCC to an output voltage VDD via a DC-DC power module to supply the series-connected IC chips, or use a main power supply combined with an auxiliary power supply unit. In actual operation, because the internal impedance (internal resistance) of each chip is not completely consistent, and different load conditions lead to differences in the chip's operating current, the operating voltage supplied to each chip is therefore inconsistent.

[0033] To ensure all chips in a series circuit function correctly, the output voltage VDD is typically increased so that even the chip with the lowest voltage division can meet its normal operating voltage. As the number of chips in series increases, the voltage consistency across each chip further decreases, placing higher demands on power supply balancing. While increasing the output voltage ensures all chips operate normally, it significantly increases the overall power consumption of the power supply circuit, thus reducing power conversion efficiency. Without increasing the supply voltage, the system may become unstable: some chips may function normally, while others malfunction due to insufficient voltage, preventing the system from achieving optimal performance.

[0034] In a series voltage divider power supply architecture, each chip must receive a corresponding divided voltage to function properly. If, during system power-up, different chips have different internal impedances or load conditions, their operating currents will also differ, leading to an uneven voltage distribution in the series link. Typically, at the initial moment of power-up, the chip only has a low-frequency clock provided by a crystal oscillator, and most functional modules are not yet operational. For computing chips, their core computing modules require high-frequency clocks to achieve the intended computing performance. These high-frequency clocks are usually generated by phase-locked loops (PLLs) or delay-locked loops (DLLs). Because PLLs or DLLs require a certain amount of time to lock their output after startup, load modules relying on their clocks cannot obtain a clock signal that meets performance requirements before locking is complete. If the system's load modules only select the clock provided by the PLL or DLL as their operating clock, an overall load imbalance will occur at the initial power-up stage. The high-frequency loads of some chips fail to start in time, resulting in different current demands from each chip in the entire series power supply chain, thus causing uneven series voltage division. Uneven voltage distribution can not only affect the normal operation of some chips, but also lead to a decrease in the stability of the entire system during the power-on phase.

[0035] See Figure 2 The diagram shows a phase-locked loop (PLL) structure. First, the names and functions of the ports are explained: PLL_CLK_IN: PLL input reference clock; CLKIN_DIV: Input clock frequency division configuration; Feedback_DIV: Feedback frequency division configuration; VCO: Voltage-controlled oscillator; DIV: Frequency divider; PLL_VLD: PLL output valid indication (locked signal); PLL_CLK_OUT: PLL output clock; DIV1~N: Frequency dividers 1~N; It should be noted that DIV1~N are used for pre-division. Figure 2 The DIV in the code is used to further divide the high-frequency clock output of the VCO phase-locked loop. Figure 2 This describes the structure of a PLL, where PLL_VLD is the lock signal generated by the Lock Detect module, indicating that the clock generated by the VCO is stable, and the clock output by the PLL is also stable. Some PLL IPs have a Lock Detect module, while others do not, but they will always provide a lock time. The external control logic then generates the corresponding lock signal after a counter reaches the Lock_timer (lock timer) time. The main load of a computing chip is usually the algorithm core module, which requires a high-frequency clock to generate the corresponding high computing power. High-frequency clocks are typically generated by PLLs, such as... Figure 2As shown, if the PLL does not lock the clock, the algorithm core module will neither work nor provide normal load to the chip. In this case, the chip is essentially in a state of load absence. Naturally, the current drawn by the chip will decrease.

[0036] In systems using phase-locked loops (PLLs) or delay-locked loops (DLLs) as high-frequency clock sources, these modules require a certain locking time after startup before outputting a stable clock signal. Before this locking is complete, the computing modules relying on the high-frequency clock cannot function properly and cannot form an effective load. For chip systems using series voltage divider power supply, this leads to differences in the internal impedance and load conditions of different chips, resulting in uneven voltage distribution across them. Even if the internal impedances of multiple chips in the series link are relatively consistent during the initial power-on phase, and the initial voltage division is relatively uniform, load changes may still occur during operation due to differences in the PLL locking completion time. Because the locking order of the PLLs or DLLs differs among different chips, the startup time of their core computing modules also differs, causing changes in load distribution and resulting in continuous changes in the voltage division in the series link, leading to uneven voltage distribution. In a series voltage divider power supply architecture, uneven voltage distribution causes significant system performance problems: chips with higher voltage divisions will suffer greater power loss, while chips with lower voltage divisions may not function properly due to insufficient power supply. This situation not only affects the performance of individual chips but also reduces the stability and reliability of the entire system.

[0037] In practical series voltage divider power supply systems, the internal impedance of each chip is not completely consistent, and the load conditions of different chips also differ, resulting in different operating currents. This inconsistency leads to differences in the operating voltage obtained by each chip. As the number of chips connected in series increases, this voltage difference accumulates further, significantly reducing the uniformity of the voltage applied across each chip. To ensure that all series-connected chips receive the required supply voltage (VDD) for normal operation, the system needs to increase the overall output voltage. However, increasing the output voltage directly leads to an increase in the overall power consumption of the power supply circuit, thereby reducing power conversion efficiency. If the supply voltage is not increased, some chips may fail to operate stably due to insufficient voltage, causing the system to be in an unstable state. In this situation, from a performance perspective, some chips may operate normally while others malfunction, preventing the system from achieving its optimal performance specifications.

[0038] Based on this, this application provides a chip clock control method and apparatus, a chip, an electronic device, and a storage medium. The method proposes a novel and optimized series voltage divider power supply scheme to reduce the impact of uneven voltage division on the operating performance of series-connected integrated circuit chips. During the chip power-up phase, to ensure that the main load modules can immediately enter the working state, the system uses a clock signal provided by a crystal oscillator, instead of using the high-frequency clock generated by a phase-locked loop (PLL). After the PLL completes locking and can provide a stable high-frequency clock output, the system automatically switches to driving the main load modules with the PLL clock. Through this clock switching method, the main load modules can obtain a usable clock and start working in the initial stage of chip power-up, thus balancing the load levels of each chip and forming a uniform voltage distribution in series voltage divider systems such as hashboards. Afterwards, once the PLL stably outputs a high-frequency clock and completes the switching configuration, the chip can operate normally in high-performance mode while maintaining the stability of the power supply voltage division. This solution improves the power supply structure and timing control, enabling each chip in the series link to obtain a stable operating voltage that matches its needs at different operating stages. This effectively reduces the overall power supply current of the circuit, improves power conversion efficiency, and significantly enhances the operational stability and reliability of the entire system.

[0039] This application's embodiments address the issue of uneven voltage distribution during power-up of series-connected chips. By implementing a clock switching circuit, it ensures that the main load module receives a usable clock signal during power-up, preventing uneven load due to lack of clock drive. Simultaneously, a low-load uniform voltage distribution strategy is employed to maintain consistent load across all series-connected chips during the initial power-up phase, resulting in a balanced voltage distribution and improved system power supply stability.

[0040] The technical solution of this application and how it solves the aforementioned technical problems are described in detail below with specific embodiments. The listed specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0041] This application provides a chip clock control method, wherein the chip includes a phase-locked loop (PLL) element and a load module. The execution entity of this method can be a clock control circuit, which can be located within the chip or externally, depending on actual needs. Figure 1 The diagram shown is a flowchart of a chip clock control method according to an embodiment of this application. The method may include:

[0042] Step S101: Obtain the clock output state of the phase-locked element.

[0043] In this embodiment, the chip includes a phase-locked loop (PLL) element and a load module. The PLL element is a circuit module used to output a stable clock signal that maintains a specific phase relationship with a reference clock. The PLL element requires a certain locking time during startup; only after locking is complete can the output clock be stably used.

[0044] A load module refers to a functional unit within a chip that consumes processing resources. In computing chips, this may include, but is not limited to, the core computing module and data pathways. These modules require a high-speed, stable clock to function properly. The clock output status refers to the stability of the current output signal of the phase-locked loop (PLL), which can be categorized as locked or unlocked. The current clock output status information is obtained by reading the lock indication signal of the PLL (e.g., the LOCK pin of the PLL or its internal status register).

[0045] Step S102: If the clock output state indicates that the phase-locked element is not locked, then a clock signal is provided to the load module of the chip according to the input clock signal of the phase-locked element.

[0046] In this embodiment, the clock signal corresponding to the phase-locked element (PLL) may include the input clock signal and the output clock signal of the PLL. Based on the clock output state of the PLL, a clock signal for supplying the load module is selected from the clock signals corresponding to the PLL. In the unlocked state, the PLL / DLL has not yet completed frequency and phase adjustment, and the output clock may drift or jitter; it is not recommended to directly supply it to sensitive load modules. If the clock output state indicates that the PLL is unlocked, then a clock signal is provided to the load module of the chip according to the input clock signal of the PLL. The input clock signal of the PLL refers to the reference clock source received by the PLL, such as a low-frequency stable clock signal generated by the internal crystal oscillator of the chip or an external clock generator, which is usually used as the reference input of the PLL / DLL. In the unlocked stage of the PLL, the load module can obtain a stable clock signal to start in time, making the load between the series-connected power supply chips more consistent, reducing voltage unevenness, thereby avoiding some chip abnormalities caused by power supply differences and improving the system's operational stability.

[0047] In this embodiment, when the phase-locked loop (PLL) element is detected to be unlocked, the clock switching control logic directly allocates the input clock signal of the PLL element to the load module, ensuring that the load module can obtain a stable low-frequency clock to start working during the initial stage of chip power-on. At this time, the input clock is typically provided by a crystal oscillator, which has a low frequency but is sufficiently stable. By dynamically using the input clock signal corresponding to the PLL element as the operating clock of the load module based on the clock output state of the PLL element when the chip is configured in the first control state (representing the unlocked state of the PLL element), optimized clock source switching during chip power-on and operation is achieved.

[0048] This application provides a chip clock control method, the method comprising: in response to the chip being configured to a first control state, acquiring the clock output state of the phase-locked element; if the clock output state indicates that the phase-locked element is not locked, then providing a clock signal to the load module of the chip according to the input clock signal of the phase-locked element. According to an embodiment of this application, in response to the chip being in a preset first control state, based on the clock output state of the phase-locked element indicating that the phase-locked element is not locked, the supply of a clock signal to the load module is determined according to the input clock signal of the phase-locked element, thereby enabling the load module to generate a load at the moment the chip is powered on, thereby optimizing the voltage division obtained by the chip in a series power supply structure.

[0049] In one possible implementation, the clock output state of the phase-locked element can be obtained by the following steps: cyclically obtaining the clock output state of the phase-locked element at fixed or non-fixed time intervals.

[0050] In this possible implementation, fixed time interval detection is used, for example, periodically detecting the clock output state of the phase-locked loop element at predetermined equal time intervals (e.g., every 10 ms or every 1000 system clock cycles). Non-fixed time interval detection is used, for example, performing detection according to dynamically changing detection intervals, such as increasing the detection frequency in the early stages of chip power-up to shorten the lock confirmation time, and decreasing the detection frequency after locking to reduce resource consumption.

[0051] In this step, the clock output status of the phase-locked loop (PLL) element is obtained cyclically at fixed or non-fixed time intervals. High-frequency detection can be used during the initial power-on phase to accelerate the determination of the PLL status. After stable operation, the detection frequency can be reduced to save chip power consumption and processing resources. Real-time monitoring of the PLL output status allows the clock switching logic to switch to a high-frequency stable clock immediately, improving the overall system efficiency. In the series power supply architecture, load consistency is ensured for all chips before PLL locking, reducing power supply fluctuations and stability issues caused by uneven voltage distribution.

[0052] In one possible implementation, the method may further perform the following steps: if the clock output state indicates that the phase-locked element is locked, then provide a clock signal to the load module according to the output clock signal of the phase-locked element.

[0053] In this possible implementation, in the locked state, the phase-locked element's output frequency is consistent with the reference clock, and its phase remains stable, ensuring a reliable clock supply to the load module. Once the phase-locked element's lock indicator signal indicates that it has entered the locked state, the control logic switches the load module's clock source to the phase-locked element's output clock signal. This clock signal features high frequency and low jitter, meeting the high-performance requirements of the load module. After the switch is complete, the load module continuously uses the high-frequency, stable clock signal output by the phase-locked element until the operating mode or phase-locked state changes.

[0054] In this step, after the phase-locked loop (PLL) element outputs a stable high-frequency clock, the clock source of the load module is switched to this high-frequency clock to ensure that the chip design performance is fully utilized under power supply safety conditions, while maintaining load balance, reducing overall power consumption and improving power conversion efficiency.

[0055] In one possible implementation, providing a clock signal to the load module based on the output clock signal of the phase-locked element can be performed by the following steps: controlling the output clock signal through a clock gating circuit, releasing the clock gating circuit when the output clock signal reaches a specified state, and using the output clock signal in the specified state to provide a clock signal to the load module.

[0056] In this possible implementation, the clock gating circuit is a logic circuit that controls whether the clock signal is transmitted to the target module. It can block or enable the clock signal without changing the source clock through an "enable / disable" control terminal. Specific implementations include AND gates, clock buffer enable terminals (BUFGCE), and dedicated gating units. The specified state refers to the state where the output clock signal meets usable conditions, such as: the phase-locked loop (PLL) element is fully locked, the output frequency and phase meet the target accuracy requirements, and the phase jitter is below a preset threshold. This state can be determined by the PLL element's lock signal (LOCK) or an internal monitoring module.

[0057] In this step, when the phase-locked element (PLL) starts working but its output clock signal has not yet reached the specified state, the clock gating circuit blocks the transmission of the output clock signal to the load module, preventing the load module from receiving an unstable clock. The system monitors the output clock state of the PLL. When the output clock meets the specified state (e.g., locking complete, stability met), the control of the clock gating circuit is released, allowing the clock signal to start transmitting. Once the clock gating is released, the load module connects to the stable output clock signal and enters normal operating mode, fully utilizing its design computing power or data processing performance.

[0058] Specifically, such as Figure 10 As shown, OSC (Oscillator): an external clock signal generator, in this embodiment a crystal oscillator, outputting a 24 MHz reference clock to the Clock Processing Module (CPM). DIV: frequency divider; PLL: phase-locked loop, receiving the reference clock and generating a high-frequency stable clock output, commonly used for frequency multiplication and low-jitter clock generation. MUX (represented by a trapezoid in the diagram, 0 and 1 represent different inputs selected for the output when SEL is 0 or 1): a clock multiplexer, used to select the clock signal from the external clock or PLL under different control states. CKG (Clock Gating): a clock gating module, used to turn the clock output on or off to prevent glitches and drive the load module during unstable phases. Before MUX selection, a clock gating module (CKG) is added to the PLL output. Figure 10 In the code, CORE_CLK and Trunk_CLK are two clock paths provided to the chip's load modules. If testing determines that one is better, the other will be shut down via gating. The MUX condition's clock_chg_en & ~Lock cannot disable the PLL output to downstream load modules when the PLL output is unstable.

[0059] In this embodiment, by blocking the output clock when the phase-locked element has not reached a specified state, instantaneous current surges or logic errors in the power supply link are prevented in the load module, ensuring system startup stability. In a series-powered chip system, this prevents some chips from prematurely entering a high-load state, maintaining load consistency during startup and significantly reducing voltage unevenness. Voltage equalization eliminates the need to increase the global VDD to compensate for low-voltage chips, reducing overall power consumption and improving power module efficiency. The load module is only connected after the output clock reaches a high stability condition, ensuring that data processing or computing power output during high-performance operation is performed under timing-safe conditions.

[0060] In one possible implementation, the input clock signal is generated by an external clock signal generator of the chip.

[0061] In this possible implementation, the external clock signal generator is a clock source circuit located outside the chip, used to generate a periodic signal that can be used as a reference clock. The external clock signal generator starts and outputs a reference clock signal, which is directly fed into the reference input terminal of the phase-locked loop (PLL) element as the input clock. After receiving the input clock signal, the PLL element stabilizes the output clock frequency at the target value and maintains a fixed relationship with the reference phase through frequency multiplication, phase detection, and feedback control. The PLL element distributes the stable output clock signal to the load module to meet its operating frequency requirements and ensure the normal operation of the module.

[0062] In this step, the external clock signal generator exhibits high output stability and minimal environmental drift, enabling the phase-locked loop (PLL) element to lock onto the circuit based on a precise reference clock, thereby improving the frequency accuracy and phase stability of the output clock. When multiple chips operate in series or parallel, sharing the reference clock from the external clock signal generator achieves system-level timing uniformity, reducing communication errors caused by clock source differences. A stable input reference clock allows the PLL element to lock faster, and the load module to enter a stable operating state earlier, helping to maintain consistent load across chips and reducing voltage unevenness issues in series power supply architectures. This reduces chip malfunctions caused by clock drift or locking delays, ensuring long-term stable operation of the system in high-performance mode.

[0063] In one possible implementation, the external clock signal generator includes one or more of the following: a crystal oscillator, an RC oscillator, a MEMS clock oscillator, a direct digital synthesizer, or a ring oscillator.

[0064] In this possible implementation, the following oscillators are used: Crystal Oscillator: Utilizes the piezoelectric resonance characteristics of a quartz crystal to generate a high-precision clock with minimal frequency drift, suitable for systems requiring high stability. RC Oscillator: Achieves oscillation using the charging and discharging of resistors and capacitors; it has a simple structure and low cost, but its frequency accuracy is lower than that of a crystal oscillator; it is suitable for low-cost, general-precision applications. MEMS Clock Oscillator: Achieves oscillation based on the vibration of a microelectromechanical system structure; it is small in size and has good vibration resistance, suitable for mobile devices. Direct Digital Synthesizer (DDS): Directly generates waveforms of a specified frequency digitally; it has high frequency resolution and fast switching speed, suitable for programmable, multi-frequency output scenarios. Ring Oscillator: Consists of several inverters connected end-to-end to form a loop oscillation; it has a simple structure and is easy to integrate, but its frequency is greatly affected by process, temperature, and voltage variations; it is mostly used for on-chip testing or non-precision clock applications.

[0065] In this step, an external clock signal generator is activated to generate a reference clock signal. This reference clock is used as the input clock signal for the phase-locked loop (PLL) element, and PLL processing is performed. After the PLL element is locked, a high-frequency stable clock signal is output to drive the load module. The type of external clock signal generator can be selected in one or more combinations according to system requirements to meet different accuracy, power consumption, size, and cost requirements.

[0066] In this possible implementation, by limiting the input clock signal source of the phase-locked element to an external clock signal generator, and allowing this generator to be selected from one or more of the following—a crystal oscillator, an RC oscillator, a MEMS clock oscillator, a direct digital synthesizer, or a ring oscillator—depending on system requirements, the following advantages are achieved: A high-quality external clock source (such as a crystal oscillator or MEMS) can reduce the phase-locking time and improve the phase accuracy and frequency stability of the output clock. Different external clock devices can be matched to different application scenarios; for example, a MEMS oscillator can be used in low-power mobile devices. An external clock source can synchronously drive multiple chips, reducing timing deviations and improving communication reliability. A stable input reference clock allows the phase-locked element to reach a stable output faster, enabling synchronous startup of load modules and reducing voltage unevenness issues in series power supply architectures. It can be widely used in integrated circuit systems requiring high-quality clock sources, such as computing chips, communication processing chips, and embedded controllers.

[0067] In one possible implementation, the phase-locked element locking includes: the output clock signal of the phase-locked element being synchronized with the frequency of a reference clock signal, and the output clock signal of the phase-locked element being synchronized with the phase of the reference clock signal.

[0068] In this possible implementation, frequency synchronization is maintained when the frequency difference between the output clock signal and the reference clock signal is within a specified small range (e.g., ±ppm level error); phase synchronization is maintained when the phase difference between the output clock signal and the reference clock signal is stable within a set phase offset range (e.g., within ± a few degrees), and this state is maintained for a certain period of time. When both of the above conditions are met simultaneously, the phase-locked element is determined to be in a locked state.

[0069] The reference clock signal and output clock signal of the phase-locked loop (PLL) are continuously sampled, and their frequency and phase data are recorded. Frequency comparison logic is used to detect the frequency difference between the two signals; when the frequency difference is lower than a preset synchronization threshold, the frequency is considered synchronized. Phase comparison logic is used to detect the phase difference between the two signals; when the phase difference remains within an acceptable range, the phase is considered synchronized. When both frequency and phase are synchronized, a lock signal is generated and transmitted to the chip's clock control logic, allowing the PLL's output clock signal to be switched to the load module for operation.

[0070] In this possible implementation, precise lock-in determination involves simultaneously detecting frequency and phase synchronization. This avoids misjudgments caused by relying on a single condition, ensuring the load module operates only under reliable clock conditions and guaranteeing system stability. A rapid sampling and comparison method allows for early determination of the lock-in state, improving system startup speed while maintaining clock quality. In a series power supply system, high-load operation only begins when all chip phase-locked loop elements meet the lock-in criteria, maintaining consistent load across chips and reducing voltage fluctuations. The load module operates under a high-frequency, stable clock condition, fully utilizing computing power and data processing capabilities while reducing the risk of logic errors caused by clock drift.

[0071] In one possible implementation, the method may further perform the following steps: adjusting the frequency of the output clock signal to a specified frequency threshold and / or adjusting the phase of the output clock signal to a specified phase threshold.

[0072] In this possible implementation, the frequency threshold is a preset permissible frequency deviation range used to determine whether the frequency adjustment of the output clock meets the standard. For example, with a reference frequency as the base, a permissible deviation of ±50 ppm is the specified frequency threshold. The phase threshold is a preset permissible phase difference range used to determine whether the phase offset between the output clock and the reference clock meets the synchronization requirements. For example, a phase difference of ±5° is set as the specified phase threshold.

[0073] The output clock signal of the phase-locked loop (PLL) is compared with the reference clock signal in terms of frequency and phase to obtain initial deviation data. If the frequency deviation exceeds a specified frequency threshold, the output clock frequency is gradually corrected to the target range by adjusting the voltage-controlled oscillator (VCO) voltage or the DLL delay chain. If the phase deviation exceeds a specified phase threshold, the loop delay or phase compensation unit is adjusted by a phase comparator until the phase of the output clock meets the preset threshold requirement with the reference clock. When both the frequency and phase are within the specified threshold range and remain stable for a certain period, the PLL is determined to be in a locked state, and a lock signal is generated to allow the load module to access the clock.

[0074] In this possible implementation, by adding frequency and / or phase adjustment steps during the phase-locked loop (PLL) process, the solution of this embodiment can achieve the following beneficial effects: By precisely adjusting the output clock frequency and phase to a preset threshold range, jitter and drift can be significantly reduced, ensuring that the load module operates normally under stringent timing requirements. The dual-parameter thresholds (frequency and phase) ensure the comprehensiveness of the lock-in state judgment, avoiding misjudgments under a single condition, thereby stabilizing system operation. The adoption of a fast feedback and gradual adjustment strategy enables frequency and phase synchronization to be completed in a shorter time, increasing the available time after chip power-on and mode switching. A stable clock is obtained more quickly, allowing multiple chip load modules to enter a consistent operating state at the same time, reducing voltage drop fluctuations and improving power supply efficiency.

[0075] In one possible implementation, the phase-locked element includes a phase-locked loop and / or a delayed-locked loop.

[0076] In this possible implementation, the phase-locked element may include, but is not limited to, a phase-locked loop (PLL) and a delay-locked loop (DLL). A PLL adjusts the oscillator frequency to match the output clock frequency with a reference clock and maintains phase lock, thereby generating a stable clock with high frequency and low jitter. A DLL, through precise delay matching, aligns the output clock phase with the reference clock and is commonly used for clock synchronization in high-speed interfaces.

[0077] In this possible implementation, a wider range of clock signal generation and synchronization capabilities are achieved by incorporating a phase-locked loop (PLL) and / or a delay-locked loop (DLL) into the phase-locked element design. The PLL provides a high-frequency, low-jitter clock, suitable for core computing modules or high-speed buses; the DLL enables precise phase alignment, suitable for high-speed interfaces and data sampling scenarios. The combination of the two can cover more application requirements. The PLL maintains frequency stability under supply voltage and temperature fluctuations; the DLL reduces jitter, maintains phase accuracy, and improves the overall system timing reliability. High-speed, stable clocks and precise phase synchronization enhance data processing speed and computing performance, enabling the chip to maintain stable operation even at peak performance. In a series power supply architecture, the phase-locked element locks faster and outputs more stably, allowing multi-chip load modules to enter a high-load state at near-synchronous moments, reducing voltage drop fluctuations and improving power conversion efficiency.

[0078] In one possible implementation, obtaining the clock output state of the phase-locked element includes: obtaining the clock output state of the phase-locked element in response to the chip being configured to a first control state; the method further includes: providing a clock signal to the load module using the output clock signal of the phase-locked element in response to the chip being configured to a second control state.

[0079] In this possible implementation, the first control state is an operating mode of the chip, used to indicate that the chip's clock source control logic is activated and to allow the output clock signal of the phase-locked element to be used to provide a clock signal to the load module. This state can be configured by the chip's internal control register or triggered by an external control signal. In response to system configuration or external instructions, the chip is set to the first control state, triggering the clock control logic, enabling the chip to manage the clock source of the load module according to the state of the phase-locked element.

[0080] This step also includes: the system control circuit or external configuration command setting the chip's operating state to a second control state. It confirms that the phase-locked element (PLI) is in a locked state, and its output clock reaches stable frequency and phase parameters. In the second control state, the clock control logic directly connects the PLI's output clock signal to the clock input of the load module. The load module operates under the drive of the high-frequency, stable clock output from the PLI, achieving the target computing power or data processing rate of the chip design.

[0081] In this possible implementation, when the chip is configured in the second control state, the output clock signal of the phase-locked element is directly used to supply time to the load module. Through the explicit definition of the second control state, the separation and correlation control of clock switching conditions and high-performance operation are realized, which facilitates system management and debugging.

[0082] The chip clock control method provided in this application will be described below with specific embodiments.

[0083] See Figure 3 The diagram shown is a schematic of a clock processing structure. Figure 3 In this diagram, OSC (Oscillator) is an external clock signal generator; in this embodiment, it is a crystal oscillator that outputs a 24 MHz reference clock to the Clock Processing Module (CPM). DIV: Frequency divider; DIV_free: Unconstrained frequency divider module, which allocates the frequency of the external reference clock to generate a suitable reference clock signal. The DIV_free module also supports bypass mode, meaning that when the PLL input is adapted to 24 MHz, the bypass frequency divider logic directly provides 24 MHz to the PLL input. PLL: Phase-Locked Loop, which receives the reference clock and generates a high-frequency stable clock output, commonly used for frequency multiplication and low-jitter clock generation. MUX (represented by a trapezoidal shape in the diagram, 0 and 1 represent different inputs selected for the output when SEL is 0 or 1): Clock multiplexer, used to select the clock signal from the external clock or the PLL under different control states. CKG (Clock Gating): A clock gating module used to turn the clock output on or off to prevent glitches and drive the load module during unstable phases. In one possible implementation, the chip clock control architecture includes an external clock source, a phase-locked loop (PLL) element, and a clock switching circuit to provide a stable clock for the load module during different operating phases, solving the problem of uneven voltage division during power-up of series-powered chips. An external clock signal generator (OSC) provides a reference input clock signal; in this example, it is a 24 MHz crystal oscillator clock. This signal is divided by a frequency divider circuit (DIV_free) to output a reference clock (RCLK) according to a set division ratio. RCLK, as the input clock signal for the PLL element, is directly fed into the PLL module for phase-locking processing. After the PLL lock is complete, a high-frequency clock (Plln_cclk_pre) is output. Plln_cclk_pre is selected by the clock switching unit, and the selected clock is used as Plln_cclk. The clock switching unit (MUX) selects the corresponding clock source based on the control state: during chip power-up or when the phase-locked loop (PLL) element is not locked, the MUX selects an external clock signal or a frequency-divided clock as the load module clock input, ensuring a stable clock drive for the main load module upon power-up; after the PLL element is locked, the MUX switches to the high-frequency stable clock output by the PLL as the load module clock input, achieving high-performance operation. The clock gating circuit (CKG) is used to avoid glitches and timing errors during switching, ensuring that the switched clock signal meets the sampling and logic requirements of the load module. Plln_cclk is determined as either CORE_CLK or Trunk_CLK after passing through the clock gating circuit.

[0084] CORE_CLK and Trunk_CLK are two clock paths provided to the chip's load modules. Figure 3 After determining which clock path, CORE_CLK or Trunk_CLK, is superior, the corresponding clock gating circuit can be used to shut down the other clock path. The chip clock is supplied by a crystal oscillator. At power-up, the crystal oscillator clock is used to supply the algorithm core module with the heaviest load, allowing the voltage distribution across the entire system to become more even. Then, once the PLL or DLL locks onto the desired clock, the PLL or DLL output clock is automatically switched to be used by the algorithm core module. For example... Figure 3 As shown, OSC is the external crystal oscillator of the chip, and either a larger or smaller clock crystal oscillator can be selected. If a larger crystal clock is supplied, considering the input requirements of the internal PLL and the jitter factor, the clock can be processed by the frequency divider module div_free to obtain the frequency that meets the PLL input and then supplied to the PLL. When the PLL generates a clock, a corresponding lock signal will also be generated. The lock signal is inverted and ANDed with the clock_chg_en configuration enable, and used as the strobe input of the Mux. In this way, the truth table in Table 1 can be obtained. When clock_chg_en is 0, the PLL clock is selected regardless of whether the PLL is locked. When clock_chg_en is 1, if the PLL is not locked, XCLK is selected as the clock; otherwise, the PLL clock is used. Of course, in order to ensure that xclk is used immediately upon power-on, the reset value of Clock_Chg_en can be set to 1. In this way, it can be ensured that the algorithm module of the main load module of the entire chip has a clock available and generates normal voltage division regardless of whether the PLL generates a clock.

[0085] Clock_Chg_en LOCK OUTPUT 0 0 PLL 0 1 PLL 1 0 XCLK (OSC_clk) 1 1 PLL

[0086] Table 1. Truth Table: Clock_chg_en & Lock & Output

[0087] See Figure 4 The following is a timing diagram. Figure 4The following signal traces are included: XCLK: Reference input clock signal, generated by an external crystal oscillator (XCLK), used as the clock source for the main load module before PLL locking. PLL_CLK_OUT: High-frequency stable clock signal output by the phase-locked element, supplied to the load module after PLL locking is completed. PLL_EN: Phase-locked element enable signal, used to start the PLL module into the phase-locking process. clock_chg_en: Indicates whether the function of selecting the OSC clock is enabled when the PLL is not locked, which is the selection terminal of the time selector MUX. PLL_CLK_VLD: PLL output valid indication signal, a high level indicates that the PLL output clock signal has been locked and stabilized. PLL_CFG_RST: PLL configuration reset signal, used to reload or reset PLL parameters to ensure reliable locking process. PLL_CFG: PLL configuration signal, loaded with target operating frequency and phase parameters during reset or initialization. Trunk_clk: The final working clock signal received by the load module. According to the switching control logic, XCLK is selected when the PLL is not locked, and PLL_CLK_OUT is selected after the PLL is locked.

[0088] right Figure 4 The demonstration describes the operation process as follows: During stages T0-T1, PLL_EN is high, and the PLL loads PLL_CFG. However, due to the time required for the PLL's internal structure to lock, PLL_CLK_VLD and PLL_CLK_OUT have not yet been generated and output. During stages T1-T2, PLL_EN remains high, and PLL_CLK_VLD being high indicates clock lock. PLL_CLK_OUT generates a high-frequency clock output normally. Stages T2-T3 demonstrate the changes in trunk_clk after clock_chg_en is pulled high. PLL_EN is pulled low at this stage because the PLL frequency will change at time T3. Typically, PLL_CFG needs to be prepared before frequency conversion, then PLL_EN is pulled low and then pulled high again (along with PLL_CFG_RST configured to reset the PLL's internal logic). After PLL_EN is pulled low, PLL_CLK_VLD is momentarily set low, and PLL_CLK_OUT disappears instantly.

[0089] During T3–T4 (operation mode switching phase), if the system control logic reconfigures the PLL (e.g., due to load mode or frequency changes), PLL_CFG_RST is set high, and the PLL is relocked. At this time, Trunk_clk is temporarily provided by XCLK. During T4–T5 (PLL relocking complete), the PLL re-enters the locked state, clock_chg_en is enabled, and Trunk_clk switches to the new PLL_CLK_OUT. The entire process maintains switching synchronization to avoid glitches and ensure the timing safety of the load module.

[0090] Figure 4 The specific timing sequence is as follows:

[0091] T0: After power-on, trunk_clk defaults to selecting the crystal oscillator clock xclk;

[0092] T1: The PLL is not locked when powered on. After the PLL is locked, trunk_clk will automatically select the PLL output clock.

[0093] T2: The PLL configuration needs to be adjusted or the PLL needs to be reset to the default frequency. At this time, the lock signal will disappear and trunk_clk will select XCLK.

[0094] T3: If the software wants to restore the PLL to the default clock frequency setting (e.g., 200MHz) or reconfigure the PLL frequency, it can configure the PLL_cfg_rst to generate a reset, which can restore the PLL parameters to the default frequency of 200MHz.

[0095] T4: If you need to pull PLL_EN low and high after reconfiguring the PLL frequency, it is similar to completing a PLL reset.

[0096] T5: After the software waits for the PLL lock, trunk_clk will select the PLL output clock.

[0097] Each PLL can be configured with clock_chg_en individually, increasing the flexibility of the PLL.

[0098] See Figure 5In another possible implementation, a chip clock control architecture is provided, which includes an external clock source (OSC) and a clock processing module (CPM). The CPM includes a frequency divider (DIV_free), a phase-locked loop (PLL), a clock switching unit (MUX), and a clock gating circuit (CKG). The CKG provides a stable clock signal to the load module at different operating stages of the chip, thereby reducing the impact of uneven power-on voltage division on system stability in a series power supply system. In this embodiment, the external clock signal generator (OSC) is a 24 MHz crystal oscillator used to generate a stable reference clock signal. This reference clock first enters the frequency divider (DIV_free), which outputs a reference clock signal RCLK according to a set division ratio through the unconstrained frequency divider (DIV). RCLK serves as the input clock signal for the PLL, which is then fed into the PLL module for phase-locked loop processing to generate a high-frequency stable output clock signal Plln_cclk_pre. Plln_cclk_pre is selected by the clock switching unit, and the selected clock is used as Plln_cclk. The clock switching unit (MUX, represented by a trapezoid in the diagram, 0 and 1 represent different inputs selected for the output when SEL is 0 or 1) selects the working clock source for the output according to the control command: When the chip is in the initial stage of power-up and the phase-locked loop (PLL) element is not locked, the MUX selects the external crystal oscillator clock XCLK or the divided RCLK as the clock input of the load module to ensure that the main load module obtains a stable clock drive upon power-up. When the PLL element is locked and outputs a stable high-frequency clock, the MUX switches to pll_clk (the clock output by the PLL), driving the load module into a high-performance working mode. The clock gating circuit CKG is used to open or close the clock signal path during clock switching to prevent glitches or unstable waveforms during the switching process from entering the load module. Figure 5 The diagram shows two independent clock gating units. Plln_cclk is determined as CORE_CLK or Trunk_CLK after passing through the clock gating circuit, and is used for clock management of the main load module (CORE_CLK) and the function control module (Trunk_CLK) respectively.

[0099] See Figure 5 The diagram and Table 2 show another clock processing structure compared to... Figure 3 The clock_chg_en function has been removed, and ~lock is now used directly as the strobe signal for the PLL clock and the XCLK Mux.

[0100] LOCK OUTPUT 0 XCLK 1 PLL

[0101] Table 2. Truth Table: Lock & Output

[0102] like Figure 6 The diagram shows a simplified timing scheme for the clock switching control, illustrating the relationship between the external crystal oscillator (XCLK) clock, the phase-locked loop (PLL) clock, the lock signal (LOCK), and the final load clock (trunk_clk). The output clock is xclk when Lock is not high; otherwise, it is the PLL output clock.

[0103] In another possible implementation, when the initial clock of the PLL lock is unstable, it is necessary to add gating control to ensure that the clock output after the gating is released is a stable clock. Figure 7 The provided timing diagram shows the timing relationship between different control signals and clock signals during the chip's power-on and operation process. Figure 7 The document details the relationship between the external crystal oscillator (XCLK) clock, the phase-locked loop (PLL) clock, the lock signal (LOCK), the clock gating signals (clock_chg_en, clk_gate), and the final load clock (trunk_clk). Based on the PLL output state, a smooth switch is performed between the external reference clock (XCLK) and the PLL output clock. Combined with the clock gating signals (clock_chg_en, clk_gate), a glitch-free switching process is ensured, thereby guaranteeing a stable clock for the load module during power-on and switching phases. See also... Figure 7 As shown in Table 3, when Lock is not pulled high, the output clock is xclk; when Lock is pulled high, but clk_gate is low, xclk is still used; when both Lock and clk_gate are high, the PLL clock is used as the output.

[0104] Clock_Chg_en Clk_gate LOCK OUTPUT 0 X X PLL 1 1 1 PLL 1 0 0 XCLK 1 0 1 XCLK 1 1 0 XCLK

[0105] Table 3. Truth Table: Clock_chg_en & clk_gate & Lock & Output

[0106] Based on the embodiments of this application, the following solutions are provided: uniform voltage division among multiple chips in a multi-chip series structure; uneven voltage division caused by different internal resistances and loads of the chips; voltage division caused by inconsistent PLL clocks of different chips in a series structure; abnormal chip power-on operation; signal transmission problems caused by uneven chip voltage division; and data CRC problems caused by uneven chip voltage division.

[0107] When the chip algorithm core can operate using only a crystal oscillator clock, the crystal oscillator clock is used to directly supply the clock signal. When the main load modules of the chip do not have high requirements for clock quality, a clock generated by a Ring-OSC can be used. A DDS clock can be used to generate the clock signal for the chip. An external clock input circuit can be used to generate the clock signal for the chip. An RC oscillator or MEMS clock oscillator can be used to generate the clock signal for the chip. Any structure or circuit capable of generating a clock can be used to implement the above voltage divider solutions.

[0108] Corresponding to the application scenarios and methods provided in the embodiments of this application, the embodiments of this application also provide a chip clock control device. For example... Figure 8 The diagram shows a structural block diagram of a chip clock control device according to an embodiment of this application. The device may include: an acquisition module 801, used to acquire the clock output state of a phase-locked element (PLE); and a first control module 802, used to provide a clock signal to the chip's load module based on the input clock signal of the PLEASE if the clock output state indicates that the PLEASE is not locked.

[0109] According to the embodiments of this application, the clock output state of the phase-locked element indicates that the phase-locked element is not locked. Based on the input clock signal of the phase-locked element, the supply of clock signal for the load module is determined, so that the load module can generate load at the moment the chip is powered on, thereby optimizing the voltage division obtained by the chip in the series power supply structure.

[0110] In one possible implementation, obtaining the clock output state of the phase-locked element includes: cyclically obtaining the clock output state of the phase-locked element at fixed or non-fixed time intervals.

[0111] In one possible implementation, the first control module is further configured to: if the clock output state indicates that the phase-locked element is locked, then provide a clock signal to the load module according to the output clock signal of the phase-locked element.

[0112] In one possible implementation, providing a clock signal to the load module based on the output clock signal of the phase-locked element includes: controlling the output clock signal through a clock gating circuit, releasing the clock gating circuit when the output clock signal reaches a specified state, and using the output clock signal in the specified state to provide a clock signal to the load module.

[0113] In one possible implementation, the input clock signal is generated by an external clock signal generator of the chip.

[0114] In one possible implementation, the external clock signal generator includes one or more of the following: a crystal oscillator, an RC oscillator, a MEMS clock oscillator, a direct digital synthesizer, or a ring oscillator.

[0115] In one possible implementation, the phase-locked element locking includes: the output clock signal of the phase-locked element being synchronized with the frequency of the reference clock signal, and the output clock signal of the phase-locked element being synchronized with the phase of the reference clock signal.

[0116] In one possible implementation, the device further includes a second control module for: adjusting the frequency of the output clock signal to a specified frequency threshold and / or adjusting the phase of the output clock signal to a specified phase threshold.

[0117] In one possible implementation, the phase-locked element includes a phase-locked loop and / or a delayed-locked loop.

[0118] In one possible implementation, the acquisition module is further configured to: acquire the clock output state of the phase-locked element in response to the chip being configured to a first control state; and further include a second control module configured to: provide a clock signal to the load module using the output clock signal of the phase-locked element in response to the chip being configured to a second control state.

[0119] The functions of each module in each device in the embodiments of this application can be found in the corresponding description in the above method, and they have corresponding beneficial effects, which will not be repeated here.

[0120] This application also provides a chip, including the chip clock control device described above.

[0121] Figure 9 This is a block diagram of an electronic device used to implement embodiments of this application. For example... Figure 9 As shown, the electronic device includes a memory 901 and a processor 902. The memory 901 stores a computer program that can run on the processor 902. When the processor 902 executes the computer program, it implements the method described in the above embodiments. The number of memories 901 and processors 902 can be one or more.

[0122] The electronic device also includes:

[0123] The communication interface 903 is used to communicate with external devices and exchange and transmit data.

[0124] If the memory 901, processor 902, and communication interface 903 are implemented independently, they can be interconnected via a bus to communicate with each other. This bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 9 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0125] Optionally, in a specific implementation, if the memory 901, processor 902, and communication interface 903 are integrated on a single chip, then the memory 901, processor 902, and communication interface 903 can communicate with each other through an internal interface.

[0126] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method provided in this application.

[0127] This application provides a computer program product, wherein the computer program product includes a computer program, which, when executed by a processor, implements the method provided in this application embodiment.

[0128] This application also provides a chip including a processor for calling and executing instructions stored in a memory, causing a communication device with the chip installed to perform the method provided in this application.

[0129] This application also provides a chip, including: an input interface, an output interface, a processor, and a memory. The input interface, output interface, processor, and memory are connected through an internal connection path. The processor is used to execute code in the memory. When the code is executed, the processor is used to execute the method provided in the application embodiment.

[0130] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting Advanced Reduced Instruction Set Machines (ARM) architecture.

[0131] Further, optionally, the aforementioned memory may include read-only memory and random access memory. The memory may be volatile memory or non-volatile memory, or may include both. Non-volatile memory may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available. Examples include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Sync Link DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0132] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.

[0133] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0134] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0135] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0136] The logic and / or steps described in the flowchart or otherwise herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0137] It should be noted that the information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0138] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0139] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0140] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope described in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip clock control method, comprising: Obtain the clock output state of the phase-locked loop (PLL) element; If the clock output state indicates that the phase-locked element is not locked, then a clock signal is provided to the load module of the chip according to the input clock signal of the phase-locked element.

2. The method according to claim 1, wherein obtaining the clock output state of the phase-locked element includes: The clock output state of the phase-locked element is obtained cyclically at fixed or non-fixed time intervals.

3. The method according to claim 1 or 2, further comprising: If the clock output state indicates that the phase-locked element is locked, then a clock signal is provided to the load module according to the output clock signal of the phase-locked element.

4. The method according to claim 3, wherein, Based on the output clock signal of the phase-locked element, a clock signal is provided to the load module, including: The output clock signal is controlled by a clock gating circuit, and the clock gating circuit is released when the output clock signal reaches a specified state. The output clock signal of the specified state is used to provide a clock signal to the load module.

5. The method according to claim 1, wherein, The input clock signal is generated by an external clock signal generator connected to the chip.

6. The method according to claim 5, wherein, The external clock signal generator includes one or more of the following: a crystal oscillator, an RC oscillator, a MEMS clock oscillator, a direct digital synthesizer, or a ring oscillator.

7. The method according to claim 3, wherein, The method further includes: Adjust the frequency of the output clock signal to a specified frequency threshold and / or adjust the phase of the output clock signal to a specified phase threshold.

8. The method according to claim 1, wherein, The phase-locked element includes: a phase-locked loop and / or a delayed-locked loop.

9. The method according to claim 1, wherein, Obtaining the clock output state of the phase-locked element includes: In response to the chip being configured to a first control state, the clock output state of the phase-locked element is obtained; The method further includes: In response to the chip being configured to a second control state, a clock signal is provided to the load module using the output clock signal of the phase-locked element.

10. A chip clock control device, the device comprising: The acquisition module is used to acquire the clock output status of the phase-locked element; The first control module is used to provide a clock signal to the load module of the chip according to the input clock signal of the phase-locked element if the clock output state indicates that the phase-locked element is not locked.

11. A chip comprising the chip clock control device of claim 10.

12. An electronic device comprising a memory, a processor, and a computer program stored in the memory, wherein the processor, when executing the computer program, implements the method of any one of claims 1-9.

13. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of any one of claims 1-9.

14. A computer program product, wherein, The computer program product includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-9.

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