Multi-adopted prediction entry for predicting recovery

Abstract

An apparatus comprising a prediction storage circuit to store a plurality of prediction entries, each prediction entry indicating whether a respective branch instruction is predicted to be taken or not taken. At least one prediction entry supports encoding of a multiple-taken entry indicating that the respective branch instruction and at least one subsequent branch instruction are each predicted to be taken. The apparatus further comprises a prediction recovery circuit to identify, in response to a flush signal, a prediction recovery address based on stored information dependent on the multiple-taken entry, wherein the prediction recovery address is an address for which at least one prediction is to be generated after the flush signal.

Description

Background Technology

[0002] This technology relates to the field of data processing. Specifically, this technology relates to branch prediction. Technical Background

[0004] The data processing apparatus may include a branch predictor that predicts whether a branch instruction should be adopted. Such predictions can be used to control the fetching of instructions from the memory system. When a prediction is incorrect, the processing pipeline flushes the instructions fetched based on that incorrect prediction. Instruction fetching can then begin based on the known outcome of the branch instruction until the branch predictor has restarted generating new predictions. Summary of the Invention

[0005] At least some examples of this technology provide an apparatus comprising: a prediction storage circuit configured to store a plurality of prediction entries, each prediction entry indicating whether a corresponding branch instruction is predicted to be adopted or not adopted, wherein at least one prediction entry supports encoding of a multi-adoption entry indicating that the corresponding branch instruction and at least one subsequent branch instruction are each predicted to be adopted; and a prediction recovery circuit configured to identify a prediction recovery address based on stored information depending on the multi-adoption entries in response to a refresh signal, the prediction recovery address being the address for which at least one prediction is to be generated after the refresh signal.

[0006] At least some examples of this technology provide a system comprising: the means described above, which is implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.

[0007] At least some examples of this technology provide a chip-integrated product that includes the system described above, wherein the system is assembled on another board together with at least one other product component.

[0008] At least some examples of this technology provide a method comprising: storing a plurality of prediction entries, each prediction entry indicating whether a corresponding branch instruction is predicted to be adopted or not adopted, wherein at least one prediction entry supports encoding of a multi-adoption entry indicating that the corresponding branch instruction and at least one subsequent branch instruction are each predicted to be adopted; and identifying a prediction recovery address based on stored information depending on the multi-adoption entry in response to a refresh signal, the prediction recovery address being the address for which at least one prediction is to be generated after the refresh signal.

[0009] At least some examples of the present technology provide a non-transitory computer-readable medium storing computer-readable code for manufacturing an apparatus, the apparatus comprising: a prediction storage circuit configured to store a plurality of prediction entries, each prediction entry indicating whether a corresponding branch instruction is predicted to be adopted or not adopted, wherein at least one prediction entry supports encoding of a multi-adoption entry indicating that the corresponding branch instruction and at least one subsequent branch instruction are each predicted to be adopted; and a prediction recovery circuit configured to identify a prediction recovery address based on stored information depending on the multi-adoption entries in response to a refresh signal, the prediction recovery address being the address for which at least one prediction is to be generated after the refresh signal.

[0010] Further aspects, features, and advantages of this technology will become apparent from the following description, which is taken in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1 An example is a data processing apparatus including an alternative predictive cache;

[0012] Figure 2 An example is shown that predictive recovery addresses are identified based on alternative path prediction;

[0013] Figure 3 An example is shown of the sequence of steps used to generate the prediction;

[0014] Figure 4 An example configuration of a marker geometry length predictor including multiple storage structures is illustrated;

[0015] Figure 5 An example of a collection-associated storage structure for storing prediction entries is shown;

[0016] Figure 6 This illustrates the sequence of steps for generating primary path predictions and alternative path predictions using a marked geometry length predictor;

[0017] Figure 7A and Figure 7B A graph illustrating program flow information including observed paths from candidate branch instructions is shown.

[0018] Figure 8A and Figure 8B A graph illustrating program flow information including observed paths from candidate polymorphic branch instructions is shown.

[0019] Figure 9 This illustrates a sequence of steps for updating program flow information;

[0020] Figure 10This illustrates the sequence of steps used to generate primary path prediction and alternative path prediction using program flow information;

[0021] Figures 11A to 11J Specific examples of predictable program flow main paths and alternative paths are shown;

[0022] Figure 12 An example is shown of a prediction pipeline that includes an alternative prediction cache;

[0023] Figure 13 Examples of systems and products containing chips are provided;

[0024] Figure 14 An example is given of determining the predicted recovery address based on multiple adoption entries; and

[0025] Figure 15A and Figure 15B Examples of multiple adoptions are shown. Detailed Implementation

[0026] According to some example embodiments, an apparatus is provided that includes a branch prediction circuit configured to generate a main path prediction for a given branch instruction of a given block of one or more instructions. In the event of an incorrect prediction (e.g., as determined by a branch parsing unit executing the given branch instruction), the branch prediction circuit may be required to begin generating predictions for different instruction blocks. To this end, the apparatus includes a block skipping circuit that, in response to a refresh signal indicating that the main path prediction is incorrect, controls the branch prediction circuit to begin generating predictions for subsequent instruction blocks identified by a prediction recovery address. This method enables the branch prediction circuit to skip instructions that begin to be fetched immediately after a refresh.

[0027] According to this technology, the branch prediction circuit is configured to further generate at least one alternative path prediction regarding an alternative program flow path to be followed if the main path prediction is incorrect. The device further includes an alternative prediction cache for storing alternative path predictions, at least until the main path prediction is determined to be incorrect. The block skip circuit is configured to identify the prediction recovery address based on the at least one alternative path prediction, and to support encoding of the alternative path prediction, which indicates that the alternative program flow path includes at least one adoption branch. Therefore, based on the alternative path prediction, the prediction recovery address can be set to a deeper future, allowing the branch prediction circuit to be controlled to start generating predictions for the deeper future more quickly. Thus, this method enables the fetching of new instructions to continue following paths that may include adoption branches without waiting for the branch prediction circuit to generate predictions. Therefore, the risk of instruction fetching abort is reduced when the branch prediction circuit resumes generating predictions after a refresh.

[0028] In some examples, a prediction pipeline may exist in which multiple stages of the prediction process can occur. The branch prediction circuit returns the main path prediction and the at least one alternative path prediction during the prediction stage of the prediction pipeline. The alternative prediction cache returns the at least one alternative path prediction during a control stage earlier in the prediction pipeline than the prediction stage. When using this prediction pipeline layout, an incorrect main path prediction can lead to prediction pipeline bubbles because: an ongoing prediction is flushed from the prediction pipeline, and a new prediction starting after prediction recovery takes one or more cycles to reach the prediction stage. This pipeline bubble then degrades instruction fetching performance. According to this technique, by using the alternative prediction cache to return the alternative path prediction to an earlier point in the prediction pipeline, the control stage can restart fetching much faster after a flush, i.e., at least one cycle faster. This reduces the size of the pipeline bubble. It should be understood that the prediction pipeline is not particularly restricted, and the branch prediction circuit is not required to be confined to the prediction pipeline. In some examples, the branch prediction circuit may span several prediction pipeline stages prior to the prediction stage, so that the main path prediction and the alternative path prediction are returned at the prediction stage.

[0029] In some examples, the branch prediction circuit is configured to generate the main path prediction and at least one alternative path prediction based on a single lookup in the prediction data. In this way, the alternative path prediction can be generated without introducing any additional delay to the generation of the main path prediction. This can be implemented in various different ways depending on the specific prediction mechanism used in the branch prediction circuit.

[0030] In some examples, the branch prediction circuit includes: a history tracking circuit for maintaining a program flow history based on prediction branch instructions that satisfy program flow history update conditions; and at least one set-associative storage structure configured to store prediction data, wherein the at least one set-associative storage structure includes a set indexed by a portion of the program flow history, the portion of the program flow history being independent of information related to the most recent prediction branch instruction that satisfies the program flow history update conditions. In such examples, looking up the storage structure based on a given index may result in a hit on multiple entries of the prediction data. Therefore, when looking up prediction data for the main path prediction, other entries from the prediction data are also identified in the same lookup. These other entries can then be used for one or more alternative path predictions. By excluding the most recent prediction branches that satisfy the program flow history update conditions from the information used to generate the set index, entries in the same set are more likely to provide alternative predictions that may be useful in the event that the most recent branch was mispredicted. The reason is that, since the set is indexed independently of information related to the most recently predicted branch instruction, the prediction entries in the set can indicate predictions for different paths of the program flow, which may involve different branches as the most recently adopted branches satisfying the program flow history update conditions (but they share a common program flow path until the corresponding most recently adopted branch in those paths). Therefore, this method provides a way to obtain multiple prediction entries related to alternative paths of the program flow in a single lookup of the set-associative storage structure.

[0031] Program flow history update conditions can be any conditions evaluated to determine whether the program flow history should be updated based on a given predicted branch. In some examples, program flow history update conditions may be satisfied for both predicted adopt branch instructions and predicted non-adopt branch instructions. However, it should be understood that the amount of data stored to represent the program flow history (and thus the frequency of updates) can be reduced by restricting program flow history update conditions to satisfying predicted adopt branch instructions but not predicted non-adopt branch instructions. In some examples, other criteria may also be considered to determine whether the program flow history should be updated based on a given predicted branch (e.g., in a specific implementation using a local history buffer, another criterion could be whether the program counter address and / or branch target address of a given branch satisfy a condition, such as being within a specific address range). Therefore, the specific program flow history update conditions that need to be met for a given predicted branch to cause an update to the program flow history can vary from one implementation to another. However, the set-associative storage structure is usually indexed by using an index value independent of the most recent branch that caused the program flow history to be updated. This means that multiple entries related to alternative program flow paths can be maintained in the same set, which are possible paths that may follow a given earlier mispredicted branch.

[0032] When multiple prediction entries are retrieved in a lookup within a set-associative storage structure, some examples distinguish these prediction entries by storing two or more prediction entries in each set associated with a corresponding label value to be compared with the label. This label depends on a portion of the program flow history, which in turn depends on information related to the most recent prediction branch instruction that satisfies the program flow history update conditions. This label can be compared with the label value in each prediction entry stored within the index set to determine which prediction entry should be used to generate the primary path prediction. Any one or more other prediction entries within the hit set can then be used to generate the at least one alternative path prediction.

[0033] In some examples, the indication of a given block (i.e., the block on which the tag is based) may depend on a program counter value. The program counter value can be the program counter value of a given branch instruction or another instruction from a given block (e.g., the first instruction in the block). The program counter value may also be hashed as part of the tag generation process.

[0034] It should be understood that in some examples, the index can be further independent of information related to the second most recently predicted branch instruction that satisfies the program flow history update conditions. This allows the set-associative storage structure to hit more entries, but at the cost of prediction accuracy. In examples configured to implement particularly aggressive predictions, increasing the independence of the index from the most recently adopted branch instruction allows alternative path predictions to be generated more deeply into the future. For example, additional alternative path predictions can be generated for additional branch instructions that are expected to be encountered beyond the current branch instructions for alternative path predictions, thereby expanding the alternative path predictions.

[0035] The set-associative memory structure described above can be one of multiple set-associative memory structures. An example of such a prediction mechanism is the Tag Geometric Length (TAGE) predictor. In some examples, there exists a long history memory structure associated with a long history length and a short history memory structure associated with a short history length. The branch prediction circuit can then identify prediction entries in those memory structures based on the different lengths of the current history for generating predictions. It should be understood that additional memory structures, such as one or more intermediate history memory structures, may also exist, each associated with a different history length between the long and short history lengths.

[0036] Some examples of the above arrangements can prioritize hits in the long history storage structure over hits in the short history storage structure to identify prediction entries to be used for the master prediction. Matching prediction entries with the longer history of the program flow indicates that the prediction generated based on that prediction entry is more likely to be accurate.

[0037] While this technique is useful for improving instruction fetching recovery, in some examples, it may be beneficial to control the allocation of alternative path predictions to the alternative prediction cache based on past observations of observed alternative paths that are more likely to provide good alternative predictions to the main path prediction. Therefore, in some examples, the apparatus may include flow tracing circuitry configured to maintain program flow information indicating one or more observed paths after a candidate branch instruction. In cases where a given branch instruction corresponds to the candidate branch instruction, the branch prediction circuitry is configured to store at least one alternative path prediction in the alternative prediction cache in response to the program flow alternative path corresponding to one of the one or more observed paths. Thus, if an alternative path prediction is generated associated with a candidate branch instruction, but the alternative path prediction does not correspond to any observed path traced in the flow tracing circuitry for the candidate branch instruction, the branch prediction circuitry may discard the alternative path prediction instead of storing it in the alternative prediction cache. Therefore, this method improves the utilization of the available capacity of the alternative prediction cache by limiting the storable predictions to paths of the program flow that have been previously observed. Therefore, by better utilizing alternative prediction caches, smaller alternative prediction caches can be implemented, which reduces associated hardware costs. Alternatively, for a given capacity of alternative prediction cache, the available capacity can be better used to provide alternative path predictions that are more likely to be used after a refresh, thereby improving performance for a given circuit area / power budget.

[0038] In some examples, the observed paths include information identifying at least one subsequent branch instruction encountered after the candidate branch instruction. Therefore, the observed paths may not only predict whether the candidate branch instruction is adopted. In fact, the observed paths may include observing whether a subsequent branch instruction is adopted or not, and may include observing whether another subsequent branch instruction is adopted or not. Therefore, alternative path predictions to be stored in the alternative prediction cache may need to correspond to such observed paths.

[0039] Given a limited capacity for encoding details of observed paths of program flow within a flow tracing circuit, in some examples, the flow tracing circuit is configured to impose a maximum limit on the number of subsequent conditional branch instructions in each of one or more observed paths. This limits the degree to which an observed path consisting of conditional branches is relevant to a particular candidate branch instruction. However, unconditional branches observed as part of an observed path can still be considered relevant and can be encoded more efficiently than conditional branches because it may be less necessary to encode information about the confidence level of whether a branch is adopted. Therefore, the flow tracing circuit can further support at least one observed path comprising multiple conditional branches corresponding to the maximum limit, followed by at least one unconditional branch instruction. Thus, if the extension consists of unconditional branches, the observed path can extend beyond the maximum limit. This can help improve performance by enabling alternative path prediction to recover from refreshed prediction lookups even deeper into the future.

[0040] This flow tracing circuit can be used to enable alternative path prediction for subsets of branch instructions. Specifically, because this technique helps improve performance in the event of incorrect main path prediction, the flow tracing circuit can be used for branch instructions considered difficult to predict. For example, the flow tracing circuit can select candidate branch instructions in response to determining that the candidate branch instructions have a misprediction rate exceeding a threshold. This helps to prioritize the limited capacity of the flow tracing circuit for the most difficult-to-predict branches, which are most likely to benefit from using an alternative prediction cache to accelerate recovery from refreshes caused by misprediction. Therefore, this method can improve the amount of performance gains achieved for a given circuit area and power budget.

[0041] In an apparatus including a branch target buffer, when the flow tracing circuit selects candidate branch instructions, one or more values ​​indicating the misprediction rate of one or more branch instructions are available. The flow tracing circuit can select which branches are selected as candidate branch instructions based on one or more values ​​indicating the misprediction rate tracked by the branch target buffer.

[0042] In some examples, several alternative path predictions may be stored simultaneously in the alternative prediction cache. Therefore, it is useful to be able to distinguish between different alternative path predictions to identify which alternative path prediction the block skip circuit should use when identifying the prediction recovery address in response to a refresh signal. Thus, the alternative prediction cache may store alternative path predictions associated with one or more pieces of information. Different pieces of information may be combined to form a label for each entry in the alternative prediction cache.

[0043] In some examples, the alternative prediction cache may be configured to store at least one alternative path prediction in association with an identifier of the given block of instructions. The identifier may, for example, depend on the program counter value associated with the first instruction of a given branch instruction or block. The identifier may also be, for example, an incrementing value corresponding to the location of an instruction block in the program. Such identifiers enable the alternative prediction cache to distinguish alternative path predictions for different instruction blocks.

[0044] In some examples, the alternative prediction cache may be configured to store at least one alternative path prediction in association with an offset for a given branch instruction. The offset may be relative to the beginning or end of the instruction block, or relative to another base address stored elsewhere. This offset enables the block skipping circuitry to determine which instructions should be fetched on the alternative path represented by the alternative path prediction.

[0045] In some examples, a given branch instruction is a polymorphic branch instruction. A polymorphic branch instruction is a branch that has multiple possible target instructions when the branch is adopted (e.g., where the branch target address depends on a data-related value generated by an earlier instruction). Therefore, the main path prediction may include a first target address, and at least one alternative path prediction may include a second target address. An alternative prediction cache can then be configured to store at least one alternative prediction in association with the second target address. Thus, the alternative prediction cache can distinguish alternative path predictions for the same polymorphic branch instruction, and therefore enables faster recovery from mispredictions caused by choosing an incorrect target address for the polymorphic branch instruction.

[0046] In some examples, the branch prediction circuitry can predict alternative path predictions that include return instructions. Return instructions can be used to signal the end of the called function, thus causing program flow to return to the previous instruction sequence. When such a function is called, the return address can be added to a data structure in memory called a call-return stack. The call-return stack can be arranged as a LIFO (Last-In, First-Out) structure and maintains the target address of the return instruction corresponding to the called function. Therefore, if such a return instruction is predicted as part of an alternative path prediction, the branch prediction circuitry can generate that alternative path prediction to include a pointer to the call-return stack, which can be stored in the alternative prediction cache so that the return address can be identified upon recovery from a flush.

[0047] According to some examples, an apparatus is provided comprising: a prediction memory circuit configured to store a plurality of prediction entries, wherein each prediction entry indicates whether a corresponding branch instruction is predicted to be adopted or not. At least one prediction entry supports encoding a multi-adoption entry indicating that the corresponding branch instruction and at least one subsequent branch instruction are each predicted to be adopted. In this way, the multi-adoption entries in the prediction memory circuit can be used to generate predictions for multiple branch instructions using a single entry, thereby enabling improved utilization of the prediction memory circuit.

[0048] The device also includes a predictive recovery circuit configured to identify a predictive recovery address based on stored information depending on the multiple adoption entries in response to a refresh signal. This predictive recovery address is the address for which at least one prediction is to be generated after the refresh signal. The predictive recovery circuit can operate in a similar manner to the block skip circuit previously described (and therefore, in some examples, the predictive recovery circuit may have any of the features previously described for the block skip circuit).

[0049] Therefore, after a refresh, multiple adoption entries can be used to identify the target address at at least one branch further into the future, compared to the possibility in implementations that do not support multiple adoption entries. By resuming prediction at that address, the extraction unit can extract instructions that follow the path of at least two adopted branches up to that target address without waiting for a new prediction. Therefore, the risk of instruction extraction aborting is lower when waiting to generate a new prediction after a refresh signal.

[0050] In some examples, the prediction circuitry performs a lookup in the prediction memory circuitry to generate a prediction for a given branch instruction, and the prediction circuitry generates memory information in response to generating the prediction for the given branch instruction and stores the memory information in the prediction recovery cache. In some such examples, the memory information may indicate an alternative path prediction, and the prediction recovery cache may correspond to the previously mentioned alternative prediction cache. Therefore, in the event of a flush, the memory information can be retrieved from the prediction recovery cache. As in the previously described example, information from the prediction recovery cache may be returned at an earlier pipeline stage than information from the prediction memory circuitry.

[0051] In some examples, a refresh signal indicates that the prediction is incorrect. When this occurs, the processing pipeline is refreshed, and the prediction circuitry stops generating predictions along paths now known to be incorrect. The prediction circuitry is instead controlled to resume prediction generation under the control of a prediction recovery circuitry as described above.

[0052] In some examples, the branch prediction circuit is configured to generate prediction and storage information based on a single lookup in the prediction storage circuit. In this way, storage information (e.g., identifying alternative path predictions) can be generated without introducing additional latency to the prediction generation. This can be implemented in various different ways depending on the specific prediction mechanism used in the branch prediction circuit.

[0053] For example, as described in the example above, a set-associative storage structure indexed by a portion of the program flow history, independent of information related to the most recent predicted branch instruction that satisfies the program flow history update conditions, can be used to locate multi-adoption entries. Multi-adoption entries can be used in place of any of the predicted entries described in the previous examples to enable the expansion of alternative path predictions without requiring additional lookups.

[0054] In some examples, two or more prediction entries in each set of the set-associative storage structure support the encoding of multi-adoption entries. In this way, multi-adoption entries can be identified as part of any lookup performed in the prediction storage circuit. In other examples, only subsets of sets or subsets of entries (paths) within a set can support multi-adoption entry encoding, where other sets or entries are restricted to encoding non-multi-adoption entries representing a single adoption branch.

[0055] In some examples, when generating predictions for candidate branch instructions, the flow tracing circuitry (such as the flow tracing circuitry described above with reference to earlier examples) may control whether to store stored information (such as alternative path predictions) based on whether a multi-adoption entry indicates a program flow corresponding to one of one or more observed paths traced by the flow tracing circuitry for the candidate branch instruction. Other aspects of the flow tracing circuitry described above may be further included in conjunction with support for multi-adoption entries. For example, one or more observed paths may include information identifying at least one subsequent branch instruction encountered after the candidate branch instruction. In some examples, the flow tracing circuitry may impose a maximum limit on the number of subsequent conditional branch instructions in each of the one or more observed paths, and the flow tracing circuitry may support at least one observed path that includes multiple conditional branch instructions corresponding to the maximum limit, which are followed by at least one unconditional branch instruction. In some examples, the flow tracing circuitry may select a candidate branch instruction in response to determining that the candidate branch instruction has a misprediction rate exceeding a threshold.

[0056] Predictive storage circuitry can store multi-adoption entries in response to specific observations in the program flow. In some examples, the subsequent branch instruction indicated as adopted by the multi-adoption entry can be an unconditional branch instruction, and therefore, this subsequent branch instruction is always adopted. In other examples, the subsequent branch instruction indicated as adopted by the multi-adoption entry can be a conditional branch instruction predicted to be adopted, and has an associated confidence value exceeding a threshold. Such confidence values ​​may have been generated over time due to repeated correct predictions about the subsequent branch instruction. In each of these examples, an opportunity is provided to compress additional predictive information in the multi-adoption predictive entries. Thus, when a lookup is performed regarding the generation of a prediction for the corresponding branch instruction, the predictive storage circuitry can further provide a prediction of the program flow by providing both the prediction of the corresponding branch instruction and at least one subsequent branch instruction, without incurring additional delays associated with further lookups.

[0057] In some examples, the predictive recovery circuit may correspond to the previously mentioned block skip circuit, and thus in some examples, the predictive recovery circuit may have any of the features described for the block skip circuit.

[0058] Now, let's explain a specific example with reference to the accompanying diagram.

[0059] Figure 1An example of a data processing apparatus 2 is illustrated schematically. The data processing apparatus has a processing pipeline 4 comprising multiple pipeline stages. In this example, the pipeline stages include: a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by the remaining stages of the pipeline; a release stage 12 for checking whether the operands required for the micro-operation are available in a register file 14, and releasing the micro-operation for execution once the operands required for a given micro-operation are available; an execution stage 16 for performing the data processing operation corresponding to the micro-operation by processing the operands read from the register file 14 to generate a result value; and a write-back stage 18 for writing the processed result back to the register file 14. It should be understood that this is merely one example of a possible pipeline architecture, and other systems may have additional stages or different stage configurations. For example, in an out-of-order processor, a register renaming stage may be included to map the architecture registers specified by program instructions or micro-operations to physical register specifiers in the identifier register file 14. In some examples, there may be a one-to-one relationship between program instructions decoded by decoding stage 10 and corresponding micro-operations processed by execution stage 16. It is also possible that there is a one-to-many or many-to-one relationship between program instructions and micro-operations, such that, for example, a single program instruction can be split into two or more micro-operations, or two or more program instructions can be merged to be processed as a single micro-operation.

[0060] Execution phase 16 includes multiple processing units for performing different types of processing operations. For example, the execution units may include: a scalar arithmetic / logic unit (ALU) 20, which performs arithmetic or logical operations on scalar operands read from register 14; a floating-point unit 22, which performs operations on floating-point values; a branching unit 24, which evaluates the results of branching operations and adjusts the program counter representing the current execution point accordingly; and a load / store unit 26, which performs load / store operations to access data in memory systems 8, 30, 32, and 34.

[0061] In this example, the memory system includes a tier-one data cache 30, a tier-one instruction cache 8, a shared tier-two cache 32, and main system memory 34. It should be understood that this is merely one example of a possible memory hierarchy, and other cache arrangements may also be provided. The specific type of processing units 20 to 26 shown in execution phase 16 is only one example, and other specific implementations may have different sets of processing units or may include multiple instances of the same type of processing units, allowing multiple micro-operations of the same type to be processed in parallel. It should be understood that... Figure 1 This is merely a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements not shown for the sake of simplicity.

[0062] like Figure 1 As shown, apparatus 2 includes a branch predictor 40 (corresponding to an example of the prediction circuitry in the appended claims) for predicting the outcome of branch instructions. The branch predictor 40 is located based on the address of the instruction provided by extraction stage 6, and provides predictions about whether those instructions include branch instructions, and for any predicted branch instructions, predictions of their branch properties (such as branch type, branch target address, and branch direction) (the predicted branch outcome, indicating whether the prediction is to accept or not accept the branch). Branch predictor 40 includes a branch target buffer (BTB) 42 for predicting the properties of the branch other than the branch direction, and a branch direction predictor (BDP) 44 for predicting the non-acceptance / acceptance outcome (branch direction). It should be understood that the branch predictor may also include other prediction structures, such as a call-return stack for predicting the return address of a function call, a loop direction predictor for predicting when a loop control instruction will terminate the loop, or other more specialized types of branch prediction structures for predicting the behavior of outcomes in a particular scenario. The branch predictor also has a global history buffer (a concrete example of a history tracing circuit) 125 that maintains the program flow history based on predicted branch instructions that satisfy the program flow history update conditions. The program flow history represents the history of the program flow prior to the current program flow point where a branch prediction is to be made. For example, whenever the branch predictor 40 predicts a predicted branch instruction that satisfies the program flow history update conditions, information about that branch (e.g., information derived from the program counter address and / or the branch target address and / or the result of the branch being accepted / not accepted) can be logically inserted into the history tracing circuit. The history tracing circuit can logically function as a first-in, first-out buffer (in some implementations, it is implemented as a circular buffer based on a pointer to the point where the next entry should be inserted in the tracing buffer), such that if there are no remaining invalid entries in the buffer, the oldest entry can be overwritten by new information. Therefore, the history tracing circuit tracks information about a specific number of recently predicted branches.

[0063] The program flow history update criteria used to determine whether a given predicted branch instruction should cause an update to the program flow history can vary depending on the specific implementation choice. In some examples, all predicted branches may cause an update to the program flow history. In other examples, the program flow history update criteria may be satisfied when a predicted branch is predicted to be adopted, but may not be satisfied when a predicted branch is predicted not to be adopted.

[0064] In some examples, program flow history update conditions may also depend on properties of a branch other than its acceptance / non-acceptance outcome. For example, the program counter address and / or the branch target address of the branch may be used to determine whether the program flow history update conditions are met. For instance, a history tracing circuit may include multiple local history buffers, each updated based on a branch having an instruction address within a corresponding address range associated with that buffer, and in this case, the instruction address (program counter address) of the branch may be checked to determine whether the program flow history update conditions are met.

[0065] Regardless of the specific program flow history update conditions for a given example of the history tracing circuit 125, the program flow history tracked by the history tracing circuit 125 can be used to form information for finding some predictive structure (such as branch direction predictor 44). For example, the program flow history can be used to generate index information and / or tags for finding set-related predictive storage structures, as discussed in more detail below.

[0066] like Figure 1 As shown, device 2 may include a table update circuit 120 that receives signals from branch unit 24 indicating the actual branching result of an instruction, such as whether an adopted branch was detected in a given block of the instruction, and if so, an indication of the branch type, target address, or other properties. This is also provided to table update circuit 120 if a branch is detected as not adopted. Table update circuit 120 then updates the state within BTB 42, branch direction predictor 44, and other branch prediction structures to take into account the actual results seen for the executed instruction block, making it more likely to make a correct prediction when the same instruction block is encountered again.

[0067] Predictions from branch predictor 40 (and particularly branch directions from BDP 44) may include several predictions regarding a single lookup address. These predictions include main path predictions that control which instructions are fetched by fetch stage 6, and alternative path predictions stored in alternative prediction cache 46. Alternative path predictions indicate alternative program flow paths to follow if the main path prediction is incorrect. For example, if the prediction is to adopt a branch instruction (i.e., as a main path prediction), the alternative path prediction could be to not adopt the branch instruction but instead adopt a subsequent branch instruction.

[0068] like Figure 1 As shown, apparatus 2 also includes a block skip circuit 48 configured to control how branch predictor 40 restarts prediction generation in the event of a refresh. A refresh can occur in response to branch unit 24 evaluating a branch instruction differently than the result predicted in the main path prediction. Any instructions in pipeline 4 that have been fetched by fetch stage 6 based on the main path prediction are refreshed, and branch predictor 40 is caused to restart a new prediction from the prediction recovery address. Block skip circuit 48 identifies the prediction recovery address based on the alternative path prediction stored in alternative prediction cache 46.

[0069] As mentioned above, alternative path prediction can indicate that alternative paths in the program flow include at least one adoption branch (which can be a different branch predicted by the main path prediction). Therefore, block skip circuit 48 can identify the predicted recovery address in a subsequent instruction block after that adoption branch. Figure 2 An example illustrating where the predicted recovery address might be is given. The program flow begins in processing block (PB) 1, which contains a sequence of instructions including branch instruction BR1. When branch predictor 40 detects BR1, BDP 44 indicates that the main path prediction is adopted (T). BTB 42 indicates PB1.1 as the instruction block targeted by BR1. Therefore, branch predictor 40 can control fetch stage 6 to begin fetching instructions from PB1.1. Branch predictor 40 further generates an alternative path prediction indicating that BR1 is not adopted and that an alternative program flow is subsequently traversed to PB2, which contains the branch instruction BR2 predicted to be adopted and branching to target block PB2.1.

[0070] When a refresh signal is received, for example, from branch unit 24, block skip circuit 48 identifies the prediction recovery address corresponding to the branch target in PB2.1 based on alternative path prediction. Block skip circuit 48 then controls branch predictor 40 to begin generating a prediction for the address corresponding to the branch target of BR2 within PB2.1. Additionally, fetch stage 6 can begin fetching instructions following BR1 based on alternative paths that would be predicted as adopted if BR1 is not adopted. Fetch stage 6 continues fetching instructions following alternative paths in the program flow until the prediction recovery address is reached, without requiring new predictions from branch predictor 40. Therefore, branch predictor 40 can restart prediction sufficiently earlier than the instructions actually fetched by fetch stage 6, thereby reducing the possibility of fetch stage 6 aborting due to predictions not being available in time. Thus, the performance of fetch stage 6 immediately following refresh can be improved.

[0071] It should be understood that, although Figure 2 An example of a main process flow and an alternative process flow is illustrated, but the predictions can differ. Some examples may involve an alternative process flow that includes multiple adoption branches through multiple processing blocks. Various examples of alternative process flows will be described later.

[0072] Figure 14 Another example is shown where multiple adoption entries are used to generate alternative stream predictions, illustrating both the main stream and the alternative stream. Similar to... Figure 2 In the example, the main path prediction generated by BDP 44 indicates that BR1(T) should be adopted. Branch predictor 40 further generates an alternative path prediction indicating that BR1 should not be adopted, and the alternative procedure flow then traverses to PB2 containing the branch instruction BR2. In this example, BDP 44 contains a multi-adoption entry corresponding to BR2, which indicates that both BR2 and the subsequent branch (i.e., BR2.1) are predicted to be adopted. Therefore, an alternative path prediction is generated to indicate that BR2 is adopted to branch to target block PB2.1, and also indicates that BR2.1 is adopted to branch to target block PB2.2. By compressing the predictions of multiple branch instructions into a single entry, the alternative path prediction can be expanded to identify prediction recovery addresses even deeper into the future, without requiring a separate prediction for BR2.1.

[0073] Therefore, when a refresh signal is received in this example, the block skip circuit 48 identifies the prediction recovery address corresponding to the branch target in PB2.2 based on alternative path prediction. As described above, the block skip circuit 48 then controls the branch predictor 40 to begin generating a prediction about the address corresponding to the branch target in BR2.1 within PB2.2, while fetch stage 6 begins fetching instructions after BR1 and following alternative path prediction via branches BR2 and BR2.1. Therefore, Figure 3The example further improves the performance of extraction stage 6 by further reducing the likelihood that extraction stage 6 will be aborted due to unavailable predictions.

[0074] According to specific criteria, multiple adoption entries may be permitted in BDP 44. For example, if BR2.1 has previously been observed as an unconditional branch instruction or is predicted to be adopted and associated with a high confidence level (e.g., exceeding a certain threshold), then the predicted entries for BR2 and BR2.1 may be compressed into a single multiple adoption entry.

[0075] It should be understood that a multi-adoption entry is not limited to indicating that two branch instructions will be adopted. In some examples, a multi-adoption entry may indicate that three or more branch instructions are each predicted to be adopted.

[0076] Figure 3 An example of the sequence of steps for generating the main path prediction and alternative path prediction, as well as skipped blocks, is illustrated. The process begins at step 100, where branch predictor 40 identifies (e.g., based on a lookup of BTB 42) the instruction block containing the given branch instruction, and uses branch direction predictor 44 to generate the main path prediction and alternative path prediction for the given branch instruction. At step 102, the main path prediction control fetch stage 6 is performed, and at step 104, the alternative path prediction is stored in the alternative prediction cache 46. At step 106, it is determined whether the main path prediction was mispredicted. This can be determined by receiving a refresh signal from branch unit 24. It should be understood that for some execution pipelines, steps 100 through 104 may be repeated for different branch instructions before the determination of executable step 106. Therefore, it should be understood that... Figure 3 The process is only about a single branch instruction.

[0077] If the primary path prediction is determined to be correct, then at step 108, the branch predictor 40 continues to generate predictions normally. For example, alternative path predictions may eventually be evicted from alternative path predictions according to the eviction policy implemented when allocating new alternative path predictions to alternative prediction cache 46.

[0078] If the main path prediction is determined to be incorrect, a refresh signal is detected at step 110, and the block skip circuit 48 retrieves the alternative path prediction from the alternative path cache 46. At step 112, the block skip circuit 48 identifies the prediction recovery address for the subsequent instruction block based on the alternative path prediction. It should be understood that the alternative path prediction information can also be conveyed to the fetch stage 6, which restarts instruction fetching after a mispredicted branch instruction based on the program flow alternative path. At step 114, the block skip circuit 48 controls the branch predictor 40 to restart prediction generation at the prediction recovery address.

[0079] Figure 4A specific example of a prediction mechanism that can be implemented in branch predictor 40 (e.g., as BDP 44) is illustrated. The prediction mechanism is a Tag Geometry (TAGE) predictor, for which branch prediction table 50 includes a base prediction table T0 and multiple TAGE tables T1 to T4, each arranged as a set-associative storage structure. While this example shows four TAGE tables for simplicity, it should be understood that the TAGE predictor can have a greater number of tables, such as eight or sixteen, if desired. The base predictor T0 is indexed only based on the program counter PC 64, while the TAGE tables T1 to T4 are indexed based on hash values ​​generated by applying hash function 82 to historical information 66 of progressively increasing length, such that T1 uses a shorter sequence of historical information compared to T2, T2 uses a shorter sequence of historical information compared to T3, and so on. In this example, T4 is the table using the longest sequence of historical information.

[0080] The index generated by hash function 82 is used to select which specific entry of TAGE table 50 to read when looking up table 50. The history information 66 used to generate the index value is derived from the program flow history tracked by the history tracing circuit 125 discussed above, and includes information about the most recently predicted branch instruction that has met the program flow history update conditions (e.g., in some specific examples, the branch instruction predicted to be adopted). For indexing purposes, history information 66 excludes the most recently predicted branch instructions that meet the program flow history update conditions. For example, if the program flow history update conditions are met only for adopted branch instructions, the index is independent of information associated with the most recently predicted branch instructions. Therefore, in the case of updating the program flow history based on branches A, B, C, and D, the portion of the program flow history used as history information 66 to generate the index value may only represent information about branches A, B, and C, excluding information about branch D. Therefore, the prediction entries in the corresponding set can indicate prediction information related to the history of A, B, C, and D, as well as A, B, C, and D' (where D' indicates a branch different from branch D, which may appear after a difference in the prediction results of one or an intermediate branch of branch C or D). Thus, two or more prediction entries can be identified in a single lookup of each TAGE table, each related to a shared earlier portion of the program flow history (e.g., the history corresponding to branches A, B, and C), but then diverging (e.g., a difference between branch D and branch D'), thus generating two or more predictions related to possible alternative paths around a given point in the program flow.

[0081] Therefore, in this example, the index of table T1 is based on historical information H[1:L(1)], the index of table T2 is based on historical information H[1:L(2)], the index of table T3 is based on historical information H[1:L(3)], and the index of table T4 is based on historical information H[1:L(4)], where L4>L3>L2>L1, so that each TAGE table uses a progressively longer historical sequence, but the index of each table is generated based on information excluding the entry H[0] that represents the most recent predicted branch that made the history updated.

[0082] Each prediction entry specifies a prediction counter (“pred”), such as a 2-bit counter, which provides a bimodal indication of whether to adopt a prediction (e.g., counter values ​​11, 10, 00, and 01 could indicate strong prediction adoption, weak prediction adoption, weak prediction non-adoption, and strong prediction non-adoption, respectively). Each entry also specifies a tag value 80, which is compared with a tag hash generated based on the indication of the current block of instructions (i.e., PC 64) and historical information 70 related to the most recent prediction branch instruction (i.e., branch D from the example above). Figure 4 In this example, the most recently predicted branch instruction is represented by H[0], which is not included in the historical information 66 used for indexing, but is used for tag generation hash 84. Although in this example, the tag hash does not depend on other entries in the history tracked by the history tracking circuit 125 (entries H[1] and later in the historical information are used for index hash 82 instead of tag hash 84), other examples may also consider one or more entries from the historical entry H[1] and later in the tag hash function.

[0083] A label hash is used to distinguish multiple predicted entries whose index hash values ​​are aliased to the same set of the table. The lookup circuitry includes: an index hash circuit 82 for generating an index hash to index into a selected set of the table; a label hash circuit 84 for generating a label hash value to be written to a newly assigned predicted entry or for comparison with the label value 80 of an existing predicted entry during a lookup; and a comparison circuit 86 for comparing the label value 80 read from the lookup entry with the calculated label hash generated by the label hash circuit 84 to determine if a hit has been detected.

[0084] For the TAGE predictor, the TAGE prediction generation circuit 68 includes a cascaded sequence of select multiplexers 88 that select among alternative predictions returned by any of the prediction tables in the generated hit prediction table 50. The base predictor 50 is always considered to have generated a hit and is used as a fallback predictor in case no other TAGE tables have generated a hit (a hit occurs when the tag in the lookup entry matches a tag hash generated based on index information). The cascaded multiplexers ensure that if table T4, indexed using the longest history sequence, generates a hit, its prediction is output as the prediction result; however, if that table does not generate a hit, then if the previous table T3 generated a hit, the T3 prediction is output as the overall prediction for the current block, and so on, such that the selected prediction is the prediction output by the table corresponding to the longest history sequence considered in the index (among those tables that generated hits). In other words, any tables that are not hit are excluded from the selection, and the table with the longest historical sequence in its index information is selected from the remaining tables. If none of the TAGE tables T1 to T4 generate a hit, the base predictor T0 is selected.

[0085] This approach is highly useful for providing high performance because a single table using a fixed-length branch history index must strike a trade-off between prediction accuracy and the likelihood of a hit in the table. Tables using relatively short branch history sequence indexes may be more likely to generate hits because the most recently seen history leading to the current block is more likely to be the same as a previously seen history sequence for which an entry is recorded in the table. However, because shorter history sequences cannot accurately distinguish different routes the program flow may have taken to reach the current block, the prediction indicated in the hit entry is more likely to be incorrect. On the other hand, for table T4 based on the longest history sequence index, this can be very useful for predicting branches that are more difficult to predict, requiring a deeper exploration of the past to characterize the program execution pattern leading to that branch and make accurate predictions. However, in subsequent cases, longer history sequences are less likely to perfectly match the history sequence leading to the current block, and therefore, the hit rate is lower in tables based on longer history sequence indexes. By providing a series of tables with varying histories for indexing, this balances these factors, allowing the most difficult-to-predict branches, which are hard to predict using other branch predictors, to be successfully predicted using the longer table T4. However, other, easier-to-predict branches, which do not require the full predictive power of T4, can be predicted using one of the earlier tables based on shorter-historical indexes. This increases the likelihood of a hit being detected in the predictive lookup, thereby increasing the percentage of successfully predicted branches and thus improving prediction accuracy and performance. Therefore, the TAGE predictor is one of the most accurate predictors known.

[0086] By indexing TAGE tables T1 through T4 independently of information H[0] associated with the most recently predicted branch instruction that satisfies the program flow history update conditions, a single lookup of the TAGE predictor can hit an index set containing two or more predicted entries that may be associated with alternative program flow paths that could be useful if the main path prediction is incorrect. Predicted entries to be used to generate the main path prediction are identified by comparing tag hash values, which depend on information associated with the most recently predicted branch instruction. Entries that do not match the tag hash value (but match the index hash) may involve different branch instructions (e.g., in different instruction blocks) but have a similar history of predicted branches (excluding the most recently predicted branch that satisfies the program flow history update conditions). Therefore, by caching alternative path predictions for use during recovery from a refresh, such entries can be used to generate alternative path predictions without causing additional lookups to the full TAGE structure.

[0087] Figure 5 An example is shown of a set that can be hit in one of the TAGE tables T1 to T4. The history (information about the most recent predicted branch that satisfies the program flow update conditions) other than H[0] is hashed by index hashing circuit 82 to obtain an index to the TAGE table. In this example, the index hit contains a set of three prediction entries (three entries are shown for brevity, but in reality, the number of entries in a set can be a power of 2). Each entry in this set can indicate a different path of the program flow. Each prediction entry is also stored in association with a corresponding tag value. The tag value is compared with a tag generated by tag hashing circuit 84 based on PC 64 and the information H[0] associated with the most recent predicted branch instruction that satisfies the program flow history update conditions to identify the prediction entry to be used to generate the main path prediction. The remaining prediction entries (i.e., prediction entries that match the index but do not match the tag) can then be used to generate alternative path predictions.

[0088] Among the remaining prediction entries used to generate alternative path predictions, some examples may include prediction entries that support encoding of multiple adoption entries indicating sequences of two or more branch instructions, each predicted to be adopted. Figure 15A An example of a program flow is illustrated, in which multiple adoption entries can be stored in, for example, one of the TAGE tables T1 through T4. The program flow begins in PB1 and adopts a branch instruction BR1 targeting PB2. PB2 then contains a branch instruction BR2, which is adopted and targets PB3. When such a program flow is observed, table update circuitry 120 can update a prediction entry in one of the TAGE tables to include the multiple adoption entries.

[0089] Figure 15BExamples of data that can be included in different types of entries are illustrated. In a single adoption prediction entry (e.g., where the prediction entry identifies the prediction result of a branch instruction), the prediction entry includes an indication of the prediction direction (i.e., adoption, T) associated with the identifier of the branch instruction BR1. As previously mentioned, the identifier of the branch instruction may be included in the label. It should be understood that in order to provide Figure 15A The predicted information for the program flow will require an additional single-adoption prediction entry to indicate that BR2 will also be adopted.

[0090] In a multi-adoption prediction entry (e.g., where the prediction entry identifies the prediction result of multiple branch instructions), the prediction entry includes an indication of the result of multiple branch instructions. In this case, the entry is associated with both BR1 and BR2, both of which are predicted to be adopted. Therefore, the prediction direction indicates two adoptions (2T). BR1 can still be used to tag the multi-adoption entry so that when looking up the prediction for BR1, the prediction information for BR1 and BR2 can be obtained in the same search. It is also possible that a separate single-adoption prediction entry (with an index and label corresponding to BR2) exists, located in the TAGE table at a different position than the multi-adoption prediction entry whose index / label corresponds to BR1.

[0091] It should be understood that while the techniques of this invention may include an index independent of the most recently predicted branch instructions that satisfy the program flow history update conditions, a more radical example may use an index independent of information associated with N most recently predicted branch instructions that satisfy the program flow history update conditions, where N is an integer greater than 1. This allows the set association structure to hit more entries, thereby enabling more predictions at the expense of accuracy. This may allow for the further identification of alternative paths that encompass a greater number of branches before the point where a misprediction is detected.

[0092] Figure 6This illustrates a sequence of steps for generating primary path and alternative path predictions using a TAGE predictor. The process begins at step 150, where a (single) lookup is initiated in the TAGE predictor. Initiating the lookup may include generating hash values ​​for index hashes and / or tag hashes based on PC 64 and historical information 66, 70 tracked by history tracing circuitry 125. At step 152, a hit on the index is detected using the program flow history, independent of information associated with the most recent predicted branch instruction that satisfies the program flow history update conditions. A set of hit identifiers is associated with a set in the TAGE table containing two or more prediction entries. At step 154, the tag of each prediction entry in this set is compared with a tag value generated based on the current block and the program flow history, which depends on information associated with the most recent predicted branch instruction that satisfies the program flow history update conditions. If a hit is found in the tag value comparison, at step 156, a primary path prediction is generated based on the hit prediction entry. At step 158, at least one alternative path prediction is generated using any other prediction entry in the set, and then the at least one alternative path prediction is stored in the alternative prediction cache 46, as in the previous example.

[0093] It should be understood that in the case of multiple hit prediction entries in branch predictor 40, alternative path predictions can be generated based on each hit prediction entry. While this provides a comprehensive overview of how the path of program flow might change if the main path prediction is incorrect, the alternative prediction cache could experience significant pressure when storing all alternative path predictions. Therefore, among the alternative path predictions that can be generated, those corresponding to previously observed paths after branch instructions are allowed to be stored in the alternative prediction cache 46. This thus limits the alternative path predictions to those that are more likely to be accurate.

[0094] For this purpose, device 2 may be provided with a flow tracing circuit 52, wherein program flow information indicating one or more observed paths following candidate branch instructions is maintained. The program flow information may be represented as a graph, an example of which is shown in... Figure 7AAs shown in the diagram. A candidate branch instruction 160 is selected for flow tracing, from which the program flow has previously been observed to follow both adopted and non-adopted paths. In response to the results of further predictions and / or parsed branches generated at execution phase 16, further program flow points are added. For example, along the non-adopted path from candidate branch instruction 160, the program flow encounters conditional branch instruction B, for which prediction circuit 40 generates a prediction. Therefore, branch instruction B is added to the observed path of the program flow, which is then divided into another adopted and non-adopted path to encounter conditional branch instructions E and F, respectively. These two conditional branch instructions are similarly added to the program flow when predictions are generated for branches E and F.

[0095] It should be understood that the program may also include unconditional branches. As shown in the figure, the adoption path from candidate branch instruction 160 encounters unconditional branch instruction A, and the prediction circuit 40 does not need to generate a prediction for this unconditional branch instruction. However, unconditional branch instruction A can be identified and added to the observed path of the program flow, which then continues to the adoption path to encounter conditional branch instruction C. When a prediction is generated for branch C, the conditional branch instruction is similarly added to the program flow.

[0096] It should be understood that the depth of the graph corresponding to the length of the observed path can be limited to reduce the capacity required to maintain the program flow information. However, if the observed path is at a limit but then encounters an unconditional branch such as an unconditional branch G, the flow tracing information can include the unconditional branch at low cost because the flow tracing circuit 52 does not need to wait for a prediction to be generated. For example, information identifying the unconditional branch can be appended to entries in the program flow information.

[0097] Each observed path from candidate branch instruction 160 can be represented as an entry in the program flow information. For example, each entry may contain information specifying the following: the program counter address of candidate branch instruction 160, the observation result of the candidate branch instruction (accepted or not accepted), the target address of the candidate branch (if accepted), and similar information for one or more subsequent branch instructions. Figure 7B Examples Figure 7A The graph can be stored as an example of entries for program flow information. The field BR0 indicates the address of the next branch encountered after the observation (DIR) from candidate branch instruction 160. The values ​​of BR0_T and BR0_N then further indicate the addresses of subsequent branches encountered for the adopted and unadopted results of the branch instruction identified by BR0. It should be understood that further information, such as BR1_T and BR1_N, may be included, indicating the branch encountered after branch E. Additionally, Figure 7BAn example is shown where information about the unconditional branch #G is included in the field BR0_N, which shows the program flow after branch B is not adopted.

[0098] In some examples, the flow tracing circuit 52 can maintain program flow information indicating one or more observed paths following a polymorphic branch instruction. A polymorphic branch instruction is a branch instruction that, when adopted, can cause multiple different target addresses. Therefore, there may be a large number of possible observed paths following a polymorphic branch instruction leading to each possible adopted path.

[0099] Figure 8A A graph illustrating program flow information for candidate polymorphic branch instruction 170 is shown. In this example, it has been observed that candidate polymorphic branch instruction 170 follows two adoption paths to target address 1 and target address 2. This can also be compared with the reference... Figure 7A The described approach adds additional points to the program flow, allowing conditional branch instructions A through G to also be included on the observed paths. Further observed paths could include candidate polymorphic branch instructions following an adoption path to target address 3, which then encounters conditional branch instruction H. Therefore, it should be understood that candidate polymorphic branch instructions can follow multiple different adoption paths, which in turn lead to different conditional branch instructions encountered on each observed path. Some examples may focus the flow tracing functionality on polymorphic branches with a small number of possible target addresses to avoid excessive complexity in the program flow information. Some examples may also replace some observed paths with newer paths, allowing the program flow information to identify some addresses among the most recently observed target addresses.

[0100] Figure 8B This illustrates how entries for program flow information can be stored in the flow tracing circuit 52. Specifically, when tracing polymorphic branch instructions, an additional field (TGT) can be used to indicate the target address of the observed branch, allowing the identification of relevant paths in the program flow when resolving or predicting the target address of the polymorphic branch.

[0101] Flow tracing circuitry 52 can be used to control which alternative path predictions are allowed to be stored in alternative prediction cache 46. For example, when alternative path predictions are generated, for instance, using the TAGE predictor described previously, flow tracing circuitry 52 is configured to determine whether any observed path corresponds to an alternative path prediction. If so, the alternative path prediction is considered more likely to be accurate, and therefore allowed to be stored in alternative prediction cache 46. On the other hand, alternative path predictions that do not correspond to any of the observed paths may not be allowed to be stored in alternative prediction cache 46.

[0102] As should be understood from the above description of the flow tracing circuit 52, the amount of program flow information generated will depend on how candidate branch instructions 160 (or candidate polymorphic branch instructions 170) are selected. Some examples may select candidate branch instructions by detecting branch instructions that are difficult to predict. For example, branch instructions that cause frequent mispredictions may be considered difficult to predict and are therefore selected as candidate branch instructions by the flow tracing circuit. Frequent mispredictions can be monitored by storing values ​​indicating the misprediction rate associated with each branch instruction. In examples including BTB 42, confidence values ​​associated with different branch predictions may already be stored. The confidence values ​​can be used for one or more other functions, in which case the same values ​​can be reused to determine whether a branch instruction has low confidence (indicating a high misprediction rate) and is therefore difficult to predict. The flow tracing circuit 52 may determine whether the misprediction rate exceeds a threshold, in which case the branch instruction may be selected as a candidate branch instruction for generating program flow information.

[0103] Figure 9 A sequence of steps for allocating or updating the observed path of the program flow by the flow tracing circuit 52 is illustrated. At step 180, a branch misprediction is detected, and the actual path of the program flow is received, for example, from branch unit 24. At step 182, the misprediction rate associated with the mispredicted branch instruction is updated to indicate the occurrence of the misprediction. At step 184, it is determined whether the misprediction rate exceeds a threshold. If not, the flow tracing circuit 52 does not consider the branch instruction sufficiently difficult to predict. Therefore, at step 186, the mispredicted branch instruction is not allocated to the flow tracing circuit 52.

[0104] On the other hand, if the misprediction rate does indeed exceed the threshold, the flow tracing circuit 52 considers the branch instruction sufficiently difficult to predict. Therefore, at step 188, it is determined whether the branch instruction already exists (i.e., has been tracked by the flow tracing circuit 52). If not, the mispredicted branch instruction is selected as a new candidate branch instruction and assigned to the entry of the flow tracing circuit 52. Then, at step 192, the actual path of the program flow received in step 180 is input as one of the observed paths of the program flow.

[0105] Returning to step 188, if the mispredicted branch instruction already exists in the flow tracing circuit 52, then at step 194, it is determined whether the actual path of the program flow received in step 180 already exists in one of the observed paths. If not, then at step 192, the actual path of the program flow is added as a new observed path. However, if the actual path of the program flow already exists in one of the observed paths, then there is no need to update the program flow information, and at step 196, the actual path of the program flow is not added as a new observed path.

[0106] After the update process is complete, at step 198, it can be determined whether a mispredicted branch instruction is followed by an unconditional branch instruction after multiple conditional branch instructions corresponding to the maximum limit. If so, the program flow information entry may have information identifying the unconditional branch appended to that entry, such that the unconditional branch instruction is added to the observed path corresponding to the actual path of the program flow.

[0107] After the flow tracing circuit 52 has tracked the observed path of the candidate branch instruction, the program flow information can then be used to control the allocation of alternative path prediction to alternative prediction cache 46. Figure 10 The following sequence of steps illustrates how program flow information can be used by branch predictor 40. At step 200, it is determined whether the current branch instruction for which a prediction is being generated corresponds to a candidate branch instruction with a corresponding entry tracked by flow tracing circuitry 52. ​​If not, at step 202, branch predictor 40 generates a main path prediction without generating an alternative path prediction. If the current branch prediction does correspond to a candidate branch instruction tracked by flow tracing circuitry 52, at step 204, a main path prediction is generated based on the prediction entry. At step 206, another prediction entry (e.g., in the same set of a set-association TAGE table as previously described, but not matching the label and therefore not used to generate a main path prediction) is compared to an observed path represented by an entry from flow tracing circuitry 52 corresponding to a candidate branch instruction. If these two do not correspond, at step 208, no alternative path prediction is generated, and therefore, the alternative path prediction is not stored in the alternative prediction cache 46. If an unused prediction entry obtained from branch predictor 40 does indeed correspond to an observed path in the path being traced for a candidate branch instruction in the flow tracing circuit 52, then branch predictor 40 generates an alternative path prediction and stores the alternative path prediction in alternative prediction cache 46 for use by block skip circuit 48.

[0108] The following are a series of examples of how the alternative path prediction and block skip circuit 48 can generate a prediction recovery address in response to a refresh signal. These examples are based on a specific example where the program flow history update condition is satisfied when a predicted branch is adopted, but not for a predicted branch that is not adopted. It should be understood that other examples may use different program flow history update conditions, in which case the pattern of which branches share the same index value may differ. Figures 11A to 11G The pattern shown in the example.

[0109] Figure 11AThis example illustrates how different paths in a program flow can be predicted based on entries in the TAGE table that share the same index. In this example, BR1.1, BR1.2, and BR2.1 will share the same index value because the historical information of the indexes used to generate these branch lookups will exclude information about the most recently adopted branch (BR1 is excluded for BR1.1 and BR1.2, and BR2 is excluded for BR2.1 – note that BR1.1 must not be adopted to reach BR1.2, and therefore is not considered a most recently adopted branch when looking up information about BR1.2). Similarly, entries in branches BR1.1.1, BR1.1.2, and BR1.2.1 share the same index because their index hash excludes information related to the most recently adopted branch BR1.1 or BR1.2.

[0110] While assigning such entries to the same set may introduce additional stress on TAGE (since multiple paths map to the same set), it can be useful for probing alternative paths without requiring any additional TAGE lookups, as shown in the following examples.

[0111] Figure 11B An example is illustrated where branch predictor 40 generates a main path prediction for processing block (PB) 1. Branch instruction BR1 is predicted to be adopted, with its target address located in PB1.1. If BR1 is later resolved to be rejected, alternative path predictions for the program flow are further generated. Specifically, alternative paths for the program flow include rejecting BR2 and adopting BR3. Branch predictor 40 may further generate a prediction for BR1.1 before, for example, BR1 is evaluated by branch unit 24.

[0112] Alternative path predictions can be stored in association with other information (e.g., via tags) that allows block skip circuit 48 to use the correct alternative path prediction and restart instruction fetching upon refresh. For example, an alternative path prediction can be stored in association with one or more of the identifier of block PB1, the offset of BR1 within PB1, or an indication of what result of BR1 corresponds to an alternative direction of the alternative path prediction (i.e., accept (T) or reject (N)). Thus, in this example, an entry in the alternative path prediction cache 46 could indicate: [PB1; BR1_offset; reject; BR2 (reject); BR3 (accept)], to indicate that the alternative path applies when the branch in PB1 and offset BR1_offset is not accepted, and to indicate that the subsequent flow is predicted to include the rejected branch BR2, followed by the accepted branch BR3.

[0113] If a refresh signal indicating that the main path prediction of BR1 is incorrect (i.e., BR1 is not actually adopted) is received, the block skip circuit 48 can use the information about BR1 and the actual result (N) received from the branch unit 24 to look up the alternative prediction cache 46 to identify the alternative path prediction. The offset of BR1 and other alternative path information BR2 (N), BR3 (T) can be transmitted to the fetch stage 6 so that instruction fetching can start from the address after BR1 in PB1 and continue to fetch instructions of PB2 and PB3 until BR3 in PB3. At the same time, the block skip circuit 48 identifies the prediction recovery address based on the alternative path prediction. For example, the prediction recovery address can be identified as the target address of BR3, and the branch predictor 40 is controlled to start generating a prediction from that address. Therefore, if the prediction must be recovered from BR1, the fetch bubble that will appear can be avoided by recovering the prediction from the target of BR3 and fetching intermediate instructions based on the alternative path information in the cache.

[0114] Figure 11C An example is given where PB1 contains two branch instructions, BR1 and BR2. The main path prediction includes BR1 being accepted along with the target address in PB1.1. If BR1 is later resolved to be unacceptable, an alternative path prediction is further generated regarding the path of the program flow. Specifically, the alternative path for the program flow includes BR2 being accepted, with its target address located in PB2.1. As in the previous example, the alternative path prediction is stored in the alternative prediction cache 46.

[0115] In this example, both the primary path prediction and the alternative path prediction are expanded by generating further predictions for BR1.1, BR2.1, and BR2.2. For example, as previously stated regarding... Figure 4 As described, the set-associative memory structure can be looked up using an index independent of the most recently predicted branch instruction (i.e., BR1) that satisfies the program flow history update conditions, thereby hitting the prediction entry corresponding to each of BR1.1, BR2.1, and BR2.2 in a single lookup. The extended main path prediction is used to further control the instruction fetching process in fetch stage 6. The extended alternative path prediction is also stored in the alternative prediction cache 46, for example, as an extension of the same alternative prediction cache entries as previously stored.

[0116] As described above, alternative path predictions are stored in alternative prediction cache 46 along with various tagging information. For example, entries in alternative prediction cache 46 may indicate: [PB1; BR1_offset; not adopted; BR2 (adopted); BR2.1 (adopted)].

[0117] If a refresh signal indicating that the main path prediction for BR1 is incorrect is received, the block skip circuit 48 may, as described above, look up the alternative prediction cache 46 to identify the prediction recovery address and the sequence of instructions to be fetched before the prediction recovery point. For example, the prediction recovery address may be identified as the target address for BR2.1, and the branch predictor 40 may be controlled to begin generating predictions from that address.

[0118] Figure 11D Examples of the same Figure 11C A similar example, but in which the main path prediction instead includes: BR1 is not accepted. Therefore, the main path of the program flow continues to BR2, which is predicted to be accepted, with its destination address located in PB2.1. If BR1 is later resolved to be accepted, an alternative path prediction is generated for the program flow. Specifically, the alternative path for the program flow includes the destination address in PB1.1. As in the previous example, the alternative path prediction is stored in the alternative prediction cache 46.

[0119] In this example, both the primary path prediction and the alternative path prediction are expanded by generating further predictions for BR1.1, BR1.2, BR2.1, and BR2.2. The expanded primary path prediction predicts that BR2.1 will be adopted, and the alternative path prediction includes that BR1.1 will not be adopted and BR1.2 will be adopted.

[0120] As described above, alternative path predictions are stored in alternative prediction cache 46 along with various tagging information. In this example, entries in alternative prediction cache 46 may indicate: [PB1; BR1_offset; Accept; BR1.1 (Not Accept); BR1.2 (Accept)].

[0121] If a refresh signal indicating that the main path prediction of BR1 is incorrect is received, the block skip circuit 48 may, as described above, look up the alternative prediction cache 46 to identify the prediction recovery address and the instruction sequence to be fetched before the prediction recovery point. For example, the prediction recovery address may be identified as the target address of BR1.2, and the branch predictor 40 may be controlled to begin generating predictions from that address.

[0122] Figure 11EAn example is given where PB1 contains a polymorphic branch instruction BR2 in an alternative path of program flow. Specifically, the main path prediction includes: BR1 is accepted, and its target address is located in PB1.1. An alternative path prediction is generated if BR1 is not accepted, and then BR2 is encountered. The alternative path prediction then represents a polymorphic prediction with a specific target address in PB2.1. Both the main path prediction and the alternative path prediction are extended by generating further predictions about BR1.1, BR2.1, and BR2.2. The extended main path prediction predicts: BR1.1 will be accepted, and the alternative path prediction includes: BR2.1 is accepted.

[0123] In addition to the various tagging information described above, or as an alternative, alternative path predictions can be further stored in association with the target address identified in the polymorphic prediction. Thus, in this example, the entry in the alternative prediction cache 46 could indicate: [PB1; BR1_offset; not adopted; BR2 (PB2.1); BR2.1 (adopted)]. This distinguishes the alternative path predictions from other results associated with different target addresses in the polymorphic branch BR2.

[0124] If a refresh signal indicating that the main path prediction of BR1 is incorrect is received, the block skip circuit 48 may, as described above, search the alternative prediction cache 46 to identify the prediction recovery address and instruction fetch sequence. For example, the prediction recovery address may be identified as the target address of BR2.1, and the branch predictor 40 may be controlled to begin generating predictions from that address.

[0125] Figure 11F An example is given of an alternative path prediction that includes a polymorphic branch instruction with an intermediate branch instruction. Specifically, PB1 contains BR1 and BR2, where the main path prediction includes: BR1 is adopted, and its target address is located in PB1.1. The alternative path prediction generated when BR1 is not adopted includes: BR2 is adopted, where the target address is located in PB2.1, and PB2.1 further contains the polymorphic branch instruction BR2.1.

[0126] When generating the main path prediction for BR1.1, the alternative path can be expanded as described above to identify the target address PB2.1.1 (not illustrated) of the polymorphic branch instruction BR2.1. The alternative path prediction can then be stored in the alternative prediction cache 46 along with the various tagging information described above. Thus, in this example, the entries in the alternative prediction cache 46 may indicate: [PB1; BR1_offset; not adopted; BR2 (adopted); BR2.1 (PB2.1.1).

[0127] If a refresh signal indicating that the main path prediction of BR1 is incorrect is received, the block skip circuit 48 may, as described above, search the alternative prediction cache 46 to identify the prediction recovery address and instruction fetch sequence. For example, the prediction recovery address may be identified as the target address of BR2.1, and the branch predictor 40 may be controlled to begin generating predictions from that address.

[0128] Figure 11G An example of generating a main path prediction using a polymorphic branch instruction is illustrated. In this example, BR1 is unconditionally adopted, but can be targeted at a different address in PB1.1 or PB1.2. The main path prediction includes a target address of PB1.1. Therefore, an alternative path prediction can be generated if the main path prediction is incorrect (i.e., targeting PB1.2 instead).

[0129] In the above example, which includes the use of alternative direction marking for alternative path predictions, the directions in both the main path prediction and the alternative path prediction are the same, meaning that branches are adopted in both. Therefore, in order for the block skip circuit 48 to identify the alternative path prediction of BR1, the alternative path prediction can be further marked by the target address instead of by the alternative direction, or by the target address as a supplement to the alternative direction. For example, the prediction recovery address could indicate: [PB1; BR1_offset; PB1.2; BR1.2 (adopted)].

[0130] If a refresh signal indicating that the main path prediction of BR1 is incorrect is received, the block skip circuit 48 may, as described above, search the alternative prediction cache 46 to identify the prediction recovery address and instruction fetch sequence. For example, the prediction recovery address may be identified as the target address of BR1.2, and the branch predictor 40 may be controlled to begin generating predictions from that address.

[0131] Figure 11H An example of generating alternative path predictions based on multi-adoption entries is illustrated. Specifically, PB1 contains BR1, and the primary path prediction includes: BR1 is adopted, and its destination address is located in PB1.1. Alternative path predictions generated regarding BR1 not being adopted include: BR2 is not adopted, and BR3 is adopted. In this example, the prediction entry used to generate the prediction for BR3 is a multi-adoption entry. Therefore, as part of the same lookup (i.e., in BDP 44), it is further predicted that BR3.1 will be adopted.

[0132] In the same example, a prediction can be generated for BR2.1. BR2.1 is not included in the alternative path prediction because BR2 is predicted to be unacceptable; however, it should be understood that if BR2 is accepted, then BR2 and BR2.1 can be compressed into a multi-acceptance entry.

[0133] Alternative path predictions can be stored in alternative prediction cache 46 as described above, and may include additional fields to specify additional branch instructions that have been predicted due to the use of multi-adoption entries. In this example, entries in alternative prediction cache 46 may indicate: [PB1; BR1_offset; not adopted; BR2 (not adopted); BR3 (adopted); BR3.1 (adopted)].

[0134] If a refresh signal indicating that the main path prediction for BR1 is incorrect is received, the block skip circuit 48 may, as described above, search the alternative prediction cache 46 to identify the prediction recovery address and the instruction sequence to be fetched before the prediction recovery point. For example, the prediction recovery address may be identified as the target address for BR3.1, and the branch predictor 40 may be controlled to begin generating predictions from that address.

[0135] Figure 11I An example is shown where the main path prediction includes BR1 not being adopted and BR2 being adopted. An additional lookup can be used to extend the main path prediction to predict branch instructions BR2.1 and BR2.2 in PB2.1. If BR1 is later resolved to be adopted, an alternative path prediction is generated for the program flow. In this example, the alternative path prediction is generated based on multiple adoption entries indicating that both BR1 and BR1.1 will be adopted. Therefore, as described above, alternative paths for the program flow are identified in a single lookup.

[0136] As described above, alternative path predictions are stored in alternative prediction cache 46 along with various tagging information. In this example, an entry in alternative prediction cache 46 may indicate: [PB1; BR1_offset; adoption; BR1.1 (adoption)].

[0137] If a refresh signal indicating that the main path prediction of BR1 is incorrect is received, the block skip circuit 48 may, as described above, look up the alternative prediction cache 46 to identify the prediction recovery address and the instruction sequence to be fetched before the prediction recovery point. For example, the prediction recovery address may be identified as the target address of BR1.2, and the branch predictor 40 may be controlled to begin generating predictions from that address.

[0138] Figure 11JAn example is illustrated where a second lookup for a multi-adoption entry can be used to further extend alternative path predictions. In this example, the primary path prediction includes BR1 being adopted. Therefore, in the same lookup, alternative path predictions can be generated if BR1 is not adopted, thus encountering BR2 and BR3, which are then adopted. In another lookup, the alternative path predictions are extended by performing another lookup to generate predictions for BR2.1 and BR3.1, both of which are identified in the multi-adoption entry. Therefore, in the same entry, the alternative path predictions can be further extended using the predictions that BR2.1.1 and BR3.1.1 are also adopted.

[0139] As described above, alternative path predictions are stored in alternative prediction cache 46 along with various tagging information. In this example, entries in alternative prediction cache 46 may indicate: [PB1; BR1_offset; not adopted; BR2 (not adopted); BR3 (adopted); BR3.1 (adopted); BR3.1.1 (adopted)].

[0140] If a refresh signal indicating that the main path prediction of BR1 is incorrect is received, the block skip circuit 48 may, as described above, look up the alternative prediction cache 46 to identify the prediction recovery address and the sequence of instructions to be fetched before the prediction recovery point. For example, the prediction recovery address may be identified as the target address of BR3.1.1, and the branch predictor 40 may be controlled to begin generating predictions from that address.

[0141] Figure 12 An example embodiment of this technology incorporated into a prediction pipeline 300 is illustrated. The prediction pipeline 300 includes multiple stages, including control stages E1 and E2 and prediction stages P0, P1, and P2. The control stages and prediction stages may overlap, as shown in this example where E2 and P0 overlap. In this example, the prediction structure is incorporated into a TAGE predictor 304; however, it should be understood that other prediction structures may be used alternatively. The TAGE predictor 304 is configured to return any generated predictions during the prediction stages (particularly at the end of stage P1).

[0142] The control phase includes a global history register (GHR) 302, an example of the previously described history trace circuit 125, in which the history of the program flow can be stored for indexing into the TAGE predictor 304. Therefore, in control phase E1, the GHR outputs an index to look up the TAGE predictor 304 to generate a prediction about the input branch instruction. The TAGE predictor 304 returns the prediction direction of the main path prediction in phase P1, and then combines this prediction direction with the prediction target address retrieved from the BTB 306 in phase P2.

[0143] TAGE 304 further generates at least one alternative path prediction according to this technique. For program flow information 308 (e.g., from... Figure 7A , Figure 7B , Figure 8A and Figure 8B The path information represented by the previously described flow tracing circuit 52 is compared to identify whether the alternative path prediction corresponds to the observed path from the input branch instruction. If so, the alternative path prediction is output to be stored in the alternative prediction cache 310. In this example, the alternative prediction cache 310 is configured to return the alternative path prediction at control stage E1, which occurs earlier than prediction stage P1 in the prediction pipeline 300, at which time the main path prediction and the alternative path prediction will be available based on lookup TAGE 304.

[0144] In response to a refresh signal indicating an incorrect main path prediction, block skip circuit 312 generates skip information identifying the prediction recovery address based on the alternative prediction cache. This prediction recovery address is then input to a control stage prior to the prediction stage, causing TAGE 304 to be controlled to begin generating predictions for the instruction block identified by the prediction recovery address. The skip information is further passed to fetch stage 6, which is then enabled to fetch instructions sequentially according to the alternative path in the program flow up to the prediction recovery address, at which point a new main path prediction is expected to be available.

[0145] The concepts described herein can be specifically embodied in a system comprising at least one packaged chip. The previously described apparatus is implemented in this at least one packaged chip (either in a specific chip of the system or distributed across more than one packaged chip). The at least one packaged chip is assembled on a board along with at least one system component. Chip-containing products may include systems assembled on another board having at least one other product component. The system or chip-containing product may be assembled into a housing or onto a structural support (such as a frame or blade).

[0146] like Figure 13As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, wherein the devices described above are implemented on a single chip or distributed across two or more chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer may be provided as a semiconductor package, which includes a protective housing (e.g., made of metal, plastic, glass, or ceramic) housing the semiconductor device implementing the aforementioned devices, and connectors such as pads, solder balls, or pins for connecting the semiconductor device to the external environment. Where more than one chip 400 is provided, these chips may be provided as individual integrated circuits (provided as separate packages), or may be packaged by a semiconductor provider into a multi-chip semiconductor package (e.g., using interposers, or by using three-dimensional integration to provide a multi-layer chip product comprising two or more vertically stacked integrated circuit layers).

[0147] In some examples, a collection of chiplets (i.e., small modular chips with specific functionalities) may be referred to as a chip in itself. Chipslets may be individually packaged in semiconductor packages and / or packaged together with other chiplets in multi-chiplet semiconductor packages (e.g., using interpolators, or by using three-dimensional integration to provide multi-layer chiplet products comprising two or more vertically stacked integrated circuit layers).

[0148] One or more packaged chips 400 are assembled on a board 402 together with at least one system component 404 to provide system 406. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, such as plastic, glass, ceramic, or flexible substrate materials such as paper, plastic, or textile materials. At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include any one or more of the following: another packaged chip (e.g., supplied by a different manufacturer or manufactured at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0149] A chip-containing product 416 is manufactured, comprising a system 406 (including a board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product components 412 include one or more additional components that are not part of system 406. As an example, in a non-exhaustive list, one or more product components 412 may include user input / output devices such as keyboards, touchscreens, microphones, speakers, displays, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical motion; thermal control devices; another packaged chip; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 may be assembled on another board 414.

[0150] Plate 402 or another plate 414 may be disposed on or within the equipment housing or other structural support (e.g., frame or blade) to provide a product that can be disposed of by a user and / or intended for operational use by personnel or company.

[0151] System 406 or chip-containing product 416 can be at least one of the following: end-user product, machine, medical device, computing or telecommunications infrastructure product, or automated control system. For example, as a non-exhaustive list, a chip-containing product can be any of the following: telecommunications equipment, mobile phone, tablet computer, laptop computer, computer, server (e.g., rack server or blade server), infrastructure equipment, networking equipment, vehicle or other automotive product, industrial machine, consumer device, smart card, credit card, smart glasses, avionics equipment, robotic equipment, camera, television, smart TV, DVD player, set-top box, wearable device, home appliance, smart meter, medical device, heating / lighting control equipment, sensor, and / or control system for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0152] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0153] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0154] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0155] Computer-readable code may include a mixture of code representations for manufacturing apparatus, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0156] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductors, magnetic disks, or optical disks. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0157] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0158] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. An apparatus, the apparatus comprising: A prediction storage circuit is configured to store a plurality of prediction entries, each prediction entry indicating whether a corresponding branch instruction is predicted to be adopted or not adopted, wherein at least one prediction entry supports encoding of a multi-adoption entry, the multi-adoption entry indicating that the corresponding branch instruction and at least one subsequent branch instruction are each predicted to be adopted. and A predictive recovery circuit is configured to identify a predictive recovery address based on stored information depending on the multiple adoption entries in response to a refresh signal, the predictive recovery address being an address for which at least one prediction is to be generated after the refresh signal.

2. The apparatus of claim 1, further comprising a prediction circuit configured to perform a lookup in the prediction storage circuit to generate a prediction about a given branch instruction; and The prediction circuit is configured to generate the stored information in response to generating a prediction about a given branch instruction and to store the stored information in a prediction recovery cache.

3. The apparatus of claim 2, wherein the refresh signal indicates that the prediction is incorrect.

4. The apparatus of claim 2 or claim 3, wherein the given branch instruction is different from the corresponding branch instruction associated with the multiple adoption entry.

5. The apparatus according to any one of claims 2 to 4, wherein the prediction circuit is configured to generate the prediction and the stored information in a single lookup in the prediction storage circuit.

6. The apparatus according to any preceding claim, wherein the apparatus comprises: A history tracing circuit is configured to maintain the program flow history based on predicted branch instructions that satisfy the program flow history update conditions; The prediction storage circuitry includes at least one set-associative storage structure, wherein the at least one set-associative storage structure includes a set indexed by a portion of the program flow history, the portion of the program flow history being independent of information related to the most recent predicted branch instruction that satisfies the program flow history update conditions.

7. The apparatus of claim 6, wherein each set comprises two or more prediction entries, each of the two or more prediction entries being stored in association with a corresponding label value to be compared with a label, the label depending on an indication of a branch instruction and depending on a portion of the program flow history, the portion of the program flow history depending on the information associated with the most recent predicted branch instruction that satisfies the program flow history update conditions.

8. The apparatus of claim 7, wherein the two or more prediction entries support the encoding of the multi-adoption entries.

9. The apparatus of claim 7 or claim 8, wherein the indication of the branch instruction depends on the program counter value.

10. The apparatus according to any one of claims 6 to 9, wherein The at least one storage structure includes multiple set-associative storage structures, wherein The plurality of set-associative storage structures include at least a long-history storage structure associated with a long history length and a short-history storage structure associated with a short history length; and In response to a given program flow history, the branch prediction circuit is configured to identify one or more prediction entries associated with the given program flow history in either the long history storage structure or the short history storage structure.

11. The apparatus according to any preceding claim, wherein the apparatus comprises: A flow tracing circuit configured to maintain program flow information indicating one or more observed paths after a candidate branch instruction; and In the case of generating a prediction for the candidate branch instruction, the flow tracing circuit is configured to store the stored information in response to the multi-adoption entry indicating the program flow corresponding to one of the observed paths in the one or more observed paths.

12. The apparatus of claim 11, wherein the one or more observed paths include information identifying at least one subsequent branch instruction encountered after the candidate branch instruction.

13. The apparatus according to claim 11 or claim 12, wherein The flow tracing circuit is configured to impose a maximum limit on the number of subsequent conditional branch instructions in each of the one or more observed paths, wherein The flow tracing circuit is configured to support at least one observed path, the at least one observed path including a plurality of conditional branch instructions corresponding to the maximum limit, the plurality of conditional branch instructions being followed by at least one unconditional branch instruction.

14. The apparatus of any one of claims 11 to 13, wherein the flow tracing circuit is configured to select the candidate branch instruction in response to determining that the candidate branch instruction has a misprediction rate exceeding a threshold.

15. The apparatus of any one of claims 1 to 14, wherein the prediction storage circuit is configured to store a multi-adoption entry that designates an unconditional branch instruction as one of the at least one subsequent branch instructions.

16. The apparatus of any one of claims 1 to 15, wherein the prediction storage circuit is configured to store multiple adoption entries, the multiple adoption entries being designated as a conditional branch instruction predicted to be adopted and having an associated confidence value exceeding a threshold as a subsequent branch instruction in the at least one subsequent branch instruction.

17. A system comprising: The apparatus according to any one of claims 1 to 16, wherein the apparatus is implemented in at least one packaged chip; At least one system component; and plate, The at least one packaged chip and the at least one system component are assembled on the board.

18. A chip-containing product comprising the system of claim 17, wherein the system is assembled on another board together with at least one other product component.

19. A method comprising: Multiple prediction entries are stored, each indicating whether a corresponding branch instruction is predicted to be adopted or not adopted, wherein at least one prediction entry supports encoding of multiple adoption entries, the multiple adoption entries indicating that the corresponding branch instruction and at least one subsequent branch instruction are each predicted to be adopted; as well as In response to a refresh signal, a predicted recovery address is identified based on storage information depending on the multiple adoption entries, the predicted recovery address being an address for which at least one prediction is to be generated after the refresh signal.

20. A non-transitory computer-readable medium storing computer-readable code for manufacturing an apparatus, the apparatus comprising: A prediction storage circuit is configured to store a plurality of prediction entries, each prediction entry indicating whether a corresponding branch instruction is predicted to be adopted or not adopted, wherein at least one prediction entry supports encoding of a multi-adoption entry, the multi-adoption entry indicating that the corresponding branch instruction and at least one subsequent branch instruction are each predicted to be adopted. and A predictive recovery circuit is configured to identify a predictive recovery address based on stored information depending on the multiple adoption entries in response to a refresh signal, the predictive recovery address being an address for which at least one prediction is to be generated after the refresh signal.

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