A strong real-time data stream format permutation method based on NEON instruction set

Abstract

The application discloses a strong real-time data stream format conversion method based on a NEON instruction set and belongs to the technical field of embedded software.The application adopts a SIMD hardware unit provided by an ARM processor to perform parallel batch processing on to-be-converted data, realizes high-performance and strong real-time storage device communication, realizes optimization of a large number of repeated memory conversion operation operations in interactive data, can greatly improve conversion efficiency, shorten data conversion operation time, accelerate data processing speed as a whole, improve the interactive performance of the system to the peripheral device, and the conversion speed is increased by more than 60% compared with a traditional C language conversion mode.

Description

Technical Field

[0001] This invention relates to a real-time data stream format replacement method based on the NEON instruction set, belonging to the field of embedded software technology. Background Technology

[0002] In high-speed communication embedded systems, due to the large volume, high frequency, and complex data types of interactive data, traditional C language methods for handling byte order conversion between the sender and receiver data streams can no longer meet the performance requirements of strong real-time capabilities. Existing technical solutions use traditional C language loop traversal for conversion, which cannot be processed in batches, has a long conversion cycle, lacks strong real-time performance, and cannot meet the high-speed communication requirements between big-endian and little-endian storage peripherals. Summary of the Invention

[0003] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a strong real-time data stream format replacement method based on the NEON instruction set, which solves the problem of embedded software data stream byte order conversion but does not meet performance indicators.

[0004] The technical solution of this invention is: a method for replacing data stream formats with high real-time performance based on the NEON instruction set, comprising: Obtain the memory layout information of the communication instruction to be converted, wherein the communication instruction includes at least one element of a basic data type; Based on the data type of each element in the communication instruction relative to the order of arrangement in the instruction, calculate the offset of each element relative to the starting address of the instruction, and construct a two-dimensional array of offsets OFFSET[k][1]. k represents the type number of the basic data type in the communication instruction, 1=0 represents the offset of the element of this type relative to the starting address of the instruction, 1=1 represents the byte length corresponding to this data type, and 1=2 represents the number of elements of this type in the communication instruction. Iterate through the two-dimensional array of offsets, for each data type: If OFFSET[k][1] equals 1, then the element of this type is copied to the output buffer in its original byte order. If OFFSET[k][1] is greater than 1, then the corresponding SIMD reversal instruction is selected according to the byte length of the data type. Combined with the number of elements of the type, OFFSET[k][2], the elements are reversed in batch parallel mode, and the result is written to the output buffer.

[0005] Furthermore, the SIMD reversal instructions are vrev16, vrev32, or vrev64 series instructions from the ARM NEON instruction set, used to perform vectorization reversal operations on data of different byte lengths.

[0006] Furthermore, the vrev16, vrev32, or vrev64 series instructions include narrow instruction versions and wide instruction versions, and the narrow instruction version and wide instruction version are selected for batch processing according to the number of elements OFFSET[k][2].

[0007] Furthermore, the batch processing includes: If the number of elements meets the minimum processing multiple of the wide instruction, the wide instruction version shall be used first. If the number of elements does not meet the processing multiple of the wide instruction but meets the minimum processing multiple of the narrow instruction, then the narrow instruction version will be used for processing. The remaining elements are processed using a byte-by-byte loop.

[0008] Furthermore, the selection criteria for the SIMD reversal instruction are as follows: When OFFSET[k][1] is 2, the vrev16 series of instructions are selected; When OFFSET[k][1] is 4, the vrev32 series instructions are selected; When OFFSET[k][1] is 8, the vrev64 series of instructions are selected.

[0009] Furthermore, the memory layout of the communication instructions is forced to be single-byte aligned by compiler instructions.

[0010] Furthermore, the process of constructing the two-dimensional array of offsets includes: Iterate through each element in the communication command in sequence; Based on the data type and quantity of the elements, the offset of each type relative to the starting address of the instruction is calculated by summing them up. The offset, byte length, and number of elements for each element type are recorded in a two-dimensional array.

[0011] Furthermore, the communication instruction is in the form of a structure, with members consisting only of basic data types, or members consisting of both basic data types and complex data types; the output buffer is a memory area independent of the input instruction, used to store the converted communication instruction.

[0012] A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of a highly real-time data stream format replacement method based on the NEON instruction set.

[0013] A real-time data stream format replacement device based on the NEON instruction set includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the real-time data stream format replacement method based on the NEON instruction set.

[0014] The advantages of this invention compared to the prior art are: (1) This invention utilizes the SIMD hardware unit provided by the ARM processor to perform parallel batch processing of the data to be converted, thereby achieving high-performance, real-time storage device communication. It optimizes a large number of repetitive memory conversion operations in the interactive data, which can significantly improve conversion efficiency, shorten data conversion operation time, accelerate the overall data processing speed, and improve the system's interactive performance with the peripheral device. Actual measurements show that it is up to 60% faster than the traditional C language conversion method.

[0015] (2) This invention unifies the interactive data of the storage mode into a two-dimensional space, summarizing the element type offset, number of elements, and offset of the element's starting address relative to the instruction's starting address for all elements in the instruction. Information in the two-dimensional space is identified sequentially, and automatic identification and classification processing are performed on data segments requiring batch processing, achieving the optimal solution for conversion efficiency. Therefore, users of this invention can ignore the limitations of whether they are big-endian or small-endian, sender or receiver, and only need to define the two-dimensional space of the module to be converted. Attached Figure Description

[0016] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of a communication instruction with multiple data types. Figure 2 This is a diagram illustrating two common types of communication commands. Figure 3 This is a schematic diagram illustrating an example of converting communication commands into a summary table of two-dimensional address offsets. Figure 4 This is a schematic diagram of the output memory after batch processing based on the offset summary table. Detailed Implementation

[0017] To better understand the above technical solutions, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present invention, rather than limitations on the technical solutions of the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0018] The following description, in conjunction with the accompanying drawings, provides a more detailed explanation of a real-time data stream format replacement method based on the NEON instruction set provided by an embodiment of the present invention. Specific implementation methods may include: Obtain the memory layout information of the communication instruction to be converted, wherein the communication instruction includes at least one element of a basic data type; Based on the data type of each element in the communication instruction relative to the order of arrangement in the instruction, calculate the offset of each element relative to the starting address of the instruction, and construct a two-dimensional array of offsets OFFSET[k][1]. k represents the type number of the basic data type in the communication instruction, 1=0 represents the offset of the element of this type relative to the starting address of the instruction, 1=1 represents the byte length corresponding to this data type, and 1=2 represents the number of elements of this type in the communication instruction. Iterate through the two-dimensional array of offsets, for each data type: If OFFSET[k][1] equals 1, then the element of this type is copied to the output buffer in its original byte order. If OFFSET[k][1] is greater than 1, then the corresponding SIMD reordering instruction is selected based on the byte length of the data type. Combined with the number of elements of that type, OFFSET[k][2], the elements are batch-parallel-processed to reverse their byte order, and the result is written to the output buffer. Figure 4 .

[0019] In the solution provided by the embodiments of the present invention, the definitions of big-endian and little-endian are as follows: a) Little-Endian: The least significant byte is stored at the lowest memory address, and the most significant byte is stored at the highest memory address.

[0020] b) Big-Endian: The most significant byte is stored at the lowest memory address, and the least significant byte is stored at the highest memory address.

[0021] For example:

[0022] This invention provides a module for quickly exchanging data in endianness to achieve high-performance, real-time data interaction between communicating parties with different byte orders.

[0023] (communication) instructions Communication instructions refer to the rules and agreements that two entities must follow to complete communication or provide services. In this invention, communication instructions specifically refer to a mutually agreed-upon information body with specific meaning that both parties in endianness communication must follow. Such instructions typically consist of multiple data sets with specific meanings, and are appended with... Figure 1 One of the composition methods will be shown below, with reference to the appendix. Figure 1 The invention is explained in detail with examples.

[0024] SIMD-based neon acceleration instruction set ARM NEON technology accelerates multimedia and signal processing algorithms (such as video encoding / decoding, 2D / 3D graphics, games, audio and speech processing, image processing, telephony, and voice synthesis), with performance at least three times that of ARMv5 and twice that of ARMv6 SIMD. NEON technology is a 128-bit SIMD architecture extension for the ARM Cortex-A series processors, designed to provide flexible and powerful acceleration for applications.

[0025] The essence of NEON lies in its ability to perform parallel computations on multiple elements within a single NEON statement, thereby improving efficiency. It is a 64 / 128-bit hybrid SIMD architecture developed by ARM, capable of enhancing the performance of multimedia and signal processing applications.

[0026] Neon has 16 128-bit quad-word registers Q0-Q15 and 32 64-bit double-word registers D0-D31, with the two registers overlapping.

[0027] This invention primarily uses the neon reversal instruction vrev to perform batch processing of memory, thereby accelerating the process.

[0028] Define basic data types and their offsets

[0029] Endianness communication only changes the byte order of different data types, while the basic data types and their offsets are consistent and known to both parties. Since a single communication instruction consists of multiple basic data type elements, and both parties know this in advance, this invention addresses the uniformity and knowing of data types by combining the SIMD instruction set to perform batch conversion of memory byte order before interaction. The input of this invention is the communication instruction before a certain conversion, and the output is the target data buffer storing the converted data.

[0030] Data preprocessing: Summarizing all data offsets carried by a single communication protocol using two-dimensional space. Communication commands can typically be converted into two component types (see appendix) Figure 2(as shown) a) A structure composed of elements of multiple basic data types: a communication protocol composed only of basic data types. b) Structures composed of elements of multiple basic data types and elements of complex data types: In addition to basic data types, communication instructions also include other complex data types (such as unions, structures, and other complex data types composed of multiple basic data types).

[0031] Both types of composition are fundamentally composed of elements of the same or different, one or more basic data types, combined in different orders. Due to the prior knowledge of communication instructions, we can obtain in advance the type, number, and address offset of each independent element in the instruction based on the instruction's starting address. Therefore, the address offsets of all elements in a communication instruction can be uniformly defined as the following two-dimensional space: OFFSET[SUB_DATA_TYPE][SUB_DATA_ELEMENT] SUB_DATA_TYE: Represents the number of basic data types carried in this communication command; SUB_DATA_ELEMENT: Fixed length 3, representing the attributes carried by each individual element in this communication instruction, including: a) OFFSET[][0]: The offset of this element relative to the starting address of the instruction in the communication instruction; b) OFFSET[][1]: Offset of data type (fixed length such as 1, 2, 4, 8, etc.); c)OFFSET[][2]: The number of elements of this type in this communication instruction; To obtain uniform and accurate instruction offset data, the memory of the instruction to be converted must be set to single-byte alignment before using this conversion module. For ARM chips, the #pragma pack (1) instruction can be used to force single-byte alignment of the memory.

[0032] First, count the number of basic data types and the number of elements of each type in the instruction in sequence. Example of the counting method: The first element in the instruction, UINT8 ucNum

[1000] , contains 1000 elements of data type UINT8. The offset of UINT8 is U_S8_LEN, therefore the offset of this type relative to the starting address of memory is... .

[0033] The second element in the instruction, UINT16 usNum

[500] , contains 500 elements of data type UINT16. The offset of UINT16 is U_S16_LEN, therefore the offset of this type relative to the starting address of memory is... .

[0034] Then, based on the statistical results, a two-dimensional space is created for summarizing the offsets of this instruction element (see appendix). Figure 3 (As shown).

[0035] Category Batch Conversion: Parallel Batch Processing Technology Based on NEON Units in ARM Cores Given the characteristics of big-endian byte order, it is necessary to reverse the memory order of all elements corresponding to basic data types with offsets greater than 1 in the instruction. The method is as follows: Starting from 0, iterate through the values ​​of the second column of the two-dimensional offset space from OFFSET[][1] to SUB_DATA_TYPE to obtain the offset size of each basic data type; When the value of the second column OFFSET[k][1] is 1, it means that the current element type is single byte and no byte order conversion is required. That is, the copy starts from the offset starting address of the element of this type, the copy length is the number of elements of this type OFFSET[][2], and the copy is made to the output buffer starting address offset by OFFSET[k][0]. When the value OFFSET[k][1] in the second column is not 1, it indicates that the basic data type of the current element has an endianness issue. In this case, the SIMD acceleration instruction set is used to perform batch memory conversion. The conversion strategy depends on the current element type OFFSET[k][1] and the number of elements of that type OFFSET[k][2]. The processing result is copied to the position with an offset of OFFSET[k][0] from the starting address of the output buffer.

[0036] Parallel acceleration instructions are selected based on the element's basic type (OFFSET[k][1]). The selection strategies are shown in the table below:

[0037] The parallel acceleration range is selected based on the number of elements (OFFSET[k][2]). This invention can identify the number of basic data types OFFSET[k][2] and select the optimal processing method. When the length of OFFSET[k][1] is greater than 1, there are two data lengths that can be batch processed for a specific basic data type. These two minimum batch processing lengths are defined as MIN_1 and MIN_q, respectively. First, try batch processing of data that are multiples of MIN_q, and then process the remaining elements using a traditional C language loop. If OFFSET[k][2] is not a multiple of MIN_q, then try batch processing of data that are multiples of MIN_1, and process the remaining elements using a traditional C language loop. If it is not a multiple of MIN_1, then process the remaining elements using a traditional C language loop.

[0038] The MIN_1 and MIN_q values ​​corresponding to different data types are shown in the table below:

[0039] Example 1: The conversion operation of the module of the present invention for the example instructions is as follows: Assuming the instruction start address is 0x00000000, the start address of the target data buffer after conversion is 0x1000000 a) Starting from address (0x00000000+0), take 1000 bytes of length U_S8_LEN, do no processing, and copy them to address (0x1000000+0); b) From Starting from the address, take 8 bytes of length U_S16_LEN in sequence, and use the vrev16q_u8 neon acceleration instruction to perform batch conversion processing of 16 bytes each time, for a total of (1000 / 16=62) times.

[0040] 1000-62 remaining 16 = 8 bytes. The vrev16_u8 neon acceleration instruction is used to perform batch conversion of 8 bytes at a time, for a total of one operation. The processing results are then stored sequentially in (0x10000000+0 +U_S8_LEN). (1000) location; c) From (0x00000000+0 +U_S8_LEN) 1000 + U_S16_LEN Starting at address 1000, four bytes of length U_S32_LEN are sequentially retrieved. The vrev32q_u8 neon acceleration instruction is used to perform batch conversion of four bytes at a time, for a total of 1000 / 4 times. The processing results are then stored sequentially in (0x10000000+0 + U_S8_LEN). 1000 + U_S16_LEN (1000) location; d) From (0x00000000+0 +U_S8_LEN) 1000 + U_S16_LEN 1000 + U_S32_LEN Starting at address 1000, four bytes of length FL_LEN are sequentially retrieved. The vrev32q_u8 neon acceleration instruction is used to perform batch conversion of four bytes at a time, for a total of 1000 / 4 times. The processing results are then stored sequentially in (0x10000000+0 +U_S8_LEN). 1000 + U_S16_LEN 1000 + U_S32_LEN (1000) location; e) From (0x00000000+0 +U_S8_LEN 1000 + U_S16_LEN 1000 + U_S32_LEN 1000+FL_LEN Starting at address 1000, two bytes of length DB_LEN are sequentially retrieved. The vrev64q_u8 neon acceleration instruction is used to perform batch conversion of two bytes at a time, for a total of 1000 / 2 times. The processing results are then stored sequentially in (0x10000000+0 +U_S8_LEN). 1000 + U_S16_LEN 1000 + U_S32_LEN 1000+FL_LEN (1000) location; Actual testing showed that using the conversion module provided by this invention to process the instruction can reduce the conversion time to less than 0.2ms, which is more than 88% faster than the traditional C language loop traversal method.

[0041] Example 2: At a certain timing stage of Project XX, a chip using little-endian storage mode needs to send a UINT16 datasheet with width and height of [missing information] every 4.5 seconds via RS422 serial port. Image data of a size of [number] bytes is sent to a peripheral device with big-endian storage and a serial port baud rate of 921600 bps. Traditional C language uses a loop to reverse the byte order, which takes approximately 6.1ms in actual testing. Theoretically, the data transmission time is calculated to be [time missing]. The actual data transmission time is approximately 3.81945 seconds, but the actual data transmission time is often greater than the theoretical calculation. Traditional C language processing methods have too little margin and cannot meet the requirement of sending one image in 4.5 seconds. Performance requirements for images of a certain size (in bytes).

[0042] The following steps demonstrate how to use this invention to perform data processing: a) Define a summary table of two-dimensional spatial address offsets

[0043] (There is only one basic data type, UINT16, so SUB_TYPE_ is 1; this instruction has only one element, so the offset relative to the instruction start address is 0, and the offset of UINT16 is U_S16_LEN, which is 2. The size of this data type is...) ).

[0044] OFFSET[0][0]:0 OFFSET[0][1]:2 OFFSET[0][2]:

[0045] b) Determine the type of neon instruction to use based on the value of OFFSET[0][1]. OFFSET[0][1] is 2. Looking up the table, we know that the vrev16(q)_u8 neon acceleration instruction is selected for parallel accelerated conversion. c) Determine the parallel conversion strategy based on the value of OFFSET[0][2]. Looking up the table, we find that the values ​​of MIN_1 and MIN_q of type UINT16 are 8 and 16 respectively. We first use vrev16q_u8 to batch process multiples of MIN_q, because... Since it is divisible by 16, the parallel conversion strategy for this instruction is determined as follows: Execute... The vrev16q_u8 neon instruction converts 16 bytes at a time.

[0046] Actual testing using the conversion module provided by this invention can reduce the conversion time to less than 2ms, which is more than 66% faster than the traditional C language loop traversal method, meeting the requirement of sending 400 commands in 4.5 seconds. 400 Achieving high-speed, real-time image data transmission with a performance requirement of 2 bytes.

[0047] This invention provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the computer to perform... Figure 1 The method described.

[0048] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0049] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0050] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0051] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0052] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

[0053] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A method for replacing data stream formats with high real-time performance based on the NEON instruction set, characterized in that, include: Obtain the memory layout information of the communication instruction to be converted, wherein the communication instruction includes at least one element of a basic data type; Based on the data type of each element in the communication instruction relative to the order of arrangement in the instruction, calculate the offset of each element relative to the starting address of the instruction, and construct a two-dimensional array of offsets OFFSET[k][1]. k represents the type number of the basic data type in the communication instruction, 1=0 represents the offset of the element of this type relative to the starting address of the instruction, 1=1 represents the byte length corresponding to this data type, and 1=2 represents the number of elements of this type in the communication instruction. Iterate through the two-dimensional array of offsets, for each data type: If OFFSET[k][1] equals 1, then the element of this type is copied to the output buffer in its original byte order. If OFFSET[k][1] is greater than 1, then the corresponding SIMD reversal instruction is selected according to the byte length of the data type. Combined with the number of elements of the type, OFFSET[k][2], the elements are reversed in batch parallel mode, and the result is written to the output buffer.

2. The method for replacing the format of a high-real-time data stream based on the NEON instruction set according to claim 1, characterized in that, The SIMD reversal instructions are vrev16, vrev32, or vrev64 series instructions in the ARM NEON instruction set, used to perform vectorized reversal operations on data of different byte lengths.

3. The method for replacing the format of a high-real-time data stream based on the NEON instruction set according to claim 2, characterized in that, The vrev16, vrev32, or vrev64 series of instructions include narrow instruction versions and wide instruction versions. The narrow instruction version and the wide instruction version are selected for batch processing based on the number of elements OFFSET[k][2].

4. The method for replacing the format of a high-real-time data stream based on the NEON instruction set according to claim 3, characterized in that, The batch processing includes: If the number of elements meets the minimum processing multiple of the wide instruction, the wide instruction version shall be used first. If the number of elements does not meet the processing multiple of the wide instruction but meets the minimum processing multiple of the narrow instruction, then the narrow instruction version will be used for processing. The remaining elements are processed using a byte-by-byte loop.

5. A method for replacing the format of a high-real-time data stream based on the NEON instruction set according to claim 2, characterized in that, The selection criteria for the SIMD reverse instruction are as follows: When OFFSET[k][1] is 2, the vrev16 series of instructions are selected; When OFFSET[k][1] is 4, the vrev32 series instructions are selected; When OFFSET[k][1] is 8, the vrev64 series of instructions are selected.

6. The method for replacing the format of a high-real-time data stream based on the NEON instruction set according to claim 1, characterized in that, The memory layout of the communication instructions is forced to be single-byte aligned by compiler instructions.

7. The method for replacing the format of a high-real-time data stream based on the NEON instruction set according to claim 1, characterized in that, The process of constructing the two-dimensional array of offsets includes: Iterate through each element in the communication command in sequence; Based on the data type and quantity of the elements, the offset of each type relative to the starting address of the instruction is calculated by summing them up. The offset, byte length, and number of elements for each element type are recorded in a two-dimensional array.

8. The method for replacing the format of a high-real-time data stream based on the NEON instruction set according to claim 1, characterized in that, The communication instructions are in the form of a structure, with members consisting only of basic data types, or members consisting of both basic and complex data types; the output buffer is a memory area independent of the input instructions, used to store the converted communication instructions.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 8.

10. A real-time data stream format replacement device based on the NEON instruction set, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 8.

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