Method, device, computer device and medium for controlling cache coherence operation

Abstract

Embodiments of the present application provide a method and device for controlling cache consistency operation, computer equipment and medium, and relate to the technical field of data access, wherein the method comprises: a processor acquires consistency setting information from a condition bit register carried by a memory access instruction in response to the memory access instruction accessing a shared array variable; a compiler acquires a consistency condition variable in response to compiling a program, acquires a correspondence between the consistency condition variable and the shared array variable, allocates a condition bit register to the consistency condition variable, and uses the condition bit register of the consistency condition variable corresponding to each shared array variable as an input of the memory access instruction of each shared array variable; when the consistency setting information indicates that the cache consistency operation is started, the cache consistency operation is initiated; and when the consistency setting information indicates that the cache consistency operation is closed, the cache consistency operation is not initiated. The scheme can efficiently, conveniently and accurately control the cache consistency operation.

Description

Technical Field

[0001] This invention relates to the field of data access technology, and in particular to a method, apparatus, computer device, and medium for controlling cache consistency operations. Background Technology

[0002] Each processor core on a modern many-core CPU has a cache to improve data access speed and ensure ease of program writing. When running a parallel program, multiple processes or threads running on multiple processor cores may read and write data in the same shared memory region. To ensure the correct execution of parallel programs, cache coherence is required between different processor cores of the same CPU and between different CPUs within the same compute node. This ensures that the same data remains consistent across the private caches of multiple processor cores within the same compute node.

[0003] Currently, there are two main cache coherence protocols: bus-based snooping coherence protocols (snooping protocols) and directory-based coherence protocols (directory protocols). The number of processor cores on a single CPU has now exceeded one hundred, and will soon reach several hundred or even thousands, posing significant challenges to both snooping and directory protocols. Snooping protocols incur substantial overhead for conducting a single bus-based snooping operation across hundreds or thousands of cores; while directory protocols require maintaining increasingly large directories, and each directory entry struggles to accurately record the sharing status of a shared cache block across all processor cores.

[0004] To reduce the overhead of cache coherence on applications, existing technologies have proposed a method to reduce redundant cache coherence operations (Chinese Patent No.: 202410831240.X). This method uses cache coherence disable and enable instructions initiated by the current thread of the application to disable and enable the cache coherence protocol of the current processor core. This technology offers a significant opportunity to reduce redundant cache coherence operations, but it requires programmers or compilers to insert the cache coherence disable and enable instructions into the program code or assembly code, which can create difficulties and workload for programmers and optimizers in some cases.

[0005] To reduce the workload of inserting cache coherency control instructions, existing technology has proposed an optimization method in automatic thread-level parallelization (Chinese Patent No.: 2024113116029). This method allows programmers to easily specify shared and private variables between threads, enabling the compiler to generate an instruction stream that only enables cache coherency operations for accessing shared variables. Furthermore, this technology also proposes cache-coherent memory access instructions that initiate a cache coherency operation request under all circumstances.

[0006] However, typically, a shared variable only has a portion of its memory area shared between threads, while the rest can be considered private to each thread. Consider the two loops in Program 1 below, where the first loop calculates the value of array A, and the second loop uses A. Using existing techniques, the entire variable A needs to be treated as a shared variable; otherwise, a thread in the second loop might not be able to access the value of A calculated by other threads. For example, if two threads perform parallel computation with the same computational load, in the first loop, thread 0 will calculate k=0~49999, and thread 1 will calculate k=50000~99999; in the second loop, thread 0 will calculate k=1~49999, and thread 1 will calculate k=50000~99998. In the second loop, the calculation of B

[50000] will use the result of A

[49999] , therefore thread 1 in the second loop will use the result calculated by thread 0 in the first loop. However, we can also observe that thread 1 primarily uses its own calculated results in the second loop, meaning that most elements in array A are thread-private. In other words, most of the memory area in array A is thread-private, with only a small portion shared between threads.

[0007] Program 1:

[0008] When parallel optimizers need to enable consistency operations only for accessing a subset of elements of a shared variable (disabling consistency operations when accessing the remaining elements), one approach is to use cached consistent memory access instructions only for a portion of the loop iterations, and to use instructions that do not produce consistency operations for the remaining iterations. This programming approach has two drawbacks: firstly, it results in two types of instructions accessing the same variable in the binary code, causing binary code bloat; secondly, it requires parallel optimizers to write programs using embedded assembly language, leading to significant modifications to the original code and programming inconveniences. Summary of the Invention

[0009] In view of this, embodiments of the present invention provide a method for controlling cache consistency operations to solve the technical problems of code bloat and difficulty in modifying program code in implementing cache consistency operations in the prior art. The method includes: In response to a memory access instruction that accesses a shared array variable, the processor obtains consistency setting information from the condition bit register carried by the memory access instruction. In response to compiling a program, the compiler obtains consistency condition variables, obtains the correspondence between the consistency condition variables and the shared array variables, allocates condition bit registers for the consistency condition variables, and uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input of the memory access instruction for each shared array variable when generating a memory access instruction for each shared array variable. When the consistency setting information indicates that consistency operation is enabled, a cache consistency operation is initiated based on the execution of the memory access instruction; when the consistency setting information indicates that consistency operation is disabled, a cache consistency operation is not initiated based on the execution of the memory access instruction.

[0010] This invention also provides an apparatus for controlling cache consistency operations, to solve the technical problems of code bloat and difficulty in modifying program code in implementing cache consistency operations in the prior art. The apparatus includes: The information acquisition module is used by the processor to obtain consistency setting information from the condition bit register carried by the memory access instruction in response to the memory access instruction of the shared array variable. In response to compiling a program, the compiler obtains the consistency condition variable, obtains the correspondence between the consistency condition variable and the shared array variable, allocates the condition bit register for the consistency condition variable, and uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input of the memory access instruction of each shared array variable when generating the memory access instruction of each shared array variable. The operation control module is used to initiate a cache consistency operation based on the execution of the memory access instruction when the consistency setting information indicates that the consistency operation is enabled; and not to initiate a cache consistency operation based on the execution of the memory access instruction when the consistency setting information indicates that the consistency operation is disabled.

[0011] This invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the above-mentioned method for controlling cache coherency operations, thereby solving the technical problems of code bloat and difficulty in modifying program code in implementing cache coherency operations in the prior art.

[0012] This invention also provides a computer-readable storage medium storing a computer program that performs any of the above-described methods for controlling cache consistency operations, in order to solve the technical problems of code bloat and difficulty in modifying program code in implementing cache consistency operations in the prior art.

[0013] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of this specification can achieve include at least the following: When a compiler responds to the compilation of a program, it obtains a consistency condition variable, obtains the correspondence between the consistency condition variable and the shared array variable, allocates a condition bit register for the consistency condition variable, and when generating a memory access instruction for each shared array variable, uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input of the memory access instruction for each shared array variable. Therefore, when the processor responds to a memory access instruction for the shared array variable, it only needs to obtain consistency setting information from the condition bit register carried by the memory access instruction. When the consistency setting information indicates that consistency operation is enabled, a cache consistency operation can be initiated based on the execution of the memory access instruction; when the consistency setting information indicates that consistency operation is disabled, no cache consistency operation can be initiated based on the execution of the memory access instruction. This system enables the retrieval of consistency settings information using only a single memory access instruction and the condition bit register carried by that instruction. The system then controls whether consistency operations are enabled or disabled based on the intent expressed in the consistency settings information. This eliminates the need to insert multiple consistency control instructions into the program code or to use multiple control instructions to control different consistency operations separately. This avoids problems such as binary code bloat and difficulty in modifying program code, and achieves efficient, convenient, and precise control of cache consistency operations. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a flowchart of a method for controlling cache consistency operations provided by an embodiment of the present invention; Figure 2 This is a structural block diagram of a computer device provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of a device for controlling cache consistency operations provided in an embodiment of the present invention. Detailed Implementation

[0016] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0017] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In this embodiment of the invention, a method for controlling cache coherency operations is provided. This method for controlling cache coherency operations can run in a processor, such as... Figure 1 As shown, the method includes: Step S101: In response to a memory access instruction that accesses a shared array variable, the processor obtains consistency setting information from the condition bit register carried by the memory access instruction. In response to compiling a program, the compiler obtains consistency condition variables, obtains the correspondence between the consistency condition variables and the shared array variables, allocates condition bit registers for the consistency condition variables, and uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input of the memory access instruction for each shared array variable when generating a memory access instruction for each shared array variable. Step S102: When the consistency setting information indicates that consistency operation is enabled, a cache consistency operation is initiated based on the execution of the memory access instruction; when the consistency setting information indicates that consistency operation is disabled, a cache consistency operation is not initiated based on the execution of the memory access instruction.

[0019] Depend on Figure 1As shown in the flowchart, in this embodiment of the invention, when the compiler responds to the compilation of a program, it obtains a consistency condition variable, obtains (or presets) the correspondence between the consistency condition variable and the shared array variable, allocates a condition bit register for the consistency condition variable, and when generating a memory access instruction for each shared array variable, uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input of the memory access instruction for each shared array variable. Therefore, when the processor responds to a memory access instruction for a shared array variable, it only needs to obtain consistency setting information from the condition bit register carried by the memory access instruction. When the consistency setting information indicates that consistency operation is enabled, a cache consistency operation is initiated based on the execution of the memory access instruction; when the consistency setting information indicates that consistency operation is disabled, no cache consistency operation is initiated based on the execution of the memory access instruction. This system enables the retrieval of consistency settings information using only a single memory access instruction and the condition bit register carried by that instruction. The system then controls whether consistency operations are enabled or disabled based on the intent expressed in the consistency settings information. This eliminates the need to insert multiple consistency control instructions into the program code or to use multiple control instructions to control different consistency operations separately. This avoids problems such as binary code bloat and difficulty in modifying program code, and achieves efficient, convenient, and precise control of cache consistency operations.

[0020] In practice, when the compiler allocates the condition bit register of the consistency condition variable in response to the compilation of a program, it stores the consistency setting information of the shared array variable corresponding to the consistency condition variable in the condition bit register, so that the processor can obtain the consistency setting information of the shared array variable according to the condition bit register carried by the memory access instruction.

[0021] In practical implementation, there are at least two methods to mark whether a processor's memory access instruction initiates a cache coherence operation. One method is to mark it using the opcode of the memory access instruction, and the other is to mark it using the input operands of the memory access instruction. The first method, in its implementation, can keep the opcode of existing memory access instructions unchanged while adding the opcode of the memory access instruction that initiates the cache coherence operation. This expands the instruction's encoding space and requires extending the functionality of the instruction decoding unit. Furthermore, it can lead to two instructions accessing the same variable in the binary code, resulting in binary code bloat. The second method may increase the instruction encoding space or extend the functionality of the instruction decoding unit due to the increase in memory access instruction operands, but it does not cause binary code bloat, thus making it more advantageous than the first method. Currently, some processor instruction sets (such as ARM) already have the ability to use condition bit registers to control the actual execution of instructions. For such instruction sets, the implementation of the second method can be done without changing or expanding the instruction encoding space; for example, information about coherence settings can be added to the condition bit register.

[0022] In practical implementation, many processors have vector processing capabilities and vector instructions. A single vector read / write instruction can simultaneously read / write multiple data items. To achieve cache coherency operations that can simultaneously control the read / write of multiple data items, this embodiment proposes that each data item should have a coherency condition bit. That is, when the memory access instruction for accessing a shared array variable is a vector read / write instruction, the coherency setting information in the condition bit register carried by the vector read / write instruction includes multiple coherency condition bits. Since the vector read / write instruction needs to complete the read / write of multiple data items, each of the multiple coherency condition bits corresponds one-to-one with a specific data item. Each coherence condition bit indicates whether a coherency operation should be initiated for the read / write of the corresponding data item. For example, when a 512-bit wide vector instruction reads eight 64-bit wide double-precision floating-point data items, the coherency setting information should include eight coherence condition bits.

[0023] In practical implementation, for a single vector read / write instruction, there may be situations where the consistency condition bits differ among multiple data points. To address this, this embodiment proposes an effective solution: when the consistency setting information indicates that consistency operation is enabled, a cache consistency operation is initiated based on the execution of the memory access instruction, including: If there is a consistency condition bit in the condition bit register carried by the vector read / write instruction that indicates the initiation of a consistency operation, then a consistency operation is initiated for all reads / writes of the data to be completed by the vector read / write instruction.

[0024] In other words, for a vector read / write instruction, if one or more data items among the multiple data items to be read or written indicate that a cache coherence operation should be initiated, then the vector instruction should initiate a cache coherence operation for all of its data. This functionality is easy to implement and has minimal overhead because the multiple data items read / written by a vector instruction are usually in the same cache block or in adjacent memory address spaces. When all the data items of a vector read / write instruction are in the same cache block or within the smallest memory unit of the same coherence operation, the vector read / write instruction only needs to initiate one cache coherence operation. That is, the cache coherence operations corresponding to all the data items of a vector read / write instruction can be merged.

[0025] In practical implementation, cache coherence operations are initiated by default in modern CPUs, meaning the process of initiating cache coherence operations described above can be implemented using existing methods. When coherence settings indicate that coherence operations should be disabled, it is also easy to avoid initiating cache coherence operations. For example, for a listening protocol, bus-based listening can be avoided; and for a directory protocol, directory queries can be avoided, and there will be no corresponding cache block records in the directory.

[0026] In practice, since it cannot be guaranteed that the memory address range accessed by all memory access instructions is cache block aligned (cache block alignment means that the starting address of the memory address range is the starting address of the cache block, and the memory address range covers several complete cache blocks), there is a risk that cache consistency cannot be guaranteed. This makes it necessary for parallel optimizers or compilers to pay attention to and avoid such risks. For example, for program 1, given that the starting address of array A is located in the middle of the cache block (each cache block is 64 bytes in size) and each element occupies 8 bytes, then A

[49998] , A

[49999] , and A

[50000] are all in the same cache block. If two threads are used for parallel computation and the computation amount of each thread is the same, then in the first loop, thread 0 will calculate k=0~49999 and thread 1 will calculate k=50000~99999; in the second loop, thread 0 will calculate k=1~49999 and thread 1 will calculate k=50000~99998. Therefore, in the second loop, the calculation of B

[50000] will use the result of A

[49999] . For thread 0, if the read and write of A

[49998] does not initiate a cache coherence operation, but only the read and write of A

[49999] initiates a cache coherence operation, then the modification of A

[49998] by thread 0 will not notify thread 1 (the processor core in which it resides); if thread 1 modifies A

[50000] at the same time that thread 0 modifies A

[49998] , it will cause the contents of the same cache block to be inconsistent in the private caches of the two processor cores.

[0027] To improve the security of the above-mentioned methods for controlling cache coherency operations, and to avoid inconsistencies in the contents of the same cache block in the private caches of two processor cores, it should be ensured that memory access instructions accessing the same shared cache block use the same consistency, that is, all of them initiate cache coherency operations or none of them initiate cache coherency operations.

[0028] In practical implementation, for many instruction sets with condition register functionality, the allocation and use of condition registers are usually controlled by the compiler. The most common optimization is if-conversion, which transforms branch execution into condition-controlled execution. For example, the branching program in Program 2 can be converted into condition-controlled execution in Program 3, where both the third and fourth steps in Program 3 will be evaluated, but only one will succeed. In existing programming languages, conditional branching is a standard syntax, but there are no specific syntax rules for consistency condition bits. To implement the above method for controlling cache consistency operations by controlling the enabling or disabling of cache consistency operations based on consistency condition bits, this embodiment proposes a programming specification for consistency condition bits, for example... 1) Declaration and assignment of consistent condition variables. Consistent condition variables can essentially be logical variables (e.g., corresponding to the bool type in C / C++), so they can be declared and assigned values ​​in the same way as logical variables.

[0029] 2) Declaration of the correspondence between consistency condition variables and shared array variables. Current programming languages ​​do not have a standard for such declarations, thus requiring a new design. To minimize modifications to programming language standards and compilers, this embodiment proposes using compiler directives to declare the correspondence between consistency condition variables and shared array variables. For example, the declaration format of a compiler directive includes compiler directive markers (indicating subsequent compiler optimizations), relation declaration markers (declaring the correspondence between consistency condition variables and shared array variables), and variable tuples. One element of the variable tuple is a consistency condition variable, and the other element is several shared array variables. Therefore, one consistency condition variable can control memory access instructions for multiple shared array variables.

[0030] Program 4 provides an example. The logical type p1 defined in line 1 of Program 4 is actually a consistency condition variable; lines 3 and 11 both declare the correspondence between p1 and the shared array variable A. The compiler directives "CC_relation" and "(p1, (A))" represent variable pairs. Lines 4-6 and 12-14 are the code for allocating computational load among threads, while lines 8 and 18 are the code for assigning values ​​to consistency condition variables. This ensures that cache blocks containing shared data between threads will trigger cache consistency operations when accessed. In current conventional compiler optimizations, the variable p1 is not used after being assigned a value, so its computation might be optimized away as redundant calculation. However, the improved compiler records the correspondence between p1 and A, explicitly stating that p1 is the input for read / write instructions of A, thus preventing the computation of p1 from being optimized away. Since p1 will be used as a consistency condition bit, it should be recorded in the condition bit register. When generating read / write instructions for A, the compiler will use the condition bit register corresponding to p1 as the input for the read / write instructions of A.

[0031] Program 2:

[0032] Program 3:

[0033] Program 4:

[0034] In this embodiment, a computer device is provided, such as... Figure 2 As shown, it includes a memory 201, a processor 202, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the method for controlling cache coherency operations as described above.

[0035] Specifically, the computer device can be a computer terminal, a server, or a similar computing device.

[0036] In this embodiment, a computer-readable storage medium is provided, which stores a computer program that performs any of the above-described methods for controlling cache consistency operations.

[0037] Specifically, computer-readable storage media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media does not include transient media, such as modulated data signals and carrier waves.

[0038] Based on the same inventive concept, this invention also provides an apparatus for controlling cache coherency operations, as described in the following embodiments. Since the principle of the apparatus for controlling cache coherency operations is similar to that of the method for controlling cache coherency operations, the implementation of the apparatus for controlling cache coherency operations can refer to the implementation of the method for controlling cache coherency operations, and repeated details will not be elaborated further. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0039] Figure 3 This is a structural block diagram of a device for controlling cache coherency operations according to an embodiment of the present invention. This device for controlling cache coherency operations can be deployed or integrated into a processor, such as... Figure 3 As shown, it includes: The information acquisition module 301 is used by the processor to acquire consistency setting information from the condition bit register carried by the memory access instruction in response to the memory access instruction for accessing the shared array variable. In response to compiling a program, the compiler acquires the consistency condition variable, acquires the correspondence between the consistency condition variable and the shared array variable, allocates the condition bit register for the consistency condition variable, and uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input of the memory access instruction for each shared array variable when generating the memory access instruction for each shared array variable. The operation control module 302 is used to initiate a cache consistency operation based on the execution of the memory access instruction when the consistency setting information indicates that the consistency operation is enabled; and not to initiate a cache consistency operation based on the execution of the memory access instruction when the consistency setting information indicates that the consistency operation is disabled. In one embodiment, when the memory access instruction for accessing the shared array variable is a vector read / write instruction, the consistency setting information in the condition bit register carried by the vector read / write instruction includes multiple consistency condition bits. The vector read / write instruction needs to complete the read / write of multiple data, and the multiple consistency condition bits correspond one-to-one with the multiple data. Each consistency condition bit is used to indicate whether a consistency operation is initiated for the read / write of the corresponding data.

[0040] In one embodiment, the operation control module is configured to initiate a consistency operation for all reads / writes of the data to be completed by the vector read / write instruction if there is a consistency condition bit in the multiple consistency condition bits in the condition bit register carried by the vector read / write instruction that indicates the initiation of a consistency operation.

[0041] In one embodiment, the apparatus further includes a declaration module, used in a compiler to declare the correspondence between the consistency condition variable and the shared array variable using a compiler directive statement. The declaration format of the compiler directive statement includes a compiler directive flag, a relation declaration flag, and a variable tuple, wherein one element of the variable tuple is a consistency condition variable and the other element is a plurality of shared array variables.

[0042] In one embodiment, the consistency condition variable is a logical variable, and the consistency condition variable is declared and assigned values ​​in the manner of a logical variable.

[0043] The embodiments of this invention achieve the following technical effects: When the compiler responds to compiling a program, it obtains a consistency condition variable, acquires the correspondence between the consistency condition variable and shared array variables, allocates a condition bit register for the consistency condition variable, and uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input to the memory access instruction when generating memory access instructions for each shared array variable. Therefore, when the processor responds to memory access instructions for accessing shared array variables, it only needs to obtain consistency setting information from the condition bit register carried by the memory access instruction. When the consistency setting information indicates that consistency operation is enabled, a cache consistency operation is initiated based on the execution of the memory access instruction; when the consistency setting information indicates that consistency operation is disabled, no cache consistency operation is initiated based on the execution of the memory access instruction. This system enables the retrieval of consistency settings information using only a single memory access instruction and the condition bit register carried by that instruction. The system then controls whether consistency operations are enabled or disabled based on the intent expressed in the consistency settings information. This eliminates the need to insert multiple consistency control instructions into the program code or to use multiple control instructions to control different consistency operations separately. This avoids problems such as binary code bloat and difficulty in modifying program code, and achieves efficient, convenient, and precise control of cache consistency operations.

[0044] Obviously, those skilled in the art should understand that the modules or steps of the above-described embodiments of the present invention can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of the present invention are not limited to any particular hardware and software combination.

[0045] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for controlling cache consistency operations, characterized in that, include: In response to a memory access instruction that accesses a shared array variable, the processor obtains consistency setting information from the condition bit register carried by the memory access instruction. Specifically, when the compiler compiles a program, it obtains a consistency condition variable, obtains the correspondence between the consistency condition variable and the shared array variable, allocates a condition bit register for the consistency condition variable, and uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input of the memory access instruction for each shared array variable when generating a memory access instruction for each shared array variable. When the consistency setting information indicates that consistency operation is enabled, a cache consistency operation is initiated based on the execution of the memory access instruction; when the consistency setting information indicates that consistency operation is disabled, a cache consistency operation is not initiated based on the execution of the memory access instruction.

2. The method for controlling cache consistency operations as described in claim 1, characterized in that, When the memory access instruction for accessing a shared array variable is a vector read / write instruction, the consistency setting information in the condition bit register carried by the vector read / write instruction includes multiple consistency condition bits. The vector read / write instruction needs to complete the read / write of multiple data, and the multiple consistency condition bits correspond one-to-one with the multiple data. Each consistency condition bit is used to indicate whether a consistency operation is initiated for the read / write of the corresponding data.

3. The method for controlling cache consistency operations as described in claim 2, characterized in that, When the consistency setting information indicates that consistency operation is enabled, a cache consistency operation is initiated based on the execution of the memory access instruction, including: If there is a consistency condition bit in the condition bit register carried by the vector read / write instruction that indicates the initiation of a consistency operation, then a consistency operation is initiated for all reads / writes of the data to be completed by the vector read / write instruction.

4. The method for controlling cache consistency operation as described in any one of claims 1 to 3, characterized in that, Also includes: In the compiler, compiler directives are used to declare the correspondence between the consistency condition variables and the shared array variables. The declaration format of the compiler directive includes compiler directive markers, relation declaration markers, and variable tuples, wherein one element of the variable tuple is a consistency condition variable and the other element is several shared array variables.

5. The method for controlling cache consistency operation as described in any one of claims 1 to 3, characterized in that, The consistency condition variable is a logical variable, and it is declared and assigned values ​​in the manner of a logical variable.

6. An apparatus for controlling cache consistency operations, characterized in that, include: The information acquisition module is used by the processor to obtain consistency setting information from the condition bit register carried by the memory access instruction in response to the memory access instruction of the shared array variable. In response to compiling a program, the compiler obtains the consistency condition variable, obtains the correspondence between the consistency condition variable and the shared array variable, allocates the condition bit register for the consistency condition variable, and uses the condition bit register of the consistency condition variable corresponding to each shared array variable as the input of the memory access instruction of each shared array variable when generating the memory access instruction of each shared array variable. The operation control module is used to initiate a cache consistency operation based on the execution of the memory access instruction when the consistency setting information indicates that the consistency operation is enabled; and not to initiate a cache consistency operation based on the execution of the memory access instruction when the consistency setting information indicates that the consistency operation is disabled.

7. The apparatus for controlling cache consistency operations as described in claim 6, characterized in that, When the memory access instruction for accessing a shared array variable is a vector read / write instruction, the consistency setting information in the condition bit register carried by the vector read / write instruction includes multiple consistency condition bits. The vector read / write instruction needs to complete the read / write of multiple data, and the multiple consistency condition bits correspond one-to-one with the multiple data. Each consistency condition bit is used to indicate whether a consistency operation is initiated for the read / write of the corresponding data.

8. The apparatus for controlling cache consistency operations as described in claim 6, characterized in that, The operation control module is configured to initiate a consistency operation for all reads and writes of the data to be completed by the vector read / write instruction if there is a consistency condition bit in the multiple consistency condition bits in the condition bit register carried by the vector read / write instruction that indicates the initiation of a consistency operation.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method for controlling cache coherency operation as described in any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that performs the method for controlling cache coherency operation as claimed in any one of claims 1 to 5.

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