A chip failure analysis method and related device

Abstract

The application discloses a chip failure analysis method and related equipment, the method comprises the following steps: analyzing the multi-modal data of the chip to be analyzed to obtain an initial failure characterization set; based on the initial failure characterization set, strategy reasoning is performed in the pre-constructed failure knowledge graph to obtain the target analysis strategy of the chip to be analyzed at present, and then the new failure characterization is determined; the initial failure characterization set and the failure knowledge graph are updated based on the new failure characterization, and the strategy reasoning step is iteratively executed until the preset convergence condition is met; when the preset convergence condition is met, the probability values of the failure mode and the root cause are calculated based on all the failure characterizations in the updated failure characterization set; based on the probability values and the updated failure knowledge graph, reverse root cause reasoning is performed to obtain the root cause of the failure of the chip to be analyzed. The application can dynamically adjust the analysis strategy according to the actual failure characterization of the chip, and improves the efficiency and accuracy of chip failure analysis, and can be widely applied in the field of chip analysis technology.

Description

Technical Field

[0001] This application relates to the field of chip analysis technology, and in particular to a chip failure analysis method and related equipment. Background Technology

[0002] As semiconductor process nodes continue to shrink, the structure of integrated circuits becomes increasingly complex, with significantly increased interlayer interconnects and device density. During manufacturing, packaging, and application, even minor process deviations, environmental stresses, or design defects can lead to chip failure. Chip failure analysis is a crucial step in ensuring product yield and reliability.

[0003] However, existing chip failure analysis processes generally employ a fixed analysis workflow. Regardless of the differences in chip failure manifestations or failure types, tests and analyses must be carried out sequentially according to preset steps, making it impossible to dynamically adjust the analysis strategy based on the actual failure characteristics of the chip. Furthermore, the analysis process relies excessively on the personal experience of technical personnel. From determining the direction of failure and selecting analysis strategies to inferring the root cause, all rely on the accumulation of historical cases and subjective judgment by technical personnel. This prolongs the failure analysis cycle, makes it difficult to accurately locate the root cause of failure, and may even lead to misjudgment of the root cause, affecting the efficiency and accuracy of chip failure analysis. Summary of the Invention

[0004] The main objective of this application is to propose a chip failure analysis method that can dynamically adjust the analysis strategy based on the actual failure characteristics of the chip, thereby improving the efficiency and accuracy of chip failure analysis.

[0005] To achieve the above objectives, one aspect of this application proposes a chip failure analysis method, including: Acquire multimodal data of the chip to be analyzed, and analyze the multimodal data to obtain an initial failure characterization set; Based on the initial failure characterization set, strategy reasoning is performed in the pre-constructed failure knowledge graph to obtain the current target analysis strategy of the chip to be analyzed. The pre-constructed failure knowledge graph is used to characterize the multi-level correlation between failure characterization, failure mode, analysis strategy, physical structure and root cause of historical analysis chips. New failure characteristics are determined based on the aforementioned target analysis strategy; Based on the new failure representation, update the initial failure representation set and the failure knowledge graph, and iteratively execute the policy reasoning steps until the preset convergence condition is met; Under the condition that the preset convergence condition is met, the probability values ​​of failure modes and root causes are calculated by using a preset probability model based on all failure representations in the updated failure representation set. Based on the probability value and the updated failure knowledge graph, reverse root cause reasoning is performed on the chip to be analyzed to obtain the root cause of the chip failure.

[0006] In some embodiments, the multimodal data includes electrical test data, hotspot distribution data, and image data; The analysis of the multimodal data yields an initial failure characterization set, including: Identify abnormal patterns in the electrical test data; Defect detection is performed on the chip to be analyzed based on the image data to obtain defect information; Based on the local hotspot data in the hotspot distribution data, determine the correspondence between the local hotspot data and the circuit layout; The abnormal mode, the defect information, and the corresponding relationship are used as initial failure characteristics to obtain the initial failure characteristic set of the chip to be analyzed.

[0007] In some embodiments, the step of constructing the failure knowledge graph includes: Acquire unstructured text data related to chip failure analysis; Identify entities in the unstructured text data and the relationships between entities, wherein the entities include at least one of failure characterization, failure mode, analysis strategy, physical structure, or root cause; By treating the entities as nodes and the relationships between the entities as paths between nodes, a failure knowledge graph is constructed.

[0008] In some embodiments, the step of performing strategy reasoning based on the initial failure representation set in a pre-constructed failure knowledge graph to obtain the current target analysis strategy for the chip to be analyzed includes: The initial failure characterization set and the analysis strategy already executed by the chip to be analyzed are taken as the current analysis state; Based on the pre-constructed failure knowledge graph, the analysis strategies that conform to the current analysis state are selected as candidate analysis strategies. The current analysis state is mapped to the corresponding node in the failure knowledge graph, and the information of the node in the failure knowledge graph is aggregated using a graph neural network model to generate a global state vector representing the current analysis state. Based on the global state vector, calculate the expected reward value obtained by executing each of the candidate analysis strategies; Based on the expected reward value, the current target analysis strategy for the chip to be analyzed is determined from a plurality of candidate analysis strategies.

[0009] In some embodiments, determining new failure characteristics based on the target analysis strategy includes: Based on the target analysis strategy, new multimodal data of the chip to be analyzed are determined; The new multimodal data is reanalyzed to obtain new failure characteristics.

[0010] In some embodiments, the step of calculating the probability values ​​of failure modes and root causes based on all failure representations in the updated failure representation set using a preset probability model includes: All failure representations in the updated failure representation set are used as independent or related evidence for different failure modes and root cause hypotheses, and the independent or related evidence is input into a preset probability model. The preset probability model performs accumulation, conflict detection, and normalization fusion processing on the independent or related evidence. Based on the fusion of accumulation, conflict detection, and normalization, the probability values ​​of the failure modes and root causes are calculated.

[0011] In some embodiments, the step of performing reverse root cause reasoning on the chip to be analyzed based on the probability value and the updated failure knowledge graph to obtain the root cause of the failure of the chip to be analyzed includes: In the updated failure knowledge graph, failure modes with a probability value greater than a preset threshold are selected as candidate failure mode nodes. Obtain the physical structural characteristics corresponding to the updated failure characterization set, and determine the corresponding physical structural nodes based on the physical structural characteristics; Starting from the candidate failure mode nodes and physical structure nodes, a reverse traversal is performed along the associated paths in the updated failure knowledge graph to obtain the upstream root cause node set. Based on the path weight of the associated path and the probability value, each root cause node in the upstream root cause node set is scored to obtain a scoring result; Based on the scoring results, the root cause of the failure of the chip to be analyzed is obtained.

[0012] To achieve the above objectives, another aspect of this application provides a chip failure analysis apparatus, the apparatus comprising: The data analysis module is used to acquire multimodal data of the chip to be analyzed and to analyze the multimodal data to obtain an initial failure characterization set. The target analysis strategy module is used to perform strategy reasoning in a pre-constructed failure knowledge graph based on the initial failure characterization set to obtain the current target analysis strategy of the chip to be analyzed. The pre-constructed failure knowledge graph is used to characterize the multi-level correlation between failure characterization, failure mode, analysis strategy, physical structure and root cause of historical analysis chips. The new failure characterization determination module is used to determine new failure characterizations based on the target analysis strategy. The inference iterative execution module is used to update the initial failure representation set and the failure knowledge graph based on the new failure representation, and iteratively execute the policy inference steps until a preset convergence condition is met; The probability value calculation module is used to calculate the probability values ​​of failure modes and root causes based on all failure representations in the updated failure representation set and a preset probability model, provided that the preset convergence conditions are met. The root cause reasoning module is used to perform reverse root cause reasoning on the chip to be analyzed based on the probability value and the updated failure knowledge graph to obtain the root cause of the failure of the chip to be analyzed.

[0013] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described above.

[0014] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods described above.

[0015] This application also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the aforementioned method.

[0016] The embodiments of this application include at least the following beneficial effects: This application provides a chip failure analysis method. The method first acquires multimodal data of the chip to be analyzed, analyzes the multimodal data to obtain a failure characterization set, and based on the initial failure characterization, performs strategy reasoning in a pre-constructed failure knowledge graph to obtain the current target analysis strategy for the failed chip. The pre-constructed failure knowledge graph is used to characterize the multi-level relationships between failure characterizations, failure modes, analysis strategies, physical structures, and root causes of historically analyzed chips. Based on the currently acquired failure characterizations, the optimal target analysis strategy for the next analysis step can be dynamically generated through reasoning in the failure knowledge graph, reducing redundant testing and blind trial and error, and improving the efficiency of the failure analysis process. Secondly, based on the target analysis strategy, new failure characterizations are determined, and based on the new failure characterizations, the failure characterization set and the failure knowledge graph are updated. The strategy reasoning steps are iteratively executed until a preset convergence condition is met. When the preset convergence condition is met, based on all failure characterizations in the updated failure characterization set, the probability values ​​of the failure mode and root cause are calculated using a preset probability model. Root cause reasoning is performed on the chip under analysis based on probability values ​​and the updated failure knowledge graph to obtain the root cause of the chip failure. By calculating the probability values ​​of the characteristic failure modes and root causes corresponding to failures under different modal data, and performing reverse root cause reasoning on the failure knowledge graph based on these probability values, the failure root cause conclusions obtained by reasoning are more objective, accurate and reliable, thus improving the accuracy and efficiency of chip failure analysis. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an implementation environment provided in an embodiment of this application; Figure 2 This is a flowchart of a chip failure analysis method provided in an embodiment of this application; Figure 3 This is a flowchart provided in an embodiment of the present application for analyzing multimodal data to obtain an initial failure characterization set; Figure 4 This is a flowchart of strategy reasoning in a pre-built failure knowledge graph provided in an embodiment of this application; Figure 5 This is a flowchart illustrating the calculation of the probability values ​​of failure modes and root causes provided in the embodiments of this application; Figure 6 This is a flowchart of reverse root cause reasoning for the chip to be analyzed, provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a chip failure analysis device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] It is understood that the terms "first," "second," "third," "fourth," etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] Current chip failure analysis processes generally employ a fixed analysis workflow. Regardless of the differences in chip failure manifestations or failure types, tests and analyses must be carried out sequentially according to preset steps, making it impossible to dynamically adjust the analysis strategy based on the actual failure characteristics of the chip. Furthermore, the analysis process relies excessively on the personal experience of technical personnel. From determining the failure direction and selecting analysis strategies to inferring the root cause, all rely on the accumulation of historical cases and subjective judgment by technical personnel. This prolongs the failure analysis cycle, makes it difficult to accurately locate the root cause of the failure, and may even lead to misjudgment of the root cause, affecting the efficiency and accuracy of chip failure analysis.

[0023] In view of this, this application provides a chip failure analysis method and related equipment. The method first acquires multimodal data of the chip to be analyzed, analyzes the multimodal data to obtain a failure characterization set, and then performs strategy reasoning in a pre-constructed failure knowledge graph based on the initial failure characterizations to obtain the current target analysis strategy for the failed chip. The pre-constructed failure knowledge graph is used to characterize the multi-level relationships between failure characterizations, failure modes, analysis strategies, physical structures, and root causes of historically analyzed chips. Based on the currently acquired failure characterizations, the optimal target analysis strategy for the next analysis step can be dynamically generated through reasoning in the failure knowledge graph, reducing redundant testing and blind trial and error, and improving the efficiency of the failure analysis process. Secondly, based on the target analysis strategy, new failure characterizations are determined, and based on these new failure characterizations, the failure characterization set and the failure knowledge graph are updated. The strategy reasoning steps are iteratively executed until a preset convergence condition is met. When the preset convergence condition is met, based on all failure characterizations in the updated failure characterization set, the probability values ​​of the failure mode and root cause are calculated using a preset probability model. Root cause reasoning is performed on the chip under analysis based on probability values ​​and the updated failure knowledge graph to obtain the root cause of the chip failure. By calculating the probability values ​​of the characteristic failure modes and root causes corresponding to failures under different modal data, and performing reverse root cause reasoning on the failure knowledge graph based on these probability values, the failure root cause conclusions obtained by reasoning are more objective, accurate and reliable, thus improving the accuracy and efficiency of chip failure analysis.

[0024] The chip failure analysis method provided in this application relates to the field of chip analysis technology. The chip failure analysis method provided in this application can be applied to a terminal, a server, or software running on a terminal or server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or in-vehicle terminal, but is not limited to these. The server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network. The software can be an application implementing the chip failure analysis method, but is not limited to the above forms.

[0025] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0026] like Figure 1 The diagram shown is a schematic representation of an implementation environment provided in an embodiment of this application. (Refer to...) Figure 1 The implementation environment includes at least one terminal 102 and a server 101. The terminal 102 and the server 101 can be connected via a network, either wirelessly or via a wired connection, to complete data transmission and exchange.

[0027] Server 101 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms.

[0028] Additionally, server 101 can also be a node server in a blockchain network. Blockchain is a novel application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and encryption algorithms.

[0029] Terminal 102 can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, etc. It can also be a vehicle-mounted terminal of the various device types described above, but is not limited to these. Terminal 102 and server 101 can be directly or indirectly connected via wired or wireless communication, and this embodiment does not impose any limitations.

[0030] For example, based on Figure 1 The implementation environment shown in this application embodiment provides a chip failure analysis method. The following description uses the application of this chip failure analysis method in server 101 as an example. It can be understood that this method can also be applied to terminal 102.

[0031] Reference Figure 2 , Figure 2 The flowchart illustrates a chip failure analysis method for servers provided in this application embodiment. The execution subject of this method can be any of the aforementioned computer devices (including servers or terminals). (Refer to...) Figure 2 The method may include the following steps: S100: Acquire multimodal data of the chip to be analyzed, and analyze the multimodal data to obtain an initial failure characterization set.

[0032] The multimodal data includes electrical test data, hotspot distribution data, and image data. Embodiments of this application can acquire multimodal data related to the chip under analysis through a multi-source heterogeneous data acquisition interface. Further, the electrical test data includes DC / AC I... Data includes V-curves, S-parameters (scattering parameters), time-series waveforms, and ATE (Automatic Test Equipment) test results; image data includes microscopic images acquired from optical microscopes, SEM (Scanning Electron Microscope), FIB (Focused Ion Beam) cross-sections, and EMMI (Eye Microscope) light emission. Hotspot distribution data includes hotspot distribution data generated by infrared thermal imaging, laser-induced resistance anomaly testing, and eye microscopy.

[0033] For example, Figure 3 This is a flowchart illustrating the analysis of multimodal data to obtain an initial failure characterization set, provided in an embodiment of this application. For example... Figure 3 As shown, the steps for analyzing multimodal data to obtain the initial failure characterization set specifically include S110-S140: S110, Identify abnormal patterns in the electrical test data.

[0034] For example, embodiments of this application employ TCN, RNN, LSTM, or attention models to identify abnormal patterns such as "suspected short circuit," "suspected dielectric breakdown," and "suspected Vth drift." Specifically, the raw signals of the electrical test data are first subjected to in-depth preprocessing. The preprocessing includes: in a semiconductor testing environment, since the IV curve or IDDQ (static power supply current) time series current often spans multiple orders of magnitude and is accompanied by system noise, logarithmic scaling or normalization algorithms are used to map the data to a unified value range, and the continuous electrical current data is divided into discrete time series samples using sliding window technology. To extract hidden feature patterns, an appropriate model architecture should be selected based on the temporal characteristics of the time series samples. For example, LSTM or RNN models can be used. These models, through their unique gating mechanisms, can capture the medium- to long-term trend drift of electrical test data signals, effectively identifying parameter degradation caused by device aging. If a TCN model is used, the TCN (Temporal Convolutional Network) utilizes its dilated causal convolution structure to accurately capture local transient spikes in high-frequency sampled data while maintaining parallel computing efficiency. Furthermore, an attention mechanism is introduced, which, by calculating the correlation weights between points within the sequence, can identify logical correlations across time periods, thereby locking in subtle dynamic leakage patterns during complex test vector switching. The identification of abnormal patterns relies on an unsupervised learning framework based on an autoencoder structure. During the identification process, the model is trained to reconstruct normal electrical reference signals with extremely high accuracy. When the data to be tested is input, the model attempts to "compress and restore" it. At this time, the residual (i.e., reconstruction error) between the input sequence and the reconstructed sequence is calculated. For normal samples that conform to known physical laws, the reconstruction error is extremely low. However, once abnormal disturbances such as soft breakdown, metal bridging, or logical conflicts occur in the electrical data, the model will be unable to accurately reconstruct the feature, resulting in a surge in reconstruction error. Potential abnormal patterns can be automatically identified by setting a dynamic threshold. S120. Defect detection is performed on the chip to be analyzed based on the image data to obtain defect information.

[0035] For example, in this embodiment of the application, object detection and segmentation networks are used to accurately locate and classify defects such as cracks, voids, bridging, dielectric breakdown holes, corrosion zones, and abnormal solder joints in images such as SEM / FIB / EMMI, and output defect information, which includes image coordinates, physical coordinates, hierarchical structure, and confidence level. In some embodiments, object detection methods such as YOLO can be used to obtain bounding boxes of targets in the image data, providing labels and confidence levels for points of interest in the image data, thereby obtaining the defect type and reliability measurement, which facilitates subsequent analysis.

[0036] S130. Based on the local hotspot data in the hotspot distribution data, determine the correspondence between the local hotspot data and the circuit layout.

[0037] In this context, local hotspot data refers to high-temperature points within the hotspot distribution data. Since infrared imaging hotspot distribution data consists of multiple hotspots and their diffusion areas, it's necessary to segment the hotspot regions. This requires cutting the hotspot regions within the hotspot distribution data and mapping them to their original circuit layout locations, thus achieving a correspondence between the hotspot data and the actual heat-generating areas. For example, in this embodiment, deep learning and clustering analysis are used to identify local hotspots and their correspondence with circuit layout areas in infrared thermal imaging hotspot distribution data or light emission images.

[0038] S140. The abnormal mode, the defect information and the correspondence are used as initial failure characteristics to obtain the initial failure characteristic set of the chip to be analyzed.

[0039] For example, in this embodiment, the initial failure characterization includes characterization type, spatial location, hierarchical structure, numerical attributes, and pattern labels, and is output in a structured manner. This embodiment uses deep learning for automatic defect identification to obtain the failure characterization, improving the efficiency and accuracy of defect detection. S200. Based on the initial failure characterization set, strategy reasoning is performed in the pre-constructed failure knowledge graph to obtain the current target analysis strategy of the chip to be analyzed. The pre-constructed failure knowledge graph is used to characterize the multi-level correlation between failure characterization, failure mode, analysis strategy, physical structure and root cause of historical analysis chips.

[0040] Failure modes refer to the forms or phenomena of malfunctions exhibited by a product or system. At the electrical level, failure modes manifest as anomalies in voltage or current sequences, such as open circuits, short circuits, leakage, high quiescent current (High IDDQ), and signal timing drift. These modes are the core objects identified by models such as TCN and LSTM in electrical test data. At the physical level, failure modes translate into visible structural damage, including chip packaging cracks, delamination, electromigration voids in metal lines, solder joint corrosion, and atomic-scale lattice dislocations or metal bridging.

[0041] The failure knowledge graph in this application embodiment is based on entities. relation The entity knowledge graph is organized in the form of triplets. Core entities encompass failure characteristics, failure modes, physical structures, analysis strategies, root causes, and FMEA (Failure Mode and Effects Analysis) entries. Relationships characterize semantic connections such as "a certain characteristic indicates a certain failure mode," "a typical root cause of a certain mode is a certain process defect," "a detectable relationship between a certain characteristic and a certain analysis method," "a certain structure is prone to a certain failure mode," and "a certain mode / root cause corresponds to a certain FMEA entry." For example, the steps for constructing a failure knowledge graph in this embodiment include: acquiring unstructured text data related to chip failure analysis; identifying entities in the unstructured text data and the relationships between entities, wherein entities include at least one of failure characteristics, failure modes, analysis strategies, physical structures, or root causes; and constructing the failure knowledge graph by using entities as nodes and the relationships between entities as paths between nodes.

[0042] For example, this application embodiment uses a Transformer semantic model to perform entity recognition and relation extraction on unstructured text such as historical failure analysis reports, FMEA documents, and product specifications of historical analysis chips. The steps include: for the numerous professional abbreviations and compound terms (such as IDDQ, Vth, OBIRCH, etc.) present in the semiconductor failure analysis field, the semantic model uses the BPE algorithm to segment the original text into a token sequence. Combining this with domain knowledge accumulated during the pre-training phase, each token is mapped to a high-dimensional vector (Embedding) containing rich semantic information, laying a digital foundation for subsequent feature extraction. Then, a multi-head self-attention mechanism begins to function at the encoding layer, capable of traversing long text spans and automatically calculating the association weights between each word and other words in the text. This mechanism enables the semantic model to no longer understand words in isolation but to capture complex contextual information. For example, when analyzing a long sentence, the semantic model can identify a strong semantic coupling between "electrical leakage" mentioned at the beginning of the sentence and "metal residue" appearing at the end. This overcomes the limitations of traditional natural language processing tools in handling long and complex sentences and ambiguities in professional contexts, accurately understanding the implicit connection between failure phenomena and inducing factors. The relation extraction stage further determines the logical connections between entities based on entity recognition, constructing structured triples. The semantic model extracts semantic features between two entities and uses a relation classifier to determine whether there are logical relationships such as causality, inclusion, detection, or triggering between them. For example, it can infer from the text that "particulate pollution (cause) leads to short circuit (pattern)" or "OBIRCH (tool) discovers luminous points (phenomenon)." Finally, the entities and relations extracted from massive amounts of unstructured literature are integrated into a unified failure knowledge graph or structured database. This provides factual basis for subsequent automated failure mode matching combined with electrical test data. After identifying entities and extracting the relationships between them, the entities and the relationships between them are represented by "representations." model structure method The knowledge of failure is structured and constructed using the related knowledge of "root causes".

[0043] Furthermore, this application embodiment also uses entity normalization and disambiguation algorithms to uniformly map entities in different documents that have different expressions but the same or similar meanings. After completing each new failure analysis case, its analysis path (including the sequence of analysis schemes used), key intermediate representations, final failure modes, and root causes are fed back to the failure knowledge graph. The confidence levels of existing relationships are dynamically updated, and conflict detection is used to resolve inconsistencies in conclusions between different cases, thereby achieving progressive expansion and self-learning evolution of the graph. The disambiguation algorithm accurately maps colloquial or non-standard expressions in unstructured text (such as "IDDQ is too high," "static current is abnormal," and "Leakage is too high") to a predefined standard knowledge base, ensuring that subsequent "representation-pattern-structure-method-root cause" associations have unique and definite semantic directions. The specific process includes: first, normalization processing, which mainly uses rule-based heuristic algorithms and string similarity algorithms to initially clean the extracted primary entities. This process addresses surface-level character-level differences, initially aligning terms that are highly similar in form, such as "SEM observation" and "SEM-Analysis," reducing computational noise for subsequent deep semantic-level disambiguation. The disambiguation algorithm primarily relies on context-aware embeddings generated by the Transformer model, determining the semantic consistency of two entities by calculating their cosine similarity in a multi-dimensional vector space. Because the Transformer semantic model captures contextual information surrounding entities, the disambiguation algorithm can distinguish subtle differences between identical words in different sentences. The algorithm uses semantic clustering to group entity point clouds that are close together in the semantic space and leverages knowledge linking technology to unify these point cloud clusters with unique IDs in a standard ontology. Finally, by constructing a probability transition matrix or scoring function, it comprehensively considers the similarity of entity characters, contextual matching, and co-occurrence frequency in historical documents. Through this multi-dimensional weighted evaluation, the disambiguation algorithm can automatically transform reports written by different engineers with varying expressions into standardized knowledge representations, providing statistically significant auxiliary decision support for failure analysis.

[0044] By transforming tacit knowledge, which was originally scattered in experience and documents, into a computable and reasonable explicit knowledge structure, a unified, complete, and sustainably evolving failure knowledge graph is provided for strategic reasoning and root cause attribution.

[0045] Furthermore, embodiments of this application formalize the traditional failure analysis process into states. action The reward-based decision-making model consists of a "state" comprised of the currently acquired set of failure characterizations and the set of executed analysis methods. Various selectable analysis strategies (such as infrared imaging, EMMI, OBIRCH, FIB cross-section, TEM, high-stress retesting, etc.) are considered "actions," while the success rate, information gain, time cost, economic cost, and destructive impact on the sample are uniformly quantified as the "reward." Based on this, a knowledge graph and graph neural network or reinforcement learning model are used for strategy reasoning. The current failure characterization of each failed sample (chip) to be analyzed is mapped to a local subgraph on the failure knowledge graph. Combining the experience of similar historical cases, the expected information gain and cost of different candidate analysis strategies in the current state are estimated, and a comprehensive priority score is calculated for each analysis strategy. The analysis strategy with the highest score is recommended as the optimal analysis strategy for the next step. With each round of analysis, newly acquired failure characterizations are added to the state set, the associated subgraphs in the failure knowledge graph are updated, and the strategy reasoning process is executed again. If the current evidence chain is insufficient to support a high-confidence root cause determination, subsequent analysis steps are iteratively recommended until the root cause confidence reaches a preset threshold or the analysis cost / time reaches the user-defined boundary conditions. In this way, this application breaks away from the traditional fixed process and experience-driven unidirectional analysis path, realizing the ability to replan the analysis path in real time based on "currently seen evidence," selectively calling appropriate analysis tools, reducing redundant testing and blind trial and error, and significantly improving the efficiency, economy, and consistency of the failure analysis process. For example, Figure 4 This is a flowchart illustrating strategy reasoning within a pre-built failure knowledge graph, as provided in an embodiment of this application. For example... Figure 4 As shown, the steps for policy reasoning in a pre-constructed failure knowledge graph specifically include S210-S250: S210. The initial failure characterization set and the analysis strategy already executed by the chip to be analyzed are taken as the current analysis state; For example, define the state space S: define the set of failure representations that have been obtained so far (e.g.: , , Action space A: defined as all available failure analysis methods (e.g., A = {OBIRCH, EMMI, FIB, SEM, TEM, ...}); Reward function R: defined as the information value gained and the cost incurred after executing a certain analysis strategy, for example: R( A) = W1 × Information Gain ( The formula is: A) - W2 × Cost(A) - W3 × Time(A); where W1, W2, and W3 are weighting information, i.e., weighting coefficients, and A is the action space. Information gain is determined by calculating the probability of the analysis strategy discovering a critical failure mode or the degree to which it increases the confidence of root cause inference in the current state.

[0046] S220. Based on the pre-constructed failure knowledge graph, the analysis strategy that conforms to the current analysis state is selected as a candidate analysis strategy.

[0047] S230. Map the current analysis state to the corresponding node in the failure knowledge graph, and use a graph neural network model to aggregate information from the nodes in the failure knowledge graph to generate a global state vector representing the current analysis state.

[0048] S240. Based on the global state vector, calculate the expected reward value obtained by executing each of the candidate analysis strategies; S250. Based on the expected reward value, determine the current target analysis strategy for the chip to be analyzed from among the multiple candidate analysis strategies.

[0049] Specifically, in this embodiment of the application, to evaluate the value of each action (analysis strategy), a graph neural network model (GNN) is used to learn complex relationships and potential paths on the failure knowledge graph, thereby calculating the Q-value (long-term cumulative expected value of reward) of each analysis strategy. First, a graph attention network (GAT) or a relational graph convolutional network (R-GCN) is used as the core model to learn the embedded representations of different nodes (failure representations, failure modes, analysis strategies, root causes) and relationships (such as "indication", "association", "correspondence") in the failure knowledge graph. Second, the current state is... All failure representation nodes and executed action nodes (executed analysis strategies) are used as inputs to the GNN model. The GNN model generates a global embedded state vector of the current analysis state by combining the structural information of the failure knowledge graph through multi-layer propagation and aggregation operations. For each optional action a∈A, the GNN model will The embedded state vector of action 'a' is concatenated with the embedded state vector of action 'a' and input into a fully connected network. The output is its Q-value, which is calculated using the following formula:

[0050] in, Refers to the current state Next action The long-term expected value of rewards.

[0051] In addition, in each round of analysis, the next action is recommended based on the Q value calculated by the GNN model: (1) Action selection: based on The probability (exploration) is used to randomly select an analysis strategy (action) that has not yet been executed; Based on the probability (utilization), select the action with the highest Q value: (2) Execution and feedback: Execution To obtain new failure characteristics (3) State update: the new state Model training: using new state transitions The GNN model is trained offline using reinforcement learning, and the strategy is continuously optimized.

[0052] This application's embodiments explore optimal analysis strategies within a failure knowledge graph using a GNN-reinforcement learning algorithm. The generation of these strategies no longer relies on human experience but is based on quantified knowledge within the failure knowledge graph and the globally optimal path learned by the GNN model. Furthermore, each time a new failure representation is discovered (i.e., a state update), the optimal analysis strategy for the current state is recalculated and recommended in real time, achieving dynamic and adaptive optimization of the failure analysis process. Additionally, by designing the Q-value (long-term cumulative reward expectation) for each analysis strategy, an analysis method that maximizes information gain is achieved.

[0053] S300. Determine new failure characteristics based on the target analysis strategy.

[0054] For example, in this application embodiment, determining new failure characteristics based on a target analysis strategy includes: determining new multimodal data of the chip to be analyzed based on the target analysis strategy; and re-analyzing the new multimodal data to obtain new failure characteristics.

[0055] S400. Based on the new failure representation, update the initial failure representation set and the failure knowledge graph, and iteratively execute the policy reasoning steps until the preset convergence condition is met.

[0056] Specifically, based on the new failure representations, after updating the initial failure representation set and failure knowledge graph, if the current chain of evidence is insufficient to support a high-confidence root cause determination, the subsequent analysis steps are iteratively recommended until the root cause confidence reaches a preset threshold or the analysis cost / time reaches the user-defined boundary convergence condition.

[0057] S500. Under the condition that the preset convergence condition is met, based on all failure representations in the updated failure representation set, the probability values ​​of failure modes and root causes are calculated using a preset probability model.

[0058] For example, Figure 5This is a flowchart illustrating the calculation of the probability values ​​of failure modes and root causes provided in an embodiment of this application. For example... Figure 5 As shown, the steps for calculating the probability values ​​of failure modes and root causes specifically include S510-S530: S510. Take all failure representations in the updated failure representation set as independent or related evidence for different failure modes and root cause hypotheses, and input the independent or related evidence into a preset probability model.

[0059] For example, the analysis output of various modal data is first regarded as independent or interrelated evidence for different failure modes and root cause hypotheses. For instance, electrical anomalies provide preliminary support for modes such as "short circuit" and "dielectric breakdown", thermal imaging hotspots provide evidence of local power consumption anomalies at a certain physical location, cracks or voids on SEM / FIB cross sections provide evidence for "mechanical fatigue" or "electromigration voids", and EDS composition anomalies provide evidence for "contamination residue" or "abnormal material ratio".

[0060] S520. The preset probability model performs accumulation, conflict detection, and normalization fusion processing on the independent or related evidence. S530. Based on the fusion processing of accumulation, conflict detection and normalization, the probability values ​​of the failure mode and root cause are calculated.

[0061] For example, a Bayesian network or D... S-evidence theory constructs "failure symptom" Failure Mode The probability model of "root cause" calculates the posterior probability (probability value) of each candidate failure mode and root cause by accumulating different evidence, detecting conflicts and normalizing the fusion. This yields a set of failure mode and root cause ranking results with quantitative confidence. In other words, it uses a Bayesian network to analyze and accumulate state transition probabilities to obtain the probability values ​​of failure modes and root causes.

[0062] S600. Based on the probability value and the updated failure knowledge graph, reverse root cause reasoning is performed on the chip to be analyzed to obtain the root cause of the failure of the chip to be analyzed.

[0063] For example, Figure 6 This is a flowchart illustrating reverse root cause reasoning of the chip to be analyzed, provided in an embodiment of this application. For example... Figure 6 As shown, the steps for reverse root cause reasoning of the chip to be analyzed specifically include S610-S650: S610. In the updated failure knowledge graph, failure modes with a probability value greater than a preset threshold are selected as candidate failure mode nodes. S620. Obtain the physical structural characteristics corresponding to the updated failure characterization set, and determine the corresponding physical structural nodes based on the physical structural characteristics. S630. Starting from the candidate failure mode nodes and physical structure nodes, perform a reverse traversal along the associated paths in the updated failure knowledge graph to obtain the upstream root cause node set. S640. Based on the path weight of the associated path and the probability value, score each root cause node in the upstream root cause node set to obtain a score result.

[0064] For example, each root cause node in the upstream root cause node set is scored based on the path weight of the associated path and the probability value.

[0065] S650. Based on the scoring results, the root cause of the failure of the chip to be analyzed is obtained.

[0066] In this embodiment of the application, a failure knowledge graph is used for reverse reasoning. Starting from the confirmed failure modes and physical structure locations, the graph is traversed upstream along the causal relationships. The path weights of the associated paths are combined with the probability values ​​to score and rank multiple potential root causes such as process defects, design defects, packaging problems, and material problems. Finally, a root cause set containing candidate root causes and their quantified probability weights is formed.

[0067] This application's embodiments transform the analysis results of different modal data into probabilistic evidence supporting specific failure modes, and employ advanced algorithms such as Bayesian networks or evidence theory for deep fusion, achieving quantitative cross-validation of the evidence chain. Finally, based on the failure knowledge graph, reverse attribution reasoning is performed to deduce the most probable process defects or design defects from the confirmed failure modes and physical locations, and output their quantitative probability weights. This makes the failure conclusions more objective, accurate, and credible, significantly improving the accuracy of root cause inference and providing a strong scientific basis for subsequent process or design modifications.

[0068] To explain in detail the principles of the technical solution of this application, the overall process of this application will be described below with reference to some specific embodiments. It is easy to understand that the following is an explanation of the technical principles of this application and should not be regarded as a limitation of this application.

[0069] In one specific embodiment, the chip failure analysis process of this application includes the following steps: S1. Acquire multimodal data of the chip under analysis through a multi-source heterogeneous data acquisition interface, and analyze the multimodal data to obtain a failure characterization set: Multimodal data includes DC / AC I Electrical data such as V-curves, S-parameters, timing waveforms, and ATE test results; hotspot distribution data generated by infrared thermal imaging, resistance anomaly testing, and low-light microscopy; and microscopic image data such as optical microscopy, SEM (scanning electron microscopy), FIB (focused ion beam) cross-sections, and EMMI (low-light microscopy) light emission. Secondly, a target detection and segmentation network is used on the image data to accurately locate and classify defects such as cracks, voids, bridging, dielectric breakdown, corrosion zones, and solder joint anomalies in SEM / FIB / EMMI images, outputting the image coordinates, physical coordinates, hierarchical structure, and confidence level of the defects. TCN, RNN, LSTM, or attention models are used to identify abnormal patterns such as "suspected short circuits," "suspected dielectric breakdowns," and "suspected Vth drift" in the electrical data and timing signals. Deep learning and cluster analysis are used to identify local hotspots and their correspondence with circuit layout areas in infrared thermal imaging or light emission images. All the above identification results are uniformly abstracted into "initial failure characterization," including characterization type, spatial location, hierarchical structure, numerical attributes, and pattern labels.

[0070] S2. Construct a failure knowledge graph around the field of chip failure: Knowledge graphs are based on entities relation The entities are organized in the form of triplets. The entities cover failure characteristics, failure modes, physical structures, analysis methods, root causes of failure, and FMEA entries. The relationships describe semantic connections such as "a certain characteristic indicates a certain failure mode", "a certain mode is typically caused by a certain process defect", "a certain characteristic and a certain analysis method are detectable", "a certain structure is prone to a certain failure mode", and "a certain mode / root cause corresponds to a certain FMEA entry".

[0071] S3. Based on the current failure representation and the executed analysis strategies, perform policy reasoning using knowledge graphs and graph neural networks or reinforcement learning models: The current representation of each failed sample is mapped to a local subgraph on the knowledge graph. Based on the experience of similar historical cases, the expected information gain and cost of different candidate analysis strategies in the current state are estimated. A comprehensive priority score is calculated for each analysis, and the method with the highest score is recommended as the optimal analysis strategy for the next step.

[0072] S4. Perform unified deep fusion and reverse attribution reasoning on the failure representations generated from all rounds and all modal data: The analysis outputs of various modes are treated as independent or interrelated evidence of different failure modes and root cause hypotheses, and Bayesian networks or D... S-evidence theory constructs "failure symptom" Failure Mode The probabilistic model for "root causes" calculates the posterior probability of each candidate failure mode and root cause by accumulating, conflict-detecting, and normalizing different pieces of evidence, resulting in a set of mode and root cause rankings with quantitative confidence. Based on this, a failure knowledge graph is used for reverse reasoning. From confirmed failure mode nodes and physical structure nodes, the weights and probability values ​​of associated paths are combined to score and rank multiple potential root causes, such as process defects, design defects, packaging problems, and material problems. This ultimately forms a root cause set containing candidate root causes and their quantified probability weights.

[0073] In summary, this application provides a chip failure analysis method. The method first acquires multimodal data of the chip to be analyzed, analyzes the multimodal data to obtain a failure characterization set, and then performs strategy reasoning in a pre-constructed failure knowledge graph based on the initial failure characterizations to obtain the current target analysis strategy for the failed chip. The pre-constructed failure knowledge graph is used to represent the multi-level relationships between failure characterizations, failure modes, analysis strategies, physical structures, and root causes of historically analyzed chips. Based on the currently acquired failure characterizations, the optimal target analysis strategy for the next analysis step can be dynamically generated through reasoning in the failure knowledge graph, reducing redundant testing and blind trial and error, and improving the efficiency of the failure analysis process. Secondly, based on the target analysis strategy, new failure characterizations are determined, and based on these new failure characterizations, the failure characterization set and the failure knowledge graph are updated. The strategy reasoning steps are iteratively executed until a preset convergence condition is met. When the preset convergence condition is met, based on all failure characterizations in the updated failure characterization set, the probability values ​​of the failure mode and root cause are calculated using a preset probability model. Root cause reasoning is performed on the chip under analysis based on probability values ​​and the updated failure knowledge graph to obtain the root cause of the chip failure. By calculating the probability values ​​of the characteristic failure modes and root causes corresponding to failures under different modal data, and performing reverse root cause reasoning on the failure knowledge graph based on these probability values, the failure root cause conclusions obtained by reasoning are more objective, accurate and reliable, thus improving the accuracy and efficiency of chip failure analysis.

[0074] like Figure 7 As shown in the diagram, this application also provides a schematic diagram of a chip failure analysis device, which can implement the above-described method. The device may include: The data analysis module 21 is used to acquire multimodal data of the chip to be analyzed and to analyze the multimodal data to obtain an initial failure characterization set; The target analysis strategy module 22 is used to perform strategy reasoning in a pre-constructed failure knowledge graph based on the initial failure characterization set to obtain the current target analysis strategy of the chip to be analyzed. The pre-constructed failure knowledge graph is used to characterize the multi-level correlation between failure characterization, failure mode, analysis strategy, physical structure and root cause of historical analysis chips. New failure characterization determination module 23 is used to determine new failure characterizations based on the target analysis strategy; The inference iteration execution module 24 is used to update the initial failure representation set and the failure knowledge graph based on the new failure representation, and iteratively execute the strategy inference steps until the preset convergence condition is met; The probability value calculation module 25 is used to calculate the probability values ​​of failure modes and root causes based on all failure representations in the updated failure representation set and through a preset probability model, provided that the preset convergence condition is met. The root cause reasoning module 26 is used to perform reverse root cause reasoning on the chip to be analyzed based on the probability value and the updated failure knowledge graph to obtain the root cause of the failure of the chip to be analyzed.

[0075] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0076] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the aforementioned chip failure analysis method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0077] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0078] Please see Figure 8 , Figure 8 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 902 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called and executed by the processor 901 using the chip failure analysis method of the embodiments of this application. The input / output interface 903 is used to implement information input and output; The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 905 transmits information between various components of the device (e.g., processor 901, memory 902, input / output interface 903, and communication interface 904); The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0079] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described chip failure analysis method.

[0080] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0081] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0082] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0083] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0084] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0086] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0087] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0089] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks. The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A chip failure analysis method, characterized in that, include: Acquire multimodal data of the chip to be analyzed, and analyze the multimodal data to obtain an initial failure characterization set; Based on the initial failure characterization set, strategy reasoning is performed in the pre-constructed failure knowledge graph to obtain the current target analysis strategy of the chip to be analyzed. The pre-constructed failure knowledge graph is used to characterize the multi-level correlation between failure characterization, failure mode, analysis strategy, physical structure and root cause of historical analysis chips. New failure characteristics are determined based on the aforementioned target analysis strategy; Based on the new failure representation, update the initial failure representation set and the failure knowledge graph, and iteratively execute the policy reasoning steps until the preset convergence condition is met; Under the condition that the preset convergence condition is met, the probability values ​​of failure modes and root causes are calculated by using a preset probability model based on all failure representations in the updated failure representation set. Based on the probability value and the updated failure knowledge graph, reverse root cause reasoning is performed on the chip to be analyzed to obtain the root cause of the chip failure.

2. The chip failure analysis method according to claim 1, characterized in that, The multimodal data includes electrical test data, hotspot distribution data, and image data; The analysis of the multimodal data yields an initial failure characterization set, including: Identify abnormal patterns in the electrical test data; Defect detection is performed on the chip to be analyzed based on the image data to obtain defect information; Based on the local hotspot data in the hotspot distribution data, determine the correspondence between the local hotspot data and the circuit layout; The abnormal mode, the defect information, and the corresponding relationship are used as initial failure characteristics to obtain the initial failure characteristic set of the chip to be analyzed.

3. The chip failure analysis method according to claim 1, characterized in that, The steps for constructing the failure knowledge graph include: Acquire unstructured text data related to chip failure analysis; Identify entities in the unstructured text data and the relationships between entities, wherein the entities include at least one of failure characterization, failure mode, analysis strategy, physical structure, or root cause; By treating the entities as nodes and the relationships between the entities as paths between nodes, a failure knowledge graph is constructed.

4. The chip failure analysis method according to claim 3, characterized in that, The step of performing strategy reasoning based on the initial failure representation set and a pre-constructed failure knowledge graph to obtain the current target analysis strategy for the chip to be analyzed includes: The initial failure characterization set and the analysis strategy already executed by the chip to be analyzed are taken as the current analysis state; Based on the pre-constructed failure knowledge graph, the analysis strategies that conform to the current analysis state are selected as candidate analysis strategies. The current analysis state is mapped to the corresponding node in the failure knowledge graph, and the information of the node in the failure knowledge graph is aggregated using a graph neural network model to generate a global state vector representing the current analysis state. Based on the global state vector, calculate the expected reward value obtained by executing each of the candidate analysis strategies; Based on the expected reward value, the current target analysis strategy for the chip to be analyzed is determined from a plurality of candidate analysis strategies.

5. The chip failure analysis method according to claim 1, characterized in that, The determination of new failure characteristics based on the target analysis strategy includes: Based on the target analysis strategy, new multimodal data of the chip to be analyzed are determined; The new multimodal data is reanalyzed to obtain new failure characteristics.

6. The chip failure analysis method according to claim 1, characterized in that, The method involves calculating the probability values ​​of failure modes and root causes based on all failure representations in the updated failure representation set using a preset probability model, including: All failure representations in the updated failure representation set are used as independent or related evidence for different failure modes and root cause hypotheses, and the independent or related evidence is input into a preset probability model. The preset probability model performs accumulation, conflict detection, and normalization fusion processing on the independent or related evidence. Based on the fusion of accumulation, conflict detection, and normalization, the probability values ​​of the failure modes and root causes are calculated.

7. The chip failure analysis method according to claim 3, characterized in that, The reverse root cause reasoning of the chip under analysis based on the probability value and the updated failure knowledge graph to obtain the root cause of the chip failure includes: In the updated failure knowledge graph, failure modes with a probability value greater than a preset threshold are selected as candidate failure mode nodes. Obtain the physical structural characteristics corresponding to the updated failure characterization set, and determine the corresponding physical structural nodes based on the physical structural characteristics; Starting from the candidate failure mode nodes and physical structure nodes, a reverse traversal is performed along the associated paths in the updated failure knowledge graph to obtain the upstream root cause node set. Based on the path weight of the associated path and the probability value, each root cause node in the upstream root cause node set is scored to obtain a scoring result; Based on the scoring results, the root cause of the failure of the chip to be analyzed is obtained.

8. A chip failure analysis device, characterized in that, The device includes: The data analysis module is used to acquire multimodal data of the chip to be analyzed and to analyze the multimodal data to obtain an initial failure characterization set. The target analysis strategy module is used to perform strategy reasoning in a pre-constructed failure knowledge graph based on the initial failure characterization set to obtain the current target analysis strategy of the chip to be analyzed. The pre-constructed failure knowledge graph is used to characterize the multi-level correlation between failure characterization, failure mode, analysis strategy, physical structure and root cause of historical analysis chips. The new failure characterization determination module is used to determine new failure characterizations based on the target analysis strategy. The inference iterative execution module is used to update the initial failure representation set and the failure knowledge graph based on the new failure representation, and iteratively execute the policy inference steps until a preset convergence condition is met; The probability value calculation module is used to calculate the probability values ​​of failure modes and root causes based on all failure representations in the updated failure representation set and a preset probability model, provided that the preset convergence conditions are met. The root cause reasoning module is used to perform reverse root cause reasoning on the chip to be analyzed based on the probability value and the updated failure knowledge graph to obtain the root cause of the failure of the chip to be analyzed.

9. An electronic device, characterized in that, Including the processor and memory; The memory is used to store programs; The processor executes the program to implement a chip failure analysis method as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements a chip failure analysis method as described in any one of claims 1 to 7.

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