Network status detection method and apparatus

Abstract

The application provides a network state detection method and device, which is applied to a device containing a system on chip (SOC), and an interrupt input pin of the SOC is electrically connected with an interrupt request pin of a physical layer chip. When the physical layer chip is initialized, a change of a physical layer link state is mapped to the interrupt request pin, an interrupt processing flow is executed in response to an interrupt trigger signal of the interrupt request pin, a current physical layer link state is acquired, and the current physical layer link state is transmitted to a preset application program based on an inter-process communication mechanism, so that the preset application program reports the current physical layer connection state information to an external controller. Through the introduction of a hardware interrupt trigger mechanism and efficient communication between a kernel and an application layer, real-time detection and rapid reporting of the network state are realized, the network state detection time is greatly shortened, system resource consumption is reduced, and the real-time detection and reporting capability of the network state can be significantly improved.

Description

Technical Field

[0001] This application relates to the field of network monitoring and detection technology, and in particular to a network status detection method and device. Background Technology

[0002] Network connectivity stability directly impacts the normal operation of devices. Taking automotive Ethernet as an example, multiple electronic control units in a vehicle communicate at high speed via Ethernet, and the physical layer connection status (such as link interruption or power failure of the peer device) needs to be monitored in real time. If physical layer faults are not reported in a timely manner, it may lead to communication interruptions, functional failures, or even endanger driving safety. However, in traditional Linux systems, network status detection relies on a periodic polling mechanism, resulting in high latency and large fluctuations in fault detection, which cannot meet the requirements of high real-time scenarios. Therefore, there is an urgent need for a technical solution that can achieve real-time detection and rapid reporting of network status anomalies to improve system reliability and response efficiency. Summary of the Invention

[0003] This application provides a network status detection method and device to solve the technical problem that the network status detection in the prior art relies on a periodic polling mechanism, which leads to high fault detection latency and large fluctuations, and cannot meet the requirements of high real-time scenarios.

[0004] In a first aspect, this application provides a network status detection method, applied to a device including a System-on-a-Chip (SOC), wherein the interrupt input pin of the SOC is electrically connected to an interrupt request pin of a physical layer chip; the method includes:

[0005] During the initialization of the physical layer chip, changes in the physical layer link state are mapped to the interrupt request pin;

[0006] In response to the interrupt trigger signal of the interrupt request pin, an interrupt handling process is executed to obtain the current physical layer link state. The interrupt trigger signal is triggered by the change in the physical layer link state.

[0007] The current physical layer link status is transmitted to a preset application based on an inter-process communication mechanism, so that the preset application reports the current physical layer link status to the target controller.

[0008] In one possible design, the interrupt handling process executed in response to the interrupt trigger signal of the interrupt request pin includes:

[0009] In response to the interrupt trigger signal, the connection status register in the physical layer chip is read through the MDIO bus. The connection status register is used to store the physical layer link status.

[0010] In one possible design, during the execution of the interrupt handling process, the physical layer chip is paused from triggering the interrupt trigger signal when it detects a change in the physical layer link state.

[0011] In one possible design, transmitting the current physical layer link state to a preset application based on an inter-process communication mechanism includes:

[0012] The current physical layer link state is encapsulated into a Netlink message using a Netlink socket in kernel space;

[0013] The Netlink message is sent to the preset application in user space.

[0014] In one possible design, after transmitting the current physical layer link state to a preset application based on the inter-process communication mechanism, the following is also included:

[0015] The physical layer chip is re-enabled to trigger the interrupt signal when it detects a change in the physical layer link state.

[0016] In one possible design, after reading the connection status register in the physical layer chip via the MDIO bus, the following is also included:

[0017] The type of interrupt event corresponding to the interrupt trigger signal is determined based on the bit fields of the connection status register.

[0018] If the interruption event is a link jitter event, the link jitter event is logged, and the transmission of the current physical layer link status to the preset application is terminated;

[0019] If the interruption event is not the link jitter event, a reporting signal is generated, which is used to indicate that the current physical layer link status is transmitted to the preset application.

[0020] In one possible design, the interruption trigger signal is triggered by a change in the physical layer link state, including:

[0021] The interruption trigger signal is triggered by the change in the physical layer link state based on an interruption triggering strategy, which is configured according to the priority of the link state.

[0022] In one possible design, prior to executing the interrupt handling process in response to the interrupt trigger signal of the interrupt request pin, the following is also included:

[0023] Based on the SOC's driver, the specified general-purpose input / output pins of the SOC are configured as interrupt input pins according to the SOC's hardware design information.

[0024] Secondly, this application provides a network status detection device applied to a device including a System-on-a-Chip (SOC), wherein the interrupt input pin of the SOC is electrically connected to an interrupt request pin of a physical layer chip; the device includes:

[0025] The initialization module maps changes in the physical layer link state to the interrupt request pin during the initialization of the physical layer chip.

[0026] The acquisition module is used to execute an interrupt handling process in response to the interrupt trigger signal of the interrupt request pin in order to acquire the current physical layer link status. The interrupt trigger signal is triggered by the change of the physical layer link status.

[0027] The sending module is used to transmit the current physical layer link status to a preset application based on an inter-process communication mechanism, so that the preset application reports the current physical layer link status to the target controller.

[0028] In one possible design, the acquisition module is used for:

[0029] In response to the interrupt trigger signal, the connection status register in the physical layer chip is read through the MDIO bus. The connection status register is used to store the physical layer link status.

[0030] In one possible design, the acquisition module is further configured to:

[0031] During the execution of the interrupt handling process, the physical layer chip is paused from triggering the interrupt trigger signal when it detects a change in the physical layer link state.

[0032] In one possible design, the sending module is used for:

[0033] The current physical layer link state is encapsulated into a Netlink message using a Netlink socket in kernel space;

[0034] The Netlink message is sent to the preset application in user space.

[0035] In one possible design, the acquisition module is further configured to:

[0036] The physical layer chip is re-enabled to trigger the interrupt signal when it detects a change in the physical layer link state.

[0037] In one possible design, the acquisition module is further configured to:

[0038] The type of interrupt event corresponding to the interrupt trigger signal is determined based on the bit fields of the connection status register.

[0039] If the interruption event is a link jitter event, the link jitter event is logged, and the transmission of the current physical layer link status to the preset application is terminated;

[0040] If the interruption event is not the link jitter event, a reporting signal is generated, which is used to indicate that the current physical layer link status is transmitted to the preset application.

[0041] In one possible design, the interrupt trigger signal is triggered by a change in the physical layer link state based on an interrupt triggering strategy configured according to the priority of the link state.

[0042] In one possible design, the device further includes: a pin registration module; the pin registration module is used for:

[0043] Based on the SOC's driver, the specified general-purpose input / output pins of the SOC are configured as interrupt input pins according to the SOC's hardware design information.

[0044] Thirdly, this application provides an electronic device, which includes an embedded device based on a Linux system, and the embedded device includes at least one of an automotive electronic control unit, an industrial Internet of Things gateway, and an edge computing device;

[0045] The electronic device includes: a memory and a processor;

[0046] The memory stores computer-executed instructions;

[0047] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0048] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible embodiments of the first aspect.

[0049] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0050] The network status detection method and device provided in this application are applied to devices including a System-on-a-Chip (SOC). The SOC's interrupt input pin is electrically connected to an interrupt request pin of the physical layer chip. During physical layer chip initialization, changes in the physical layer link state are mapped to the interrupt request pin. An interrupt handling process is executed in response to the interrupt trigger signal from the interrupt request pin to obtain the current physical layer link state. The interrupt trigger signal is triggered by the interrupt request pin based on changes in the physical layer link state. The current physical layer link state is transmitted to a preset application program based on an inter-process communication mechanism, enabling the preset application program to report the current physical layer link state to the target controller. By introducing a hardware interrupt trigger mechanism and efficient communication between the kernel and application layer, real-time network status detection and rapid reporting are achieved, significantly shortening network status detection time, reducing system resource consumption, and significantly improving real-time network status detection and reporting capabilities. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0052] Figure 1 This is a schematic diagram of the architecture for network state detection in existing technologies;

[0053] Figure 2 This is a schematic diagram illustrating the interaction between the PHY chip and the SOC provided in this application;

[0054] Figure 3 A schematic diagram of the architecture of the network state detection method provided in this application;

[0055] Figure 4 Flowchart of the network status detection method provided in this application Figure 1 ;

[0056] Figure 5 Flowchart of the network status detection method provided in this application Figure 2 ;

[0057] Figure 6 This application provides a schematic diagram of the structure of a network status detection device.

[0058] Figure 7 A schematic diagram of another network status detection device provided in this application;

[0059] Figure 8 A schematic diagram of the electronic device structure provided in this application.

[0060] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0062] Devices containing System-on-Chip (SOC), such as Linux-based embedded devices like automotive Ethernet electronic control units (ECUs), industrial IoT gateways, or edge computing devices, need to maintain a stable connection with external controllers such as microcontroller units (MCUs) via the Ethernet physical layer (PHY). When the link is interrupted (e.g., a broken cable or power failure of the peer device), the fault must be detected within milliseconds and a diagnostic fault code (DTC) must be reported. For example, an automotive ECU needs to monitor the Ethernet link status in real time while the vehicle is in motion. If the link is abnormal, it may cause communication interruption, which in turn affects the normal operation of in-vehicle functions such as Advanced Driver Assistance Systems (ADAS) and Over-the-Air Technology (OTA) upgrades. Furthermore, in industrial automation scenarios, network status anomalies between devices need to be quickly located and repaired to avoid production interruptions or data loss.

[0063] In existing technologies such as Figure 1As shown, the SOC periodically reads the PHY's Link status via a serial communication bus, such as Management Data Input / Output (MDIO). This process, T0, defaults to 1000 milliseconds. The status is then reported to the application layer's / sys / class / net / eth0 / carrier node via the MAC and PHY driver framework, with a latency T1 of approximately 100 milliseconds. The application periodically accesses the / sys / class / net / eth0 / carrier node to obtain the status, with a latency currently of 100 milliseconds. If an anomaly occurs, the fault is periodically sent to the MCU via periodic inter-chip communication between the SOC and MCU, with a latency T3 currently of 10 milliseconds. The MCU then reports a DTC (Disruption Troubleshooting) to the outside world. It is evident that the Linux system relies on a multi-level process involving periodic MDIO reading of PHY registers, driver framework reporting, application layer polling, and cross-chip communication, resulting in high fault detection latency and a large latency fluctuation range, which cannot meet the requirements of high real-time scenarios. For example, in automotive scenarios, if the Ethernet cable suddenly disconnects, the SOC needs to periodically poll to detect the fault, then report it to the MCU via the driver framework and application layer, and finally complete the DTC reporting through inter-chip communication. The total delay may exceed 1 second, causing safety functions to fail. In addition, the periodic polling mechanism continues to consume CPU resources even when there is no fault, reducing system efficiency.

[0064] To address the aforementioned problems in the existing technology, this application provides a network status detection method and device. The inventive concept of the network status detection method provided in this application is as follows: Changes in the physical layer link status (such as link up or link down) are mapped to an interrupt request pin of the physical layer chip, such as the INTB (Interrupt B) pin of the PHY chip. Then, utilizing the SOC's interrupt handling mechanism, the interrupt trigger signal triggered by the physical layer link status change is quickly responded to, thereby obtaining the physical layer link status. Finally, through an inter-process communication mechanism, such as Netlink technology, the physical layer link status is transmitted to the application layer, such as a preset application, thereby bypassing the multi-level reporting latency of traditional driver frameworks, significantly reducing the total latency of network status detection and reporting, and simultaneously improving system stability and resource utilization.

[0065] It should be noted that the network status detection method and device provided in this application are not limited to embedded devices based on Linux systems, but can also be used on devices of any operating system that use interrupts instead of polling for status monitoring. There are no limitations on the type of device or the operating system it runs on.

[0066] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0067] Figure 2 This is a schematic diagram illustrating the interaction between the PHY chip and the SOC provided in this application, such as... Figure 2 As shown, the PHY chip and the SOC can interact through three sets of hardware links. MDIO is a bidirectional management data channel, and the Management Data Clock (MDC) is a synchronous clock output from the SOC to the PHY, used to jointly support the reading and writing of PHY configuration and status. The PHY's INTB interrupt pin is unidirectionally connected to the SOC's General-Purpose Input / Output (GPIO) interface, used to convert physical layer link status changes (link up / down) detected by the PHY into interrupt signals. The SOC can receive this interrupt through its own GPIO and trigger the interrupt handling mechanism, while simultaneously obtaining PHY status information through the MDIO and MDC links. This is achieved through... Figure 2 The hardware structure shown can provide basic support for the network status detection method and device provided in this application.

[0068] Figure 3 This is a schematic diagram of the architecture of the network state detection method provided in this application. Figure 4 Flowchart of the network status detection method provided in this application Figure 1 ,like Figure 3 and Figure 4 As shown, this method is applied to a device containing a System-on-a-Chip (SoC), where the SoC's interrupt input pin is electrically connected to an interrupt request pin of the physical layer chip. The method includes:

[0069] S101. During physical layer chip initialization, changes in the physical layer link state are mapped to the interrupt request pin.

[0070] For example, by configuring registers, changes in the link state of the physical layer chip, such as from link up to link down or link down to link up in the Ethernet link of T1, can be mapped to the interrupt request pin of the physical layer chip.

[0071] S102. In response to the interrupt trigger signal of the interrupt request pin, execute the interrupt handling process to obtain the current physical layer link status.

[0072] like Figure 3As shown, the SOC's interrupt input pin is electrically connected to an interrupt request pin, such as the INTB pin, of the physical layer chip. This interrupt request pin of the physical layer chip is configured to map to changes in the physical layer link state. When the physical layer link state changes, for example, from link up to link down or from link down to link up, the interrupt request pin will change, thereby triggering the interrupt trigger signal.

[0073] The interrupt trigger signal is used by the interrupt request pin to trigger an interrupt request from the SOC. For example, when the Ethernet cable is disconnected, the PHY chip detects that the link status has changed from link up to link down, the INTB pin is pulled low, and an interrupt is triggered from the SOC.

[0074] The SOC's interrupt input pin is electrically connected to an interrupt request pin on the physical layer chip. The current link status of the physical layer chip can be read via the MDIO bus. The interrupt input pin receives the interrupt trigger signal from the interrupt request pin, and then responds to the interrupt trigger signal to enter the interrupt handler function to execute the interrupt handling process.

[0075] The interrupt handler function is a callback function executed by the SOC after receiving an interrupt trigger signal. The physical layer link status is obtained by executing the interrupt handling process; the physical layer link status refers to whether the current connection status of the physical layer link is linkup or link down.

[0076] As can be seen, the interrupt request pin directly reflects the physical layer link status change. Communication between the interrupt request pin and the interrupt input pin triggers the SOC interrupt, thereby replacing periodic polling with a hardware interrupt triggering mechanism, realizing real-time network status detection, avoiding the delay of software polling, and reducing CPU resource consumption.

[0077] In one possible design, the interrupt handling process is executed in response to the interrupt trigger signal on the interrupt request pin, including:

[0078] In response to an interrupt trigger signal, the connection status register in the physical layer chip is read via the MDIO bus.

[0079] The physical layer link status is stored in the connection status register of the physical layer chip, such as the 0x1d register. The current physical layer link status is obtained by reading the connection status register in the physical layer chip via the MDIO bus. For example, in automotive Ethernet, the bit field of the 0x1d register indicates whether the link is in a link-up or link-down state.

[0080] In some embodiments, during the interrupt handling process, the physical layer chip is paused from triggering an interrupt trigger signal when it detects a change in the physical layer link state, so as to avoid triggering the interrupt trigger signal to execute the interrupt handling process before the current interrupt handling process has ended.

[0081] S103. Based on the inter-process communication mechanism, the current physical layer link status is transmitted to the preset application, so that the preset application reports the current physical layer link status to the target controller.

[0082] Continue to refer to Figure 3 As shown, the SOC transmits the read physical layer link status to a preset application (APP) based on an inter-process communication mechanism. The preset application can be configured as a user space to receive the physical layer link status, such as a fault monitoring program. In an in-vehicle system, the preset application can be the diagnostic fault code reporting module for the ECU. This application does not limit the specific content of the preset application.

[0083] The pre-defined application generates the corresponding DTC based on the received physical layer link status and sends the DTC to the target controller, such as the vehicle main control MCU, through inter-chip communication to realize DTC reporting.

[0084] In one possible design, step S103 transmits the current physical layer link status to a preset application based on an inter-process communication mechanism. Possible implementation methods include:

[0085] The current physical layer link state is encapsulated into a Netlink message using a Netlink socket in kernel space, and then the Netlink message is sent to a preset application in user space.

[0086] After obtaining the current physical layer link state, the System-on-a-Chip (SoC) encapsulates the current physical layer link state into a data packet, such as a Netlink message, through an inter-process communication (IPC) socket interface, and then sends the encapsulated data packet to the user-space predefined application. Encapsulating and transmitting the physical layer link state through IPC avoids the multi-level reporting process of traditional driver frameworks, effectively shortening the data transmission path.

[0087] It's worth noting that Netlink is an inter-process communication mechanism provided by the Linux kernel for bidirectional data transfer between user space and kernel space. Based on socket communication, it uses asynchronous communication. User space can communicate through the standard socket application programming interface (API), while kernel space requires a dedicated kernel API.

[0088] Kernel communication mechanisms include, but are not limited to, Netlink. When the device is running other operating systems, the kernel communication mechanism is the communication mechanism supported by the operating system in actual working conditions.

[0089] As can be seen, by encapsulating and sending data packets using sockets, the latency problem caused by multi-level reporting in traditional driver frameworks can be solved. Specifically, the direct communication mechanism of sockets allows data packets to bypass the node update and polling process of the driver framework and be directly transmitted to the application layer, thereby significantly shortening the reporting time of fault information.

[0090] The network status detection method provided in this application maps changes in the physical layer link state to an interrupt request pin of the physical layer chip. Changes in the physical layer link state trigger a transition on this interrupt request pin, thereby triggering an interrupt trigger signal. The interrupt request pin is electrically connected to the interrupt input pin of the System-on-a-Chip (SOC). The interrupt trigger signal is transmitted from the interrupt request pin to the interrupt input pin, triggering the SOC to respond to the interrupt trigger signal and execute an interrupt handling process, enabling the SOC to respond immediately after a change in the physical layer link state. By replacing the traditional periodic polling mechanism with a hardware interrupt trigger signal, the latency fluctuations caused by task scheduling or system load in the polling mechanism can be avoided, solving the problem of high latency and instability in physical layer status detection. After the SOC executes the interrupt handling process and obtains the physical layer link state, it transmits the physical layer link state to the application layer based on an inter-process communication (IPC) mechanism, allowing the application layer to report it to the corresponding target controller. The introduction of the IPC mechanism bypasses the multi-level reporting process of the traditional driver framework, directly transmitting the physical layer link state to the application layer, reducing communication layers and latency. As can be seen, the network status detection method provided in this application forms an efficient link from physical layer status detection to application layer reporting, which can significantly shorten the total latency of status detection, such as fault detection and reporting, while reducing system resource consumption and improving the real-time detection and processing capabilities of network status.

[0091] Figure 5 Flowchart of the network status detection method provided in this application Figure 2 This method is applied to devices containing a System-on-a-Chip (SoC), where the SoC's interrupt input pin is electrically connected to an interrupt request pin in the physical layer chip. For example... Figure 5 As shown, the method includes:

[0092] S201, a driver based on the SOC, configures the specified general-purpose input / output pins of the SOC as interrupt input pins according to the hardware design information of the SOC.

[0093] The hardware design information of a System-on-a-Chip (SoC), such as in the chip datasheet or hardware design guide, typically specifies the pins that can be configured to respond to interrupts. Therefore, SoC-based drivers can configure the general-purpose input / output pins specified by the SoC as interrupt input pins based on the SoC's hardware design information, thus registering the interrupt input pins. Drivers are used to initialize, manage, and abstract the various modules within the SoC, giving each module responsive functionality.

[0094] S202. During physical layer chip initialization, changes in the physical layer link state are mapped to the interrupt request pin.

[0095] For example, by configuring registers, changes in the link state of the physical layer chip, such as from link up to link down or link down to link up in the Ethernet link of T1, can be mapped to the interrupt request pin of the physical layer chip.

[0096] S203. In response to the interrupt trigger signal of the interrupt request pin, execute the interrupt handling process to obtain the current physical layer link status.

[0097] The interruption trigger signal is triggered by changes in the physical layer link state.

[0098] After receiving the interrupt trigger signal from the interrupt request pin of the physical layer chip, the interrupt input pin of the SOC reads the connection status register of the physical layer chip to obtain the current physical layer link status in response to the interrupt trigger signal.

[0099] The physical layer link status is stored in the connection status register of the physical layer chip, and the SOC can obtain the physical layer link status by reading the connection status register of the physical layer chip.

[0100] In some embodiments, the interruption trigger signal is triggered by a physical layer link state change based on an interruption triggering policy, which is configured according to the priority of the link state.

[0101] For example, before mapping physical layer link state changes to interrupt request pins of physical layer devices, an interrupt triggering strategy can be configured based on the priority of the link states, such as primary link, secondary link, etc. For instance, the interrupt triggering strategy could be that primary link interrupts have high priority, and the interrupt request pin can be directly mapped to a hardware interrupt, while secondary link jitter has low priority, and the interrupt trigger signal is only triggered when the primary link is stable. After a physical layer link state change, an interrupt trigger signal is triggered based on the interrupt triggering strategy.

[0102] In other embodiments, the priority configuration of the interruption triggering strategy can be based on the type and impact of link state changes. For example, since link disconnection leads to data transmission interruption, emergency operations such as fault diagnosis and link switching can be triggered by prioritizing the response. The interruption of the link-up state can be configured with low priority, allowing state synchronization and reporting to be delayed until system resources are idle. Therefore, the interruption priority of the link-down state can be set higher than that of the link-up state. Furthermore, the priority can be configured in conjunction with the link data transmission rate. For example, the interruption priority for state changes of 10Gbps high-speed links is higher than that of links with rates of 1Gbps and below, ensuring that state changes of high-speed transmission channels are processed first and avoiding data packet loss due to response delays.

[0103] By configuring interrupt triggering strategies based on link status priorities, the problem of uneven distribution of interrupt resources in multi-link scenarios can be solved. This ensures that changes in the status of critical links trigger interrupts first, avoiding low-priority events from occupying interrupt resources, thereby improving the system's response efficiency to critical faults.

[0104] Furthermore, after executing the interrupt handling procedure to read the connection status register of the physical layer chip in step S203, the process also includes:

[0105] S204. Determine the type of interrupt event corresponding to the interrupt trigger signal based on the bit field identifier of the connection status register.

[0106] When responding to an interrupt trigger signal, the SOC identifies the type of interrupt event based on the bit fields of the physical layer chip's connection status register, such as link interruption, link recovery, or jitter, and then performs differentiated processing for different types of interrupt events. The bit fields of the physical layer chip's connection status register can be used to identify the type of interrupt event, or the type of interrupt event can be identified through the bit fields in the historical records of the physical layer chip's connection status register.

[0107] S205a. If the interruption event is a link jitter event, trigger the log to record the link jitter event and terminate the transmission of the current physical layer link status to the preset application.

[0108] For example, if the interruption event is of type link recovery or jitter, and the interruption event is determined to be a link jitter event, then only the log is recorded and the physical layer connection status report is not triggered.

[0109] S205b: If the interruption event is not a link jitter event, generate a reporting signal.

[0110] The reporting signal is used to indicate that the current physical layer link status should be transmitted to the preset application.

[0111] If the interruption event is not a link jitter event, then the current interruption event is determined to be a link interruption event, and a reporting signal is generated to respond to the transmission of physical layer connection status information.

[0112] By classifying and processing interruption events, the problem of meaningless interruption events consuming system resources can be solved. Differentiated processing reduces resource consumption for link jitter events while ensuring rapid response to genuine link interruption events, improving system accuracy and resource utilization. It should be noted that in some embodiments, a link jitter event refers to a non-valid state change event in the physical layer link that occurs frequently and instantaneously within a preset time window, involving link up / link down state switching. Link jitter events can be determined by reading bit fields such as the number of state transitions and the duration of a single state transition from the physical layer chip's connection status register via the MDIO bus. For example, these bit fields are compared with preset time window thresholds, switching frequency thresholds, and state duration thresholds. If the number of transitions within the preset time window is greater than or equal to the corresponding threshold, and the duration of a single state transition is less than the corresponding threshold, then it is determined to be a link jitter event; otherwise, it is determined to be a non-link jitter event.

[0113] S206. The response reporting signal transmits the current physical layer link status to the preset application based on the inter-process communication mechanism, so that the preset application reports the current physical layer link status to the target controller.

[0114] The possible implementation methods, principles, and technical effects of step S206 are similar to those of step S103. For details, please refer to the foregoing description, which will not be repeated here.

[0115] In some embodiments, after receiving the physical layer link status, the preset application can also perform some operations. For example, according to project requirements, it can report the corresponding DTC for the physical layer link status that is link down. If the link is restored to up, the DTC can also be deleted.

[0116] In some embodiments, after transmitting the current physical layer link state to a preset application based on an inter-process communication mechanism, the method further includes: re-enabling the physical layer chip to trigger an interrupt signal when a change in the physical layer link state is detected.

[0117] For example, the current physical layer link status is transmitted to a preset application based on the inter-process communication mechanism. After the reporting process of this link status is completed, the interrupt triggering function of the physical layer chip is reactivated, so that the physical layer chip can restore its ability to detect subsequent changes in the physical layer link status. When a new status change is detected, the interrupt triggering signal can be triggered again to realize the continuous cyclic detection and reporting of the link status.

[0118] The network status detection method provided in this application achieves real-time detection and rapid reporting of network status by introducing a hardware interrupt triggering mechanism and efficient communication between the kernel and application layer. This significantly shortens network status detection time, reduces system resource consumption, and substantially improves real-time network status detection and reporting capabilities. Furthermore, by configuring an interrupt triggering strategy based on link status priority, the problem of uneven interrupt resource allocation in multi-link scenarios can be resolved. And by classifying and processing interrupt events, the problem of meaningless interrupt events consuming system resources can be addressed.

[0119] After testing, the network detection method provided in this application shows that after the physical layer device detects a change in its link connection status with the external device, the process from triggering the interrupt signal to the SOC receiving the physical layer connection status information takes approximately 50 milliseconds. The SOC, based on its kernel communication mechanism, notifies the preset application of the physical layer connection status information in approximately 10 milliseconds. The preset application sends the information to the MCU via chip-to-chip communication between the SOC and an external controller, such as the MCU, in approximately 10 milliseconds, and then the MCU reports a DTC (Distributed Troubleshooting Condition). Therefore, the time from the physical layer device triggering the interrupt request pin transition to the physical layer connection status information, such as a fault report, being sent to the MCU is approximately 50 + 10 + 10 = 70 milliseconds. The SOC can report the physical layer connection status information to the external controller, such as the MCU, within 100 milliseconds. The status reporting time is relatively stable, with fluctuations not exceeding 20 milliseconds.

[0120] Figure 6 This is a schematic diagram of a network status detection device provided in this application. This device is applied to a device containing a System-on-a-Chip (SOC), where the SOC's interrupt input pin is electrically connected to an interrupt request pin of the physical layer chip. For example... Figure 6 As shown, the network status detection device 40 provided in this application includes:

[0121] The initialization module 401 maps changes in the physical layer link state to the interrupt request pin during physical layer chip initialization.

[0122] The acquisition module 402 is used to execute an interrupt handling process in response to the interrupt trigger signal of the interrupt request pin in order to obtain the current physical layer link status. The interrupt trigger signal is triggered by the change of the physical layer link status.

[0123] The sending module 403 is used to transmit the current physical layer link status to a preset application based on the inter-process communication mechanism, so that the preset application reports the current physical layer link status to the target controller.

[0124] In one possible design, module 402 is used for:

[0125] In response to an interrupt trigger signal, the connection status register in the physical layer chip is read via the MDIO bus. The connection status register is used to store the physical layer link status.

[0126] In one possible design, the acquisition module 402 is also used for:

[0127] During the interrupt handling process, the physical layer chip is paused from triggering an interrupt signal when it detects a change in the physical layer link state.

[0128] In one possible design, the sending module 402 is used for:

[0129] The current physical layer link state is encapsulated into a Netlink message using a Netlink socket in kernel space;

[0130] Sends Netlink messages to a default application in user space.

[0131] In one possible design, the acquisition module 402 is also used for:

[0132] The physical layer chip is re-enabled when an interrupt trigger signal is detected upon detecting a change in the physical layer link state. In one possible design, the acquisition module 402 is also used for:

[0133] The type of interrupt event corresponding to the interrupt trigger signal is determined based on the bit fields of the connection status register.

[0134] If the interruption event is a link jitter event, the link jitter event will be logged, and the transmission of the current physical layer link status to the preset application will be terminated.

[0135] If the interruption event is not a link jitter event, a reporting signal is generated. The reporting signal is used to indicate that the current physical layer link status is transmitted to the preset application.

[0136] In one possible design, the interrupt trigger signal is triggered by a change in the physical layer link state based on an interrupt triggering strategy, which is configured according to the priority of the link state.

[0137] exist Figure 6 On this basis, Figure 7 A schematic diagram of another network status detection device provided in this application is shown below. Figure 7 As shown, the network status detection device 40 provided in this application further includes: a pin registration module 404, which is used for:

[0138] The SOC-based driver configures the SOC's designated general-purpose input / output pins as interrupt input pins according to the SOC's hardware design information.

[0139] The network status detection device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0140] Figure 8 The schematic diagram of the electronic device structure provided in this application is as follows: Figure 8 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus.

[0141] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0142] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0143] The electronic device 50 includes a Linux-based embedded device, which may include at least one of an automotive electronic control unit, an industrial IoT gateway, and an edge computing device.

[0144] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0145] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0146] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus. This application also provides a computer program product, including a computer program that, when executed by a processor, implements the aforementioned method.

[0147] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0148] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0149] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0150] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0151] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0152] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0153] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0154] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0155] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A network state detection method, characterized in that, The method, applicable to devices comprising a System-on-a-Chip (SOC), wherein an interrupt input pin of the SOC is electrically connected to an interrupt request pin of a physical layer chip, comprises: During the initialization of the physical layer chip, changes in the physical layer link state are mapped to the interrupt request pin; In response to the interrupt trigger signal of the interrupt request pin, an interrupt handling process is executed to obtain the current physical layer link state. The interrupt trigger signal is triggered by the change in the physical layer link state. The current physical layer link status is transmitted to a preset application based on an inter-process communication mechanism, so that the preset application reports the current physical layer link status to the target controller.

2. The method according to claim 1, characterized in that, The interrupt handling process, executed in response to the interrupt trigger signal of the interrupt request pin, includes: In response to the interrupt trigger signal, the connection status register in the physical layer chip is read through the MDIO bus. The connection status register is used to store the physical layer link status.

3. The method according to claim 1, characterized in that, Also includes: During the execution of the interrupt handling process, the physical layer chip is paused from triggering the interrupt trigger signal when it detects a change in the physical layer link state.

4. The method according to claim 2, characterized in that, The transmission of the current physical layer link state to a preset application based on the inter-process communication mechanism includes: The current physical layer link state is encapsulated into a Netlink message using a Netlink socket in kernel space; The Netlink message is sent to the preset application in user space.

5. The method according to claim 3, characterized in that, After transmitting the current physical layer link state to the preset application based on the inter-process communication mechanism, the method further includes: The physical layer chip is re-enabled to trigger the interrupt signal when it detects a change in the physical layer link state.

6. The method according to claim 2, characterized in that, After reading the connection status register in the physical layer chip via the MDIO bus, the method further includes: The type of interrupt event corresponding to the interrupt trigger signal is determined based on the bit fields of the connection status register. If the interruption event is a link jitter event, the link jitter event is logged, and the transmission of the current physical layer link status to the preset application is terminated; If the interruption event is not the link jitter event, a reporting signal is generated, which is used to indicate that the current physical layer link status is transmitted to the preset application.

7. The method according to claim 1, characterized in that, The interruption trigger signal is triggered by a change in the physical layer link state, including: The interruption trigger signal is triggered by the change in the physical layer link state based on an interruption triggering strategy, which is configured according to the priority of the link state.

8. The method according to any one of claims 1-7, characterized in that, Before executing the interrupt handling process in response to the interrupt trigger signal of the interrupt request pin, the following steps are also included: Based on the SOC's driver, the specified general-purpose input / output pins of the SOC are configured as interrupt input pins according to the SOC's hardware design information.

9. A network status detection device, characterized in that, An apparatus applicable to a device comprising a System-on-a-Chip (SOC), wherein an interrupt input pin of the SOC is electrically connected to an interrupt request pin of a physical layer chip; the apparatus comprises: The initialization module maps changes in the physical layer link state to the interrupt request pin during the initialization of the physical layer chip. The acquisition module is used to execute an interrupt handling process in response to the interrupt trigger signal of the interrupt request pin in order to acquire the current physical layer link status. The interrupt trigger signal is triggered by the change of the physical layer link status. The sending module is used to transmit the current physical layer link status to a preset application based on an inter-process communication mechanism, so that the preset application reports the current physical layer link status to the target controller.

10. An electronic device, characterized in that, The electronic device includes a Linux-based embedded device, which includes at least one of an automotive electronic control unit, an industrial IoT gateway, and an edge computing device. The electronic device includes: a memory and a processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-8.

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