Memory device for inputting and outputting data by sharing multiple channels

Abstract

The present disclosure relates to memory devices for inputting and outputting data through sharing multiple channels. A memory device includes a first core die including N first channels and a second core die including N second channels. The first channels of the first core die and the second channels of the second core die input and output data by receiving a common write command and a common read command.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0175953, filed on November 29, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Various embodiments of this disclosure relate to a memory device for inputting and outputting data using a wide bandwidth in a manner that shares commands among at least two of a plurality of channels included in a core die. Background Technology

[0003] Stacked memory systems (such as high-bandwidth memory (HBM) systems) are widely used in a variety of applications due to their improved bandwidth and energy efficiency. Unlike existing memory systems that utilize parallel data buses, stacked memory systems comprise a stacked memory device consisting of a base die and multiple core dies interconnected via through-silicon vias (TSVs). Each of the multiple core dies includes multiple channels. Each of the multiple channels can input and output data by performing write and read operations. Summary of the Invention

[0004] According to one embodiment of this disclosure, a memory device may include a first core die and a second core die. The first core die includes N first channels, and the second core die includes N second channels. The first and second channels can input data by receiving a common write command and output data by receiving a common read command.

[0005] According to one embodiment of this disclosure, a memory device may include: a first core die including N first channels, a second core die including N second channels, a third core die including N third channels, and a fourth core die including N fourth channels. The first and third channels can input first data by receiving a common write command and output first data by receiving a common read command. The second and fourth channels can input second data by receiving a common write command and output second data by receiving a common read command.

[0006] According to one embodiment of this disclosure, a memory device may include: a first core die including N first channels, a second core die including N second channels, a third core die including N third channels, and a fourth core die including N fourth channels. The first, second, third, and fourth channels can input and output data through shared write commands and shared read commands.

[0007] According to one embodiment of this disclosure, a memory device may include: a base die configured to output write commands and read commands, and configured to input and output first data and second data; a first memory column including a first core die and a second core die, wherein the first core die includes a plurality of first channels and the second core die includes a plurality of second channels; and a second memory column including a third core die and a fourth core die, wherein the third core die includes a plurality of third channels and the fourth core die includes a plurality of fourth channels. The first channels in the first core die and the second channels in the second core die can input and output the first data by sharing write commands and sharing read commands. The third channels in the third core die and the fourth channels in the fourth core die can input and output the second data by sharing write commands and sharing read commands. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an embodiment of a memory device according to the present disclosure.

[0009] Figure 2 It is shown Figure 1 A block diagram of an embodiment of the base die included in the memory device shown.

[0010] Figure 3 It is shown Figure 2 A block diagram of an embodiment of the memory controller included in the base die shown.

[0011] Figure 4 It is shown Figure 2 The diagram shows a block diagram of an embodiment of the data input / output circuitry included in the basic die shown.

[0012] Figure 5 It is shown Figure 1 A block diagram illustrating an embodiment of the channels included in each core die shown.

[0013] Figure 6 It is used to describe Figure 1 The diagram shows the operation of the base die and the core die.

[0014] Figure 7 It is used to describe Figure 1 The timing diagrams for the operations of the base die and core die are shown.

[0015] Figures 8 to 11 This is a diagram used to illustrate the operation of a memory device according to embodiments of the present disclosure.

[0016] Figure 12 This is a block diagram illustrating an embodiment of a memory system according to the present disclosure. Detailed Implementation

[0017] In the following detailed description, the term "preset" means that the value of a parameter is predetermined when the parameter is used in a process or algorithm. Depending on the embodiment, the value of a parameter may be set before or at the start of the process or algorithm, or while the process or algorithm is executing.

[0018] Terms such as "first" and "second," used to distinguish multiple components without indicating the number or order of components, are not limited to any particular component. For example, the first component can be called the second component, and vice versa.

[0019] When a component is referred to as "coupled" or "connected" to another component, it should be understood that these components can be directly coupled or connected to each other, or can be coupled or connected to each other through another component in between. Conversely, when a component is referred to as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other, with no other component in between.

[0020] "Logic high" and "logic low" are used to describe the logic level of a signal. A signal having a "logic high" is different from a signal having a "logic low". For example, when a signal having a first voltage corresponds to a signal having a "logic high", a signal having a second voltage can correspond to a signal having a "logic low". According to one embodiment, a "logic high" can be set to a voltage higher than a "logic low". According to one embodiment, the logic levels of a signal can be set to different logic levels or opposite logic levels. For example, in some embodiments, a signal having a logic high can be set to a logic low, while in other embodiments, a signal having a logic low can be set to a logic high.

[0021] The present disclosure is described in more detail below by way of examples. The examples are for illustrative purposes only, and the scope of the present disclosure is not limited by the examples.

[0022] Figure 1 An embodiment of the memory device 1 according to the present disclosure is shown. For example... Figure 1 As shown, the memory device 1 may include a base die 100 and a plurality of core dies 111, 112, 113, 114, 115, 116, 117 and 118.

[0023] The base die 100 may include a memory controller (MC) 101 and data input / output (DATA I / O) circuitry 103.

[0024] The memory controller 101 can generate commands for controlling multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118, i.e. Figure 2 The memory controller 101 can output commands WT and RD to multiple channels CH0 to CH15 included in multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. The memory controller 101 can simultaneously output commands WT or RD to at least two channels CH0 to CH15 included in multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. The memory controller 101 can output commands WT and RD for controlling internal operations (e.g., write operations to stored data and read operations to output data) of multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118.

[0025] After the write operation begins, the data input / output circuit 103 can output the data (i.e., Figure 2 The data input / output circuit 103 outputs data to multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. After a read operation begins, the data input / output circuit 103 can receive data from the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. Figure 2 Data in DATA.

[0026] The base die 100 can simultaneously output commands WT or RD to at least two channels of CH0 to CH15 among multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. The base die 100 can input and output data DATA through at least two channels of CH0 to CH15 among multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118.

[0027] Multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118 can be vertically stacked on base die 100. More specifically, core die 111 can be vertically stacked on base die 100. Core die 112 can be vertically stacked on core die 111. Core die 113 can be vertically stacked on core die 112. Core die 114 can be vertically stacked on core die 113. Core die 115 can be vertically stacked on core die 114. Core die 116 can be vertically stacked on core die 115. Core die 117 can be vertically stacked on core die 116. Core die 118 can be vertically stacked on core die 117.

[0028] Multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118 may include multiple channels CH0 through CH15. Core die 111 may include first channel CH0 through fourth channel CH3. Core die 112 may include fifth channel CH4 through eighth channel CH7. Core die 113 may include ninth channel CH8 through twelfth channel CH11. Core die 114 may include thirteenth channel CH12 through sixteenth channel CH15. Core die 115 may include first channel CH0 through fourth channel CH3. Core die 116 may include fifth channel CH4 through eighth channel CH7. Core die 117 may include ninth channel CH8 through twelfth channel CH11. Core die 118 may include thirteenth channel CH12 through sixteenth channel CH15. For ease of description, each of the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118 has been shown as including only four channels. However, in other embodiments, each of the multiple core dies may be implemented with a different number of channels, such as eight channels and sixteen channels.

[0029] The first channel CH0 of core die 111, the fifth channel CH4 of core die 112, the ninth channel CH8 of core die 113, and the thirteenth channel CH12 of core die 114 can share the path for input commands WT or RD. The second channel CH1 of core die 111, the sixth channel CH5 of core die 112, the tenth channel CH9 of core die 113, and the fourteenth channel CH13 of core die 114 can share the path for input commands WT or RD. The third channel CH2 of core die 111, the seventh channel CH6 of core die 112, the eleventh channel CH10 of core die 113, and the fifteenth channel CH14 of core die 114 can share the path for input commands WT or RD. The fourth channel CH3 of core die 111, the eighth channel CH7 of core die 112, the twelfth channel CH11 of core die 113, and the sixteenth channel CH15 of core die 114 can share the path for input commands WT or RD.

[0030] The first channel CH0 of core die 115, the fifth channel CH4 of core die 116, the ninth channel CH8 of core die 117, and the thirteenth channel CH12 of core die 118 can share the path for input commands WT or RD. The second channel CH1 of core die 115, the sixth channel CH5 of core die 116, the tenth channel CH9 of core die 117, and the fourteenth channel CH13 of core die 118 can share the path for input commands WT or RD. The third channel CH2 of core die 115, the seventh channel CH6 of core die 116, the eleventh channel CH10 of core die 117, and the fifteenth channel CH14 of core die 118 can share at least one path for input commands WT or RD. The fourth channel CH3 of core die 115, the eighth channel CH7 of core die 116, the twelfth channel CH11 of core die 117, and the sixteenth channel CH15 of core die 118 can share the path for input commands WT or RD.

[0031] The first channel CH0 of core die 111 and the first channel CH0 of core die 115 can share the path for input commands WT or RD. The second channel CH1 of core die 111 and the second channel CH1 of core die 115 can share the path for input commands WT or RD. The third channel CH2 of core die 111 and the third channel CH2 of core die 115 can share the path for input commands WT or RD. The fourth channel CH3 of core die 111 and the fourth channel CH3 of core die 115 can share the path for input commands WT or RD.

[0032] The fifth channel CH4 of core die 112 and the fifth channel CH4 of core die 116 can share the path for input commands WT or RD. The sixth channel CH5 of core die 112 and the sixth channel CH5 of core die 116 can share the path for input commands WT or RD. The seventh channel CH6 of core die 112 and the seventh channel CH6 of core die 116 can share the path for input commands WT or RD. The eighth channel CH7 of core die 112 and the eighth channel CH7 of core die 116 can share the path for input commands WT or RD.

[0033] Channel 9 CH8 of core die 113 and channel 9 CH8 of core die 117 can share the path for input commands WT or RD. Channel 10 CH9 of core die 113 and channel 10 CH9 of core die 117 can share the path for input commands WT or RD. Channel 110 of core die 113 and channel 110 of core die 117 can share the path for input commands WT or RD. Channel 12 CH11 of core die 113 and channel 12 CH11 of core die 117 can share the path for input commands WT or RD.

[0034] Channel 13 (CH12) of core die 114 and channel 13 (CH12) of core die 118 can share the path for input commands WT or RD. Channel 14 (CH13) of core die 114 and channel 14 (CH13) of core die 118 can share the path for input commands WT or RD. Channel 15 (CH14) of core die 114 and channel 15 (CH15) of core die 118 can share the path for input commands WT or RD.

[0035] The first channel CH0 to the fourth channel CH3 of core die 111, the fifth channel CH4 to the eighth channel CH7 of core die 112, the ninth channel CH8 to the twelfth channel CH11 of core die 113, and the thirteenth channel CH12 to the sixteenth channel CH15 of core die 114 can form a first memory column RANK0 for setting bandwidth. The first channel CH0 to the fourth channel CH3 of core die 115, the fifth channel CH4 to the eighth channel CH7 of core die 116, the ninth channel CH8 to the twelfth channel CH11 of core die 117, and the thirteenth channel CH12 to the sixteenth channel CH15 of core die 118 can form a second memory column RANK1 for setting bandwidth.

[0036] Each of the first channel CH0 to the fourth channel CH3 of core die 111, each of the fifth channel CH4 to the eighth channel CH7 of core die 112, each of the ninth channel CH8 to the twelfth channel CH11 of core die 113, each of the thirteenth channel CH12 to the sixteenth channel CH15 of core die 114, each of the first channel CH0 to the fourth channel CH3 of core die 115, each of the fifth channel CH4 to the eighth channel CH7 of core die 116, each of the ninth channel CH8 to the twelfth channel CH11 of core die 117, and each of the thirteenth channel CH12 to the sixteenth channel CH15 of core die 118 may each include multiple pseudo-channels that operate independently to increase bandwidth. For example, Figure 5 Pseudo-channels P0 and P1 are shown. Write and read operations can be performed independently for each of the multiple pseudo-channels (e.g., P0 and P1) included in each of the first channel CH0 to the sixteenth channel CH15.

[0037] Figure 2 This is a block diagram illustrating an embodiment of the base die 100. (As shown) Figure 2 As shown, the base die 100 includes a memory controller 101, a data input / output circuit 103, a first physical layer (1st PHY) 105, and a second physical layer (2nd PHY) 107.

[0038] The memory controller 101 can decode the command address (i.e. Figure 3 The memory controller 101 generates write commands WT and read commands RD using the CA (logic level combination) in the memory. The write command WT is enabled when a command address CA with a logic level combination for performing a write operation is input. The memory controller 101 also generates read commands RD, which are enabled when a command address CA with a logic level combination for performing a read operation is input. The memory controller 101 can output the write commands WT and read commands RD to multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118 via the first physical layer 105. The memory controller 101 can also output the write commands WT and read commands RD to multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118 via the second physical layer 107.

[0039] exist Figure 3In this system, the memory controller 101 can generate a first internal clock ICLK, a second internal clock QCLK, a third internal clock IBCLK, and a fourth internal clock QBCLK by dividing the frequency of the clock CLK. The memory controller 101 can also sequentially generate these four internal clocks by dividing the frequency of the clock CLK.

[0040] After the write operation begins, the memory controller 101 can, according to Figure 3 The memory controller 101 generates input data IND from external data ED. After a write operation begins, the memory controller 101 can generate input data IND by correcting any errors in the external data ED. After a read operation begins, the memory controller 101 can generate external data ED based on output data OUTD. After a read operation begins, the memory controller 101 can generate external data ED by correcting any errors in the output data OUTD.

[0041] After a write operation begins, the data input / output circuit 103 can generate data DATA synchronously with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK based on the input data IND. The data input / output circuit 103 can also generate data DATA by serializing the input data IND synchronously with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK after the write operation begins. The data input / output circuit 103 can also output the data DATA to multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118 via the first physical layer 105 and the second physical layer 107 after the write operation begins. The data DATA can be common data comprising multiple bits and stored in memory circuitry.

[0042] After the read operation begins, the data input / output circuit 103 can generate output data OUTD synchronously with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK based on the data DATA. After the read operation begins, the data input / output circuit 103 can also generate output data OUTD by deserializing the data DATA synchronously with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK. After the read operation begins, the data input / output circuit 103 can receive data DATA from multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118 through the first physical layer 105 and the second physical layer 107.

[0043] The first physical layer 105 can be electrically connected to the memory controller 101, the data input / output circuit 103, and multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. The first physical layer 105 can be electrically connected to vias (TSVs) penetrating the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. The first physical layer 105 can receive write commands WT and read commands RD from the memory controller 101. The first physical layer 105 can output the write commands WT and read commands RD to the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. After a write operation begins, the first physical layer 105 can receive data DATA from the data input / output circuit 103. After a write operation begins, the first physical layer 105 can output data DATA to multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. After a read operation begins, the first physical layer 105 can receive data DATA from the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. After a read operation begins, the first physical layer 105 can output data DATA to the data input / output circuit 103. The first physical layer 105 can be electrically connected to the first channel CH0 and the second channel CH1 of core die 111, the fifth channel CH4 and the sixth channel CH5 of core die 112, the ninth channel CH8 and the tenth channel CH9 of core die 113, the thirteenth channel CH12 and the fourteenth channel CH13 of core die 114, the first channel CH0 and the second channel CH1 of core die 115, the fifth channel CH4 and the sixth channel CH5 of core die 116, the ninth channel CH8 and the tenth channel CH9 of core die 117, and the thirteenth channel CH12 and the fourteenth channel CH13 of core die 118.

[0044] The second physical layer 107 can be electrically connected to the memory controller 101, the data input / output circuit 103, and multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. The second physical layer 107 can be electrically connected to vias (TSVs) penetrating the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. The second physical layer 107 can receive write commands WT and read commands RD from the memory controller 101. The second physical layer 107 can output the write commands WT and read commands RD to the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. After a write operation begins, the second physical layer 107 can receive data DATA from the data input / output circuit 103. After a write operation begins, the second physical layer 107 can output data DATA to multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. After a read operation begins, the second physical layer 107 can receive data DATA from the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118. After a read operation begins, the second physical layer 107 can output data DATA to the data input / output circuit 103. The second physical layer 107 can be electrically connected to the third channel CH2 and the fourth channel CH3 of core die 111, the seventh channel CH6 and the eighth channel CH7 of core die 112, the eleventh channel CH10 and the twelfth channel CH11 of core die 113, the fifteenth channel CH14 and the sixteenth channel CH15 of core die 114, the third channel CH2 and the fourth channel CH3 of core die 115, the seventh channel CH6 and the eighth channel CH7 of core die 116, the eleventh channel CH10 and the twelfth channel CH11 of core die 117, and the fifteenth channel CH14 and the sixteenth channel CH15 of core die 118.

[0045] The first physical layer 105 and the second physical layer 107 can be implemented using physical layers (PHYs), which are responsible for the generation, transmission, reception and physical connection of signals and data between the base die 100 and multiple core dies 111 to 118.

[0046] Figure 3 It is shown Figure 2 The diagram shows a block diagram of an embodiment of the memory controller 101 included in the base die 100. The memory controller 101 may include a write / read control circuit (WT / RD CTR) 110, an internal clock generation circuit (ICLK GEN) 120, and an error correction circuit (ECC) 130.

[0047] The write / read control circuit 110 can generate a write command WT and a read command RD by decoding the command address CA. The write command WT is enabled when the command address CA, having a logic level combination for performing a write operation, is input. Similarly, the write / read control circuit 110 can generate a read command RD, enabled when the command address CA, having a logic level combination for performing a read operation, is input. The command address CA can include multiple bits, can have a logic level combination for controlling each of the write and read operations of each of the multiple core dies 111, 112, 113, 114, 115, 116, 117, and 118, and can be input from an external device.

[0048] The internal clock generation circuit 120 can generate a first internal clock ICLK, a second internal clock QCLK, a third internal clock IBCLK, and a fourth internal clock QBCLK based on clock CLK. The internal clock generation circuit 120 can generate the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK by dividing the frequency of clock CLK. For example, the internal clock generation circuit 120 can generate the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK by dividing the frequency of clock CLK in half, with each internal clock having a frequency that is half the frequency of clock CLK. In this case, the generation time of the second internal clock QCLK can be half the period of clock CLK later than the phase of the first internal clock ICLK. The generation time of the third internal clock IBCLK can be half the period of clock CLK later than the phase of the second internal clock QCLK. The generation time of the fourth internal clock QBCLK can be half the period of clock CLK later than the phase of the third internal clock IBCLK. Therefore, the third internal clock IBCLK and the first internal clock ICLK can be generated with phases out of phase with respect to each other. The fourth internal clock QBCLK and the second internal clock QCLK can also be generated with phases out of phase with respect to each other. The clock CLK can be set as a periodically switching signal to synchronize the operation of the base die 100 and multiple core dies 111, 112, 113, 114, 115, 116, 117 and 118.

[0049] After a write operation begins, the error correction circuit 130 can generate input data IND based on external data ED. The error correction circuit 130 can generate input data IND by correcting any errors in the external data ED after the write operation begins. After a read operation begins, the error correction circuit 130 can generate external data ED based on output data OUTD. The error correction circuit 130 can generate external data ED by correcting any errors in the output data OUTD after the read operation begins. In one embodiment, the error correction circuit 130 can be implemented using a common ECC circuit that corrects any errors in the data using error correction codes (ECC). The operation of the error correction circuit 130 in correcting any errors in the data can be configured to generate data by inverting the bits of the data with errors. Each of the external data ED, input data IND, and output data OUTD can be common data comprising multiple bits and stored in memory circuitry.

[0050] Figure 4 It is shown Figure 2 The block diagram shows an embodiment of the data input / output circuitry 103 included in the base die 100. The data input / output circuitry 103 may include a serializer 210 and a deserializer 220.

[0051] After the write operation begins, the serialization circuit 210 can receive input data IND synchronously with any one of the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK. The serialization circuit 210 can generate data DATA by serializing the input data IND after the write operation begins.

[0052] After the read operation begins, the deserialization circuit 220 can receive data DATA synchronously with any one of the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK, and the fourth internal clock QBCLK. The deserialization circuit 220 can generate output data OUTD by deserializing the received data DATA after the read operation begins.

[0053] Figure 5 This is a block diagram illustrating an embodiment of the channels included in each of core dies 111 to 118.

[0054] like Figure 5As shown, the core die 111 may include a first channel CH0 to a fourth channel CH3. Each of the first channel CH0 to the fourth channel CH3 may include a first pseudo-channel P0 and a second pseudo-channel P1 that operate independently to increase bandwidth. Write and read operations can be performed independently for each of the first pseudo-channel P0 and the second pseudo-channel P1.

[0055] Core dies 112, 113, 114, 115, 116, 117 and 118 can be implemented using the same construction as core die 111.

[0056] Figure 6 This is a diagram used to describe the operation of the base die 100 and the core dies 111 to 114.

[0057] The memory controller 101 can simultaneously output the write command WT to the first channel CH0 of core die 111 and the fifth channel CH4 of core die 112 via the first physical layer 105. After the write operation begins, the data input / output circuit 103 can output 256 bits of data DATA to the first channel CH0 of core die 111 via the first physical layer 105. The first channel CH0 of core die 111 can store 256 bits of data DATA. After the write operation begins, the data input / output circuit 103 can output 256 bits of data DATA to the fifth channel CH4 of core die 112 via the first physical layer 105. The fifth channel CH4 of core die 112 can store 256 bits of data DATA.

[0058] The memory controller 101 can simultaneously output the write command WT to channel CH8 (ninth channel) of core die 113 and channel CH12 (thirteenth channel) of core die 114 via the first physical layer 105. After the write operation begins, the data input / output circuit 103 can output 256 bits of data DATA to channel CH8 (ninth channel) of core die 113 via the first physical layer 105. Channel CH8 (ninth channel) of core die 113 can store 256 bits of data DATA. After the write operation begins, the data input / output circuit 103 can output 256 bits of data DATA to channel CH12 (thirteenth channel) of core die 114 via the first physical layer 105. Channel CH12 (thirteenth channel) of core die 114 can store 256 bits of data DATA.

[0059] The memory controller 101 can simultaneously output the read command RD to the first channel CH0 of core die 111 and the fifth channel CH4 of core die 112 via the first physical layer 105. The first channel CH0 of core die 111 can output 256 bits of data DATA via the first physical layer 105. The data input / output circuit 103 can receive the 256 bits of data DATA output from the first channel CH0 of core die 111 via the first physical layer 105 after the read operation begins, and can generate output data OUTD by deserializing the data DATA. The memory controller 101 can generate external data ED by correcting any errors in the output data OUTD after the read operation begins, and can output the external data ED to an external device. The fifth channel CH4 of core die 112 can output 256 bits of data DATA via the first physical layer 105. The data input / output circuit 103 can receive 256 bits of data DATA output from the fifth channel CH4 of the core die 112 via the first physical layer 105 after the read operation begins, and can generate output data OUTD by deserializing the data DATA. The memory controller 101 can generate external data ED by correcting any errors in the output data OUTD after the read operation begins, and can output the external data ED to an external device.

[0060] The memory controller 101 can simultaneously output the read command RD to channel CH8 of core die 113 and channel CH12 of core die 114 via the first physical layer 105. Channel CH8 of core die 113 can output 256 bits of data DATA via the first physical layer 105. The data input / output circuit 103 can receive the 256 bits of data DATA output from channel CH8 of core die 113 via the first physical layer 105 after the read operation begins, and can generate output data OUTD by deserializing the data DATA. The memory controller 101 can generate external data ED by correcting any errors in the output data OUTD after the read operation begins, and can output the external data ED to an external device. Channel CH12 of core die 114 can output 256 bits of data DATA via the first physical layer 105. The data input / output circuit 103 can receive 256 bits of data DATA output from the thirteenth channel CH12 of the core die 114 via the first physical layer 105 after the read operation begins, and can generate output data OUTD by deserializing the data DATA. The memory controller 101 can generate external data ED by correcting any errors in the output data OUTD after the read operation begins, and can output the external data ED to an external device.

[0061] In one embodiment of this disclosure, the data DATA has been implemented such that the data DATA is input and output in 256 bits, but the data DATA can be implemented in a variety of numbers of bits, such as 128 bits, 512 bits or 1024 bits.

[0062] As described above, since at least two of the multiple channels included in the multiple core dies 111 to 118 input and output data respectively by sharing the command WT or RD, the memory device 1 can input and output data DATA with a wider bandwidth (512 bits) than the bandwidth (256 bits) that data DATA passes through when inputting and outputting through a single channel.

[0063] Figure 7 This is a timing diagram describing the operation of the base die 100 and the core dies 111 and 112. (Refer to...) Figure 7 The operation of the base die 100 and the core die 111 will be described below. In this case, the read operation for the first channel CH0 of the core die 111 and the fifth channel CH4 of the core die 112 is described as follows.

[0064] At time T1, memory controller 101 generates read command RD, which is enabled when a command address CA with a combination of logic levels for performing a read operation is input.

[0065] The memory controller 101 outputs the read command RD simultaneously to the first channel CH0 of the core die 111 and the fifth channel CH4 of the core die 112 through the first physical layer 105.

[0066] At time T2, memory controller 101 generates a first internal clock ICLK by dividing the frequency of clock CLK.

[0067] The data input / output circuit 103 receives 256 bits of data DATA generated by the first pseudo-channel P0 included in the first channel CH0 of the core die 111 synchronously with the first internal clock ICLK, and generates output data OUTD by deserializing the data DATA. After the read operation begins, the memory controller 101 generates external data ED by correcting any errors in the output data OUTD, and outputs the external data ED to an external device.

[0068] At time T3, memory controller 101 generates a second internal clock QCLK by dividing the frequency of clock CLK.

[0069] The data input / output circuit 103 receives 256 bits of data DATA generated by the second pseudo-channel P1 included in the first channel CH0 of the core die 111 in sync with the second internal clock QCLK, and generates output data OUTD by deserializing the data DATA. After the read operation begins, the memory controller 101 generates external data ED by correcting any errors in the output data OUTD, and outputs the external data ED to an external device.

[0070] At time T4, memory controller 101 generates a third internal clock IBCLK by dividing the frequency of clock CLK.

[0071] The data input / output circuit 103 receives 256 bits of data DATA generated by the first pseudo-channel P0, included in the fifth channel CH4 of the core die 112, synchronously with the third internal clock IBCLK, and generates output data OUTD by deserializing the data DATA. After the read operation begins, the memory controller 101 generates external data ED by correcting any errors in the output data OUTD and outputs the external data ED to an external device.

[0072] At time T5, memory controller 101 generates a fourth internal clock QBCLK by dividing the CLK frequency of the clock.

[0073] The data input / output circuit 103 receives 256 bits of data DATA generated by the second pseudo-channel P1, included in the fifth channel CH4 of the core die 112, synchronously with the fourth internal clock QBCLK, and generates output data OUTD by deserializing the data DATA. After the read operation begins, the memory controller 101 generates external data ED by correcting any errors in the output data OUTD and outputs the external data ED to an external device.

[0074] As described above, since at least two of the multiple channels included in the multiple core dies 111 to 118 input and output data respectively by sharing the command WT or RD, the memory device 1 can input and output data DATA with a wider bandwidth (512 bits) than the bandwidth (256 bits) through which data DATA is input and output through one channel.

[0075] Figure 8 This is a diagram illustrating the operation of a memory device 1 according to an embodiment of the present disclosure. (Refer to...) Figure 8The operation of memory device 1 will be described below. In this case, the write and read operations for the first channel CH0 of core die 111 and the fifth channel CH4 of core die 112, which are adjacent to each other, and the eleventh channel CH10 of core die 113 and the fifteenth channel CH14 of core die 114, which are adjacent to each other, are described as follows.

[0076] The memory controller 101 of the base die 100 can simultaneously output the write operation command CMD to the first channel CH0 of the core die 111 and the fifth channel CH4 of the core die 112 via the first physical layer 105. The memory controller 101 of the base die 100 can simultaneously output the write operation command CMD to the eleventh channel CH10 of the core die 113 and the fifteenth channel CH14 of the core die 114 via the second physical layer 107. Figure 8 The CMD command shown can include write commands that perform write operations, i.e. Figure 2 WT in the middle.

[0077] The first channel CH0 of core die 111 and the fifth channel CH4 of core die 112 are adjacent channels. The eleventh channel CH10 of core die 113 and the fifteenth channel CH14 of core die 114 are adjacent channels.

[0078] After the write operation begins, the data input / output circuit 103 of the base die 100 can output 256 bits of data DATA to the first channel CH0 of the core die 111 and the fifth channel CH4 of the core die 112 via the first physical layer 105. After the write operation begins, the data input / output circuit 103 of the base die 100 can output 256 bits of data DATA to the eleventh channel CH10 of the core die 113 and the fifteenth channel CH14 of the core die 114 via the second physical layer 107.

[0079] The first channel CH0 of core die 111 can store 256 bits of data DATA received through the first physical layer 105 after a write operation begins. The fifth channel CH4 of core die 112 can also store 256 bits of data DATA received through the first physical layer 105 after a write operation begins. The first channel CH0 of core die 111 and the fifth channel CH4 of core die 112 can store a combined 512 bits of data DATA after a single write operation begins.

[0080] The eleventh channel CH10 of core die 113 can store 256 bits of data DATA received via the second physical layer 107 after a write operation begins. The fifteenth channel CH14 of core die 114 can also store 256 bits of data DATA received via the second physical layer 107 after a write operation begins. The eleventh channel CH10 of core die 113 and the fifteenth channel CH14 of core die 114 can store a combined 512 bits of data DATA after a single write operation begins.

[0081] The memory controller 101 of the base die 100 can simultaneously output the read operation command CMD to the first channel CH0 of the core die 111 and the fifth channel CH4 of the core die 112 via the first physical layer 105. The memory controller 101 of the base die 100 can simultaneously output the read operation command CMD to the eleventh channel CH10 of the core die 113 and the fifteenth channel CH14 of the core die 114 via the second physical layer 107. Figure 8 The CMD command shown can include a read command that performs a read operation, i.e. Figure 2 RD in the middle.

[0082] After a read operation begins, the first channel CH0 of core die 111 can output 256 bits of data DATA through the first physical layer 105. After a read operation begins, the fifth channel CH4 of core die 112 can also output 256 bits of data DATA through the first physical layer 105. The first channel CH0 of core die 111 and the fifth channel CH4 of core die 112 can output a combined 512 bits of data DATA after a single read operation begins.

[0083] After a read operation begins, channel 110 of core die 113 can output 256 bits of data DATA through the second physical layer 107. Similarly, channel 15 of core die 114 can output 256 bits of data DATA through the second physical layer 107 after a read operation begins. Channels 110 of core die 113 and 15 of core die 114 can output a combined 512 bits of data DATA after a single read operation begins.

[0084] After the read operation begins, the data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the first channel CH0 of the core die 111 through the first physical layer 105. After the read operation begins, the data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the fifth channel CH4 of the core die 112 through the first physical layer 105.

[0085] After the read operation begins, the data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the eleventh channel CH10 of the core die 113 via the second physical layer 107. Similarly, after the read operation begins, the data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the fifteenth channel CH14 of the core die 114 via the second physical layer 107.

[0086] Since two adjacent channels in the multiple channels included in the multiple core dies 111 to 118 input and output data respectively by sharing the command CMD, the memory device 1 can input and output data DATA with a wider bandwidth (512 bits) than the bandwidth (256 bits) that data DATA passes through when inputting and outputting through a single channel.

[0087] Figure 9 This is a diagram illustrating the operation of a memory device 1 according to an embodiment of the present disclosure. (Refer to...) Figure 9 The operation of memory device 1 is described. In this case, the write and read operations for the first channel CH0 of core die 111 and the ninth channel CH8 of core die 113, which are spaced apart from each other, and the seventh channel CH6 of core die 112 and the fifteenth channel CH14 of core die 114, which are spaced apart from each other, are described as follows.

[0088] The memory controller 101 of the base die 100 can output the write operation command CMD to the first channel CH0 of the core die 111 and the ninth channel CH8 of the core die 113 via the first physical layer 105. The memory controller 101 of the base die 100 can output the write operation command CMD to the seventh channel CH6 of the core die 112 and the fifteenth channel CH14 of the core die 114 via the second physical layer 107. Figure 9 The CMD command shown can include write commands that perform write operations, i.e. Figure 2 WT in the middle.

[0089] The first channel CH0 of core die 111 and the ninth channel CH8 of core die 113 are separated from each other by core die 112. The seventh channel CH6 of core die 112 and the fifteenth channel CH14 of core die 114 are separated from each other by core die 113.

[0090] After the write operation begins, the data input / output circuit 103 of the base die 100 can output 256 bits of data DATA to the first channel CH0 of the core die 111 and to the ninth channel CH8 of the core die 113 via the first physical layer 105. After the write operation begins, the data input / output circuit 103 of the base die 100 can output 256 bits of data DATA to the seventh channel CH6 of the core die 112 and to the fifteenth channel CH14 of the core die 114 via the second physical layer 107.

[0091] The first channel CH0 of core die 111 can store 256 bits of data DATA received through the first physical layer 105 after a write operation begins. The ninth channel CH8 of core die 113 can also store 256 bits of data DATA received through the first physical layer 105 after a write operation begins. The first channel CH0 of core die 111 and the ninth channel CH8 of core die 113 can store a combined 512 bits of data DATA after a single write operation begins.

[0092] The seventh channel CH6 of core die 112 can store 256 bits of data DATA received via the second physical layer 107 after a write operation begins. The fifteenth channel CH14 of core die 114 can also store 256 bits of data DATA received via the second physical layer 107 after a write operation begins. The seventh channel CH6 of core die 112 and the fifteenth channel CH14 of core die 114 can store a combined 512 bits of data DATA after a single write operation begins.

[0093] The memory controller 101 of the base die 100 can output the command CMD for read operations to the first channel CH0 of the core die 111 and the ninth channel CH8 of the core die 113 via the first physical layer 105. The memory controller 101 of the base die 100 can output the command CMD for read operations to the seventh channel CH6 of the core die 112 and the fifteenth channel CH14 of the core die 114 via the second physical layer 107. Figure 9 The CMD command shown can include a read command that performs a read operation, i.e. Figure 2 RD in the middle.

[0094] After a read operation begins, the first channel CH0 of core die 111 can output 256 bits of data DATA through the first physical layer 105. Similarly, the ninth channel CH8 of core die 113 can output 256 bits of data DATA through the first physical layer 105 after a read operation begins. The first channel CH0 of core die 111 and the ninth channel CH8 of core die 113 can output a combined 512 bits of data DATA after a single read operation begins.

[0095] After a read operation begins, channel CH6 of core die 112 can output 256 bits of data DATA through the second physical layer 107. Similarly, channel CH14 of core die 114 can output 256 bits of data DATA through the second physical layer 107 after a read operation begins. Channels CH6 of core die 112 and CH14 of core die 114 can output a combined 512 bits of data DATA after a single read operation begins.

[0096] After the read operation begins, the data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the first channel CH0 of the core die 111 through the first physical layer 105. After the read operation begins, the data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the ninth channel CH8 of the core die 113 through the first physical layer 105.

[0097] After the read operation begins, the data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the seventh channel CH6 of the core die 112 via the second physical layer 107. Similarly, after the read operation begins, the data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the fifteenth channel CH14 of the core die 114 via the second physical layer 107.

[0098] As described above, since two channels spaced apart from each other in the multiple channels included in the multiple core dies 111 to 118 input and output data respectively by sharing the command CMD, the memory device 1 can input and output data DATA with a wider bandwidth (512 bits) than the bandwidth (256 bits) through which data DATA is input and output by a single channel.

[0099] Figure 10 This is a diagram illustrating the operation of a memory device 1 according to an embodiment of the present disclosure. (Refer to...) Figure 10The operation of memory device 1 is described below. Write and read operations are performed on the second channel CH1 of core die 111, the sixth channel CH5 of core die 112, the tenth channel CH9 of core die 113 and the fourteenth channel CH13 of core die 114, which are adjacent to each other, as well as write and read operations are performed on the fourth channel CH3 of core die 111, the eighth channel CH7 of core die 112, the twelfth channel CH11 of core die 113 and the sixteenth channel CH15 of core die 114, which are adjacent to each other.

[0100] The memory controller 101 of the base die 100 can output the write operation command CMD to the second channel CH1 of the core die 111, the sixth channel CH5 of the core die 112, the tenth channel CH9 of the core die 113, and the fourteenth channel CH13 of the core die 114 via the first physical layer 105. The memory controller 101 of the base die 100 can output the write operation command CMD to the fourth channel CH3 of the core die 111, the eighth channel CH7 of the core die 112, the twelfth channel CH11 of the core die 113, and the sixteenth channel CH15 of the core die 114 via the second physical layer 107. Figure 10 The CMD command shown can include write commands that perform write operations, i.e. Figure 2 WT in the middle.

[0101] The second channel CH1 of core die 111, the sixth channel CH5 of core die 112, the tenth channel CH9 of core die 113, and the fourteenth channel CH13 of core die 114 are adjacent channels. The fourth channel CH3 of core die 111, the eighth channel CH7 of core die 112, the twelfth channel CH11 of core die 113, and the sixteenth channel CH15 of core die 114 are adjacent channels.

[0102] After the write operation begins, the data input / output circuit 103 of the base die 100 can output 256 bits of data DATA to the second channel CH1 of the core die 111, the sixth channel CH5 of the core die 112, the tenth channel CH9 of the core die 113, and the fourteenth channel CH13 of the core die 114 via the first physical layer 105. After the write operation begins, the data input / output circuit 103 of the base die 100 can output 256 bits of data DATA to the fourth channel CH3 of the core die 111, the eighth channel CH7 of the core die 112, the twelfth channel CH11 of the core die 113, and the sixteenth channel CH15 of the core die 114 via the second physical layer 107.

[0103] The second channel CH1 of core die 111 can store 256 bits of data DATA received through the first physical layer 105 after the start of a write operation. The sixth channel CH5 of core die 112 can store 256 bits of data DATA received through the first physical layer 105 after the start of a write operation. The tenth channel CH9 of core die 113 can store 256 bits of data DATA received through the first physical layer 105 after the start of a write operation. The fourteenth channel CH13 of core die 114 can store 256 bits of data DATA received through the first physical layer 105 after the start of a write operation. The second channel CH1 of core die 111, the sixth channel CH5 of core die 112, the tenth channel CH9 of core die 113, and the fourteenth channel CH13 of core die 114 can store a combined 1024 bits of data DATA after the start of a single write operation.

[0104] The fourth channel CH3 of core die 111 can store 256 bits of data DATA received through the second physical layer 107 after a write operation begins. The eighth channel CH7 of core die 112 can store 256 bits of data DATA received through the second physical layer 107 after a write operation begins. The twelfth channel CH11 of core die 113 can store 256 bits of data DATA received through the second physical layer 107 after a write operation begins. The sixteenth channel CH15 of core die 114 can store 256 bits of data DATA received through the second physical layer 107 after a write operation begins. The fourth channel CH3 of core die 111, the eighth channel CH7 of core die 112, the twelfth channel CH11 of core die 113, and the sixteenth channel CH15 of core die 114 can store a combined 1024 bits of data DATA after a single write operation begins.

[0105] The memory controller 101 of the base die 100 can output the command CMD for read operations to the second channel CH1 of the core die 111, the sixth channel CH5 of the core die 112, the tenth channel CH9 of the core die 113, and the fourteenth channel CH13 of the core die 114 via the first physical layer 105. The memory controller 101 of the base die 100 can output the command CMD for read operations to the fourth channel CH3 of the core die 111, the eighth channel CH7 of the core die 112, the twelfth channel CH11 of the core die 113, and the sixteenth channel CH15 of the core die 114 via the second physical layer 107. Figure 10 The CMD command shown can include a read command that performs a read operation, i.e. Figure 2 RD in the middle.

[0106] The second channel CH1 of core die 111 can output 256 bits of data DATA through the first physical layer 105 after a read operation begins. The sixth channel CH5 of core die 112 can output 256 bits of data DATA through the first physical layer 105 after a read operation begins. The tenth channel CH9 of core die 113 can output 256 bits of data DATA through the first physical layer 105 after a read operation begins. The fourteenth channel CH13 of core die 114 can output 256 bits of data DATA through the first physical layer 105 after a read operation begins. The second channel CH1 of core die 111, the sixth channel CH5 of core die 112, the tenth channel CH9 of core die 113, and the fourteenth channel CH13 of core die 114 can output a combined 1024 bits of data DATA after a single read operation begins.

[0107] Core die 111's fourth channel CH3 can output 256 bits of data DATA through the second physical layer 107 after a read operation begins. Core die 112's eighth channel CH7 can output 256 bits of data DATA through the second physical layer 107 after a read operation begins. Core die 113's twelfth channel CH11 can output 256 bits of data DATA through the second physical layer 107 after a read operation begins. Core die 114's sixteenth channel CH15 can output 256 bits of data DATA through the second physical layer 107 after a read operation begins. Core die 111's fourth channel CH3, core die 112's eighth channel CH7, core die 113's twelfth channel CH11, and core die 114's sixteenth channel CH15 can output a combined 1024 bits of data DATA after a single read operation begins.

[0108] The data input / output circuit 103 of the base chip 100 can receive 256 bits of data DATA from the second channel CH1 of the core die 111, the sixth channel CH5 of the core die 112, the tenth channel CH9 of the core die 113, and the fourteenth channel CH13 of the core die 114 through the first physical layer 105 after the read operation begins.

[0109] The data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the fourth channel CH3 of the core die 111, the eighth channel CH7 of the core die 112, the twelfth channel CH11 of the core die 113, and the sixteenth channel CH15 of the core die 114 through the second physical layer 107 after the read operation begins.

[0110] As described above, since four adjacent channels in the multiple channels included in the multiple core dies 111 to 118 input and output data respectively by sharing the command CMD, the memory device 1 can input and output data DATA with a wider bandwidth (1024 bits) than the bandwidth (256 bits) through which data DATA is input and output by a single channel.

[0111] Figure 11 This is a diagram illustrating the operation of a memory device 1 according to an embodiment of the present disclosure. (Refer to...) Figure 11The operation of memory device 1 is described. In this case, write and read operations for the second channel CH1 of core die 111 and the sixth channel CH5 of core die 112 included in the first memory column RANK0, and write and read operations for the fourth channel CH3 of core die 115 and the eighth channel CH7 of core die 116 included in the second memory column RANK1 are described as follows.

[0112] The memory controller 101 of the base die 100 can output the write operation command CMD to the second channel CH1 of the core die 111 and the sixth channel CH5 of the core die 112 via the first physical layer 105. The memory controller 101 of the base die 100 can output the write operation command CMD to the fourth channel CH3 of the core die 115 and the eighth channel CH7 of the core die 116 via the second physical layer 107. Figure 11 The CMD command shown can include write commands that perform write operations, i.e. Figure 2 WT in the middle.

[0113] The data input / output circuit 103 of the base die 100 can output 256 bits of data DATA to the second channel CH1 of the core die 111 and to the sixth channel CH5 of the core die 112 via the first physical layer 105 after the write operation begins. The data input / output circuit 103 of the base die 100 can also output 256 bits of data DATA to the fourth channel CH3 of the core die 115 and to the eighth channel CH7 of the core die 116 via the second physical layer 107 after the write operation begins.

[0114] The second channel CH1 of core die 111 can store 256 bits of data DATA received through the first physical layer 105 after the start of a write operation. The sixth channel CH5 of core die 112 can also store 256 bits of data DATA received through the first physical layer 105 after the start of a write operation. The second channel CH1 of core die 111 and the sixth channel CH5 of core die 112 can store a combined 512 bits of data DATA after the start of a single write operation.

[0115] The fourth channel CH3 of core die 115 can store 256 bits of data DATA received via the second physical layer 107 after a write operation begins. The eighth channel CH7 of core die 116 can also store 256 bits of data DATA received via the second physical layer 107 after a write operation begins. The fourth channel CH3 of core die 115 and the eighth channel CH7 of core die 116 can store a combined 512 bits of data DATA after a single write operation begins.

[0116] The memory controller 101 of the base die 100 can output the command CMD for read operations to the second channel CH1 of the core die 111 and the sixth channel CH5 of the core die 112 via the first physical layer 105. The memory controller 101 of the base die 100 can output the command CMD for read operations to the fourth channel CH3 of the core die 115 and the eighth channel CH7 of the core die 116 via the second physical layer 107. Figure 11 The CMD command shown can include a read command that performs a read operation, i.e. Figure 2 RD in the middle.

[0117] The second channel CH1 of core die 111 can output 256 bits of data DATA through the first physical layer 105 after a read operation begins. The sixth channel CH5 of core die 112 can also output 256 bits of data DATA through the first physical layer 105 after a read operation begins. The second channel CH1 of core die 111 and the sixth channel CH5 of core die 112 can output a combined 512 bits of data DATA after a single read operation begins.

[0118] The fourth channel CH3 of core die 115 can output 256 bits of data DATA through the second physical layer 107 after a read operation begins. The eighth channel CH7 of core die 116 can also output 256 bits of data DATA through the second physical layer 107 after a read operation begins. The fourth channel CH3 of core die 115 and the eighth channel CH7 of core die 116 can output a combined 512 bits of data DATA after a single read operation begins.

[0119] The data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the second channel CH1 of the core die 111 through the first physical layer 105 after the read operation begins. The data input / output circuit 103 of the base die 100 can also receive 256 bits of data DATA from the sixth channel CH5 of the core die 112 through the first physical layer 105 after the read operation begins.

[0120] The data input / output circuit 103 of the base die 100 can receive 256 bits of data DATA from the fourth channel CH3 of the core die 115 via the second physical layer 107 after the read operation begins. The data input / output circuit 103 of the base die 100 can also receive 256 bits of data DATA from the eighth channel CH7 of the core die 116 via the second physical layer 107 after the read operation begins.

[0121] Since two of the multiple channels included in the multiple core dies 111 to 118 input and output data respectively via a shared command CMD, the memory device 1 can input and output data DATA with a wider bandwidth (512 bits) than the bandwidth (256 bits) that data DATA passes through a single channel for input and output.

[0122] Figure 12 This is a block diagram illustrating an embodiment of the memory system 2 according to the present disclosure.

[0123] like Figure 12 As shown, the memory system 2 includes a printed circuit board (PCB) 11, a substrate 13, an interposer 15, a memory device 17, and a processor 19.

[0124] PCB 11 interconnects multiple electronic components to form an electronic circuit (not shown). The electronic circuit may include a memory system 2. Copper layers, solder masks, silkscreens, etc., may be formed on PCB 11. Circuit paths for transmitting signals or electricity are formed in the copper layers. Solder masks prevent damage to the circuit and protect specific areas where components may be soldered. Furthermore, silkscreens indicate the location or information of electronic components in the form of characters or symbols printed on the surface of PCB 11.

[0125] The substrate 13 is formed on the PCB 11, for example, via bump pads 111, and mechanically supports the interposer 15, memory device 17, and processor 19. The substrate 13 typically serves as an insulator, i.e., the material that forms the physical basis of the PCB 11. Materials for the substrate 13 include FR4 as an insulator made of glass fiber and epoxy resin, ceramics primarily used in high-frequency circuits or high-temperature environments (because ceramics can withstand high temperatures and have excellent thermal conductivity), and polyimide used as a base material for flexible PCBs due to its flexibility.

[0126] Intermediate layer 15 is formed on substrate 13 via bump pads 111 and includes lines for connection to electronic components (e.g., memory device 17 and processor 19) that do not have the same form factor or pin arrangement. Intermediate layer 15 can convert signals at different interfaces.

[0127] Memory device 17 is formed on interposer layer 15 via microbump pads 113. Memory device 17 can store data applied by processor 19 or output data stored in memory device 17 to processor 19 under the control of processor 19. Memory device 17 includes a base die 120 and a plurality of core dies 121-1 to 121-L. Core dies 121-1 to 121-L can be stacked on base die 120 via microbump pads 113. Base die 120 and core dies 121-1 to 121-L are vertically connected via vias (TSVs). The number L of core dies 121-1 to 121-L can be, for example, 4, 8, 12, or 16. For example, when each of the core dies 121-1 to 121-12 has eight channels, core dies 121-1 to 121-4, core dies 121-5 to 121-8, and core dies 1212-9 to 121-12 can each include 32 channel regions, and can send data to and receive data from the processor 19 in units of memory columns consisting of 32 channels.

[0128] The base die 120 controls the data transfer between the processor 19 and the core dies 121-1 to 121-L. The base die 120 can... Figure 2 The WT or RD command outputs to multiple channels included in multiple core dies 121-1 to 121-L (i.e. Figure 1 At least two channels from CH0 to CH15 of the multiple core dies 121-1 to 121-L. The base die 120 can input and output data DATA through at least two channels from CH0 to CH15 of the multiple core dies 121-1 to 121-L. Each of the multiple core dies 121-1 to 121-L can perform write and read operations; the write operation stores the data DATA in multiple channels (i.e., ...). Figure 1 The read operation output is stored in at least two channels (CH0 to CH15) of the above channels (i.e., multiple channels). Figure 1 Data DATA in at least two channels of CH0 to CH15 in the multiple core dies 121-1 to 121-L. Because at least two of the multiple channels included in the multiple core dies 121-1 to 121-L are shared. Figure 2 The data DATA can be input and output by the commands WT or RD, respectively, so the memory device 17 can input and output the data DATA with a wider bandwidth (512 bits or 1024 bits) than the bandwidth (256 bits) that the data DATA passes through a single channel for input and output.

Claims

1. A memory device, comprising: The first core nude chip consists of N first channels; as well as The second core wafer, which includes N second channels, The first channel and the second channel input data by receiving a common write command and output data by receiving a common read command.

2. The memory device according to claim 1, wherein: The second core die is stacked on top of the first core die in the stacking direction; as well as The first channel of the first core die and the second channel of the second core die, which receive the common write command and the common read command, are aligned in the stacking direction.

3. The memory device according to claim 2, wherein, The first channel of the first core die and the second channel of the second core die, which receive the common write command and the common read command, are adjacent to each other in the stacking direction.

4. The memory device of claim 1, further comprising a base die, said base die: The common write command and the common read command are output to the first channel and the second channel; and The data is input and output through the first channel and the second channel.

5. The memory device according to claim 4, wherein, The underlying bare wafer includes: A memory controller that: generates the write command and the read command based on a command address; generates a first internal clock to a fourth internal clock by dividing the frequency of a clock; generates input data based on external data after the start of a write operation; and generates the external data based on output data after the start of a read operation. A first physical layer, electrically connected to the N first channels and the N second channels, wherein the first physical layer: outputs the write command, the read command, and the data to the N first channels and the N second channels; and receives the data from the N first channels and the N second channels; A second physical layer, electrically connected to the N first channels and the N second channels, wherein the second physical layer: outputs the write command, the read command, and the data to the N first channels and the N second channels; and receives the data from the N first channels and the N second channels; and The data input / output circuitry is synchronized with the first to the fourth internal clocks: After the write operation begins, the data is generated based on the input data. After the read operation begins, the output data is generated based on the data.

6. The memory device according to claim 5, wherein, The memory controller includes: The write / read control circuit generates the write command and the read command by decoding the command address; An internal clock generation circuit that generates the first internal clock to the fourth internal clock by dividing the frequency of the clock; and Error correction circuit, which: After the write operation begins, the input data is generated by correcting errors in the external data; and After the read operation begins, the output data is output as external data by correcting errors in the output data.

7. The memory device according to claim 5, wherein, The data input / output circuit includes: A serialization circuit, wherein, after the write operation begins, it receives and serializes the input data synchronously with the first to the fourth internal clocks; and A deserialization circuit that: receives the data synchronously with the first to the fourth internal clocks after the read operation begins; and generates the output data by deserializing the data.

8. A memory device, comprising: The first core nude chip consists of N first channels; The second core die includes N second channels; The third core wafer includes N third channels; as well as The fourth core die, which includes N fourth channels, The first channel and the third channel input the first data by receiving a common write command and output the first data by receiving a common read command. The second channel and the fourth channel input the second data by receiving a common write command and output the second data by receiving a common read command.

9. The memory device according to claim 8, wherein: The second core die is stacked on top of the first core die in the stacking direction. The third core die is stacked on top of the second core die in the stacking direction, and The fourth core die is stacked on top of the third core die in the stacking direction.

10. The memory device according to claim 9, wherein: The first channel of the first core die and the third channel of the third core die, which receive the common write command and the common read command, are aligned in the stacking direction. The second channel of the second core die and the fourth channel of the fourth core die, which receive the common write command and the common read command, are aligned in the stacking direction.

11. The memory device according to claim 8, wherein: The first channel of the first core die receiving the common write command and the third channel of the third core die are spaced apart from each other via the second core die, and The second channel of the second core die and the fourth channel of the fourth core die, which receive the common write command and the common read command, are spaced apart from each other through the third core die.

12. The memory device of claim 8, further comprising a base die, the base die being: The common write command and the common read command are output to the first channel and the third channel; The first data is input and output through the first channel and the third channel; The common write command and the common read command are output to the second channel and the fourth channel; as well as The second data is input and output through the second channel and the fourth channel.

13. The memory device according to claim 12, wherein, The underlying bare wafer includes: A memory controller that: generates the write command and the read command based on a command address; generates a first internal clock to a fourth internal clock by dividing the frequency of a clock; generates input data based on external data after the start of a write operation; and generates the external data based on output data after the start of a read operation. A first physical layer is electrically connected to the N first channels, the N second channels, the N third channels, and the N fourth channels, and the first physical layer: outputs the write command, the read command, and the first data to the N first channels, the N second channels, the N third channels, and the N fourth channels; and receives the first data from the N first channels, the N second channels, the N third channels, and the N fourth channels; A second physical layer, electrically connected to the N first channels, the N second channels, the N third channels, and the N fourth channels, wherein the second physical layer: outputs the write command, the read command, and the second data to the N first channels, the N second channels, the N third channels, and the N fourth channels; and receives the second data from the N first channels, the N second channels, the N third channels, and the N fourth channels; and The data input / output circuitry is synchronized with the first to the fourth internal clocks: After the write operation begins, the first data and the second data are generated based on the input data; and After the read operation begins, the output data is generated based on the first data and the second data.

14. The memory device according to claim 13, wherein, The memory controller includes: The write / read control circuit generates the write command and the read command by decoding the command address; An internal clock generation circuit that generates the first internal clock to the fourth internal clock by dividing the frequency of the clock; and Error correction circuit, which: After the write operation begins, the input data is generated by correcting errors in the external data; and After the read operation begins, the output data is output as external data by correcting errors in the output data.

15. The memory device according to claim 13, wherein, The data input / output circuit includes: A serialization circuit, which: after the write operation begins, receives the input data synchronously with the first to the fourth internal clocks; and generates the first data and the second data by serializing the input data; and A deserialization circuit, which: after the read operation begins, receives the first data and the second data synchronously with the first internal clock to the fourth internal clock; and generates the output data by deserializing the first data and the second data.

16. A memory device, comprising: The first core nude chip consists of N first channels; The second core die includes N second channels; The third core wafer includes N third channels; as well as The fourth core die, which includes N fourth channels, The first channel, the second channel, the third channel, and the fourth channel input and output data through shared write commands and shared read commands.

17. The memory device according to claim 16, wherein: The second core die is stacked on top of the first core die in the stacking direction. The third core die is stacked on top of the second core die in the stacking direction, and The fourth core die is stacked on top of the third core die in the stacking direction.

18. The memory device according to claim 17, wherein, The first channel of the first core die, the second channel of the second core die, the third channel of the third core die, and the fourth channel of the fourth core die, which receive the common write command and the common read command, are aligned in the stacking direction.

19. The memory device according to claim 16, wherein: The first channel of the first core die and the second channel of the second core die, which receive the common write command and the common read command, are adjacent to each other in the stacking direction. The second channel of the second core die and the third channel of the third core die, which receive the common write command and the common read command, are adjacent to each other in the stacking direction. The third channel of the third core die and the fourth channel of the fourth core die, which receive the common write command and the common read command, are adjacent to each other in the stacking direction.

20. The memory device of claim 16, further comprising a base die, said base die: The common write command and the common read command are output to at least four of the N first channels, the N second channels, the N third channels, and the N fourth channels; and The data is input and output through at least four of the N first channels, the N second channels, the N third channels, and the N fourth channels.

21. The memory device according to claim 20, wherein, The underlying bare wafer includes: A memory controller that: generates the write command and the read command based on a command address; generates a first internal clock to a fourth internal clock by dividing the frequency of a clock; generates input data based on external data after the start of a write operation; and generates the external data based on output data after the start of a read operation. A first physical layer, electrically connected to the N first channels, the N second channels, the N third channels, and the N fourth channels, wherein the first physical layer: outputs the write command, the read command, and the data to at least four of the N first channels, the N second channels, the N third channels, and the N fourth channels; and receives the data from the at least four of the N first channels, the N second channels, the N third channels, and the N fourth channels. A second physical layer, electrically connected to the N first channels, the N second channels, the N third channels, and the N fourth channels, wherein the second physical layer: outputs the write command, the read command, and the data to at least four of the N first channels, the N second channels, the N third channels, and the N fourth channels; and receives the data from the at least four of the N first channels, the N second channels, the N third channels, and the N fourth channels; and The data input / output circuitry is synchronized with the first to the fourth internal clocks: After the write operation begins, the data is generated based on the input data; and After the read operation begins, the output data is generated based on the data.

22. The memory device according to claim 21, wherein, The memory controller includes: The write / read control circuit generates the write command and the read command by decoding the command address; An internal clock generation circuit that generates the first internal clock to the fourth internal clock by dividing the frequency of the clock; and Error correction circuit, which: After the write operation begins, the input data is generated by correcting errors in the external data; and After the read operation begins, the output data is output as external data by correcting errors in the output data.

23. The memory device of claim 21, wherein, The data input / output circuit includes: A serialization circuit, which: after the write operation begins, receives the input data synchronously with the first to the fourth internal clocks; and generates the data by serializing the input data; and A deserialization circuit that: receives the data synchronously with the first to the fourth internal clocks after the read operation begins; and generates the output data by deserializing the data.

24. A memory device, comprising: The basic die, which outputs write and read commands; and inputs and outputs first and second data. A first storage column includes a first core die and a second core die, wherein the first core die includes a plurality of first channels, and the second core die includes a plurality of second channels; and The second storage column includes a third core die and a fourth core die, wherein the third core die includes multiple third channels, and the fourth core die includes multiple fourth channels. The first channel in the first core die and the second channel in the second core die input and output the first data by sharing the write command and the read command. The third channel in the third core die and the fourth channel in the fourth core die input and output the second data by sharing the write command and the read command.

25. The memory device according to claim 24, wherein, The memory device independently performs write and read operations on the first storage column and write and read operations on the second storage column.

26. The memory device of claim 24, wherein: In the stacking direction, the first core die is stacked on the base die, the second core die is stacked on the first core die, the third core die is stacked on the second core die, and the fourth core die is stacked on the third core die. The first channel in the first core die that shares the write command and the read command, and the second channel in the second core die that shares the write command and the read command, are aligned in the stacking direction. The third channel in the third core die that shares the write command and the read command, and the fourth channel in the fourth core die that shares the write command and the read command, are aligned in the stacking direction.

27. The memory device of claim 26, wherein: The first channel in the first core die that shares the write command and the read command, and the second channel in the second core die that shares the write command and the read command, are adjacent to each other in the stacking direction. The third channel in the third core die that shares the write command and the read command, and the fourth channel in the fourth core die that shares the write command and the read command, are adjacent to each other in the stacking direction.

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