SPI-based CPU-FPGA co-program dynamic loading and resource scheduling method

Abstract

The application belongs to the technical field of embedded systems, and particularly relates to a CPU-FPGA cooperative program dynamic loading and resource scheduling method based on SPI, which is realized based on a CPU-FPGA cooperative embedded system and comprises dynamic loading, resource scheduling and SPI bus optimization in cooperative work. The dynamic loading comprises program fragmentation and data structure design, incremental loading and breakpoint resuming mechanism and double-buffer loading and verification mechanism. The resource scheduling comprises establishment of a task attribute model, FPGA resource real-time monitoring and mapping and a dynamic scheduling algorithm. The SPI bus optimization comprises double-mode frame structure transmission design, adaptive SPI clock adjustment and interruption and DMA cooperative transmission. The method improves the FPGA program dynamic loading efficiency and reliability, the resources of the CPU and the FPGA have high scheduling cooperativeness, the utilization rate is high, and the optimized SPI bus can meet the real-time requirement of the system.

Description

Technical Field

[0001] This invention belongs to the field of embedded system technology and relates to dynamic loading of FPGA programs, FPGA resource management and allocation, and communication optimization technology in embedded systems where CPU and FPGA work together to accelerate processing. Specifically, it is a CPU-FPGA collaborative program dynamic loading and resource scheduling method based on SPI. Background Technology

[0002] The CPU-FPGA collaborative architecture, with its flexibility and versatility, is widely used in modern industrial control, smart terminals, IoT devices, and communication terminals. In this architecture, the CPU is mainly responsible for management and control, while the FPGA handles parallel processing. Working together based on their unique advantages, they have become a mainstream solution for improving the functionality and performance of embedded systems. The SPI bus, as a mature serial communication interface, requires only four signal lines (clock line SCLK, master output / slave input MOSI, master input / slave output MISO, and chip select signal SS / CS) to achieve data transmission between chips. It features simple wiring, low hardware cost, stable transmission rate (supporting adjustable speeds from 1Mbps to 50Mbps), strong resistance to electromagnetic interference, and strong environmental adaptability. It is widely used in the communication and configuration environments between CPUs and FPGAs in small and medium-sized embedded systems.

[0003] As embedded systems demand increasing task complexity and response speed, dynamic adaptability has become a key element for system optimization. However, existing CPU-FPGA collaborative architectures based on the SPI bus have significant shortcomings in three aspects: dynamic program updates, efficient resource utilization, and bus transmission optimization. These shortcomings severely restrict the performance of embedded systems and the efficiency of engineering implementation.

[0004] (a) FPGA program dynamic loading has low efficiency and insufficient reliability.

[0005] Traditional FPGA program loading methods have significant limitations: First, they rely on JTAG interfaces or Flash memory, requiring the device to be shut down before updating the program using specialized tools, making it unsuitable for dynamic loading and upgrades during operation. Second, some dynamic loading methods use parallel buses, which, while increasing transmission speed, also increase hardware design complexity and power consumption, making them unsuitable for resource-constrained small to medium-sized embedded devices. Therefore, the simple and low-cost SPI bus has become the primary method for dynamically loading FPGA programs in recent years; however, it faces three major challenges in practical engineering applications:

[0006] 1. Low transmission efficiency: Current engineering applications commonly use a complete image transmission mode without modularizing the FPGA program. In scenarios with limited SPI bus speeds, loading a complete image (typically several MB) takes seconds, which is insufficient to meet the stringent real-time requirements of industrial control and other fields.

[0007] 2. Transmission reliability deficiencies: The system lacks an effective mechanism for resuming interrupted transmissions, which is particularly prominent in the electromagnetic interference environments common in industrial control systems. If the transmission is interrupted due to interference or system malfunction, a complete mirror transmission must be restarted, further reducing loading efficiency and increasing system recovery time.

[0008] 3. Status monitoring gap: The characteristics of the SPI bus make it impossible to provide real-time feedback on the FPGA's receiving status during the loading process. The CPU can only determine the transmission result by polling, which is prone to two classic faults: "false success" or "deadlock".

[0009] (ii) The resource scheduling coordination between CPU and FPGA is lacking and the utilization rate is low.

[0010] The resource management of CPU and FPGA has long been in a state of "each doing its own thing" without a dynamic coordination mechanism, which is mainly reflected in the following three aspects:

[0011] 1. Task allocation mechanism needs optimization: Existing CPU task scheduling algorithms fail to fully consider the constraints of FPGA hardware resource capacity, resulting in a mismatch between task allocation and FPGA capacity, which in turn leads to task execution failure or crashes. For example, in a smart sensor environment, the CPU does not assess the total number of DSP cores within the FPGA and continuously allocates high-frequency signal processing tasks to the FPGA, causing device processing latency to exceed the system's set range and severely impacting real-time performance.

[0012] 2. Lack of flexibility in resource allocation: Critical resources within the FPGA (such as LUTs, RAM, and DSPs) are allocated statically. Once the device starts up, the resource allocation remains fixed. This can cause high-priority tasks to fail to execute due to low-priority tasks occupying resources for extended periods. For example, in industrial control, an emergency stop detection task (high priority) may experience delayed response due to a filtering task (low priority) within the FPGA occupying critical logic resources, posing a potential safety risk and reducing user experience.

[0013] 3. Lack of Real-Time Load Awareness: The device lacks an effective mechanism for real-time monitoring of resource usage, preventing the CPU from obtaining the real-time load status of the FPGA. This leads to two extreme load imbalance problems: first, when FPGA resource utilization exceeds 90%, tasks continue to be allocated, causing resource overload; second, when a large amount of FPGA resources are idle, the CPU fails to allocate tasks in a timely manner, resulting in resource waste.

[0014] (iii) There are bottlenecks in the SPI bus transmission method.

[0015] As the core communication channel between the CPU and FPGA, the SPI bus transmission method has the following problems in a system collaborative optimization environment:

[0016] 1. Lack of priority management: The existing transmission method does not differentiate the transmission of task information (such as the mixed synchronous transmission of various types of information such as program loading, task instructions and status feedback), which leads to critical control instructions (such as emergency interruption, resource destruction and fault reset) being blocked by a large amount of data. The response delay of high-priority data displayed in real time cannot meet the real-time requirements of industry.

[0017] 2. Poor clock parameter adaptability: Most industrial equipment currently uses a fixed SPI clock frequency, which cannot be adaptively modified according to the transmitted content and environmental interference after system startup. Therefore, this one-time configuration has two extreme problems: first, data errors are prone to occur in environments with strong electromagnetic interference; second, the bus bandwidth cannot be fully utilized in stable environments.

[0018] 3. High CPU utilization: The current SPI transmission method relies excessively on CPU core interrupt handling, requiring an interrupt to be triggered for each data transmission. This design leads to excessive CPU utilization for terminal task processing, affecting the execution of other tasks. Summary of the Invention

[0019] To overcome the technical shortcomings of existing technologies, such as low efficiency and insufficient reliability of dynamic FPGA program loading, lack of resource scheduling coordination between CPU and FPGA and low utilization, and bottlenecks in SPI bus transmission, which make it difficult to adapt to the real-time requirements of the system, this invention provides a CPU-FPGA collaborative program dynamic loading and resource scheduling method based on SPI.

[0020] This invention addresses the aforementioned problems by employing a three-pronged approach: modular incremental loading, dynamic resource collaborative scheduling, and SPI bus priority management. This approach fills the technological gap in dynamic loading and intelligent scheduling of the SPI bus in small and medium-sized CPU-FPGA collaborative embedded systems. It can be directly applied to the design, development, upgrading, and operation and maintenance of embedded devices, significantly reducing development costs and improving system reliability and scalability. It also significantly enhances the feasibility of engineering implementation and is suitable for small and medium-sized embedded system devices with limited resources and high requirements for real-time performance and reliability.

[0021] This invention provides a CPU-FPGA co-program dynamic loading and resource scheduling method based on SPI, implemented using a CPU-FPGA co-embedded system. The CPU-FPGA co-embedded system includes a CPU main control module, a DMA controller, an FPGA computing module, an external interface module, and a power supply module. The CPU main control module is connected to a first SPI FLASH via an SPI bus to store program and configuration information. The CPU main control module interacts with the external interface module through an SGMII high-speed Ethernet interface and a UART serial communication interface. The DMA controller is connected to both the CPU main control module and the FPGA computing module via an SPI bus, and is used for high-speed data transmission between them to reduce CPU load. The FPGA computing module, as the core computing unit, is connected to the DMA controller via an SPI bus to receive instructions and return computing results. The CPU main control module and the FPGA computing module interact via the SPI bus through the DMA controller, rather than being directly connected, to improve data throughput efficiency and reduce CPU interrupt handling overhead. The FPGA computing module is connected to a second SPI... The FLASH memory is used to store its own configuration program and operation parameters. The JTAG debugging interface of the FPGA operation module is connected to the external interface module to realize external communication and online debugging of the system. The SGMII interface of the external interface module is used for high-speed Ethernet transmission, the UART interface is used for low-speed serial communication, and the JTAG interface is used for FPGA debugging and programming. The FPGA operation module is connected to a second SPI FLASH memory and supports online firmware updates and hardware debugging through the JTAG interface. The power supply module provides power to the CPU-FPGA collaborative embedded system. The method includes dynamic loading, resource scheduling, and SPI bus optimization for collaborative operation. The dynamic loading includes program fragmentation and data structure design, incremental loading and breakpoint resume mechanism, and double buffer loading and verification mechanism. The resource scheduling includes establishing a task attribute model, real-time monitoring and mapping of FPGA resources, and dynamic scheduling algorithm. The SPI bus optimization includes dual-mode frame structure transmission design, adaptive SPI clock adjustment, and interrupt and DMA collaborative transmission.

[0022] Preferably, the method for program segmentation and data structure design is as follows: the configuration program of the FPGA operation module is split according to the functional modules, and different functional modules are loaded into different logical segments of the FPGA operation module; each logical segment contains a three-level structure, namely data header, payload data and reserved area, and all segment files are pre-stored in the first SPI FLASH connected to the CPU main control module, which supports individual updates by module ID without replacing the entire program.

[0023] The preferred method for incremental loading and breakpoint resume mechanism is as follows:

[0024] The entire program package or necessary program modules are transferred during the initial load. Subsequent updates initiate an incremental transfer process, which is as follows:

[0025] Step a, Version Comparison: The CPU main control module sends a query command for the required updated module version to the FPGA computing module via the SPI bus to obtain the version number of each currently running functional module program;

[0026] Step b, Update Detection: The CPU main control module compares the target version stored locally with the current version of the FPGA computing module, and only updates the program of the functional module whose version number is greater than the current version number;

[0027] Step c, Record breakpoints: The FPGA operation module internally sets a load status register to record the received fragment sequence number in real time. When the transmission is interrupted (such as power fluctuations or communication errors), the data in this register is not lost.

[0028] Step d, Resumption Mechanism: After the device resumes communication, the CPU main control module actively reads the breakpoint record of the FPGA computing module and starts transmitting from the missing fragment to avoid retransmitting the received correct data.

[0029] The preferred method for the dual-buffered loading and verification mechanism is as follows: Two independent temporary buffers and a processing area are divided within the FPGA computing module. When the FPGA computing module receives fragmented data, it first writes it to the temporary buffer and performs CRC32 verification and validity checks. After successful data verification, the data is copied from the temporary buffer to the processing area via the FPGA computing module's internal configuration interface, awaiting further processing. If verification fails, the fragment is cleared, and an error response is sent to the CPU main control module via the SPI bus. Upon receiving the error response data, the CPU main control module retransmits the fragmented data to ensure that the processing area always stores a valid program. After all fragments are transmitted, the FPGA computing module sends a loading completion command, and the CPU main control module triggers a partial update signal for the FPGA computing module. The updated function module program is dynamically loaded and takes effect in real time without requiring a system restart.

[0030] Preferably, the resource scheduling processing steps are as follows:

[0031] Step S1: Generate the task attribute model table and update the resource monitoring status table;

[0032] The CPU main control module generates tasks to be executed and establishes a task attribute model for each task, marking priority level, resource requirement list, and response time deadline. Priority levels are divided into P0, P1, P2, and P3, where P0 is urgent, P1 is high, P2 is medium, and P3 is low. The smaller the priority value, the higher the priority, and the priority is scalable. The resource requirement list quantifies the types and quantities of FPGA resources required by the task, including logic resources, storage resources, and computing resources; the resource requirement list is scalable. The response time deadline marks the upper limit of the task's response time and execution cycle; the response time deadline is scalable.

[0033] The FPGA integrates a resource monitoring module that scans resource status in real time via hardware logic. Its sub-steps are as follows:

[0034] Step S11, Resource Status Tracking: Continuously monitor the usage of various types of resources and record the total capacity, occupancy, and available balance of each type of resource;

[0035] Step S12, Topology modeling: Establish a dynamic mapping relationship table between physical resources and logical functions, record the ID of the currently running module, the type / quantity of resources occupied, the starting address, and mark non-reconfigurable areas to avoid task allocation conflicts;

[0036] Step S13, Load Prediction Feedback: The resource monitoring module sends the resource occupancy table and load rate (current resource utilization = occupancy / total capacity) to the CPU main control module in real time via SPI interrupt. The CPU main control module performs resource demand analysis based on the monitoring data to provide a basis for dynamic resource allocation.

[0037] Step S2: The CPU main control module executes a triple intelligent scheduling strategy based on the task priority of the task to be executed, the resource requirement list, the real-time load status of the FPGA computing module, and the available margin in the resource monitoring table.

[0038] Step S21: Check resource availability;

[0039] If there are sufficient resources and the task requirements are met, proceed directly to the task execution phase.

[0040] If resources are insufficient, then task priority will be determined:

[0041] Determine the priority of the task to be executed and the task currently being executed. If the priority of the task to be executed is higher than that of the task currently being executed, pause the low-priority task being executed and save its state, and release the resources occupied by the low-priority task for the high-priority task to use. If the priority of the task to be executed is lower than that of the task currently being executed, wait for the high-priority task being executed to complete and wait for the resources to be released before executing.

[0042] Step S22: Preemption determination;

[0043] During the task execution phase, the task being executed runs on the allocated resources. During this phase, the resource monitoring module continuously tracks the resource status. If a higher-priority task triggers preemption during task execution, the current task is paused and its resources are released, allowing the higher-priority task to be executed first. After the task is completed, it is determined whether the task occupied the preempted resources. If it was preempted, a resource reclamation operation is performed to release the preempted resources and update the resource monitoring table. If it was a normally allocated resource, the task directly releases the resources it occupied and updates the resource monitoring table.

[0044] Step S23: Task queue check;

[0045] After the resources are released, the CPU main control module checks if there are any waiting tasks. If there are, it returns to step S1 and repeats the above scheduling process. If not, the CPU main control module enters an idle state.

[0046] Preferably, during the processing, the resource scheduling unit prioritizes allocating continuously available resource addresses to tasks.

[0047] Preferably, resource scheduling also includes adaptive load balancing adjustment during the process: when the load rate of the FPGA computing module is greater than the set overload threshold, the CPU triggers a load reduction strategy, suspends low-priority tasks and releases resources; when the load rate of the FPGA computing module is lower than the low-load threshold, the CPU starts a load increase strategy, wakes up waiting low-priority tasks or assigns new tasks, and ensures that resource utilization is maintained in the optimal range through real-time value perception and elastic resource scheduling.

[0048] Preferably, the overload threshold is 90%, the underload threshold is 30%, and the optimal range of resource utilization is 40%~80%.

[0049] Preferably, SPI bus optimization involves the execution of resource scheduling tasks, and the steps of SPI bus optimization are as follows:

[0050] Step A1: The CPU main control module configures the SPI to DMA transfer mode, and the subsequent sending and receiving of data frames are automatically completed by the DMA channel;

[0051] Step A2: Data transmission and priority processing;

[0052] The CPU main control module initiates DMA transfer by writing the address and length of the data frame to be sent into the DMA channel descriptor, triggering a DMA transfer request. The DMA then begins reading data from memory and sending it to the SPI bus. After receiving the data frame, the SPI interface of the FPGA computing module directly writes it into the temporary buffer of the FPGA computing module without the involvement of the FPGA core. There are no CPU interrupts throughout the process. The CPU only sends a completion interrupt to the CPU main control module when the DMA transfer is completed. The CPU main control module responds to the interrupt, updates the transfer status, and prepares for the next DMA transfer.

[0053] During transmission, data is sent in a dual-mode frame structure, which includes instruction frames and data frames. Instruction frames are management frames with high priority, used to transmit control commands and status queries. They can preempt the bus during transmission, interrupting the current data frame transmission. Instruction frames are sent directly through the CPU main control module. Data frames have low priority and are used to transmit program fragments and task data. They are transmitted in the order of the transmission queue and cannot preempt the bus. Data frame transmission is automatically completed by the DMA channel. After transmission is completed, the CPU main control module is notified to update the transmission status through a DMA interrupt.

[0054] When the SPI interface of the FPGA computing module detects that the frame header is a management frame during data transmission, it immediately triggers an SPI receive interrupt. The FPGA pauses the current data frame processing flow, prioritizes the execution of the control instructions corresponding to the management frame, and sends an interrupt to the CPU main control module after completion to synchronize the instruction execution results. The FPGA computing module then resumes DMA data frame transmission. If the frame header is a data frame, it directly enters the normal data transmission flow. The data frame is automatically written to the temporary buffer of the FPGA computing module through the DMA controller without the involvement of the CPU main control module.

[0055] Step A3: Transmission verification and adaptive clock adjustment;

[0056] Step A31: Data CRC verification;

[0057] After each frame of data transmission is completed, data CRC verification is performed. If the verification is successful, the process returns to the SPI data transmission stage in step A2. If the verification fails, the number of consecutive failures is judged.

[0058] Step A32: Determine the number of consecutive failures;

[0059] If the number of consecutive failures is greater than or equal to 3, it is determined that the current environment is under strong interference, triggering the adaptive adjustment of the SPI clock frequency to automatically reduce the clock frequency to improve transmission stability; if the number of consecutive failures is less than 3, it returns to the SPI data transmission stage of step A2.

[0060] Step A33: Successful adjustment determination;

[0061] After the SPI clock frequency is adaptively adjusted, it is determined whether the adjustment was successful within a specified time. If so, the process returns to the SPI data transmission stage in step A2 and continues to transmit using the new frequency; otherwise, the process proceeds to determine the number of adjustments.

[0062] Step A34: Adjustment count judgment;

[0063] If the number of adjustments is less than 10, return to step A32 to trigger adaptive adjustment of the SPI clock frequency;

[0064] If the number of adjustments is greater than or equal to 10, an error log will be recorded and an alert will be triggered. The process will then be terminated, awaiting manual intervention for investigation.

[0065] Preferably, the SPI clock frequency is adaptively adjusted by the CPU main control module based on the transmitted content and the intensity of environmental interference. When transmitting instruction frames, the highest clock frequency supported by the system is used to shorten the instruction response time, ensuring that critical control instructions take effect quickly. When transmitting data frames, a medium frequency is used. If three consecutive frames fail to verify, it is determined to be a strong interference environment, and the frequency is automatically reduced. After ten consecutive successful transmissions, the frequency gradually increases back to the highest frequency. This balances transmission speed and stability, adapting the optimal transmission clock frequency to the environment.

[0066] The technical solution provided by this invention has the following technical effects compared with the prior art:

[0067] 1. Improve dynamic loading efficiency: Design a modular incremental loading system for FPGA programs based on the SPI bus, which significantly shortens the single loading time and supports breakpoint resumption and automatic recovery in case of transmission errors, thereby improving the loading success rate;

[0068] 2. Resource Coordination and Intelligent Scheduling: Design a dynamic matching mechanism for CPU and FPGA resources to achieve real-time coordination of task allocation and hardware resources, reduce task response latency, improve FPGA resource utilization, and dynamically avoid resource overload or idle imbalance.

[0069] 3. Optimize SPI transmission method: Design a hierarchical transmission strategy and adaptive adjustment mechanism to shorten the response delay of key instructions, reduce the transmission error rate, and optimize bus utilization. Attached Figure Description

[0070] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0071] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0072] Figure 1 This is a hardware design architecture diagram of the CPU-FPGA collaborative embedded system according to a certain embodiment of the present invention;

[0073] Figure 2 This is a software design composition diagram of the CPU-FPGA co-program dynamic loading and resource scheduling method based on SPI according to a certain embodiment of the present invention;

[0074] Figure 3 This is a flowchart illustrating the resource scheduling process in a certain embodiment of the present invention;

[0075] Figure 4 This is a flowchart illustrating the SPI bus management optimization process in a certain embodiment of the present invention;

[0076] Figure 5 This is a schematic diagram of a dual-mode frame structure in a certain embodiment of the present invention. Detailed Implementation

[0077] To better understand the above-mentioned objectives, features, and advantages of the present invention, the solutions of the present invention will be further described below. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0078] In this description, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. It should also be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joint" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0079] Many specific details are set forth in the following description in order to provide a full understanding of the invention, but the invention may also be practiced in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of the invention, and not all embodiments.

[0080] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0081] In one embodiment, such as Figure 1 As shown, a CPU-FPGA collaborative program dynamic loading and resource scheduling method based on SPI is disclosed. The CPU-FPGA collaborative embedded system includes a CPU main control module, a DMA controller, an FPGA computing module, an external interface module, and a power supply module. The CPU main control module is connected to a first SPI FLASH via an SPI bus to store program and configuration information. The CPU main control module interacts with the external interface module through an SGMII high-speed Ethernet interface and a UART serial communication interface. The DMA controller is connected to both the CPU main control module and the FPGA computing module via an SPI bus, and is used for high-speed data transmission between the two to reduce CPU load. The FPGA computing module, as the core computing unit, is connected to the DMA controller via an SPI bus to receive instructions and return computing results. The CPU main control module and the FPGA computing module interact via the SPI bus through the DMA controller, rather than being directly connected, to improve data throughput efficiency and reduce CPU interrupt handling overhead. The FPGA computing module is connected to a second SPI... The FLASH memory is used to store its own configuration program and operation parameters. The JTAG debugging interface of the FPGA operation module is connected to the external interface module to realize external communication and online debugging of the system. The SGMII interface of the external interface module is used for high-speed Ethernet transmission, the UART interface is used for low-speed serial communication, and the JTAG interface is used for FPGA debugging and programming. The FPGA operation module is connected to a second SPI FLASH memory and supports online firmware updates and hardware debugging through the JTAG interface. The power supply module provides power to the CPU-FPGA collaborative embedded system. The method includes dynamic loading, resource scheduling, and SPI bus optimization for collaborative operation. The dynamic loading includes program fragmentation and data structure design, incremental loading and breakpoint resume mechanism, and double buffer loading and verification mechanism. The resource scheduling includes establishing a task attribute model, real-time monitoring and mapping of FPGA resources, and dynamic scheduling algorithm. The SPI bus optimization includes dual-mode frame structure transmission design, adaptive SPI clock adjustment, and interrupt and DMA collaborative transmission.

[0082] Dynamic loading solves the problems of low efficiency and poor reliability in loading FPGA programs via the SPI bus. The implementation takes an industrial control scenario as an example, with hardware selection balancing performance and cost. The CPU is an STM32H743IGH6 (ARM Cortex-M7 core, 400MHz clock speed, supports SPI master mode, dual-channel DMA, and has rich peripheral interfaces). The FPGA is a Lattice ECP5-45F (5K logic units, supports partial reconfiguration, built-in SPI slave interface and hardware resource monitoring module). The first and second SPI FLASH memory units both use 64MB SPI Flash to store FPGA program fragments and system configuration parameters. The power supply module outputs 5V (CPU and FPGA voltage) and supports overvoltage / overcurrent protection. The CPU-FPGA collaborative embedded system also includes a series of auxiliary circuits, such as an SPI signal isolation circuit: using an ISO7740 digital isolation chip with an isolation voltage of 2500Vrms to cope with common-mode interference in industrial environments. A status indication circuit includes three LED indicators (power indicator, loading status indicator, and error alarm indicator), which use different flashing frequencies and colors to reflect the system status. JTAG, UART serial port, and SGMII interface serve as debugging interfaces for program burning and on-site debugging. CPU software development: Based on SourceInsight, programmed in C language, using the HAL library to configure SPI, DMA, and interrupts; FPGA development: Implemented using Verilog HDL for resource monitoring modules, SPI slave interface, and some reconfiguration logic; Auxiliary tools: Python scripts for program fragmentation and metadata generation.

[0083] The process of dynamically loading software is as follows.

[0084] I. Offline preprocessing stage.

[0085] 1) Program compilation and fragmentation:

[0086] Verilog compiles FPGA functional modules into .bit configuration files; a Python script parses the .bit file, splits it into .bin format segments by module, calculates the CRC32 check value of each segment, and writes it to the metadata area;

[0087] 2) Storage and burning:

[0088] The CPU program (including loading logic and scheduling algorithm) and FPGA segment files are burned into the CPU's internal Flash via UART.

[0089] II. Dynamic loading phase at runtime.

[0090] 1) Loading trigger and initialization (CPU side):

[0091] After the CPU powers on, it initializes the SPI controller; receives external trigger signals, and parses the target module ID and version number.

[0092] 2) Version comparison and resource check:

[0093] The CPU sends a command frame via SPI to query the current module version of the FPGA. After receiving the command, the FPGA reads the version number from its internal register and returns a data frame via MISO. The CPU compares the versions and finds differences (e.g., V0.1.1.0 > V01.0.0), and continues to send resource query commands to confirm that the target configuration area of ​​the FPGA is free.

[0094] 3) Incremental fragmentation transmission:

[0095] The CPU reads the difference fragments of the target module from the first SPI FLASH (only the 5 fragments added in V1.1.0), configures the DMA transmission parameters, starts DMA transmission, and waits for ACK feedback from the FPGA after sending each data frame. After the FPGA receives the data frame, it writes it to a temporary buffer through DMA, completes the CRC check, and returns a successful reception instruction.

[0096] 4) Resuming interrupted downloads:

[0097] If transmission is interrupted (e.g., SPI disconnection), the FPGA records the largest received fragment ID in the loading status register; after communication is restored, the CPU sends a breakpoint query command, reads the status register value, and continues transmission from the breakpoint fragment to avoid duplicate transmission.

[0098] 5) Program activation and verification:

[0099] After all the chip transfers are completed, the FPGA sends a loading completion command, and the CPU triggers a partial FPGA reconfiguration signal; the FPGA copies the temporary buffer data to the computing area, starts the update enable module and notifies the CPU; the CPU reads the status register of the FPGA module, and after confirming that it is running normally, it lights up the loading success LED in green.

[0100] Based on the above embodiments, in a preferred embodiment, the program fragmentation and data structure design specifically involves: splitting the configuration program of the FPGA operation module according to functional modules, with different functional modules loaded into different logical segments of the FPGA operation module; each logical segment contains a three-level structure, namely a data header, payload data, and a reserved area. All fragment files are pre-stored in the first SPI FLASH connected to the CPU main control module, supporting individual updates by module ID without requiring a complete program replacement. Specifically, the FPGA operation module is divided into a core algorithm area, a filtering processing area, and an interface communication area according to functional modules. The data header stores the unique ID of the functional module, version number, target configuration area address, CRC32 check value, total number of fragments and current sequence number, reserved extension fields, etc. The payload data stores the binary payload data of the functional module, with its length dynamically adjusted according to the fragment size. The reserved area is used for future functional expansion, such as adding digital signatures. All fragment files are pre-stored in the first SPI FLASH on the CPU main control module side, supporting individual updates by module ID without requiring a complete program replacement.

[0101] Based on the above embodiments, in a preferred embodiment, the incremental loading and breakpoint resume mechanism specifically involves: transmitting the complete program package or loading necessary program modules during the initial loading; and initiating an incremental transmission process during subsequent updates, wherein the incremental transmission process is as follows:

[0102] Step a, Version Comparison: The CPU main control module sends a query command for the required updated module version to the FPGA computing module via the SPI bus to obtain the version number of each currently running functional module program;

[0103] Step b, Update Detection: The CPU main control module compares the target version stored locally with the current version of the FPGA computing module, and only updates the program of the functional module whose version number is greater than the current version number;

[0104] Step c, Record breakpoints: The FPGA operation module internally sets a load status register to record the received fragment sequence number in real time. When the transmission is interrupted (such as power fluctuations or communication errors), the data in this register is not lost.

[0105] Step d, Resumption Mechanism: After the device resumes communication, the CPU main control module actively reads the breakpoint record of the FPGA computing module and starts transmitting from the missing fragment to avoid retransmitting the received correct data.

[0106] Based on the above embodiments, in a preferred embodiment, the double-buffered loading and verification mechanism is as follows: Two independent temporary buffers and a processing area are divided within the FPGA computing module. When the FPGA computing module receives fragmented data, it first writes it to the temporary buffer and performs CRC32 verification and validity checks. After successful data verification, the data is copied from the temporary buffer to the processing area through the internal configuration interface of the FPGA computing module, awaiting further processing. If verification fails, the fragment is cleared, and an error response is sent to the CPU main control module via the SPI bus. Upon receiving the error response data, the CPU main control module retransmits the fragmented data to ensure that the processing area always stores a valid program. After all fragments are transmitted, the FPGA computing module sends a loading completion command, and the CPU main control module triggers a partial update signal from the FPGA computing module. The updated function module program is dynamically loaded in real time and takes effect without requiring a system restart.

[0107] Based on the above embodiments, in a preferred embodiment, resource scheduling achieves collaborative optimization of CPU and FPGA resources through task attribute modeling, real-time resource monitoring, and dynamic scheduling algorithms. The specific processing steps of resource scheduling are as follows:

[0108] Step S1: Generate the task attribute model table and update the resource monitoring status table;

[0109] The CPU main control module generates tasks to be executed and establishes a task attribute model for each task, marking priority level, resource requirement list, and response time deadline. Priority levels are divided into P0, P1, P2, and P3, where P0 is urgent, P1 is high, P2 is medium, and P3 is low. The smaller the priority value, the higher the priority, and the priority is scalable. The resource requirement list quantifies the types and quantities of FPGA resources required by the task, including logic resources, storage resources, and computing resources; the resource requirement list is scalable. The response time deadline marks the upper limit of the task's response time and execution cycle; the response time deadline is scalable.

[0110] The FPGA integrates a resource monitoring module that scans resource status in real time via hardware logic. Its sub-steps are as follows:

[0111] Step S11, Resource Status Tracking: Continuously monitor the usage of various types of resources and record information such as the total capacity, occupancy, and available balance of each type of resource;

[0112] Step S12, Topology modeling: Establish a dynamic mapping relationship table between physical resources and logical functions, record the ID of the currently running module, the type / quantity of resources occupied, the starting address, and mark non-reconfigurable areas to avoid task allocation conflicts;

[0113] Step S13, Load Prediction Feedback: The resource monitoring module sends the resource occupancy table and load rate (current resource utilization = occupancy / total capacity) to the CPU main control module in real time via SPI interrupt. The CPU main control module performs resource demand analysis based on the monitoring data to provide a basis for dynamic resource allocation.

[0114] Step S2: The CPU main control module executes a triple intelligent scheduling strategy to achieve optimal resource allocation based on the task priority of the task to be executed, the resource requirement list, the real-time load status of the FPGA computing module, and the available margin in the resource monitoring table.

[0115] Step S21: Check resource availability;

[0116] If there are sufficient resources and the task requirements are met, proceed directly to the task execution phase.

[0117] If resources are insufficient, then task priority will be determined:

[0118] The system determines the priorities of the task to be executed and the currently executing task. If the priority of the task to be executed is higher than that of the currently executing task, the currently executing lower-priority task is paused and its state is saved. The context of the lower-priority task (intermediate data, status parameters) is temporarily stored in the BRAM area reserved by the FPGA computing module, and the resources occupied by the lower-priority task are released for use by the higher-priority task. If the priority of the task to be executed is lower than that of the currently executing task, the system waits for the currently executing higher-priority task to complete and for the resources to be released before proceeding. For example, when a P0-level fault detection task is triggered, the P2-level data filtering task can be paused and the DSP core it occupies can be released.

[0119] Step S22: Preemption determination;

[0120] During the task execution phase, the task being executed runs on the allocated resources. During this phase, the resource monitoring module continuously tracks the resource status. If a higher-priority task triggers preemption during task execution, the current task is paused and its resources are released, allowing the higher-priority task to be executed first. After the task is completed, it is determined whether the task occupied the preempted resources. If it was preempted, a resource reclamation operation is performed to release the preempted resources and update the resource monitoring table. If it was a normally allocated resource, the resource it occupied is released directly.

[0121] Step S23: Task queue check;

[0122] After the resources are released, the CPU main control module checks if there are any waiting tasks. If there are, it returns to step S1 and repeats the above scheduling process. If not, the CPU main control module enters an idle state.

[0123] Based on the above embodiments, in a preferred embodiment, the resource scheduling unit prioritizes allocating continuous and available resource addresses to tasks during processing to reduce resource fragmentation; for example, it allocates two adjacent BRAMs (with continuous addresses) to a task instead of two separate independent BRAMs to improve data access efficiency.

[0124] Based on the above embodiments, in a preferred embodiment, resource scheduling further includes adaptive load balancing adjustment during the processing: when the load rate of the FPGA computing module is greater than the set overload threshold, the CPU triggers a load reduction strategy, suspends low-priority tasks and releases resources; when the load rate of the FPGA computing module is lower than the low-load threshold, the CPU starts a load increase strategy, wakes up waiting low-priority tasks or assigns new tasks, and ensures that resource utilization is maintained in the optimal range through real-time value assignment perception and elastic resource scheduling.

[0125] Based on the above embodiments, in a preferred embodiment, the overload threshold is 90%, the underload threshold is 30%, and the optimal range of resource utilization is 40%~80%.

[0126] Based on the above embodiments, in a preferred embodiment, the execution task of resource scheduling is transmitted via the SPI bus. Optimizing the SPI bus can improve transmission efficiency and reliability. The steps for SPI bus optimization are as follows:

[0127] Step A1: The CPU main control module configures the SPI to DMA transfer mode, and the subsequent sending and receiving of data frames are automatically completed by the DMA channel;

[0128] Step A2: Data transmission and priority processing;

[0129] The CPU main control module initiates DMA transfer by writing the address and length of the data frame to be sent into the DMA channel descriptor, triggering a DMA transfer request. The DMA then begins reading data from memory and sending it to the SPI bus. After receiving the data frame, the SPI interface of the FPGA computing module directly writes it into the temporary buffer of the FPGA computing module without the involvement of the FPGA core. There are no CPU interrupts throughout the process. The CPU only sends a completion interrupt to the CPU main control module when the DMA transfer is completed. The CPU main control module responds to the interrupt, updates the transfer status, and prepares for the next DMA transfer.

[0130] During transmission, data is sent in a dual-mode frame structure, which includes instruction frames and data frames. Instruction frames are management frames with high priority, used to transmit control commands and status queries. They can preempt the bus during transmission, interrupting the current data frame transmission. Instruction frames are sent directly through the CPU main control module. Data frames have low priority and are used to transmit program fragments and task data. They are transmitted in the order of the transmission queue and cannot preempt the bus. Data frame transmission is automatically completed by the DMA channel. After transmission is completed, the CPU main control module is notified to update the transmission status through a DMA interrupt.

[0131] When the SPI interface of the FPGA computing module detects that the frame header is a management frame during data transmission, it immediately triggers an SPI receive interrupt. The FPGA pauses the current data frame processing flow, prioritizes the execution of the control instructions corresponding to the management frame, and sends an interrupt to the CPU main control module after completion to synchronize the instruction execution results. The FPGA computing module then resumes DMA data frame transmission. If the frame header is a data frame, it directly enters the normal data transmission flow. The data frame is automatically written to the temporary buffer of the FPGA computing module through the DMA controller without the involvement of the CPU main control module.

[0132] Step A3: Transmission verification and adaptive clock adjustment;

[0133] Step A31: Data CRC verification;

[0134] After each frame of data transmission is completed, data CRC verification is performed. If the verification is successful, the process returns to the SPI data transmission stage in step A2. If the verification fails, the number of consecutive failures is judged.

[0135] Step A32: Determine the number of consecutive failures;

[0136] If the number of consecutive failures is greater than or equal to 3, it is determined that the current environment is under strong interference, triggering the adaptive adjustment of the SPI clock frequency to automatically reduce the clock frequency to improve transmission stability; if the number of consecutive failures is less than 3, it returns to the SPI data transmission stage of step A2.

[0137] Step A33: Successful adjustment determination;

[0138] After the SPI clock frequency is adaptively adjusted, it is determined whether the adjustment was successful within a specified time. If so, the process returns to the SPI data transmission stage in step A2 and continues to transmit using the new frequency; otherwise, the process proceeds to determine the number of adjustments.

[0139] Step A34: Adjustment count judgment;

[0140] If the number of adjustments is less than 10, return to step A32 to trigger adaptive adjustment of the SPI clock frequency;

[0141] If the number of adjustments is greater than or equal to 10, an error log will be recorded and an alert will be triggered. The process will then be terminated, awaiting manual intervention for investigation.

[0142] Specifically, the formats of command frames and data frames are as follows: Figure 5 As shown.

[0143] Based on the above embodiments, in a preferred embodiment, the SPI clock frequency is adaptively adjusted by the CPU main control module dynamically adjusting the SPI clock frequency according to the transmitted content and the intensity of environmental interference. When transmitting instruction frames, the highest clock frequency supported by the system is used to shorten the instruction response time and ensure that critical control instructions take effect quickly. When transmitting data frames, a medium frequency is used. If three consecutive frames fail to verify, it is determined to be a strong interference environment, and the frequency is automatically reduced. After ten consecutive successful transmissions, the frequency gradually increases back to the highest frequency. This balances transmission speed and stability, and adapts the optimal transmission clock frequency according to the environment.

[0144] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the present invention. Although detailed descriptions have been provided with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments, and they should all be covered within the protection scope of the claims.

Claims

1. A method for dynamic loading and resource scheduling of CPU-FPGA co-programs based on SPI, characterized in that, It is based on a CPU-FPGA collaborative embedded system, which includes a CPU main control module, a DMA controller, an FPGA computing module, an external interface module, and a power supply module. The CPU main control module is connected to a first SPI FLASH via an SPI bus to store program and configuration information. The CPU main control module interacts with the external interface module through an SGMII high-speed Ethernet interface and a UART serial communication interface. The DMA controller is connected to the CPU main control module and the FPGA computing module via an SPI bus. The FPGA computing module is connected to a second SPI FLASH to store its own configuration program and computing parameters. The JTAG debugging interface of the FPGA computing module is connected to the external interface module. The power supply module provides power to the entire CPU-FPGA collaborative embedded system. The method includes collaborative dynamic loading, resource scheduling, and SPI bus optimization; The dynamic loading includes program fragmentation and data structure design, incremental loading and breakpoint resume mechanism, and double buffer loading and verification mechanism. The resource scheduling includes establishing a task attribute model, real-time monitoring and mapping of FPGA resources, and dynamic scheduling algorithms. The SPI bus optimization includes dual-mode frame structure transmission design, adaptive SPI clock adjustment, and interrupt and DMA coordinated transmission.

2. The method for dynamic loading and resource scheduling of CPU-FPGA co-programs based on SPI according to claim 1, characterized in that, The program segmentation and data structure design is as follows: the configuration program of the FPGA operation module is split according to the functional modules, and different functional modules are loaded into different logical segments of the FPGA operation module; each logical segment contains a three-level structure, namely data header, payload data and reserved area. All segment files are pre-stored in the first SPI FLASH connected to the CPU main control module, which supports individual updates by module ID without replacing the entire program.

3. The method for dynamic loading and resource scheduling of CPU-FPGA co-programs based on SPI according to claim 1, characterized in that, The incremental loading and breakpoint resume mechanism is as follows: The entire program package or necessary program modules are transferred during the initial load. Subsequent updates initiate an incremental transfer process, which is as follows: Step a, Version Comparison: The CPU main control module sends a query command for the required updated module version to the FPGA computing module via the SPI bus to obtain the version number of each currently running functional module program; Step b, Update Detection: The CPU main control module compares the target version stored locally with the current version of the FPGA computing module, and only updates the program of the functional module whose version number is greater than the current version number; Step c, Record breakpoints: The FPGA operation module internally sets a load status register to record the received fragment sequence number in real time. When the transmission is interrupted, the data in this register is not lost. Step d, Resumption Mechanism: After the device resumes communication, the CPU main control module actively reads the breakpoint record of the FPGA computing module and starts transmitting from the missing fragment to avoid retransmitting the received correct data.

4. The CPU-FPGA co-program dynamic loading and resource scheduling method based on SPI according to claim 1, characterized in that, The dual-buffered loading and verification mechanism works as follows: Two independent temporary buffers and a computation area are defined within the FPGA computing module. When the FPGA computing module receives fragmented data, it first writes it to the temporary buffer and performs CRC32 verification and validity checks. After successful verification, the data is copied from the temporary buffer to the computation area via the FPGA computing module's internal configuration interface, awaiting further processing. If verification fails, the fragment is cleared, and an error response is sent to the CPU main control module via the SPI bus. Upon receiving the error response data, the CPU main control module retransmits the fragmented data to ensure that the computation area always stores a valid program. After all fragments are transmitted, the FPGA computing module sends a loading completion command, and the CPU main control module triggers a partial update signal from the FPGA computing module. The update function module program is dynamically loaded and takes effect in real time without requiring a system restart.

5. The method for dynamic loading and resource scheduling of CPU-FPGA co-programs based on SPI according to any one of claims 1-4, characterized in that, The steps for resource scheduling are as follows: Step S1: Generate the task attribute model table and update the resource monitoring status table; The CPU main control module generates tasks to be executed and establishes a task attribute model for each task, marking the priority level, resource requirement list and response time deadline; the priority levels are divided into P0, P1, P2 and P3, P0 is urgent, P1 is high, P2 is medium and P3 is low. The smaller the priority value, the higher the priority, and the priority can be expanded. The resource requirements list is used to quantify the types and quantities of FPGA resources required for a task. The FPGA resource types include logic resources, storage resources, and computing resources. The resource requirements list is expandable. The response time deadline is used to mark the upper limit of the task response time and the execution cycle. The response time deadline is expandable. The FPGA integrates a resource monitoring module that scans resource status in real time via hardware logic. Its sub-steps are as follows: Step S11, Resource Status Tracking: Continuously monitor the usage of various types of resources and record the total capacity, occupancy, and available balance of each type of resource; Step S12, Topology modeling: Establish a dynamic mapping relationship table between physical resources and logical functions, record the ID of the currently running module, the type / quantity of resources occupied, the starting address, and mark non-reconfigurable areas to avoid task allocation conflicts; Step S13, Load Prediction Feedback: The resource monitoring module sends the resource occupancy table and load rate to the CPU main control module in real time via SPI interrupt. The CPU main control module performs resource demand analysis based on the monitoring data to provide a basis for dynamic resource allocation. Step S2: The CPU main control module executes a triple intelligent scheduling strategy based on the task priority of the task to be executed, the resource requirement list, the real-time load status of the FPGA computing module, and the available margin in the resource monitoring table. Step S21: Check resource availability; If there are sufficient resources and the task requirements are met, proceed directly to the task execution phase. If resources are insufficient, then task priority will be determined: Determine the priority of the task to be executed and the task currently being executed. If the priority of the task to be executed is higher than that of the task currently being executed, pause the low-priority task being executed and save its state, and release the resources occupied by the low-priority task for the high-priority task to use. If the priority of the task to be executed is lower than that of the task currently being executed, wait for the high-priority task being executed to complete and wait for the resources to be released before executing. Step S22: Preemption determination; During the task execution phase, the task being executed runs on the allocated resources. During this phase, the resource monitoring module continuously tracks the resource status. If a higher priority task triggers preemption during task execution, the current task is paused and resources are released, allowing the higher priority task to be executed first. After the task is completed, determine whether the task has occupied preempted resources. If it has preempted resources, perform a resource reclamation operation to release the preempted resources and update the resource monitoring table. If it has normally allocated resources, directly release the resources it occupies and update the resource monitoring table. Step S23: Task queue check; After the resources are released, the CPU main control module checks if there are any waiting tasks. If there are, it returns to step S1 and repeats the above scheduling process. If not, the CPU main control module enters an idle state.

6. The method for dynamic loading and resource scheduling of CPU-FPGA co-programs based on SPI according to claim 5, characterized in that, During the processing, the resource scheduling unit prioritizes allocating continuously available resource addresses to tasks.

7. The CPU-FPGA co-program dynamic loading and resource scheduling method based on SPI according to claim 6, characterized in that, Resource scheduling also includes adaptive load balancing during the process: when the load rate of the FPGA computing module is greater than the set overload threshold, the CPU triggers a load reduction strategy, suspends low-priority tasks and releases resources; when the load rate of the FPGA computing module is lower than the low-load threshold, the CPU starts a load increase strategy, wakes up waiting low-priority tasks or assigns new tasks, and ensures that resource utilization is maintained in the optimal range through real-time value perception and elastic resource scheduling.

8. The CPU-FPGA co-program dynamic loading and resource scheduling method based on SPI according to claim 7, characterized in that, The overload threshold is 90%, the underload threshold is 30%, and the optimal range for resource utilization is 40% to 80%.

9. The method for dynamic loading and resource scheduling of CPU-FPGA co-programs based on SPI according to claim 8, characterized in that, The execution task of the resource scheduling requires transmission via the SPI bus, and the steps for SPI bus optimization are as follows: Step A1: The CPU main control module configures the SPI to DMA transfer mode, and the subsequent sending and receiving of data frames are automatically completed by the DMA channel; Step A2: Data transmission and priority processing; The CPU main control module initiates DMA transfer by writing the address and length of the data frame to be sent into the DMA channel descriptor, triggering a DMA transfer request. The DMA then begins reading data from memory and sending it to the SPI bus. After receiving the data frame, the SPI interface of the FPGA computing module directly writes it into the temporary buffer of the FPGA computing module without the involvement of the FPGA core. There are no CPU interrupts throughout the process. The CPU only sends a completion interrupt to the CPU main control module when the DMA transfer is completed. The CPU main control module responds to the interrupt, updates the transfer status, and prepares for the next DMA transfer. During transmission, data is sent in a dual-mode frame structure, which includes instruction frames and data frames. The instruction frame is a management frame with high priority, used to transmit control commands and status queries. It can preempt the bus during transmission and interrupt the current data frame transmission. The instruction frame is sent directly through the CPU main control module. Data frames are low priority and are used to transmit program fragments and task data. They are transmitted in the order of the transmission queue and cannot preempt the bus. Data frame transmission is automatically completed by the DMA channel. After transmission is completed, the CPU main control module is notified to update the transmission status through a DMA interrupt. When the SPI interface of the FPGA computing module detects that the frame header is a management frame during data transmission, it immediately triggers an SPI receive interrupt. The FPGA pauses the current data frame processing flow, prioritizes the execution of the control instructions corresponding to the management frame, and sends an interrupt to the CPU main control module after completion to synchronize the instruction execution results. The FPGA computing module then resumes DMA data frame transmission. If the frame header is a data frame, it directly enters the normal data transmission flow. The data frame is automatically written to the temporary buffer of the FPGA computing module through the DMA controller without the involvement of the CPU main control module. Step A3: Transmission verification and adaptive clock adjustment; Step A31: Data CRC verification; After each frame of data transmission is completed, data CRC verification is performed. If the verification is successful, the process returns to the SPI data transmission stage in step A2. If the verification fails, the number of consecutive failures is judged. Step A32: Determine the number of consecutive failures; If the number of consecutive failures is greater than or equal to 3, it is determined that the current environment is under strong interference, triggering the adaptive adjustment of the SPI clock frequency to automatically reduce the clock frequency to improve transmission stability. If the number of consecutive failures is less than 3, return to the SPI data transmission stage in step A2; Step A33: Successful adjustment determination; After the SPI clock frequency is adaptively adjusted, it is determined whether the adjustment was successful within a specified time. If so, the process returns to the SPI data transmission stage in step A2 and continues to transmit using the new frequency; otherwise, the process proceeds to determine the number of adjustments. Step A34: Adjustment count judgment; If the number of adjustments is less than 10, return to step A32 to trigger adaptive adjustment of the SPI clock frequency; If the number of adjustments is greater than or equal to 10, an error log will be recorded and an alert will be triggered. The process will then be terminated, awaiting manual intervention for investigation.

10. The method for dynamic loading and resource scheduling of CPU-FPGA co-programs based on SPI according to claim 9, characterized in that, The SPI clock frequency adaptive adjustment is achieved by the CPU main control module dynamically adjusting the SPI clock frequency according to the transmitted content and the intensity of environmental interference. When transmitting instruction frames, the highest clock frequency supported by the system is used; when transmitting data frames, a medium frequency is used. When three consecutive frames fail to verify, it is determined to be a strong interference environment, and the frequency is automatically reduced. After ten consecutive frames are successfully transmitted, the frequency gradually increases back to the highest frequency.

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