Test question examination method and device, electronic equipment and computer storage medium

Abstract

The application provides a test method for testing a test problem, which comprises the following steps: obtaining corresponding first fault information under a first test mode, the first fault information comprising a first test condition, a first test vector, and a first logical address of a plurality of first failed storage units in a chip to be tested, and obtaining a first test vector type corresponding to each first test vector; determining a test strength corresponding to the first test mode; generating a test program of a second test mode based on the first test condition, the first test vector type, and the test strength; performing a function test on the chip to be tested by using the test program of the second test mode; obtaining second fault information, the second fault information comprising a second logical address of a plurality of second failed storage units in the chip to be tested; and determining whether the test result corresponding to the first test mode is incorrect based on the first logical address and the second logical address. Thus, the test result of the chip to be tested obtained under the first test mode is detected.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a method, apparatus, electronic device, and computer storage medium for testing problems. Background Technology

[0002] In wafer (CP) testing of memory chips, the behavior of writing and reading parameters to the chip is called functional testing.

[0003] To perform functional testing on a memory chip, the expected values ​​for writing and reading must be set in advance. Then, the actual measured data values ​​for writing and reading are compared with the pre-set expected values. If the actual measured data values ​​are equal to the expected values, the memory chip is qualified; otherwise, the memory chip is unqualified.

[0004] In existing technologies, the development and review of test code by humans may introduce test problems. As a result, during the subsequent testing of memory chips based on the test code, a qualified memory chip may be mistakenly identified as a defective memory chip, which means that the test of memory chips is incorrect, resulting in test errors and affecting the yield. Summary of the Invention

[0005] This invention provides a method, apparatus, electronic device, and computer storage medium for testing problems, aiming to detect the test results of the chip under test obtained in a first test mode.

[0006] According to a first aspect of the present invention, the technical solution of the present invention provides a method for testing a problem, comprising: In the first test mode, the chip under test is functionally tested and the corresponding first fault information is obtained. The first fault information includes the first test condition, the first test vector, and the first logical address of a plurality of first failure memory units in the chip under test corresponding to the first test mode. Based on the first test vector, obtain the first test vector type corresponding to each first test vector; Determine the test intensity corresponding to the first test mode; Based on the first test conditions, the first test vector type, and the test intensity, a test program for the second test mode is generated; The chip under test is functionally tested using the test program of the second test mode to obtain second fault information, which includes the second logical address of a plurality of second failure memory units in the chip under test. Based on the first logical address and the second logical address, determine whether the test result corresponding to the first test mode is incorrect.

[0007] Optionally, determining the test intensity corresponding to the first test mode includes: Determine the test algorithm corresponding to each of the first failed storage units under the first test mode; Based on the test algorithm corresponding to each first failed storage unit under the first test mode, the number of read operations for each first failed storage unit is determined. Based on the number of read operations for each of the first failed memory cells, the first read equivalent stress intensity for each of the first failed memory cells is determined. The first read equivalent stress intensity of each first failed memory cell is accumulated to obtain the test intensity corresponding to the first test mode.

[0008] Optionally, based on the number of read operations for each of the first failed memory cells, the first read equivalent stress intensity corresponding to each of the first failed memory cells is determined, including: Determine the maximum address bit of the row containing the first failed memory cell and the cell address bit of the first failed memory cell in the chip under test; Based on the maximum address bit, the cell address bit, and the number of read operations, the first read equivalent force intensity of the test algorithm on the first failed storage cell is obtained.

[0009] Optionally, determining whether the test result corresponding to the first test mode is incorrect based on the first logical address and the second logical address includes: Based on the first logical address of the plurality of first failed memory units, the corresponding first failure mode is obtained. The first failure mode is used to characterize the feature image formed by the plurality of first failed memory units in the physical space. Based on the second logical address, the corresponding second failure mode is obtained, and the second failure mode characterizes the feature image formed by the second failure storage unit in the physical space. The first failure mode is compared with the second failure mode to determine whether there is an error in the test result corresponding to the first test mode.

[0010] Optionally, the first failure mode is compared with the second failure mode to determine whether there is an error in the test result of the first test mode, including: Based on the first failure mode and the second failure mode, determine the first failure type corresponding to the first failure mode and the second failure type corresponding to the second failure mode; If the first failure type and the second failure type are different, then it is determined that the test result of the first test mode is incorrect.

[0011] Optionally, comparing the first failure mode with the second failure mode to determine whether there is an error in the test result of the first test mode further includes: If the first failure type and the second failure type are the same, and both are quarter block failure types, determine whether the number of the second logical addresses is equal to the number of the first logical addresses; If the number of the second logical addresses is equal to the number of the first logical addresses, then the test result of the first test mode is determined to be correct. If the number of the second logical addresses is not equal to the number of the first logical addresses, then it is determined that there is an error in the test result of the first test mode.

[0012] Optionally, comparing the first failure mode with the second failure mode to determine whether there is an error in the test result of the first test mode further includes: If the first failure type and the second failure type are the same, and both are single-word line failure types, then the test result of the first test mode is determined to be correct.

[0013] According to a second aspect of the present invention, the technical solution of the present invention provides a testing device for implementing the testing method for the above-described testing problem, comprising: The first test module is used to perform functional tests on the chip under test in a first test mode and obtain corresponding first fault information. The first fault information includes a first test condition corresponding to the first test mode, a first test vector, and a first logical address of a plurality of first failure memory units in the chip under test. The test vector type determination module is used to obtain the first test vector type corresponding to each first test vector based on the first test vector; The test intensity determination module is used to determine the test intensity corresponding to the first test mode; The test program generation module is used to generate a test program for the second test mode based on the first test conditions, the first test vector type, and the test intensity. The second logical address acquisition module is used to perform functional testing on the chip under test using the test program of the second test mode, and acquire second fault information, the second fault information including the second logical address of a plurality of second failed memory units in the chip under test; The judgment module determines whether the test result corresponding to the first test mode is incorrect based on the first logical address and the second logical address.

[0014] According to a third aspect of the present invention, the present invention provides an electronic device, including a memory and a processor for storing code, wherein the processor is configured to execute the code in the memory to implement the verification method for the aforementioned test problem.

[0015] According to a fourth aspect of the present invention, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the verification method for the test problem as described above.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: The present invention provides a method, apparatus, electronic device, and computer storage medium for testing problems. In a first test mode, functional testing is performed on the chip under test, and corresponding first fault information is obtained. This first fault information includes a first test condition, a first test vector, and the first logical address of a plurality of first failed memory cells in the chip under test corresponding to the first test mode. Based on the first test vector, a first test vector type corresponding to each first test vector is obtained. The test intensity corresponding to the first test mode is determined. Based on the first test condition, the first test vector type, and the test intensity, a test program for a second test mode is generated. Therefore, the test intensity of the second test mode matches that of the first test mode, and the test conditions and test vector types of the second test mode are set to be the same as those of the first test mode. Furthermore, since the chip under test is functionally tested using the test program of the second test mode, and second fault information is obtained, including the second logical address of a plurality of second failed memory cells in the chip under test, the test result corresponding to the first test mode is judged to be erroneous based on the first logical address and the second logical address. Therefore, the test result of the chip under test obtained in the first test mode is detected. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the testing method for the test problem in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the testing device for the test problem according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0019] As described in the background section, how to detect the test results of the chip under test obtained in the first test mode has become a technical problem that the industry needs to solve.

[0020] In view of this, the technical solution of the present invention provides a method for verifying test problems. In a first test mode, functional testing is performed on the chip under test, and corresponding first fault information is obtained. The first fault information includes a first test condition corresponding to the first test mode, a first test vector, and a first logical address of a plurality of first failed memory cells in the chip under test. Based on the first test vector, a first test vector type corresponding to each first test vector is obtained. The test intensity corresponding to the first test mode is determined. Based on the first test condition, the first test vector type, and the test intensity, a test program for a second test mode is generated. Furthermore, by performing functional testing on the chip under test using the test program of the second test mode, second fault information is obtained. The second fault information includes a second logical address of a plurality of second failed memory cells in the chip under test. Based on the first logical address and the second logical address, it is determined whether the test result corresponding to the first test mode is incorrect. Therefore, the test result of the chip under test obtained in the first test mode is detected.

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0024] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 This is a flowchart illustrating the detection method for testing problems according to an embodiment of the present invention.

[0026] Please refer to Figure 1 The embodiments of the present invention provide a method for detecting test problems, which may include: S100: In the first test mode, perform functional tests on the chip under test and obtain the corresponding first fault information. The first fault information includes the first test conditions, the first test vector, and the first logical address of a plurality of first failure memory units in the chip under test corresponding to the first test mode.

[0027] The first test mode can be as described in the background section, where the chip under test is tested using manually written test code.

[0028] In this embodiment, the test conditions refer to the condition parameters provided by the test equipment when testing the chip under test, such as voltage, temperature and timing conditions.

[0029] In this embodiment, the first test conditions may include: test voltage, test temperature, and test timing.

[0030] In this embodiment, a test vector refers to a specific set of data used in memory testing to verify the correctness of the memory chip's functionality.

[0031] In this embodiment, test vectors can be expressed based on different algorithms. The test vector type corresponds to the algorithm used to express the test vector, such as MARCH-type algorithms, Checkerboard algorithms, or SCAN algorithms.

[0032] In this embodiment, the first test vector type is any one of the following: MARCH algorithm, Checkerboard algorithm, or SCAN algorithm.

[0033] In this embodiment, a failed memory cell refers to a faulty memory cell identified in the chip under test after performing a CP test. The logical address of the failed memory cell refers to the address information of the faulty memory cell in the chip under test.

[0034] In this embodiment, after the test code based on the first test mode tests the chip under test, the corresponding test results can be obtained, that is, the corresponding first fault information can be obtained, namely the first test conditions, the first test vector and the first logical address of several first failure memory units.

[0035] S200: Based on the first test vector, obtain the first test vector type corresponding to each first test vector.

[0036] As mentioned earlier, the test vector type corresponds to the algorithm used to express the test vector.

[0037] In this embodiment, the corresponding first test vector type can be obtained based on the first test vector.

[0038] S300: Determine the test intensity corresponding to the first test mode.

[0039] The test intensity is characterized as the total intensity of the first read equivalent force applied to all the first failed memory cells under the first test mode.

[0040] In this embodiment, after performing CP testing based on the first test mode and determining the corresponding first failed memory cell, the test intensity of the corresponding first test mode can be obtained by applying a first read equivalent force to all the first failed memory cells and based on the applied first read equivalent force.

[0041] S400: Based on the first test conditions, the first test vector type, and the test intensity, generate a test program for the second test mode.

[0042] Specifically, a test program for testing the test results corresponding to the first test mode can be generated based on the first test conditions, the first test vector type, and the corresponding test intensity corresponding to the first test mode, that is, a test program corresponding to the second test mode can be generated.

[0043] S500: Perform functional testing on the chip under test using the test program of the second test mode, and obtain second fault information. The second fault information includes the second logical address of a plurality of second failure memory units in the chip under test.

[0044] In this embodiment, the second fault information may further include a second test condition and a second test vector corresponding to the second test mode. The second test condition is the same as the first test condition, and the test vector type of the second test vector is the same as the first test vector type.

[0045] In this embodiment, the second fault storage unit is the fault storage unit determined in the chip under test after performing a CP test on the chip under test in the second test mode.

[0046] S600: Based on the first logical address and the second logical address, determine whether the test result corresponding to the first test mode is incorrect.

[0047] In this embodiment, after the chip under test is tested in the second test mode based on the test program, the test result corresponding to the first test mode can be compared with the first logical address corresponding to the first test mode and the second logical address corresponding to the second test mode to determine whether the test result corresponding to the first test mode is incorrect.

[0048] As can be seen, this invention achieves the detection of test results for the chip under test obtained under the first test mode by matching the equivalent capabilities of the second test mode and the first test mode, and by matching the test conditions and test vector types of the second test mode with those of the first test mode, respectively. Based on this, the first test mode is tested using the second test mode, and the test result corresponding to the first test mode is determined to be erroneous based on the first logical address and the second logical address.

[0049] As a specific embodiment, S300, determining the test intensity corresponding to the first test mode may include: S310: Determine the test algorithm corresponding to each of the first failed memory units under the first test mode.

[0050] The test algorithm is an algorithm for reading and writing the first failed memory unit in the first test mode, specifically the MARCH algorithm or the Checkerboard algorithm.

[0051] In this embodiment, the test algorithm may include multiple read and write operations and corresponding operands. For example, a read and write operation with operand R0 indicates that a value is read from the memory unit, and the expected value is logic 0.

[0052] In this embodiment, the testing algorithm is different, resulting in different numbers and operations for each first failed memory cell.

[0053] S320: Based on the aforementioned test algorithms, determine the number of read operations for each first failed memory cell.

[0054] In this embodiment, after determining the test algorithm corresponding to each of the first failed storage units, read and write operations can be performed on each of the failed storage units based on the test algorithm corresponding to each of the first failed storage units, and the number of read and write operations corresponding to the test algorithm corresponding to each of the first failed storage units can be determined from the test algorithms corresponding to each of the first failed storage units, so as to determine the number of read operations corresponding to each of the first failed storage units.

[0055] In one specific embodiment, the test algorithm (r0, w1, r1) is represented by 3 read operations, i.e., read 0, write 1, read 0.

[0056] S330: Based on the number of read operations for each of the first failed memory cells, determine the first read equivalent stress intensity corresponding to each of the first failed memory cells.

[0057] In this embodiment, after determining the number of read operations for each first failed memory cell, the corresponding first read equivalent stress intensity can be determined based on the number of read operations and the relevant information of the corresponding first failed memory cell.

[0058] S340: The first read equivalent stress intensity of each first failed memory cell is accumulated to obtain the test intensity corresponding to the first test mode.

[0059] As a specific implementation, S330: Determining the first read equivalent stress intensity corresponding to each of the first failed memory cells based on the number of read operations of each of the first failed memory cells may include: S331: Determine the maximum address bit of the row containing the first failed memory cell and the cell address bit of the first failed memory cell in the chip under test.

[0060] The maximum address bit is equal to the number of memory cells in the row where the first failed memory cell is located in the chip under test.

[0061] S332: Based on the maximum address bit, the cell address bit, and the number of read operations, obtain the first read equivalent force intensity of the test algorithm on the first failed storage cell.

[0062] In this embodiment, the first read equivalent stress intensity of the test algorithm on the first failed memory cell is obtained based on the maximum address bit, the cell address bit, and the number of read operations, and can be determined by the following formula: RES=(Ni)·op Where N is the maximum address bit of the row where the first failed memory cell is located, i is the cell address bit of the first failed memory cell, op is the number of read operations, and RES is the first read equivalent stress intensity.

[0063] As a specific embodiment, determining whether the test result corresponding to the first test mode is incorrect based on the first logical address and the second logical address may include: S610: Based on the first logical address of the plurality of first failed storage units, obtain the corresponding first failure mode, wherein the first failure mode is used to characterize the feature image formed by the plurality of first failed storage units in physical space.

[0064] The failure modes can include quarter block failure, single word line failure, double word line failure, double bit line failure, single bit line failure, and single bit failure.

[0065] In this embodiment, a corresponding feature image can be constructed based on the first logical address of the first failed memory cell in the first test mode, and the corresponding failure mode can be determined, i.e., the first failure mode can be determined.

[0066] S620: Based on the second logical address, obtain the corresponding second failure mode, wherein the second failure mode characterizes the feature image formed by the second failure storage unit in the physical space.

[0067] In this embodiment, a corresponding feature image can be constructed based on the second logical address of the second failed storage unit under the second test mode, and the corresponding failure mode can be determined, i.e., the second failure mode can be determined.

[0068] S630: Compare the first failure mode with the second failure mode to determine whether there is an error in the test result corresponding to the first test mode.

[0069] In this embodiment, the accuracy of the test result of the first test mode is determined by comparing whether different feature images are the same, that is, by comparing the first failure mode with the second failure mode.

[0070] As one implementation method, S630, comparing the first failure mode with the second failure mode to determine whether there is an error in the test result of the first test mode, may include: S631: Based on the first failure mode and the second failure mode, determine the first failure type corresponding to the first failure mode and the second failure type corresponding to the second failure mode.

[0071] S632: If the first failure type and the second failure type are not the same, then it is determined that there is an error in the test result of the first test mode.

[0072] In this embodiment, the failure type corresponds to the failure mode, which can specifically include quarter block failure type, single word line failure type, double word line failure type, double bit line failure type, single bit line failure type, and single bit failure type, etc.

[0073] In this embodiment, after determining the first failure mode and the second failure mode, the corresponding failure type can be determined according to the failure mode, and the test results can be judged accordingly.

[0074] In one specific embodiment, if the first failure type is a quarter-block failure type and the second failure type is a single-word line failure type, that is, the failure types of the two tests are different, then it can be determined that there is an error in the test result of the first test mode.

[0075] In this embodiment, if the first failure type and the second failure type are the same, further testing is required.

[0076] In an optional implementation, S630, comparing the first failure mode with the second failure mode to determine whether there is an error in the test result of the first test mode, may further include: S633: If the first failure type and the second failure type are the same, and both are quarter-block failure types, determine whether the number of the second logical addresses is equal to the number of the first logical addresses.

[0077] The number of logical addresses refers to the number of failed memory units during the test.

[0078] S634: If the number of the second logical addresses is equal to the number of the first logical addresses, then the test result of the first test mode is determined to be correct.

[0079] S635: If the number of the second logical addresses is not equal to the number of the first logical addresses, then it is determined that there is an error in the test result of the first test mode.

[0080] In this embodiment, when the first failure type and the second failure type are the same and both are quarter-block failure types, and it is further determined that the number of failed memory cells in the first test mode is equal to the number of failed memory cells in the second test mode, the test result of the first test mode can be determined to be correct; otherwise, the test result of the first test mode is determined to be incorrect.

[0081] As another optional implementation, S630, comparing the first failure mode with the second failure mode to determine whether there is an error in the test result of the first test mode, may further include: S636: If the first failure type and the second failure type are the same, and both are single-word line faults, then the test result of the first test mode is determined to be correct.

[0082] In summary, the solution provided by the embodiments of the present invention involves performing functional testing on the chip under test in a first test mode and obtaining corresponding first fault information. The first fault information includes a first test condition, a first test vector, and the first logical address of a plurality of first failed memory cells in the chip under test corresponding to the first test mode. Based on the first test vector, a first test vector type corresponding to each first test vector is obtained. The test intensity corresponding to the first test mode is determined. Based on the first test condition, the first test vector type, and the test intensity, a test program for a second test mode is generated. Therefore, the test intensity of the second test mode matches that of the first test mode, and the test conditions and test vector types of the second test mode are set to be the same as those of the first test mode. Furthermore, since the chip under test is functionally tested using the test program of the second test mode, and second fault information is obtained, the second fault information includes the second logical address of a plurality of second failed memory cells in the chip under test. Based on the first logical address and the second logical address, it is determined whether the test result corresponding to the first test mode is incorrect. Therefore, the test result of the chip under test obtained in the first test mode is detected.

[0083] Accordingly, please refer to Figure 2 Embodiments of the present invention also provide a testing device for implementing the testing method for the testing problem as described above, which may include: The first test module 100 is used to perform functional tests on the chip under test in a first test mode and obtain corresponding first fault information. The first fault information includes a first test condition corresponding to the first test mode, a first test vector, and a first logical address of a plurality of first failure memory units in the chip under test.

[0084] The test vector type determination module 200 is used to obtain the first test vector type corresponding to each first test vector based on the first test vector.

[0085] The test intensity determination module 300 is used to determine the test intensity corresponding to the first test mode.

[0086] The test program generation module 400 is used to generate a test program for the second test mode based on the first test conditions, the first test vector type, and the test intensity.

[0087] The second logical address acquisition module 500 is used to perform functional testing on the chip under test using the test program of the second test mode, and acquire second fault information, the second fault information including the second logical addresses of a plurality of second failed memory units in the chip under test.

[0088] The judgment module 600 determines whether the test result corresponding to the first test mode is incorrect based on the first logical address and the second logical address.

[0089] As a specific embodiment, the test strength determination module 300 may include: The algorithm determination submodule is used to determine the test algorithm corresponding to each of the first failed storage units under the first test mode.

[0090] The operation count determination submodule is used to determine the number of read operations for each first failed storage unit based on the test algorithm corresponding to each first failed storage unit under the first test mode.

[0091] A single equivalent stress determination submodule is used to determine the first read equivalent stress intensity corresponding to each of the first failed memory cells based on the number of read operations performed on each of the first failed memory cells.

[0092] The test intensity determination submodule is used to accumulate the first read equivalent stress intensity of each first failed memory unit to obtain the test intensity corresponding to the first test mode.

[0093] In this embodiment, a single equivalent stress determination submodule includes: The address determination unit is used to determine the maximum address bit of the row where the first failed memory cell is located and the cell address bit of the first failed memory cell in the chip under test. An equivalent stress determination unit is used to obtain the first read equivalent stress intensity of the test algorithm on the first failed memory unit based on the maximum address bit, the unit address bit, and the number of read operations.

[0094] As a specific implementation method, the determination module may include: The first feature image acquisition submodule is used to acquire the corresponding first failure mode based on the first logical address of the plurality of first failed storage units. The first failure mode is used to characterize the feature image formed by the plurality of first failed storage units in the physical space. The second feature image acquisition submodule is used to acquire the corresponding second failure mode based on the second logical address. The second failure mode characterizes the feature image formed by the second failure storage unit in the physical space. The comparison and judgment submodule is used to compare the first failure mode with the second failure mode and determine whether there is an error in the test result corresponding to the first test mode.

[0095] In one optional embodiment, the comparison and judgment submodule may include: The failure type determination unit is used to determine a first failure type corresponding to the first failure mode and a second failure type corresponding to the second failure mode based on the first failure mode and the second failure mode.

[0096] The first judgment unit is used to determine that the test result of the first test mode is incorrect if the first failure type and the second failure type are not the same.

[0097] In another optional embodiment, the comparison and judgment submodule may further include: The second judgment unit is used to determine whether the number of the second logical addresses is equal to the number of the first logical addresses if the first failure type and the second failure type are the same and both are quarter-block failure types. The third judgment unit is used to determine that the test result of the first test mode is correct if the number of the second logical addresses is equal to the number of the first logical addresses. The fourth judgment unit is used to determine that the test result of the first test mode is incorrect if the number of the second logical addresses is not equal to the number of the first logical addresses.

[0098] In one implementation, the comparison and judgment submodule may further include: The fifth judgment unit is used to determine that the test result of the first test mode is correct if the first failure type and the second failure type are the same and both are single-word line fault types.

[0099] Since the testing device for the test problem in this embodiment corresponds to the testing method for the test problem described above, please refer to the detailed explanation of the corresponding part in the testing method for the test problem for the explanation of each feature structure in the testing device for the test problem in this embodiment, and it will not be repeated here.

[0100] In addition, please refer to Figure 3The present invention also provides an electronic device, including a memory 710, a processor 720, and a program stored in the memory 710 and executable on the processor 720. When the processor 720 executes the program, it performs the steps of the method described above. The processor 720 is capable of communicating with the memory 710 via a bus 730.

[0101] Furthermore, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the verification method for the test problem as described above.

[0102] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0103] In a typical configuration, a computer includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0104] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0105] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0106] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for verifying a test problem, characterized in that, include: In the first test mode, the chip under test is functionally tested and the corresponding first fault information is obtained. The first fault information includes the first test condition, the first test vector, and the first logical address of a plurality of first failure memory units in the chip under test corresponding to the first test mode. Based on the first test vector, obtain the first test vector type corresponding to each first test vector; Determine the test intensity corresponding to the first test mode; Based on the first test conditions, the first test vector type, and the test intensity, a test program for the second test mode is generated; The chip under test is functionally tested using the test program of the second test mode to obtain second fault information, which includes the second logical address of a plurality of second failure memory units in the chip under test. Based on the first logical address and the second logical address, determine whether the test result corresponding to the first test mode is incorrect.

2. The method for verifying the test problem as described in claim 1, characterized in that, Determining the test intensity corresponding to the first test mode includes: Determine the test algorithm corresponding to each of the first failed storage units under the first test mode; Based on the aforementioned test algorithms, the number of read operations for each first failed storage unit is determined; Based on the number of read operations for each of the first failed memory cells, the first read equivalent stress intensity for each of the first failed memory cells is determined. The first read equivalent stress intensity of each first failed memory cell is accumulated to obtain the test intensity corresponding to the first test mode.

3. The method for verifying the test problem as described in claim 2, characterized in that, Based on the number of read operations for each of the first failed memory cells, the first read equivalent stress intensity corresponding to each of the first failed memory cells is determined, including: Determine the maximum address bit of the row containing the first failed memory cell and the cell address bit of the first failed memory cell in the chip under test; Based on the maximum address bit, the cell address bit, and the number of read operations, the first read equivalent force intensity of the test algorithm on the first failed storage cell is obtained.

4. The testing method for the test problem as described in claim 1, characterized in that, The step of determining whether the test result corresponding to the first test mode is incorrect based on the first logical address and the second logical address includes: Based on the first logical address of the plurality of first failed memory units, the corresponding first failure mode is obtained. The first failure mode is used to characterize the feature image formed by the plurality of first failed memory units in the physical space. Based on the second logical address, the corresponding second failure mode is obtained, and the second failure mode characterizes the feature image formed by the second failure storage unit in the physical space. The first failure mode is compared with the second failure mode to determine whether there is an error in the test result corresponding to the first test mode.

5. The method for verifying the test problem as described in claim 4, characterized in that, The first failure mode is compared with the second failure mode to determine whether there is an error in the test result of the first test mode, including: Based on the first failure mode and the second failure mode, determine the first failure type corresponding to the first failure mode and the second failure type corresponding to the second failure mode; If the first failure type and the second failure type are different, then it is determined that the test result of the first test mode is incorrect.

6. The method for verifying the test problem as described in claim 5, characterized in that, The comparison between the first failure mode and the second failure mode to determine whether there is an error in the test result of the first test mode also includes: If the first failure type and the second failure type are the same, and both are quarter block failure types, determine whether the number of the second logical addresses is equal to the number of the first logical addresses; If the number of the second logical addresses is equal to the number of the first logical addresses, then the test result of the first test mode is determined to be correct. If the number of the second logical addresses is not equal to the number of the first logical addresses, then it is determined that there is an error in the test result of the first test mode.

7. The method for verifying the test problem as described in claim 5, characterized in that, The comparison between the first failure mode and the second failure mode to determine whether there is an error in the test result of the first test mode also includes: If the first failure type and the second failure type are the same, and both are single-word line failure types, then the test result of the first test mode is determined to be correct.

8. A testing device for a test problem, characterized in that, include: The first test module is used to perform functional tests on the chip under test in a first test mode and obtain corresponding first fault information. The first fault information includes a first test condition corresponding to the first test mode, a first test vector, and a first logical address of a plurality of first failure memory units in the chip under test. The test vector type determination module is used to obtain the first test vector type corresponding to each first test vector based on the first test vector; The test intensity determination module is used to determine the test intensity corresponding to the first test mode; The test program generation module is used to generate a test program for the second test mode based on the first test conditions, the first test vector type, and the test intensity. The second logical address acquisition module is used to perform functional testing on the chip under test using the test program of the second test mode, and acquire second fault information, the second fault information including the second logical address of a plurality of second failed memory units in the chip under test; The judgment module determines whether the test result corresponding to the first test mode is incorrect based on the first logical address and the second logical address.

9. An electronic device, characterized in that, The method includes a memory, a processor, and a program stored in the memory and executable on the processor, characterized in that the processor, when executing the program, implements the steps of the method according to any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-7.

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