Balancing circuit, communication method, and communication device

Abstract

Embodiments of the present application provide an equalization circuit, a communication method and a communication device, and relate to the field of communication, and are used for realizing real-time and automatic adjustment of system flatness according to dynamic scene changes. In the method, a first device can perform amplitude equalization on a first signal in a first bandwidth through P equalization sub-circuits respectively according to acquired flatness information, obtain P equalized signals, and superimpose the P equalized signals to obtain an equalized signal. The flatness information is used to indicate amplitude variation of a second signal in the first bandwidth, in other words, the flatness information can be used to indicate real-time system flatness, so that the first device can dynamically and automatically adjust the system flatness in real time according to the flatness information, to realize automatic amplitude equalization of the signal (such as the first signal) in the first bandwidth.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to an equalization circuit, a communication method, and a communication device. Background Technology

[0002] As communication bandwidth increases and frequency range expands, the amplitude uniformity of signals within the band deteriorates, resulting in poorer gain flatness. Summary of the Invention

[0003] This application provides an equalization circuit, a communication method, and a communication device to achieve real-time and automatic adjustment of the system's flatness according to dynamic scene changes.

[0004] To achieve the above objectives, this application adopts the following technical solution:

[0005] In a first aspect, an equalization circuit is provided, comprising: P equalization sub-circuits connected in parallel on an analog signal transmission line, where P is an integer greater than 1. Each of the P equalization sub-circuits performs amplitude equalization on a first signal to obtain P equalized signals, wherein the center frequencies of any two equalized signals are different, and / or the amplitudes corresponding to the center frequencies are different; the P equalized signals are superimposed and output through the analog signal transmission line.

[0006] As described in the first aspect, the equalization circuit includes multiple equalization sub-circuits connected in parallel on the analog signal transmission line. These multiple equalization sub-circuits, namely the aforementioned P equalization sub-circuits, can equalize the amplitude of the first signal at different frequency points, resulting in P equalized signals. The center frequencies of any two of the P equalized signals are different, and / or the amplitudes corresponding to those center frequencies are different. That is, each of the P equalization sub-circuits can create a dip of arbitrary amplitude at any frequency point. The P equalized signals are superimposed and output through the analog signal transmission line; that is, the first signal undergoes amplitude equalization through the equalization curve synthesized by the P equalization sub-circuits. Since the P equalization sub-circuits can synthesize an equalization curve with arbitrary waveforms, the flatness of the system can be automatically adjusted in real time according to changes in the dynamic scene, improving system performance. Furthermore, the waveform variation range of this equalization curve is large, which can meet the needs of different scenarios.

[0007] In one possible design, each of the P equalization sub-circuits includes an adjustable resistor unit and an adjustable resonator unit, which are connected in series. The adjustable resistor unit is used to adjust the amplitude of the first signal, and the adjustable resonator unit is used to adjust the frequency of the first signal. In this way, each of the P equalization sub-circuits can adjust both the amplitude and frequency of the first signal.

[0008] In one possible design, the adjustable resistor unit includes M fixed resistors connected in parallel, a series-to-parallel converter, and M switches. Each of the M switches corresponds one-to-one with one of the M fixed resistors. The series-to-parallel converter controls the M switches, which in turn control the conduction or deactivation of the M fixed resistors. The conduction or deactivation of the M fixed resistors is related to the resistance value formed by the M fixed resistors, where M is an integer greater than 1. Thus, the amplitude of the first signal can be adjusted by regulating the resistance value of each of the P equalization sub-circuits.

[0009] In one possible design, the adjustable resistor unit includes a sliding resistor and a mechanical device. The mechanical device is used to adjust the resistance value of the sliding resistor by adjusting the pins of the sliding resistor, so as to achieve precise and continuous adjustment of the resistance value of each of the P equalization sub-circuits, thereby achieving adjustment of the amplitude of the first signal.

[0010] In one possible design, the mechanical component is a mechanical servo motor, which reuses existing mechanical components to reduce the difficulty of implementation; alternatively, the mechanical component can be a new mechanical component to improve the flexibility of implementation, without limitation.

[0011] In one possible design, the adjustable resonator unit includes a variable capacitor, a fixed inductor, and a first digital-to-analog converter (DAC). The variable capacitor and the fixed inductor are connected in series. The variable capacitor is connected to the first DAC, which adjusts the capacitance value of the variable capacitor by adjusting the voltage value. It can be understood that the series connection of the variable capacitor and the fixed inductor forms a resonator. Changing the capacitance value of the variable capacitor causes a change in the resonant frequency of the resonator, thereby achieving frequency adjustment of the first signal.

[0012] In one possible design, the variable capacitor can be a varactor diode, which reuses existing electronic components to reduce the difficulty of implementation; or, the variable capacitor can also be a new electronic component to improve the flexibility of implementation, without limitation.

[0013] In one possible design, the adjustable resonator unit also includes a fixed capacitor connected in parallel with the variable capacitor, thereby increasing the capacitance range of each equalization sub-circuit.

[0014] In one possible design, the tunable resonator unit includes a fixed capacitor, N microstrip lines, N-1 diodes, and a second digital-to-analog converter (DAC). The fixed capacitor is connected in series with the N microstrip lines. Two microstrip lines arranged sequentially within the N microstrip lines are connected via one of the N-1 diodes, where N is an integer greater than 1. The N-1 diodes are connected to the second DAC, which controls the conduction or deactivation of the N-1 diodes by adjusting their voltage values. The conduction or deactivation of the N-1 diodes is related to the connection length formed by the N microstrip lines. It can be understood that the N microstrip lines can be equivalent to a variable inductor; changing the connection length of the N microstrip lines is equivalent to changing the inductance value of the variable inductor. The resonant frequency of the resonator composed of the fixed capacitor and the N microstrip lines will also change accordingly, thereby achieving frequency adjustment of the first signal. Furthermore, the N microstrip lines, being equivalent to a variable inductor, are suitable for high-frequency scenarios (such as frequencies exceeding 1 gigahertz (GHz), or even down to the terahertz band), enabling amplitude equalization in high-frequency systems.

[0015] In one possible design, the frequency range of the first signal is within the first bandwidth, and P equalized signals are superimposed and output through an analog signal transmission line to obtain an equalized signal; the difference between the maximum and minimum amplitude of the equalized signal within the first bandwidth is less than or equal to a first value, so as to achieve amplitude equalization of the equalized signal obtained after the first signal is equalized by P equalization sub-circuits within the first bandwidth.

[0016] Secondly, a communication method is provided. This method can be applied to, or executed by, a first device. The first device can be a communication device, a functional module (e.g., a processor, a chip, or a chip system), or a logic node, logic module, or software capable of implementing all or part of the functions of the first device. The method includes: acquiring flatness information; performing amplitude equalization on a first signal using P equalization sub-circuits based on the flatness information to obtain P equalized signals; and superimposing the P equalized signals to obtain an equalized signal. Wherein, the flatness information is used to indicate the amplitude variation of a second signal within a first bandwidth; the frequency range of the first signal is within the first bandwidth; the center frequencies of any two equalized signals among the P equalized signals are different, and / or the amplitudes corresponding to the center frequencies are different; P is an integer greater than 1; the difference between the maximum and minimum amplitudes of the equalized signal within the first bandwidth is less than or equal to a first value.

[0017] Based on the method described in the second aspect, the first device can perform amplitude equalization on the first signal within the first bandwidth using P equalization sub-circuits according to the acquired flatness information, obtaining P equalized signals, and then superimposing the P equalized signals to obtain an equalized signal. This flatness information is used to indicate the amplitude change of the second signal within the first bandwidth; in other words, the flatness information can be used to indicate the real-time system flatness. Thus, the first device can dynamically and automatically adjust the system flatness in real time according to the flatness information to achieve automatic amplitude equalization of the signal (such as the first signal mentioned above) within the first bandwidth.

[0018] In one possible design, based on flatness information, P equalization sub-circuits are used to perform amplitude equalization on the first signal to obtain P equalized signals. This includes: determining an equalization curve based on the flatness information, and controlling the P equalization sub-circuits to perform amplitude equalization on the first signal according to their respective hardware parameters, thereby obtaining P equalized signals. The equalization curve is used to determine the hardware parameters of the P equalization sub-circuits, and the hardware parameters of any two equalization sub-circuits are different. That is, the first device can calculate the equalization curve based on the flatness information to control the hardware circuits (i.e., the P equalization sub-circuits) in real time to achieve automatic amplitude equalization of the signal (such as the first signal mentioned above) within a first bandwidth.

[0019] In one possible design, the first bandwidth includes X frequency points. Determining the equalization curve based on flatness information includes: determining the average amplitude of the second signal at the X frequency points based on the flatness information; determining X target amplitudes based on the average amplitude; and determining the equalization curve based on the X target amplitudes. Here, X is an integer greater than 1, the X target amplitudes correspond one-to-one with the X frequency points, and the i-th target amplitude is equal to the difference between the amplitude of the second signal at the i-th frequency point and the average amplitude, where i is an integer greater than 0 and less than or equal to X. That is, the first device can determine an accurate equalization curve based on the X target amplitudes corresponding to each of the X frequency points, thereby improving the accuracy (P = X) of the hardware parameters of the P equalization sub-circuits determined by the first device using the equalization curve.

[0020] In one possible design, before controlling the P equalization sub-circuits to perform amplitude equalization on the first signal according to their respective hardware parameters, the process includes: sending P indication messages to the P equalization sub-circuits according to their respective hardware parameters. Each of the P indication messages corresponds one-to-one with one of the P equalization sub-circuits. The j-th indication message in the P indication messages instructs the j-th equalization sub-circuit to perform amplitude equalization on the first signal using its corresponding hardware parameters. j is an integer greater than 0 and less than or equal to P, thus enabling on-demand indication and flexibility.

[0021] In one possible design, based on flatness information, the first signal is amplitude-equalized using P equalization sub-circuits to obtain P equalized signals. This includes: determining whether the flatness information satisfies a first condition; and if the flatness information satisfies the first condition, performing amplitude equalization on the first signal using the P equalization sub-circuits based on the flatness information to obtain P equalized signals. The first condition includes: the amplitude variation range of the second signal within a first bandwidth is greater than a second value. That is, the first device only needs to trigger the P equalization sub-circuits to perform amplitude equalization on the first signal when the flatness information satisfies the first condition. This avoids triggering the P equalization sub-circuits to perform amplitude equalization on the first signal even when the flatness information does not satisfy the first condition, i.e., the amplitude variation range of the second signal within the first bandwidth is less than or equal to the second value (assuming the amplitude of the second signal within the first bandwidth is equalized), thus reducing resource and hardware overhead.

[0022] In one possible design, obtaining flatness information includes: sending a second signal to a second device and receiving flatness information from the second device. The second signal is used by the second device to perform flatness measurement. In this way, the first device does not need to perform flatness measurement itself, reducing its computational overhead.

[0023] In one possible design scheme, when the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; that is, in the downlink communication scenario, the second signal can be carried in existing cells or channels (such as the above-mentioned SSB, CSI-RS, PSS, SSS, DMRS, PT-RS, or physical downlink channel) to reduce the implementation difficulty, or it can be carried in new cells or channels (such as the above-mentioned DL-FRS) to improve the implementation flexibility, without limitation.

[0024] When the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: uplink flatness reference signal UP-FRS, DMRS, sounding reference signal SRS, phase tracking reference signal PT-RS, or physical uplink channel; that is, in the uplink scenario, the second signal can be carried in existing cells or channels (such as the above-mentioned DMRS, SRS, PT-RS, or physical uplink channel) to reduce the implementation difficulty, or it can be carried in new cells or channels (such as the above-mentioned UP-FRS) to improve the implementation flexibility, without limitation.

[0025] In one possible design, obtaining flatness information includes: receiving a second signal from a second device and measuring the flatness of the second signal to obtain flatness information. That is, the first device can directly measure the flatness of the second signal to obtain flatness information without needing to send feedback to the second device, thereby reducing the resource overhead of the first device.

[0026] In one possible design scheme, when the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; that is, in the downlink communication scenario, the second signal can be carried in existing cells or channels (such as the above-mentioned SSB, CSI-RS, PSS, SSS, DMRS, PT-RS, or physical downlink channel) to reduce the implementation difficulty, or it can be carried in new cells or channels (such as the above-mentioned DL-FRS) to improve the implementation flexibility, without limitation.

[0027] When the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: Uplink Flatness Reference Signal (UP-FRS), DMRS, Sounding Reference Signal (SRS), Phase Tracking Reference Signal (PT-RS), or Physical Uplink Channel. That is, in the uplink communication scenario, the second signal can be carried in existing cells or channels (such as the aforementioned DMRS, SRS, PT-RS, or Physical Uplink Channel) to reduce implementation difficulty, or it can be carried in new cells or channels (such as the aforementioned UP-FRS) to improve implementation flexibility, without limitation.

[0028] Thirdly, a communication method is provided, which can be applied to, or executed by, a second device. The second device can be a communication device, a functional module (e.g., a processor, chip, or chip system), or a logic node, logic module, or software capable of implementing all or part of the functions of the second device. The method includes: receiving a second signal from a first device and measuring the flatness of the second signal to obtain flatness information; and sending the flatness information to the first device. The flatness information is used to indicate the amplitude variation of the second signal within a first bandwidth.

[0029] In one possible design, when the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; when the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: uplink flatness reference signal UP-FRS, DMRS, sounding reference signal SRS, phase tracking reference signal PT-RS, or physical uplink channel.

[0030] Other technical effects of the method described in the third aspect can be referred to the technical effects of the method described in the second aspect, and will not be repeated here.

[0031] Fourthly, a communication method is provided, which can be applied to a second device, such as being executed by the second device. The second device can be a communication device, a functional module (e.g., a processor, chip, or chip system), or a logic node, logic module, or software capable of implementing all or part of the functions of the second device. The method includes: acquiring a second signal and sending the second signal to a first device. The second signal is used by the first device to perform flatness measurement.

[0032] In one possible design, when the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; when the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: uplink flatness reference signal UP-FRS, DMRS, sounding reference signal SRS, phase tracking reference signal PT-RS, or physical uplink channel.

[0033] Other technical effects of the method described in the fourth aspect can be referred to the technical effects of the method described in the second aspect, and will not be repeated here.

[0034] Fifthly, a communication device is provided. The communication device includes: a module for performing the method described in the second aspect, such as a transceiver module and a processing module. The transceiver module is used to indicate the transceiver functions of the communication device, and the processing module is used to perform functions of the communication device other than the transceiver functions.

[0035] For example, the communication device described in the fifth aspect includes an equalization circuit. A processing module is used to acquire flatness information, and based on the flatness information, to perform amplitude equalization on a first signal through P equalization sub-circuits to obtain P equalized signals, and then superimpose the P equalized signals to obtain an equalized signal. The flatness information is used to indicate the amplitude variation of a second signal within a first bandwidth. The equalization circuit includes P equalization sub-circuits, the frequency range of the first signal is within the first bandwidth, the center frequencies of any two of the P equalized signals are different, and / or the amplitudes corresponding to the center frequencies are different, where P is an integer greater than 1; the difference between the maximum and minimum amplitudes of the equalized signal within the first bandwidth is less than or equal to a first value.

[0036] In one possible design, the processing module is further configured to determine the equalization curve based on the flatness information, and control the P equalization sub-circuits to perform amplitude equalization on the first signal respectively, based on the hardware parameters of the P equalization sub-circuits, to obtain P equalized signals. The equalization curve is used to determine the hardware parameters of the P equalization sub-circuits, and the hardware parameters of any two of the P equalization sub-circuits are different.

[0037] In one possible design, the first bandwidth includes X frequency points. The processing module is further configured to determine the average amplitude of the second signal at the X frequency points based on flatness information, and to determine X target amplitudes based on the average amplitude. Here, X is an integer greater than 1, the X target amplitudes correspond one-to-one with the X frequency points, and the i-th target amplitude among the X target amplitudes is equal to the difference between the amplitude of the second signal at the i-th frequency point and the average amplitude, where i is an integer greater than 0 and less than or equal to X.

[0038] In one possible design, before controlling the P equalization sub-circuits to perform amplitude equalization on the first signal according to their respective hardware parameters, the transceiver module sends P indication messages to the P equalization sub-circuits according to their respective hardware parameters. Each of the P indication messages corresponds one-to-one with one of the P equalization sub-circuits. The j-th indication message in the P indication messages instructs the j-th equalization sub-circuit to use its corresponding hardware parameters to perform amplitude equalization on the first signal, where j is an integer greater than 0 and less than or equal to P.

[0039] In one possible design, the processing module is further configured to determine whether the flatness information satisfies a first condition, and if the flatness information satisfies the first condition, to perform amplitude equalization on the first signal through P equalization sub-circuits based on the flatness information, thereby obtaining P equalized signals. The first condition includes: the amplitude variation range of the second signal within a first bandwidth is greater than a second value.

[0040] In one possible design, the transceiver module is further configured to send a second signal to the second device and receive flatness information from the second device. The second signal is used by the second device to perform flatness measurements.

[0041] In one possible design, when the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; when the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: uplink flatness reference signal UP-FRS, DMRS, sounding reference signal SRS, phase tracking reference signal PT-RS, or physical uplink channel.

[0042] In one possible design, the transceiver module is further configured to receive a second signal from a second device. The processing module is further configured to perform flatness measurement on the second signal to obtain flatness information.

[0043] In one possible design, when the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; when the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: uplink flatness reference signal UP-FRS, DMRS, sounding reference signal SRS, phase tracking reference signal PT-RS, or physical uplink channel.

[0044] Optionally, the transceiver module may include a sending module and a receiving module. The sending module implements the sending function of the communication device described in the fifth aspect, and the receiving module implements the receiving function of the communication device described in the fifth aspect.

[0045] Optionally, the communication device described in the fifth aspect may further include a storage module storing programs or instructions. When the processing module executes the program or instructions, the communication device can perform the method described in the second aspect.

[0046] Optionally, the communication device described in the fifth aspect may be the first device, or a chip (system) or other component or assembly that can be disposed in the first device, or a device that includes the first device. This application does not limit this.

[0047] Furthermore, the technical effects of the communication device described in the fifth aspect can be referred to the technical effects of the method described in the second aspect, and will not be repeated here.

[0048] A sixth aspect provides a communication device. The communication device includes: a module for performing the method described in the third aspect, such as a transceiver module and a processing module. The transceiver module is used to indicate the transceiver functions of the communication device, and the processing module is used to perform functions of the communication device other than the transceiver functions.

[0049] For example, a transceiver module is used to receive a second signal from a first device. A processing module is used to measure the flatness of the second signal to obtain flatness information; the transceiver module is also used to send the flatness information to the first device. The flatness information is used to indicate the amplitude variation of the second signal within a first bandwidth.

[0050] In one possible design, when the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; when the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: uplink flatness reference signal UP-FRS, DMRS, sounding reference signal SRS, phase tracking reference signal PT-RS, or physical uplink channel.

[0051] Optionally, the transceiver module may include a sending module and a receiving module. The sending module implements the sending function of the communication device described in the sixth aspect, and the receiving module implements the receiving function of the communication device described in the sixth aspect.

[0052] Optionally, the communication device described in the sixth aspect may further include a storage module storing programs or instructions. When the processing module executes the program or instructions, the communication device can perform the method described in the sixth aspect.

[0053] Optionally, the communication device described in the sixth aspect may be a second device, or a chip (system) or other component or assembly that can be disposed in the second device, or a device that includes the second communication device; this application does not limit this.

[0054] Furthermore, the technical effects of the communication device described in the sixth aspect can be referred to the technical effects of the method described in the third aspect, and will not be repeated here.

[0055] A seventh aspect provides a communication device. The communication device includes: modules for performing the method described in the fourth aspect, such as a transceiver module and a processing module. The transceiver module is used to indicate the transceiver functions of the communication device, and the processing module is used to perform functions of the communication device other than the transceiver functions.

[0056] For example, a processing module is used to acquire the second signal. A transceiver module is used to send the second signal to the first device. The second signal is used by the first device to perform flatness measurement.

[0057] In one possible design, when the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; when the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: uplink flatness reference signal UP-FRS, DMRS, sounding reference signal SRS, phase tracking reference signal PT-RS, or physical uplink channel.

[0058] Optionally, the transceiver module may include a transmitting module and a receiving module. The transmitting module implements the transmitting function of the communication device described in the seventh aspect, and the receiving module implements the receiving function of the communication device described in the seventh aspect.

[0059] Optionally, the communication device described in the seventh aspect may further include a storage module storing programs or instructions. When the processing module executes the program or instructions, the communication device can perform the method described in the fourth aspect.

[0060] Optionally, the communication device described in the seventh aspect may be a second device, or a chip (system) or other component or assembly that can be disposed in the second device, or a device that includes the second device; this application does not limit this.

[0061] Furthermore, the technical effects of the communication device described in the seventh aspect can be referred to the technical effects of the method described in the fourth aspect, and will not be repeated here.

[0062] Eighthly, a communication device is provided. The communication device includes a processor configured to execute the method described in any one of the possible implementations of the second to fourth aspects.

[0063] In one possible design, the communication device described in the eighth aspect may further include a transceiver. This transceiver may be a transceiver circuit or an interface circuit. The transceiver can be used for communication between the communication device described in the eighth aspect and other communication devices.

[0064] In one possible design, the communication device described in the eighth aspect may further include a memory. This memory may be integrated with the processor or disposed separately. The memory may be used to store computer programs and / or data relating to the methods described in any of the second to fourth aspects.

[0065] In the embodiments of this application, the communication device described in the eighth aspect may be the first device described in the second aspect; or, the communication device described in the eighth aspect may be the second device described in the third or fourth aspect.

[0066] Furthermore, the technical effects of the communication device described in the eighth aspect can be referred to the technical effects of the method described in any of the implementations of the second to fourth aspects, and will not be repeated here.

[0067] A ninth aspect provides a communication device. The communication device includes a processor coupled to a memory, the processor executing a computer program stored in the memory such that the communication device performs the method described in any of the possible implementations of the second to fourth aspects.

[0068] In one possible design, the communication device described in the ninth aspect may further include a transceiver. This transceiver may be a transceiver circuit or an interface circuit. The transceiver can be used for communication between the communication device described in the ninth aspect and other communication devices.

[0069] In the embodiments of this application, the communication device described in the ninth aspect may be the first device described in the second aspect; or, the communication device described in the ninth aspect may be the second device described in the third or fourth aspect.

[0070] Furthermore, the technical effects of the communication device described in the ninth aspect can be referred to the technical effects of the method described in any of the implementations of the second to fourth aspects, and will not be repeated here.

[0071] A tenth aspect provides a communication device including a processor and a memory; the memory is used to store a computer program, which, when executed by the processor, causes the communication device to perform the method described in any one of the second to fourth aspects.

[0072] In one possible design, the communication device described in the tenth aspect may further include a transceiver. The transceiver may be a transceiver circuit or an interface circuit. The transceiver can be used for communication between the communication device described in the tenth aspect and other communication devices.

[0073] In the embodiments of this application, the communication device described in the tenth aspect may be the first device described in the second aspect; or, the communication device described in the tenth aspect may be the second device described in the third or fourth aspect.

[0074] Furthermore, the technical effects of the communication device described in the tenth aspect can be referred to the technical effects of the method described in any of the implementations of the second to fourth aspects, and will not be repeated here.

[0075] Eleventhly, a communication device is provided, comprising: a processor; the processor being coupled to a memory and, after reading a computer program from the memory, executing the method as described in any one of the second to fourth aspects according to the computer program.

[0076] In one possible design, the communication device described in the eleventh aspect may further include a transceiver. This transceiver may be a transceiver circuit or an interface circuit. The transceiver can be used for communication between the communication device described in the eleventh aspect and other communication devices.

[0077] In the embodiments of this application, the communication device described in the eleventh aspect can be the first device described in the second aspect; or, the communication device described in the eleventh aspect can be the second device described in the third or fourth aspect.

[0078] Furthermore, the technical effects of the communication device described in the eleventh aspect can be referred to the technical effects of the method described in any of the implementations of the second to fourth aspects, and will not be repeated here.

[0079] In a twelfth aspect, a communication system is provided. The communication system includes the first device described in the second aspect and the second device described in the third aspect.

[0080] In a thirteenth aspect, a communication system is provided. The communication system includes the first device described in the second aspect and the second device described in the fourth aspect.

[0081] In a fourteenth aspect, a communication chip is provided, wherein instructions are stored that, when the chip is operated on a communication device, cause the method described in any one of the second to fourth aspects to be implemented.

[0082] In a fifteenth aspect, a computer-readable storage medium is provided, comprising: a computer program or instructions; when the computer program or instructions are executed on a computer, causing the computer to perform the method described in any one of the possible implementations of the second to fourth aspects.

[0083] In a sixteenth aspect, a computer program product is provided, comprising a computer program or instructions that, when executed on a computer, cause the computer to perform the method described in any one of the possible implementations of the second to fourth aspects. Attached Figure Description

[0084] Figure 1 A schematic diagram illustrating the in-band unevenness introduced by hardware devices;

[0085] Figure 2 A schematic diagram illustrating the in-band unevenness caused by beam switching;

[0086] Figure 3 A schematic diagram illustrating in-band unevenness in multipath scenarios;

[0087] Figure 4 This is a schematic diagram illustrating in-band unevenness in a communication system.

[0088] Figure 5 A schematic diagram illustrating how a hardware-preset equalizer addresses in-band unevenness.

[0089] Figure 6 A schematic diagram of a fixed equalization circuit composed of RLC circuits and its response;

[0090] Figure 7 A schematic diagram of pre-equalization for the baseband algorithm;

[0091] Figure 8 A diagram illustrating why a pre-built hardware equalizer cannot be applied to all different scenarios;

[0092] Figure 9 A schematic diagram of the architecture of a communication system provided in this application embodiment. Figure 1 ;

[0093] Figure 10 A schematic diagram of the architecture of a communication system provided in this application embodiment. Figure 2 ;

[0094] Figure 11 A schematic diagram illustrating the connection between an equalization circuit and an existing unit, provided in an embodiment of this application;

[0095] Figure 12 A schematic diagram of the architecture of a communication system provided in this application embodiment. Figure 3 ;

[0096] Figure 13This is a schematic diagram of the structure of an equalization circuit provided in an embodiment of this application;

[0097] Figure 14 A schematic diagram of an equalization curve synthesized by an equalization circuit, provided in an embodiment of this application;

[0098] Figure 15 This application provides a schematic diagram illustrating different resistance values ​​of an adjustable resistor unit corresponding to different amplitudes.

[0099] Figure 16 A schematic diagram of the structure of an adjustable resistor unit provided in this application embodiment. Figure 1 ;

[0100] Figure 17 A schematic diagram of the structure of an adjustable resistor unit provided in this application embodiment. Figure 2 ;

[0101] Figure 18 A schematic diagram of the structure of an adjustable resonant unit provided in this application embodiment. Figure 1 ;

[0102] Figure 19 This is a schematic diagram illustrating how the capacitance value of a varactor diode changes with the applied reverse voltage, as provided in an embodiment of this application.

[0103] Figure 20 A schematic diagram of the structure of an adjustable resonant unit provided in this application embodiment. Figure 2 ;

[0104] Figure 21 A flowchart illustrating a communication method provided in an embodiment of this application. Figure 1 ;

[0105] Figure 22 A flowchart illustrating a communication method provided in an embodiment of this application. Figure 2 ;

[0106] Figure 23 A schematic diagram of the structure of a communication device provided in this application embodiment. Figure 1 ;

[0107] Figure 24 A schematic diagram of the structure of a communication device provided in this application embodiment. Figure 2 . Detailed Implementation

[0108] For ease of understanding, the technical terms involved in the embodiments of this application will be introduced below.

[0109] 1. Reference signal (RS)

[0110] A reference signal, also known as a pilot signal, is a known signal provided by the transmitter to the receiver for channel estimation or channel sounding. Reference signals can be divided into uplink reference signals and downlink reference signals. Uplink reference signals can be signals sent from a terminal device to a network device; that is, the transmitter is the terminal device and the receiver is the network device. Uplink reference signals can be used for uplink channel estimation (such as for coherent demodulation and detection in network devices, or for calculating precoding, or for determining uplink scheduling), or for uplink channel quality measurement. Downlink reference signals can be signals sent from a network device to a terminal device; that is, the transmitter is the network device and the receiver is the terminal device. Downlink reference signals can be used for downlink channel estimation (such as for coherent detection and demodulation in terminal devices), downlink channel quality measurement, or cell search.

[0111] Uplink reference signals include sounding reference signal (SRS), demodulation reference signal (DMRS), tracking reference signal (TRS), and phase tracking reference signal (PT-RS). Downlink reference signals include channel status information reference signal (CSI-RS), DMRS, cell reference signal (CRS), synchronization signal block (SSB), primary synchronization signal (PSS), secondary synchronization signal (SSS), and PT-RS.

[0112] 2. Flatness within the band

[0113] With the rapid development of information technology, modern communication systems face unprecedented challenges and opportunities. In recent years, the explosive growth in data transmission demand has driven the need for wider system bandwidth. With the widespread adoption of the internet and mobile devices, global data traffic is growing exponentially. The commercialization of 5G mobile communication technology also marks the beginning of a new era in communication technology. 5G not only provides higher transmission rates but also supports large-scale device connections and low-latency communication, all of which rely on increasingly wider system bandwidth. Future mobile communication technologies will further enhance bandwidth and achieve even higher communication speeds.

[0114] As communication bandwidth and frequency range increase, the amplitude uniformity of in-band signals deteriorates. Wideband communication systems operate over a wide frequency range, making it difficult to ensure signal transmission consistency, thus increasing signal amplitude fluctuations and worsening frequency domain gain flatness. Gain flatness refers to the range of amplitude variation of a wideband signal within a certain frequency range. Generally, communication systems aim for the amplitude of the wideband signal to remain constant with frequency changes, ensuring a uniform distribution of signal energy across the entire operating bandwidth. This guarantees signal transmission quality, reduces interference, and improves signal reception efficiency. Gain flatness can also be called in-band flatness or any other possible name, without limitation. In the embodiments of this application, "amplitude," "amplitude value," and "gain" can be used interchangeably without limitation.

[0115] Poor in-band flatness can cause the signal amplitude on a certain subcarrier to be too small or too large, resulting in a high bit error rate during baseband processing and thus affecting the overall communication rate. Ideally, the system's transmit power is evenly distributed across all subcarriers within the entire band. However, uneven in-band gain can cause an imbalance in the actual power among subcarriers, resulting in insufficient power for some subcarriers, leading to a decrease in communication rate, while excessive power for others results in insufficient power for some subcarriers.

[0116] The causes of in-band unevenness in communication systems can include: inherently uneven frequency or amplitude response of the hardware system, gain fluctuations caused by beam switching during user movement, or superposition of multipath signals in multipath scenarios, which will be introduced below.

[0117] (1) The hardware system has an inherently uneven frequency or amplitude response;

[0118] As system bandwidth increases, the response of many hardware devices becomes uneven in broadband systems. The transmission loss of radio frequency signals in transmission lines also increases with higher frequencies, which is one reason for the uneven gain of many devices. With the increase in system bandwidth, the frequency spacing between low-frequency and high-frequency bands within the operating frequency band also becomes larger, leading to increasingly poorer device flatness. This is especially true in cascaded systems with multiple devices, where the unevenness problem increasingly needs to be addressed.

[0119] For example, such as Figure 1 As shown, the transmitting end can amplify the signal input amplifier and transmit it to the receiving end via an antenna; the receiving end can receive the signal via an antenna and amplify the received signal via an amplifier for use in subsequent steps. It can be understood that, as... Figure 1The gain curve shown has frequency (f) on the horizontal axis and amplitude (or magnitude) on the vertical axis. Because the response of the antenna and amplifier in a broadband system is not flat, the signal transmitted by the transmitter and the signal received by the receiver both have uneven gain (i.e., amplitude) in the frequency domain.

[0120] (2) Gain fluctuations caused by beam switching during user movement;

[0121] When a user equipment (UE) moves, the beam it uses to communicate with network devices changes. Different beams have different gains at the same frequency, resulting in spectral fluctuations in the UE. For example, ... Figure 2 As shown in (a), the original beam used for communication between the user equipment and the network equipment is beam #1. Due to the broadband signal, the gain of the same beam fluctuates at different frequencies, resulting in inherent fluctuations in the in-band flatness of the user equipment. After the user equipment moves, the beam used for communication between the user equipment and the network equipment changes, switching from beam #1 to beam #2. Since beam #2 may be different from beam #1, the in-band flatness of the user equipment will change again. Figure 2 As shown in (b), the horizontal axis represents frequency and the vertical axis represents amplitude. The gain of beam #1 and beam #2 differs at the same frequency point, which causes some fluctuation in the in-band flatness of the user equipment.

[0122] (3) Superposition of multipath signals in multipath scenarios;

[0123] Multipath propagation refers to a signal originating from the same transmitter but, due to environmental factors such as reflections from objects, reaching the receiver via multiple paths. The receiver then simultaneously receives signals transmitted through these multiple paths. For example, ... Figure 3 As shown in (a), network devices can transmit signals via direct radial path to the terminal device. Alternatively, network devices can transmit signals via reflection from objects, such as buildings in the environment, i.e., via reflective radial path to the terminal device. In multipath scenarios, the same signal travels along paths of different distances, such as the direct path and the reflected path, to reach the receiver. Due to the Doppler effect, the phase and amplitude of the broadband signal at different frequencies will change. The superposition of these changes will cause fluctuations in the in-band signal amplitude, resulting in in-band unevenness.

[0124] like Figure 3As shown in (b), the horizontal axis represents frequency, and the vertical axis represents amplitude. The amplitude of the signal reaching the terminal device from the network device via the direct path changes regularly with frequency; that is, the curve of amplitude changing with frequency is a sloping line with a slope of k (the value of k is not limited). The amplitude of the signal reaching the terminal device from the network device via the reflected path changes irregularly with frequency; that is, the curve of amplitude changing with frequency is a curve with a slope of k. The superposition of the signals reaching the terminal device via the direct path and the signals reaching the terminal device via the reflected path will cause fluctuations in the in-band signal amplitude, forming in-band unevenness.

[0125] Based on the above introduction, such as Figure 4 As shown, the horizontal axis represents frequency, and the vertical axis represents amplitude. Assuming the system bandwidth ranges from component carrier (CC)#1 to CC#5, theoretically, the optimal communication system requires uniform amplitude values ​​across all sub-bands, with overall power evenly distributed across the frequency bands. However, the above factors can cause in-band unevenness, including two types: 1) differences in amplitude values ​​between CCs (between sub-bands), such as a significant difference between CC1 and CC2; 2) differences within a single CC (within a sub-band), such as amplitude differences within CC4. Inter-sub-band unevenness leads to power waste; for example, CC1 may have excessive power while CC2 has insufficient power. In-band unevenness is generally difficult to resolve, and demodulation is typically based on the minimum amplitude value during communication, reducing system performance.

[0126] 3. Solutions for unevenness within the band

[0127] The most common solutions to in-band unevenness (such as between CC1 and CC2 mentioned above) in current communication systems can include hardware compensation equalization and algorithm compensation equalization, which will be introduced below.

[0128] (1) Hardware compensation equalization;

[0129] Hardware-compensated equalization improves in-band flatness by pre-installing a gain equalization circuit in the hardware. The working principle is as follows: the transmitting or receiving end (requiring a pre-installed gain equalization circuit) pre-evaluates the in-band flatness of the entire communication system, obtaining a gain flatness curve for the entire band. Then, based on this curve, the transmitting or receiving end designs an equalizer circuit with an opposite trend and inserts it into the system, thereby improving the overall in-band flatness. Generally, the higher the frequency of the communication system, the lower the gain; therefore, a circuit structure is typically designed to reduce the gain at low frequencies, resulting in a flatter overall in-band gain.

[0130] For example, such as Figure 5As shown, the horizontal axis represents frequency, and the vertical axis represents amplitude. The transmitting or receiving end can obtain the amplitude and frequency information of the system through actual measurement or predictive simulation, i.e., the system flatness response, or the system flatness curve. Based on the system flatness curve, the transmitting or receiving end can fit and design a curve with an inverse slope. This inverse slope curve is the amplitude-frequency response curve desired by the equalizer, i.e., the equalizer response. Based on the inverse slope curve, the transmitting or receiving end uses resistive capacitors or microstrip lines to design a circuit that roughly meets the requirements, generally called an equalizer. The transmitting or receiving end inserts this equalizer into the system link, so that the system flatness response and the equalizer response are balanced, thereby obtaining a relatively flat system flatness, i.e., a relatively flat final response.

[0131] Fixed equalizer circuits can be constructed from resistor-capacitor networks, microstrip lines, etc. For example, such as... Figure 6 As shown in (a), the equalizer circuit may include a fixed resistor R, a fixed inductor L, and a fixed capacitor C. The response of this equalizer circuit is as follows: Figure 6 As shown in (b), the horizontal axis represents frequency and the vertical axis represents amplitude. This equalizer circuit can create a dip in transmission loss at a specific frequency point, such as f1. For example, the equalizer circuit can be implemented by a microstrip circuit, which can achieve equalization of high-frequency systems.

[0132] (2) Algorithm-based compensation equilibrium;

[0133] In communication systems, to cope with changing scenarios, when the transmitting or receiving end detects significant in-band fluctuations, it can weight the baseband signal to improve flatness within a certain range. This approach requires the transmitting or receiving end to have prior knowledge of the in-band flatness information, or to obtain this information through calibration measurements before system use. When the baseband signal passes through a digital-to-analog converter (DAC), the transmitting or receiving end sets weighting values ​​across all bands to output a baseband signal with flatness opposite to the system's flatness. In this way, the uneven baseband signal, after passing through an uneven hardware system, can output a flat signal.

[0134] For example, such as Figure 7As shown, the horizontal axis represents frequency (f), and the vertical axis represents amplitude. System measurements revealed that the amplitude values ​​of CC1, CC2, and CC3 within the system band are all different: CC1 has an amplitude of 1.5, CC2 has an amplitude of 1, and CC3 has an amplitude of 1.2. Taking CC2, which has the smallest amplitude, as the reference, to achieve better flatness, the baseband signal amplitude can be weighted during signal generation. Specifically, the amplitude value of CC1 output is multiplied by a coefficient of 0.66, and the amplitude value of CC3 output is multiplied by a coefficient of 0.83. At this point, the amplitude values ​​of CC1 and CC3 are close to those of CC2, thus achieving amplitude equalization.

[0135] However, based on the two methods mentioned above, it is impossible to adjust the flatness of the system in real time and automatically according to dynamic scene changes.

[0136] Specifically, the aforementioned hardware-based equalization method uses a fixed and unadjustable equalization curve, generally only applicable to communication systems in fixed states, such as microwave point-to-point communication and satellite communication. This typically requires a fixed scenario and a fixed state. When the scenario changes, the in-band amplitude-frequency response curve may change, making the preset equalization circuit ineffective.

[0137] For example, such as Figure 8 As shown, in scenario A, the signal sent from the network device to the terminal device arrives at the terminal device through the direct path. In this case, a pre-set gain equalization circuit in the hardware circuit can improve the in-band flatness. In scenario B, the signal sent from the network device to the terminal device arrives at the terminal device through the reflection of objects, such as buildings in the environment. In this case, the pre-set equalization circuit cannot play a role and may even worsen the in-band flatness.

[0138] The aforementioned algorithmic compensation equalization method also requires prior knowledge of the system's in-band flatness to pre-calculate the amplitude weighting value of the baseband signal. The amplitude weighting value forcibly reduces the power of the originally high-power sub-bands to bring the power of all sub-bands close to that of the lowest-power sub-band. This fails to maximize the system's hardware performance, sacrifices the effective number of bits of the analog-to-digital converter (ADC), and wastes resources. Furthermore, algorithmic compensation equalization methods typically adjust on a sub-band basis (as in CC1 and CC2 above), failing to flexibly adjust amplitude values ​​according to frequency information and thus unable to achieve finer-grained adjustments, such as improving the flatness within a sub-band (as in CC3 above).

[0139] Therefore, how to achieve real-time and automatic adjustment of the system's flatness based on dynamic scene changes is an urgent problem to be solved.

[0140] In summary, to address the aforementioned technical problems, this application proposes the following technical solutions to achieve real-time and automatic adjustment of the system's flatness based on dynamic scene changes.

[0141] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0142] The technical solutions of this application embodiment can be applied to various communication systems, such as Bluetooth systems, wireless fidelity (WiFi) systems, long-range radio (LoRa), vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, machine-to-machine (M2M) communication systems, machine-type communication (MTC), Internet of Things (IoT) communication systems, 4th generation (4G) communication systems such as long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, worldwide interoperability for microwave access (WiMAX) communication systems, satellite communication systems, 5G communication systems such as new radio (NR) systems, and future communication systems, etc.

[0143] In a communication system, a device can send signals to or receive signals from another device. These signals can include information, signaling, or data. The term "device" can also be replaced with entities, network entities, communication equipment, communication modules, nodes, communication nodes, etc.

[0144] This application will present various aspects, embodiments, or features relating to systems that may include multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches are also possible.

[0145] In addition, to better understand the embodiments of this application, the following points are made before introducing the embodiments of this application.

[0146] In the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design that is described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0147] In the embodiments of this application, the terms "information," "signal," "message," "channel," and "signaling" may sometimes be used interchangeably. It should be noted that, without emphasizing their distinction, their intended meanings are consistent. Similarly, "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing their distinction, their intended meanings are consistent. Furthermore, the " / " mentioned in this application can be used to indicate an "or" relationship. It is understood that in this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing an instruction information used to indicate A, it can be understood that the instruction information carries A, directly indicates A, or indirectly indicates A.

[0148] In this embodiment, the information indicated by the instruction information is called the information to be instructed. In specific implementations, there are many ways to indicate the information to be instructed, such as, but not limited to, directly indicating the information to be instructed, such as the information to be instructed itself or its index; or indirectly indicating the information to be instructed by indicating other information, wherein there is an association between the other information and the information to be instructed. Alternatively, only a part of the information to be instructed may be indicated, while the other parts are known or pre-agreed upon. For example, the instruction of specific information can be achieved by using a pre-agreed (e.g., protocol-defined) arrangement of various pieces of information, thereby reducing instruction overhead to some extent.

[0149] Furthermore, the specific indication method can also be any existing indication method, such as, but not limited to, the above-mentioned indication methods and their various combinations. Specific details of various indication methods can be found in existing technologies, and will not be repeated here. As described above, for example, when multiple pieces of information of the same type need to be indicated, the indication methods for different pieces of information may differ. In the specific implementation process, the required indication method can be selected according to specific needs. This application embodiment does not limit the selected indication method; therefore, the indication methods involved in this application embodiment should be understood to cover various methods that enable the party to be indicated to obtain the information to be indicated.

[0150] The information to be instructed can be sent as a whole or divided into multiple sub-information messages, and the sending period and / or timing of these sub-information messages can be the same or different. This application does not limit the specific sending method. The sending period and / or timing of these sub-information messages can be predefined, for example, according to a protocol, or configured by the transmitting device by sending configuration information to the receiving device.

[0151] The terms "first," "second," and various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. For example, they distinguish different instruction information. Similarly, "first network region" and "second network region" are simply used to distinguish different regions and do not limit their order. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., are not necessarily different.

[0152] "Predefined" or "pre-configured" can be achieved by pre-saving corresponding codes, tables, or other means that can be used to indicate relevant information in the device (e.g., including terminal devices and network devices). This application does not limit the specific implementation method. "Saving" can mean saving in one or more memories. These memories can be separate installations or integrated into the encoder or decoder, processor, or communication device. Alternatively, some memories can be separate installations, while others are integrated into the decoder, processor, or communication device. The type of memory can be any form of storage medium, and this application does not limit this.

[0153] The “protocol” mentioned in the embodiments of this application may refer to standard protocols in the field of communication, such as LTE protocol, NR protocol and related protocols applied to future communication systems. The embodiments of this application do not limit this.

[0154] In the embodiments of this application, descriptions such as "when," "under the circumstances," "if," and "if" all refer to the fact that the device (e.g., a terminal device or a network device) will make corresponding processing under certain objective circumstances. They are not time limits, nor do they require the device (e.g., a terminal device or a network device) to have a judgment action when implementing it, nor do they imply any other limitations.

[0155] In the embodiments of this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to XX" can be understood as the destination of the information being XX, which may include direct transmission via the air interface or indirect transmission by other units or modules via the air interface. "Receive information from YY" can be understood as the source of the information being YY, which may include direct reception from YY via the air interface or indirect reception from YY by other units or modules via the air interface. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface. In other words, sending and receiving can occur between devices, such as between network devices and terminal devices, or within a device, such as between components, modules, chips, software modules, or hardware modules within the device via a bus, wiring, or interface.

[0156] The network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0157] To facilitate understanding of the embodiments of this application, let's first take... Figure 9 The communication system illustrated herein is used as an example to illustrate a communication system applicable to embodiments of this application. For example, Figure 9 A schematic diagram of the architecture of a communication system provided in this application embodiment. Figure 1 .

[0158] like Figure 9 As shown, the communication system mainly includes: a first device and a second device.

[0159] The first communication device and the second communication device can be either network devices or terminal devices. When the first communication device is a network device, the second communication device can be a terminal device; when the first communication device is a terminal device, the second communication device can be a network device.

[0160] The network device can be a device with wireless transceiver capabilities, or it can be a chip or chip system located in the device, situated in the access network (AN) of the communication system, to provide access services to the terminal. For example, the network device can be a radio access network (RAN) device, specifically an access network device in a future communication system, or in a future mobile communication system. The network device may also have other naming conventions, all of which are covered within the protection scope of the embodiments of this application, and the embodiments of this application do not impose any limitations on them. Alternatively, network equipment can also include 5G, such as a gNB in ​​a New Radio (NR) system, or one or a group of antenna panels (including multiple antenna panels) of a 5G base station. It can also be network nodes constituting a gNB, transmission and reception point (TRP), transmission point (TP), or transmission measurement function (TMF), such as a central unit (CU), distributed unit (DU), CU-control plane (CP), CU-user plane (UP), or radio unit (RU), RSU with base station functionality, or wired access gateway, or 5G core network elements, etc. Alternatively, network equipment can also include: access points (APs) in WiFi systems, wireless relay nodes, wireless backhaul nodes, various forms of macro base stations, micro base stations (also called small cells), relay stations, access points, wearable devices, vehicle-mounted equipment, etc.

[0161] CU and DU can be configured separately or included in the same network element, such as a baseband unit (BBU). RU can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs). It is understood that network equipment can be CU nodes, DU nodes, or a combination of both. Furthermore, CUs can be classified as network equipment in the access network (RAN) or the core network (CN); there are no restrictions on this classification.

[0162] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0163] In this embodiment, the form of the network device is not limited. The device used to implement the function of the network device can be the network device itself, or it can be a device that supports the network device in implementing the function, such as a chip system. The device can be installed in the network device or used in conjunction with the network device.

[0164] The terminal equipment can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. The terminal equipment can be a terminal device with transceiver capabilities, or it can be a chip or chip system installed in the terminal device. This terminal equipment can also be referred to as user equipment (UE), access terminal equipment, subscriber unit, user station, mobile station (MS), mobile station, remote station, remote terminal equipment, mobile device, user terminal equipment, terminal equipment, wireless communication equipment, user agent, or user device. The terminal devices in the embodiments of this application may be mobile phones, cellular phones, smartphones, tablets (such as tablets), wireless data cards, personal digital assistants (PDAs), wireless modems, handsets, laptop computers, machine-type communication (MTC) terminal devices, computers with wireless transceiver capabilities, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, smart home devices (e.g., refrigerators, televisions, air conditioners, electricity meters, etc.), intelligent robots, robotic arms, workshop equipment, wireless terminal devices in autonomous driving, wireless terminal devices in industrial control, wireless terminal devices in self-driving, wireless terminal devices in telemedicine, wireless terminal devices in smart grids, wireless terminal devices in transportation safety, wireless terminal devices in smart cities, and smart homes. The terminal equipment in this application can be a wireless terminal device (e.g., a vehicle-mounted terminal device), a roadside unit (RSU) with terminal device functionality, or flying equipment (e.g., intelligent robots, hot air balloons, drones, airplanes). The terminal equipment in this application can also be a vehicle-mounted module, vehicle-mounted component, vehicle-mounted chip, or vehicle-mounted unit integrated into a vehicle as one or more components or units, a transportation vehicle with wireless communication functionality, or a communication module. The terminal equipment can also be other devices with terminal device functionality; for example, it can be a device that functions as a terminal device in D2D communication.

[0165] The embodiments of this application do not limit the form of the terminal device. The device used to implement the functions of the terminal device can be the terminal device itself; it can also be a device that supports the terminal device in implementing the functions, such as a chip system. This device can be installed in the terminal device or used in conjunction with the terminal device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices. The terminal device typically has a communication module, circuit, or chip that performs the corresponding communication functions. The terminal device can also be configured with program instructions for performing the corresponding communication functions.

[0166] In this communication system, the first device can perform amplitude equalization on the first signal within the first bandwidth using P equalization sub-circuits based on the acquired flatness information, obtaining P equalized signals. These P equalized signals are then superimposed to obtain a balanced signal. This flatness information indicates the amplitude change of the second signal within the first bandwidth; in other words, it indicates the real-time system flatness. Thus, the first device can dynamically and automatically adjust the system flatness in real time based on the flatness information to achieve automatic amplitude equalization of the signal (such as the first signal mentioned above) within the first bandwidth.

[0167] It is understood that the embodiments of this application can be applied to any wireless communication system or wired communication system, and are not limited to narrowband communication or broadband communication, nor are they limited to fixed communication scenarios or mobile communication scenarios, that is, they are not limited to whether the terminal device is mobile or fixed.

[0168] For example, based on wireless communication scenarios, Figure 10 A schematic diagram of the architecture of a communication system provided in this application embodiment. Figure 2 ,like Figure 10 As shown, taking a network device as the transmitter and a terminal device as the receiver (i.e., a downlink communication scenario) as an example, the network device and the terminal device communicate wirelessly via an air interface. On the network device side, the network device, i.e., the transmitter, may include a baseband unit, an intermediate frequency unit (or an intermediate frequency system), a radio frequency unit (or a radio frequency front-end), and an antenna unit; the terminal device, i.e., the receiver, may include an antenna unit, a radio frequency unit (or a radio frequency front-end), an intermediate frequency unit (or an intermediate frequency system), and a baseband unit.

[0169] At the transmitting end, the baseband unit encodes the information to be transmitted and sends the output analog signal to the intermediate frequency unit via a DAC. The intermediate frequency unit performs preliminary gain control and power amplification on the analog signal output from the baseband unit and sends the processed intermediate frequency signal to the radio frequency unit. The radio frequency unit converts the processed intermediate frequency signal to the radio frequency band, amplifies the power, and sends the amplified radio frequency signal to the antenna unit. The antenna unit then sends the radio frequency signal to the terminal device.

[0170] At the receiving end, the antenna unit receives the radio frequency (RF) signal transmitted over the air interface and sends the RF signal to the RF unit. The RF unit can perform preliminary gain control and power amplification on the RF signal and send the processed RF signal to the intermediate frequency (IF) unit. The IF unit can convert the processed RF signal to the IF band, amplify its power, and send the amplified IF signal to the baseband unit. The baseband unit digitizes the IF signal using an ADC and demodulates it to recover the information.

[0171] Understandable, based on Figure 10 In the communication system shown in this application embodiment, corresponding to the communication method (e.g., corresponding to the software adaptive equalization algorithm), the transmitting end or the receiving end contains a baseband unit. That is, the communication method of this application embodiment can be carried in the baseband algorithm of the network device and / or the terminal device (deployed in the existing baseband unit, for example, by adding a new module, such as an adaptive equalization algorithm module). Corresponding to the equalization circuit, the transmitting end or the receiving end contains an intermediate frequency unit or a radio frequency unit. That is, the equalization circuit of this application embodiment can be located in the intermediate frequency unit or the radio frequency unit of the network device and / or the terminal device. This application embodiment does not limit this.

[0172] For example, taking the equalization circuit of this application embodiment as being located or deployed in the intermediate frequency unit, such as... Figure 11 As shown, the equalization circuit can be connected in series in the existing intermediate frequency link. The power supply module of the existing system can supply power to the equalization circuit. The equalization circuit can be connected to the power supply module through the power supply interface. The equalization circuit can communicate with processors such as microcontrollers, field programmable gate arrays (FPGAs), central processing units (CPUs), and digital signal processors (DSPs) through the control interface, such as through electrical connections.

[0173] An analog intermediate frequency (IF) signal (denoted as analog IF signal #1) is input to the equalization circuit through an analog signal input interface. The equalization circuit performs amplitude equalization on the analog IF signal #1, such as adjusting the amplitude of analog IF signal #1 at different frequency points to obtain analog IF signal #2. The equalization circuit outputs analog IF signal #2 through an analog signal output interface. For example, when the equalization circuit is deployed at the transmitting end, it can send analog IF signal #2 to the RF unit of the transmitting end through the analog signal output interface; when the equalization circuit is deployed at the receiving end, it sends analog IF signal #2 to the baseband unit of the receiving end through the analog signal output interface, without limitation. The amplitude adjustment of the signal can be controlled by a processor, such as a microcontroller, FPGA, CPU, or DSP, through communication. For example, the processor can issue instructions through a communication protocol or directly control the level, without limitation. It can be understood that the above... Figure 11 Taking the equalization circuit located or deployed in the intermediate frequency unit as an example, the equalization circuit is located or deployed in the radio frequency unit, and its connection with the existing unit is the same as described above. Figure 11 Similarly, this can be understood by reference and will not be elaborated further. It is understood that the equalization circuit can also be connected to and controlled by any controller or control circuit with control functions in other transmitting or receiving devices, without limitation. Optionally, in the embodiments of this application, the communication protocol can be a module-specific protocol instruction or an existing protocol, and can be a serial peripheral interface (SPI), a two-wire serial communication interface (Inter-Integrated Circuit, I / O), or a serial peripheral interface (SPI). 2 C) Various serial ports such as RS-232. The interfaces of the hardware modules of the transmitting or receiving devices can include: analog signal input interfaces, analog signal output interfaces, control interfaces, and power supply interfaces. The analog signal input interface can be used to input the system's original analog signals; the analog signal output interface can be used to output processed analog signals with different frequency amplitude values; the control interface can be used to communicate with the baseband (unit) and transmit control commands; the power supply interface can be used to power the hardware modules. For example, in a wired communication scenario... Figure 12 A schematic diagram of the architecture of a communication system provided in this application embodiment. Figure 3 ,like Figure 12 As shown, the transmitting end and the receiving end communicate via wired communication through transmission lines or optical fibers. The transmitting end can consist of a baseband unit, an intermediate frequency unit (or an intermediate frequency system), and a transmitting front end; the receiving end can consist of a receiving front end, an intermediate frequency unit (or an intermediate frequency system), and a baseband unit.

[0174] At the transmitting end, the signal to be transmitted is processed by the baseband unit to generate an analog baseband signal, which is then sent to the intermediate frequency (IF) unit. The IF unit amplifies and filters the analog baseband signal and sends the processed IF signal to the transmitting front end. The transmitting front end modulates the processed IF signal onto radio frequency (RF) or optical signals and then transmits it to the receiving end via a transmission line or optical fiber. At the receiving end, the receiving front end receives the signal transmitted via the transmission line or optical fiber and sends the received signal to the IF unit. The IF unit converts the signal into an IF signal, amplifies and filters it, and then sends the amplified and filtered IF signal to the baseband unit. The baseband unit demodulates the amplified and filtered IF signal to reconstruct the original signal.

[0175] Optionally, the transmitting front end can be a radio frequency (RF) front end (or RF unit), or it can be an optical module, laser generator, or other devices, without limitation. In the embodiments of this application, the transmitting method and transmission line type are not limited, and it can be applied to any system with an analog intermediate frequency unit. Based on Figure 12 In the communication system shown in this application embodiment, corresponding to the communication method (e.g., corresponding to the software adaptive equalization algorithm), the transmitting end or the receiving end contains a baseband unit. That is, the communication method of this application embodiment can be carried in the baseband algorithm of the transmitting end and / or the receiving end (deployed in the existing baseband unit, for example, by adding a new module, such as an adaptive equalization algorithm module). Corresponding to the equalization circuit, the transmitting end or the receiving end contains an intermediate frequency unit. That is, the equalization circuit of this application embodiment can be located in the intermediate frequency unit of the transmitting end and / or the receiving end. This application embodiment does not limit this.

[0176] It is understandable that the above Figures 9-10 ,as well as Figure 12 This is a simplified diagram for ease of understanding; other devices may also be included in this communication system. Figures 9-10 ,as well as Figure 12 It was not drawn.

[0177] The following will combine Figures 13-20 The equalization circuit provided in the embodiments of this application will be described in detail.

[0178] For example, Figure 13 This is a schematic diagram of an equalization circuit provided in an embodiment of this application. Figure 13 As shown, the equalization circuit may include P equalization sub-circuits, which are connected in parallel on the analog signal (main) transmission line, where P is an integer greater than 1. That is, the equalization circuit may include multiple equalization sub-circuits connected in parallel, and the specific value of P is not limited in the embodiments of this application.

[0179] Each of the P equalization sub-circuits can perform amplitude equalization on the first signal, or in other words, the P equalization sub-circuits can equalize the amplitude of the first signal at different frequency points to obtain P equalized signals. This equalization circuit can be located or deployed in the intermediate frequency unit or radio frequency unit of the transmitting end and / or the receiving end. At the transmitting end, the first signal can be the signal that the transmitting end needs to transmit, and the transmitting end can perform amplitude equalization on the first signal through each of the P equalization sub-circuits. At the receiving end, the first signal can be the signal received by the receiving end, and the receiving end can perform amplitude equalization on the first signal through each of the P equalization sub-circuits. The frequency range of the first signal is within a first bandwidth, which can be the system bandwidth or scheduling bandwidth, etc. This application embodiment does not limit the frequency range of the first bandwidth.

[0180] Each of the P equalization sub-circuits can adjust the amplitude and / or frequency of the first signal, meaning each of the P equalization sub-circuits can generate a dip at a specific frequency. In other words, each of the P equalization sub-circuits can create a dip of arbitrary amplitude at any frequency. Based on the above, the equalization circuit is connected to the processor. The processor can adjust the equalization amplitude (i.e., the amplitude corresponding to the dip) and equalization frequency (i.e., the frequency corresponding to the dip) of each of the P equalization sub-circuits, allowing the P equalization sub-circuits to synthesize an equalization curve of arbitrary waveform. Each of the P equalization sub-circuits adjusts the amplitude and / or frequency of the first signal to obtain P equalized signals. The center frequencies (corresponding to the equalization frequencies) of any two of the P equalized signals are different from the amplitudes corresponding to the center frequencies (corresponding to the equalization amplitudes).

[0181] An equalization circuit can be understood as a hardware-adjustable equalization circuit, comprising multiple equalization sub-circuits connected in parallel. Each equalization sub-circuit can adjust the amplitude and frequency of a signal (such as the first signal mentioned above), thus enabling the creation of a dip of arbitrary amplitude at any frequency point. Because this equalization sub-circuit is connected in parallel to the analog signal transmission line, it can fit the amplitude control curve of any waveform, achieving complex equalization waveforms. It has a wide range of applications and fine equalization granularity (frequency point granularity), allowing for precise amplitude adjustment.

[0182] For example, such as Figure 14As shown in (a), taking P=3 as an example, the equalization circuit can include equalization sub-circuit #1, equalization sub-circuit #2, and equalization sub-circuit #3. Equalization sub-circuit #1, equalization sub-circuit #2, and equalization sub-circuit #3 are connected in parallel on the analog signal main transmission line. The processor adjusts the equalization amplitude and equalization frequency of equalization sub-circuit #1, equalization sub-circuit #2, and equalization sub-circuit #3. For example, the equalization amplitude of equalization sub-circuit #1 is a1, and the equalization frequency is f1 (i.e., equalization sub-circuit #1 corresponds to response #1); the equalization amplitude of equalization sub-circuit #2 is a2, and the equalization frequency is f2 (i.e., equalization sub-circuit #2 corresponds to response #2); the equalization amplitude of equalization sub-circuit #3 is a3, and the equalization frequency is f3 (i.e., equalization sub-circuit #3 corresponds to response #3). Figure 14 As shown in (b), the horizontal axis represents frequency and the vertical axis represents amplitude. Responses #1, #2, and #3 can be superimposed to form the equalization curve of waveform #1. The waveform of this equalization curve can be related to the values ​​of f1, a1, f2, a2, f3, and a3. It should be understood that any two of f1, f2, and f3, and / or any two of a1, a2, and a3 are different. This application embodiment does not limit the specific values ​​of f1, a1, f2, a2, f3, and a3.

[0183] In one possible design, P equalized signals are superimposed and output through an analog signal transmission line to obtain an equalized signal; the difference between the maximum and minimum amplitudes of the equalized signal within the first bandwidth is less than or equal to the first value.

[0184] That is, the first signal is amplitude-equalized by an equalization curve synthesized from P equalization sub-circuits to obtain an equalized signal. The difference between the maximum and minimum amplitudes of this equalized signal within the first bandwidth is less than or equal to a first value. In this case, the amplitude of the equalized signal within the first bandwidth can be considered equalized. It is understood that the specific value of the first value is not limited in the embodiments of this application.

[0185] Based on the above introduction, the structure of the equalization circuit will be described below using one of the P equalization sub-circuits as an example.

[0186] In one possible design, each of the P equalization sub-circuits includes an adjustable resistor unit and an adjustable resonator unit, which are connected in series.

[0187] The adjustable resistor unit can be used to adjust the amplitude of the first signal. It can be understood that the resistance value determines the magnitude of transmission loss (i.e., equalization amplitude), and different resistance values ​​of the adjustable resistor unit result in different amplitude equalization capabilities for the first signal. For example, taking the a-th equalization sub-circuit out of P equalization sub-circuits (a is an integer greater than 0 and less than or equal to M), the a-th equalization sub-circuit includes an adjustable resistor unit #1 and an adjustable resonant unit #1. With the resonant frequency (e.g., f1) corresponding to the adjustable resonant unit #1 remaining constant, such as... Figure 15 As shown, the horizontal axis represents frequency, and the vertical axis represents amplitude. When the resistance value of adjustable resistor unit #1 is K1, it corresponds to response #1; when the resistance value of adjustable resistor unit #2 is K2, it corresponds to response #2; and when the resistance value of adjustable resistor unit #3 is K3, it corresponds to response #3. The values ​​of K1, K2, and K3 are different. At this time, the amplitudes of responses #1, #2, and #3 at f1 are different, or in other words, the dips produced by responses #1, #2, and #3 at f1 are different. Each of the P equalization sub-circuits can adjust the amplitude of the first signal by adjusting the resistance value of its respective adjustable resistor unit.

[0188] The adjustable resonator unit can be used to adjust the frequency of the first signal. It can be understood that the adjustable resonator unit can be equivalently represented as a resonator consisting of a resistor, inductor, and capacitor connected in series. When the inductance or capacitance changes, the resonant frequency of the resonator also changes accordingly, and the resonant frequency can determine the trough frequency (i.e., the equalization frequency). Each of the P equalization sub-circuits can adjust the frequency of the first signal by adjusting the resonant frequency of its respective adjustable resonator unit. Optionally, in this embodiment, the inductor and capacitor are not limited to discrete components (such as structure 3 below), but can also be other forms of inductors and capacitors such as microstrip lines (such as structure 4), as long as their equivalent circuit principle is inductance and capacitance. This embodiment does not limit this.

[0189] The following section will use the following structure as an example to introduce the adjustable resistor unit in detail.

[0190] Structure 1: such as Figure 16 As shown, the adjustable resistor unit may include M fixed resistors connected in parallel, a series-to-parallel converter, and M switches.

[0191] In this configuration, M switches correspond one-to-one with M fixed resistors, and the M switches can be used to control the conduction or deactivation of the M fixed resistors. These M switches are connected to a serial-to-parallel converter, whose bit count can be greater than or equal to the number of fixed resistors. The serial-to-parallel converter can control the M switches; for example, each bit of the converter can control one of the M switches. Optionally, the serial-to-parallel converter can be connected to a processor or any other controller or control circuit with control functions. This converter is controlled by a baseband communication protocol and can convert the protocol information sent by the baseband unit (at the transmitting or receiving end) into a level that controls the selection of the switches, thereby controlling the opening and closing of the M switches. The opening and closing of the M switches can control the conduction or deactivation of the M fixed resistors, and the conduction or deactivation of the M fixed resistors can be associated with the resistance value formed by the M fixed resistors. M is an integer greater than 1. Thus, the serial-to-parallel converter uses the M switches to control the conduction or deactivation of the M fixed resistors to obtain different resistance values. This embodiment does not limit the specific value of M. It is understood that the switch can be an analog switch, such as a single-pole single-throw switch, without limitation.

[0192] For example, taking the a-th equalization sub-circuit out of P equalization sub-circuits (a is an integer greater than 0 and less than or equal to M), assuming M = 16, the adjustable resistor unit of this a-th equalization sub-circuit includes 16 fixed resistors connected in parallel, a serial-to-parallel converter, and 16 switches. In this case, the serial-to-parallel converter can be a 16-bit converter, with each of the 16 bits corresponding to one of the 16 switches. The 16 fixed resistors can be denoted as R1-R16, where R1-R16 represent resistors with different resistance values. For example, the resistance values ​​of R1-R16 increase in increments of 20 ohms, with R1 having a resistance of 10 ohms, R2 having a resistance of 30 ohms, ..., and R16 having a resistance of 310 ohms. Each resistor in R1-R16 can correspond to a single-pole single-throw switch (a total of 16 single-pole single-throw switches), and the opening and closing of these 16 single-pole single-throw switches can be controlled by a 16-bit serial-to-parallel converter chip.

[0193] For example, if the equalization resistance required for the a-th equalization sub-circuit is 10 ohms, the serial-to-parallel converter can convert the serial signal into a 16-bit parallel signal to control the single-pole single-throw switch corresponding to R1 to close, and the single-pole single-throw switches corresponding to R2-R16 to open. In this case, the resistance value of the adjustable resistor unit of the a-th equalization sub-circuit can be the resistance value of R1, i.e., 10 ohms. As another example, if the equalization resistance required for the a-th equalization sub-circuit is 77 ohms, the serial-to-parallel converter can convert the serial signal into a 16-bit parallel signal to control the single-pole single-throw switches corresponding to R7 and R10 to close, and the single-pole single-throw switches corresponding to the other resistors in R1-R16 (excluding R7 and R10) to open. In this case, the resistance value of the adjustable resistor unit of the a-th equalization sub-circuit can be the resistance value obtained by connecting R7 (130 ohms) and R10 (190 ohms) in parallel, i.e., 77 ohms, and so on. Further details are omitted.

[0194] It is understood that the resistance values ​​of the M fixed resistors contained in each of the P equalization sub-circuits can be the same or different, without limitation; the number of fixed resistors (i.e., M) contained in each of the P equalization sub-circuits, and the resistance values ​​of the fixed resistors contained therein, can be the same or different, without limitation.

[0195] Structure 2: such as Figure 17 As shown, the adjustable resistor unit may include a sliding resistor and mechanical components.

[0196] The mechanical device can be used to adjust the resistance value of the sliding resistor by adjusting its pins. This mechanical device can be connected to a processor, such as a microcontroller, FPGA, CPU, or DSP. The processor can control the mechanical device to achieve precise control of the sliding pin position of the sliding rheostat, thereby enabling continuous adjustment of the resistance value to obtain different resistance values. This application does not limit the range of resistance values ​​for the sliding rheostat.

[0197] In one possible design, the mechanical component is a mechanical servo motor, that is, existing electronic components are reused to reduce the difficulty of implementation; or, the variable capacitor can also be a new electronic component to improve the flexibility of implementation, without limitation.

[0198] It is understood that the above structures 1 and 2 are merely examples, and the adjustable resistor unit can also be any other possible structure without limitation.

[0199] The following section uses the following structure as an example to introduce the tunable resonator unit in detail.

[0200] Structure 3: such as Figure 18 As shown, the adjustable resonator unit may include a variable capacitor, a fixed inductor, and a first DAC.

[0201] In this circuit, a variable capacitor and a fixed inductor are connected in series to form a resonator. The variable capacitor can be connected to a first DAC, which can be used to adjust the capacitance value of the variable capacitor by adjusting the voltage value. The first DAC can be connected to a processor, such as a microcontroller, FPGA, CPU, or DSP. The processor can send instructions to the first DAC via a serial port protocol. After receiving the instruction, the first DAC can generate the required analog voltage value and apply it to the variable capacitor to change the capacitance value, thereby changing the resonant frequency of the resonator.

[0202] In one possible design, the variable capacitor can be a varactor diode, which reuses existing electronic components to reduce the difficulty of implementation; or, the variable capacitor can also be a new electronic component to improve the flexibility of implementation, without limitation.

[0203] For example, taking a varactor diode as the variable capacitor, the first DAC can change the capacitance value of the varactor diode by applying a reverse voltage to it. Figure 19 As shown, the horizontal axis represents the reverse voltage value (voltage, V), and the vertical axis represents the capacitance value (C) of the varactor diode. Under the same temperature conditions (e.g., a constant temperature environment, taking 25°C as an example), the larger the reverse voltage applied by the first DAC to the varactor diode, the smaller the capacitance value of the varactor diode, and the higher the resonant frequency of the resonator; conversely, the smaller the reverse voltage applied by the first DAC to the varactor diode, the larger the capacitance value of the varactor diode, and the lower the resonant frequency of the resonator. This application does not limit the specific model of the varactor diode in its embodiments. It is understood that the adjustable resonator unit may not include the first DAC; for example, the adjustable resonator unit can directly reuse the DAC of an existing system to reduce the complexity of hardware implementation. This application does not limit the comparison of its embodiments.

[0204] In one possible design, the adjustable resonator unit may further include a fixed capacitor, which may be connected in parallel with a variable capacitor to increase the capacitance range of the equalization sub-circuit. It is understood that the number of fixed capacitors can be one or more, without limitation; the capacitance values ​​of these fixed capacitors can be the same or different, without limitation; the specific values ​​of the one or more fixed capacitors are not limited in the embodiments of this application.

[0205] Structure 4: such as Figure 20 As shown, the tunable resonator unit may include a fixed capacitor, N microstrip lines, N-1 diodes, and a second DAC.

[0206] In this configuration, a fixed capacitor is connected in series with N microstrip lines. Two microstrip lines arranged sequentially within the N microstrip lines are connected via one of N-1 diodes. For example, these N microstrip lines can be denoted as microstrip line #1 to microstrip line #N, arranged sequentially in the order of #1 to #N. Here, two sequentially arranged microstrip lines can refer to two microstrip lines arranged in a continuous sequence, such as microstrip line #1 and microstrip line #2, microstrip line #2 and microstrip line #3, ..., microstrip line #N-1 and microstrip line #N, etc. Taking microstrip line #1 and microstrip line #2 as an example, they can be connected via a single diode. The N microstrip lines need to be connected sequentially via N-1 diodes, where N is an integer greater than 1. This embodiment does not limit the specific value of N.

[0207] N-1 diodes are connected to a second DAC, which can be used to control the conduction or deactivation of the N-1 diodes by adjusting their voltage values. For example, the second DAC can be connected to a processor, such as a microcontroller, FPGA, CPU, or DSP. The processor can send commands to the second DAC via a serial port protocol. After receiving the command, the second DAC can generate bias voltages for each of the N-1 diodes. The second DAC can control the conduction or deactivation of the N-1 diodes by applying a bias voltage to each diode.

[0208] The conduction or deactivation of these N-1 diodes is related to the connection length formed by the N microstrip lines. For example, as Figure 20 As shown, taking N=4 as an example, the four microstrip lines are denoted as microstrip line #1, microstrip line #2, microstrip line #3, and microstrip line #4. Microstrip lines #1, #2, #3, and #4 are arranged sequentially, with microstrip line #1 connected in series with a fixed capacitor C1. Microstrip lines #1 and #2 are connected via diode #1, #2 and #3 via diode #2, and #3 and #4 via diode #3. When the second DAC controls only diode #1 to conduct, the connection length formed by N microstrip lines can be the length of microstrip line #1; when the second DAC controls only diodes #1 and #2 to conduct, the connection length formed by N microstrip lines can be the sum of the lengths of microstrip lines #1 and #2; when the second DAC controls only diodes #1, #2, and #3 to conduct, the connection length formed by N microstrip lines can be the sum of the lengths of microstrip lines #1, #2, and #3; when the second DAC controls all diodes #1, #2, #3, and #4 to conduct, the connection length formed by N microstrip lines can be the sum of the lengths of microstrip lines #1, #2, #3, and #4.

[0209] The N-segment microstrip line can be equivalent to a variable inductor; therefore, the fixed capacitor and the N-segment microstrip line can be equivalent to a resonator. Changing the connection length formed by the N-segment microstrip line can be equivalent to changing the inductance value of the variable inductor. At this time, the resonant frequency of the resonator formed by the fixed capacitor and the N-segment microstrip line will also change accordingly, thereby achieving resonant frequency adjustment. Specifically, the longer the connection length formed by the N-segment microstrip line, the larger the inductance value of its equivalent variable inductor, and the lower the resonant frequency of the resonator; conversely, the shorter the connection length formed by the N-segment microstrip line, the smaller the inductance value of its equivalent variable inductor, and the lower the resonant frequency of the resonator. It is understood that the adjustable resonator unit may not include a second DAC; for example, the adjustable resonator unit can directly reuse the DAC of an existing system to reduce the complexity of hardware implementation. This application does not limit this aspect.

[0210] It is understandable that, compared to structure 3 above, the tunable resonant unit shown in structure 4 uses N-segment microstrip lines as equivalent to a variable inductor, which can be applied to high-frequency (such as frequency ranges exceeding 1 gigahertz (GHz), or even to the terahertz band) scenarios, and can realize high-frequency systems, such as amplitude equalization of millimeter-wave band signals.

[0211] It is understood that structures 3-4 above are merely examples, and the tunable resonant unit can be any other possible structure without limitation.

[0212] Based on the descriptions of structures 1-4 above, the two structures of the adjustable resistor unit and the two structures of the adjustable resonant unit can be combined or coupled together. For example, the adjustable resistor unit shown in structure 1 and the adjustable resonant unit shown in structure 3 can form an equalization sub-circuit (denoted as type #1); the adjustable resistor unit shown in structure 1 and the adjustable resonant unit shown in structure 4 can form an equalization sub-circuit (denoted as type #2); the adjustable resistor unit shown in structure 2 and the adjustable resonant unit shown in structure 3 can form an equalization sub-circuit (denoted as type #3); and the adjustable resistor unit shown in structure 2 and the adjustable resonant unit shown in structure 4 can form an equalization sub-circuit (denoted as type #4). Each of the P equalization sub-circuits can be of the same type, such as all P equalization sub-circuits being one of type #1, type #2, type #3, or type #4; or, each of the P equalization sub-circuits can be of different types, such as some of the P equalization sub-circuits being type #1 and others being type #2, etc., without limitation.

[0213] Based on the above introduction, the names of the equalization circuit, equalization sub-circuit, adjustable resistor unit, and adjustable resonator unit are merely examples. The equalization circuit, equalization sub-circuit, adjustable resistor unit, and adjustable resonator unit can be replaced with any other possible names without limitation.

[0214] In summary, the equalization circuit includes multiple equalization sub-circuits connected in parallel on the analog signal transmission line. These multiple equalization sub-circuits, namely the aforementioned P equalization sub-circuits, can equalize the amplitude of the first signal at different frequency points, resulting in P equalized signals. The center frequencies of any two of these P equalized signals are different, and / or their corresponding amplitudes are different. That is, each of the P equalization sub-circuits can create a dip of arbitrary amplitude at any frequency point. These P equalized signals are superimposed and output through the analog signal transmission line; that is, the first signal undergoes amplitude equalization through the equalization curve synthesized by the P equalization sub-circuits. Since the P equalization sub-circuits can synthesize an equalization curve with arbitrary waveforms, the system's flatness can be automatically adjusted in real time according to dynamic scene changes, improving system performance. Furthermore, the waveform variation range of this equalization curve is large, which can meet the needs of different scenarios.

[0215] The above combination Figures 13-20 The equalization circuit provided in the embodiments of this application is described in detail below. Figures 21-22 The communication method provided in the embodiments of this application will be described in detail.

[0216] For example, Figure 21 This is a flowchart illustrating a communication method provided in an embodiment of this application. The method is applicable to the aforementioned communication system and involves interaction between a first device and a second device. Both the first device and the second device may include the aforementioned... Figure 13 The equalization circuit shown below, hereinafter, includes the above-described first device. Figure 13 Taking the equalization circuit shown as an example, the first device includes an equalization circuit, which can be understood as having the aforementioned equalization circuit pre-installed in the hardware circuit of the first device. Figure 13 The equalization circuit shown can be located or deployed in the intermediate frequency unit or radio frequency unit of the first device, without limitation.

[0217] like Figure 21 As shown, the flow of this communication method is as follows:

[0218] S2101, the first device acquires flatness information.

[0219] The flatness information can be used to indicate the amplitude variation of the second signal within the first bandwidth. The amplitude variation of the second signal within the first bandwidth can characterize: the flatness of the system within the first bandwidth, the range of amplitude variation of the second signal within the first bandwidth, or, in other words, how the amplitude of the second signal changes with frequency (within the first bandwidth). The frequency range of the second signal is the first bandwidth, which can be the system bandwidth, scheduling bandwidth, etc. This application embodiment does not limit the frequency range of the first bandwidth.

[0220] The following example illustrates the specific implementation of the first device acquiring flatness information.

[0221] Implementation 1: The first device sends a second signal to the second device. Correspondingly, the second device receives the second signal from the first device.

[0222] The second device measures the flatness of the second signal to obtain flatness information.

[0223] The second device sends flatness information to the first device. Correspondingly, the first device receives flatness information from the second device.

[0224] The second signal can be used by the second device to measure flatness. The implementation of the first method is described below using the following scenario as an example.

[0225] Scenario 1: The first device is a network device, and the second device is a terminal device.

[0226] The second signal can be at least one of the following: downlink flatness reference signal (DL-FRS), SSB, CSI-RS, PSS, SSS, DMRS, PT-RS, or physical downlink channel. That is, in the downlink communication scenario shown in Scenario 1, the second signal can be carried in existing cells or channels (such as the aforementioned SSB, CSI-RS, PSS, SSS, DMRS, PT-RS, or physical downlink channel) to reduce implementation difficulty, or it can be carried in new cells or channels (such as the aforementioned DL-FRS) to improve implementation flexibility, without limitation.

[0227] It is understood that the above-mentioned DL-FRS is a newly defined reference signal for flatness measurement in this application embodiment. The DL-FRS may have the following characteristics: the DL-FRS is a broadcast signal; it has frequency domain power consistency, or the DL-FRS performs frequency domain power allocation in a manner known to the second device, i.e., the terminal device; it has time domain sparsity, for example, it is transmitted once at intervals of 1 second (s), 10 seconds, or longer; the time-frequency resource configuration of the DL-FRS can be periodic, aperiodic, or semi-static.

[0228] The specific implementation principle of the first device sending SSB, CSI-RS, PSS, SSS, DMRS, PT-RS, or physical downlink channel to the second device is similar to existing implementations and can be understood by reference. For example, taking the second signal as an SSB, the first device can simultaneously send multiple SSBs to the second device using frequency division multiplexing, i.e., extending the SSB in the frequency domain. The indices of the multiple simultaneously sent SSBs can be the same or different, and they can be sent using the same beam or different beams; this application does not limit this. The physical downlink channel can include physical downlink data channels and physical downlink control channels, such as a physical downlink shared channel (PDSCH) or a physical downlink control channel (PDCCH), etc., and is not limited thereto.

[0229] Based on the above introduction, Scenario 1 utilizes downlink transmission resources to obtain flatness information, as downlink transmission resources are typically more abundant. Furthermore, the first device can broadcast a second signal (such as DL-FRS, SSB, etc.) to the second device to reduce overhead, and the broadcast interval can be set to second-level timed transmission. Therefore, the second device can measure the flatness in real time and feed it back to the first device, enabling the first device to obtain real-time flatness information, thus meeting the needs of different scenarios.

[0230] The following section describes the specific implementation of the second device, namely the terminal device, measuring the flatness of the second signal and obtaining flatness information.

[0231] For example, a network device can send a reference signal to a terminal device at intervals of frequency, such as DL-FRS. Multiple reference signals at frequency intervals (such as X, where X is an integer greater than 1) can ultimately cover the entire operating frequency band (such as the first bandwidth mentioned above). After receiving multiple reference signals at frequency intervals, the terminal device can summarize the amplitude values ​​of different frequency points, such as X frequency points. For example, assuming the minimum amplitude in the first bandwidth is A (the amplitude corresponding to the a-th frequency point among the X frequency points is A, where a is an integer greater than 0 and less than or equal to X), the terminal device can subtract A from the amplitude values ​​of the other X-1 frequency points (excluding the a-th frequency point) to obtain the gain (denoted as C) of each of the X frequency points, where the gain C of the a-th frequency point is 0. The terminal device can then summarize the gains C of the X frequency points to obtain the (gain) flatness information of the system. It should be noted that the above implementation is only an example, and the terminal device can also perform flatness measurement on the second signal in any other possible way to obtain flatness information, without limitation.

[0232] Scenario 2: The first device is a terminal device, and the second device is a network device.

[0233] The second signal can be at least one of the following: uplink flatness reference signal (UP-FRS), DMRS, SRS, PT-RS, or physical uplink channel. That is, in the uplink communication scenario shown in Scenario 2, the second signal can be carried in an existing cell or channel (such as the aforementioned SRS, PT-RS, or physical uplink channel) to reduce implementation difficulty, or it can be carried in a new cell or channel (such as the aforementioned UP-FRS) to improve implementation flexibility, without limitation.

[0234] It is understood that the above-mentioned UP-FRS is a newly defined reference signal for flatness measurement in this application embodiment. Similar to the above-mentioned DL-FRS, the UP-FRS may have the following characteristics: the UP-FRS is a broadcast signal; it has frequency domain power consistency, or the UP-FRS performs frequency domain power allocation in a manner known to the first device, i.e., the terminal device; it has time domain sparsity, for example, being transmitted once at intervals of 1s, 10s, or longer; the time-frequency resources of the DL-FRS can be periodic, aperiodic, or semi-static.

[0235] The specific implementation principle of the first device sending SSB, CSI-RS, PSS, SSS, DMRS, PT-RS, or physical downlink channel to the second device is similar to the existing implementation and can be used for reference and understanding. The physical uplink channel can include physical uplink data channels and physical uplink control channels, such as the physical uplink shared channel (PUSCH) or the physical uplink control channel (PUCCH), etc., without limitation.

[0236] Based on the above introduction, Scenario 2 utilizes uplink transmission resources to obtain flatness information. The first device can broadcast a second signal (such as UP-FRS) to the second device to reduce overhead. Furthermore, the broadcast interval can be set to seconds. Therefore, the second device can measure the flatness in real time and feed it back to the first device, enabling the first device to obtain real-time flatness information, thus meeting the needs of different scenarios. Additionally, the second device can measure the flatness based on the second signal sent by the first device. Since the second device is a network device, its capabilities are stronger than those of the terminal device. Therefore, the flatness information obtained by the second device is more comprehensive and accurate. It should be understood that the implementation principle of the second device (i.e., the network device) measuring the flatness of the second signal to obtain flatness information is similar to the implementation principle of the terminal device measuring the flatness of the second signal to obtain flatness information in Scenario 1. This principle can be understood by reference and will not be elaborated further.

[0237] As can be understood, based on the descriptions of Scenario 1 and Scenario 2 above, the first device can obtain flatness information by receiving flatness information from the second device. In this way, the first device does not need to perform flatness measurements itself, reducing its computational overhead.

[0238] Implementation 2: The second device acquires the second signal.

[0239] The second device sends a second signal to the first device. Correspondingly, the first device receives the second signal from the second device.

[0240] The first device measures the flatness of the second signal to obtain flatness information.

[0241] The second signal can be used by the first device to measure flatness. The following scenario illustrates implementation 2.

[0242] Scenario 3: The first device is a terminal device, and the second device is a network device.

[0243] The second signal can be at least one of the following: DL-FRS, SSB, CSI-RS, PSS, SSS, DMRS, PT-RS, or a physical downlink channel. That is, in the downlink communication scenario shown in Scenario 3, the second signal can be carried in existing cells or channels (such as the aforementioned SSB, CSI-RS, PSS, SSS, DMRS, PT-RS, or physical downlink channels) to reduce implementation difficulty, or it can be carried in new cells or channels (such as the aforementioned DL-FRS) to improve implementation flexibility; no limitation is imposed. It should be understood that the specific implementation of the first device, i.e., the terminal device, measuring the flatness of the second signal to obtain flatness information is similar to the implementation principle of the terminal device measuring the flatness of the second signal to obtain flatness information in Scenario 1 above, and can be understood by reference; further details are omitted.

[0244] It is understandable that the specific description of the second signal in Scenario 3 can be found in the relevant description of the second signal in Scenario 1 above, and will not be repeated here.

[0245] Scenario 4: The first device is a network device, and the second device is a terminal device.

[0246] The second signal can be at least one of the following: UP-FRS, DMRS, SRS, PT-RS, or a physical uplink channel. That is, in uplink communication scenarios, the second signal can be carried in existing cells or channels (such as DMRS, SRS, PT-RS, or a physical uplink channel) to reduce implementation difficulty, or it can be carried in new cells or channels (such as UP-FRS) to improve implementation flexibility; there are no limitations. It should be understood that the specific implementation of the first device, i.e., the network device, measuring the flatness of the second signal to obtain flatness information is similar to the implementation principle of the terminal device measuring the flatness of the second signal to obtain flatness information in scenario 1 above, and can be understood by reference; it will not be elaborated further.

[0247] It is understandable that the specific description of the second signal in Scenario 4 can be found in the relevant description of the second signal in Scenario 2 above, and will not be repeated here.

[0248] Based on the above description, in scenario 4, the first device can directly measure the flatness based on the second signal sent by the second device. Since the first device is a network device, its capabilities are stronger than those of the terminal device. Therefore, the flatness information obtained by the first device in measuring the flatness is more comprehensive and accurate.

[0249] It is understandable that, based on the above descriptions of scenarios 3 and 4, the second device can directly measure the flatness according to the second signal sent by the second device to obtain flatness information without having to provide feedback to the second device. This can reduce the resource overhead of the first device.

[0250] It should be understood that scenarios 1-4 above are merely examples, and the first device can obtain flatness information in any other possible way without limitation; the naming of the flatness information, the second signal, and the first bandwidth above are merely examples, and the flatness information, the second signal, and the first bandwidth can be replaced with any other possible names without limitation.

[0251] S2102, the first device performs amplitude equalization on the first signal through P equalization sub-circuits based on the flatness information, and obtains P equalized signals.

[0252] The equalization circuit may include P equalization sub-circuits, where P is an integer greater than 1. This application does not limit the specific value of P; for details, please refer to the above description. Figure 13 The specific details of the equalization circuit shown are not elaborated here. The frequency range of the first signal is within the first bandwidth, that is, it can be less than or equal to the first bandwidth, without limitation. The first signal can be a transmitted signal. When the first device is the transmitter, the first signal can be the signal that the first device needs to send out; when the first device is the receiver, the first signal can be the signal that the first device receives. The first device can use a preset equalization circuit, that is, P equalization sub-circuits, to equalize the amplitude of the first signal at different frequency points according to the flatness information obtained in step S2101 above, to obtain P equalized signals.

[0253] The following describes the specific implementation of the first device, which uses P equalization sub-circuits to perform amplitude equalization on the first signal based on flatness information, to obtain P equalized signals.

[0254] In one possible design, the first device determines the equilibrium curve based on the flatness information.

[0255] The first device controls the P equalization sub-circuits to perform amplitude equalization on the first signal according to their respective hardware parameters, thereby obtaining P equalized signals.

[0256] The equalization curve can be used to determine the hardware parameters of each of the P equalization sub-circuits, such as the resistance values ​​of the adjustable resistor units corresponding to each of the P equalization sub-circuits (e.g., the resistance values ​​formed by the M fixed resistors in structure 1 above, or the resistance values ​​of the sliding resistors in structure 2 above, etc.) and the resonant frequencies of the adjustable resonator units (e.g., the capacitance values ​​of the variable capacitor and the inductance values ​​of the fixed inductor in structure 3 above, or the capacitance values ​​of the fixed capacitor and the connection lengths formed by the N microstrip lines in structure 4 above, etc.). Since the hardware parameters of any two equalization sub-circuits in the P equalization sub-circuits are different, the center frequencies and / or the amplitudes corresponding to the center frequencies of any two of the P equalized signals are different. For a detailed explanation, please refer to the above... Figure 13 The relevant details of the equalization circuit shown will not be elaborated upon here.

[0257] In one possible design, the first bandwidth may include X frequency points, and the first device determines the equalization curve based on flatness information, including:

[0258] The first device determines the average amplitude of the second signal at X frequency points based on the flatness information.

[0259] The first device determines X target amplitudes based on the average amplitude.

[0260] The first device determines the equilibrium curve based on X target amplitudes.

[0261] Wherein, X frequency points can be reference frequency points selected within the first bandwidth, and X is an integer greater than 1. The embodiment of this application does not limit the value of X. X target amplitudes can correspond one-to-one with X frequency points. The i-th target amplitude among the X target amplitudes is equal to the difference between the amplitude of the second signal at the i-th frequency point and the average amplitude. i is an integer greater than 0 and less than or equal to X. The embodiment of this application does not limit the specific value of i.

[0262] For example, the baseband unit of the first device determines an amplitude-frequency curve #1 based on the acquired flatness information. The horizontal axis of this amplitude-frequency curve #1 represents frequency, and the vertical axis represents amplitude. This amplitude-frequency curve #1 corresponds to X frequency points on the horizontal axis and the amplitude of each of the X frequency points on the vertical axis. The first device can calculate the average amplitude of the second signal at the X frequency points based on their respective amplitudes, denoted as P1. The first device can subtract the amplitudes of each of the X frequency points from P1 to obtain the target amplitudes for each of the X frequency points, denoted as P2. The first device can then plot an amplitude-frequency curve #2 based on the X frequency points and their target amplitudes. This amplitude-frequency curve #2 represents frequency on the horizontal axis and amplitude on the vertical axis; it is an equalization curve. This equalization curve is the equalization curve synthesized by the P equalization sub-circuits required by the first device's equalization circuit.

[0263] It is understandable that the first device can directly calculate the hardware parameters of each of the P equalization sub-circuits based on the equalization curve; or, before the equalization circuit is pre-set in the first device, the protocol predefines or pre-configures a table of different equalization curves and the hardware parameters of each of the P equalization sub-circuits. In this case, the first device can select the hardware parameters of each of the P equalization sub-circuits corresponding to the equalization curve determined above. It should be noted that if each of the P equalization sub-circuits performs amplitude equalization on the first signal, then P equals X. In this case, the first device can determine the hardware parameters of each of the P equalization sub-circuits based on the equalization curve. If only some of the P equalization sub-circuits perform amplitude equalization on the first signal, then P is greater than X. In this case, the first device can select X equalization sub-circuits from the P equalization sub-circuits based on the equalization curve and determine the hardware parameters of each of the X equalization sub-circuits. This application embodiment does not limit the specific implementation of the first device selecting X equalization sub-circuits from the P equalization sub-circuits based on the equalization curve. For ease of understanding, the following description uses P equal to X as an example.

[0264] In one possible design, before the first device controls the P equalization sub-circuits to perform amplitude equalization on the first signal according to their respective hardware parameters, the following steps are included:

[0265] The first device sends P instruction messages to the P equalization sub-circuits based on their respective hardware parameters.

[0266] In this embodiment, each of the P indication messages corresponds one-to-one with one of the P equalization sub-circuits. The j-th indication message among the P indication messages can be used to instruct the j-th equalization sub-circuit to perform amplitude equalization on the first signal using its corresponding hardware parameters. j is an integer greater than 0 and less than or equal to P. This embodiment does not limit the specific value of j. That is, the first device can send control protocols (such as the aforementioned P indication messages) to the equalization circuit based on the hardware parameters of each of the P equalization sub-circuits. Each of the P equalization sub-circuits can then adjust the resistance values ​​of their respective adjustable resistor units (such as the resistance values ​​formed by the M fixed resistors in structure 1, or the resistance values ​​of the sliding resistor in structure 2) and the resonant frequencies of their adjustable resonator units (such as the capacitance values ​​of the variable capacitor and the inductance values ​​of the fixed inductor in structure 3, or the capacitance values ​​of the fixed capacitor and the connection length formed by the N microstrip lines in structure 4), so that the P equalization sub-circuits can fit the aforementioned equalization curve. This allows for on-demand indication and flexibility.

[0267] After the P equalization sub-circuits adjust the resistance values ​​of their respective adjustable resistor units and the resonant frequencies of their adjustable resonator units, the first device can control the P equalization sub-circuits to perform amplitude equalization on the first signal, resulting in P equalized signals. In other words, the first device can input the first signal into the P equalization sub-circuits for amplitude equalization to obtain P equalized signals. Furthermore, the first device can automatically adjust the flatness of the hardware system in reverse according to real-time changes in the dynamic scene, adaptively aligning gain bottlenecks and achieving adaptive real-time adjustment of in-band flatness.

[0268] In one possible design, the first device performs amplitude equalization on the first signal using P equalization sub-circuits based on flatness information, resulting in P equalized signals, including:

[0269] The first device determines whether the flatness information meets the first condition. The first condition may include: the amplitude variation range of the second signal within the first bandwidth is greater than the second value.

[0270] When the flatness information meets the first condition, the first device performs amplitude equalization on the first signal through P equalization sub-circuits according to the flatness information to obtain P equalized signals.

[0271] For example, such as Figure 22 As shown, the first device can acquire flatness information (measured by the first or second device). Then, the first device can judge the flatness information. If the flatness information satisfies the first condition—that is, the amplitude variation range of the second signal within the first bandwidth is greater than the second value—then the system can be considered to have in-band (within the first bandwidth) flatness. At this point, the first device needs to calculate the equalization curve based on the flatness information and issue control commands (i.e., the aforementioned P indication information) to the P equalization sub-circuits. This allows the P equalization sub-circuits to adjust the resistance value of their respective adjustable resistor units and the resonant frequency of their adjustable resonator units according to the received indication information, thereby achieving adaptive real-time flatness adjustment.

[0272] Conversely, when the first device determines that the flatness information does not meet the first condition, that is, when the amplitude variation range of the second signal within the first bandwidth is less than or equal to the second value, the gain of the system can be considered flat, and the system operates normally. In this way, it can avoid triggering P equalization sub-circuits to perform amplitude equalization on the first signal even when the flatness information does not meet the first condition, thereby reducing resource and hardware overhead.

[0273] Optionally, the first device can also periodically trigger equalization commands, that is, the first device can periodically acquire flatness information and judge the acquired flatness information to re-execute the above steps, which will not be elaborated further. It can be understood that the periodically acquired flatness information can be the flatness information updated in real time by the first device (as described in implementation 2 above) or the second device (as described in implementation 1 above) according to the dynamic scene changes. Therefore, the first device can determine the equalization curve based on the real-time updated flatness information and correct it through hardware circuits (such as the hardware parameters of each of the P equalization sub-circuits above) to achieve automatic in-band (within the first bandwidth) amplitude equalization. It can be understood that the specific value of the second value is not limited in the embodiments of this application. Optionally, after the P equalization sub-circuits adjust the resistance value of their respective adjustable resistor units and the resonant frequency of their respective adjustable resonator units according to the instruction information they receive, the first device can continue to acquire real-time flatness information and judge the acquired flatness information to re-execute the above steps, which will not be elaborated further.

[0274] It should be understood that the above implementation is merely an example, and the first device can also determine the flatness information in any other possible way without limitation.

[0275] It should be understood that the naming of the above instructions and the first condition is merely an example, and the instructions and the first condition can be replaced with any other possible names without limitation.

[0276] S2103, the first device superimposes P equalized signals to obtain an equalized signal.

[0277] Based on the above Figure 13 The equalization circuit shown has P equalization sub-circuits connected in parallel on the analog signal (main) transmission line. The first device superimposes the P equalized signals; that is, the first signal undergoes amplitude equalization using the equalization curve synthesized by the P equalization sub-circuits to obtain an equalized signal, which is output through the analog signal (main) transmission line. The difference between the maximum and minimum amplitude of the equalized signal within a first bandwidth is less than or equal to a first value. In this case, the amplitude of the equalized signal within the first bandwidth can be considered equalized. It is understood that the specific value of the first value is not limited in this embodiment. It is understood that when the first device is a transmitter, it can send the equalized signal to the receiving device; when the first device is a receiver, it can demodulate the equalized signal for subsequent steps. This embodiment does not limit this.

[0278] In summary, the first device can perform amplitude equalization on the first signal within the first bandwidth using P equalization sub-circuits based on the acquired flatness information, obtaining P equalized signals. These P equalized signals are then superimposed to obtain a balanced signal. This flatness information indicates the amplitude change of the second signal within the first bandwidth; in other words, it indicates the real-time system flatness. Thus, the first device can dynamically and automatically adjust the system flatness in real time based on the flatness information to achieve automatic amplitude equalization of the signal within the first bandwidth (such as the first signal mentioned above).

[0279] It is understood that the above refers to the first device including ( Figure 13 Taking the equalization circuit shown as an example, the specific implementation of automatic amplitude equalization in the first device will be introduced. The second device includes... Figure 13 The principle behind the automatic amplitude equalization implemented by the equalization circuit shown is similar to that of the first device, and can be understood by reference, without further explanation. The above communication method can be applied to any communication system requiring communication flatness, and this application does not limit it.

[0280] The above combination Figures 21-22 The communication method provided in the embodiments of this application is described in detail below. Figures 23-24 This document describes in detail the communication apparatus used to perform the communication method provided in the embodiments of this application.

[0281] Figure 23 This is a schematic diagram of the structure of the communication device provided in the embodiments of this application. Figure 1 For example, such as Figure 23 As shown, the communication device 2300 includes a transceiver module 2301 and a processing module 2302. For ease of explanation, Figure 23 Only the main components of the communication device 2300 are shown.

[0282] The transceiver module 2301 is used to perform the above. Figure 21 The sending and receiving functions of the method shown are executed by the processing module 2302. Figure 21 The method shown includes functions other than sending and receiving.

[0283] Optionally, the transceiver module 2301 may include a transmitting module. Figure 23 (not shown in the image) and receiving module ( Figure 23 (Not shown in the diagram). The transmitting module implements the transmitting function of the communication device 2300, and the receiving module implements the receiving function of the communication device 2300.

[0284] Optionally, the communication device 2300 may also include a storage module. Figure 23(Not shown in the image), the storage module stores programs or instructions. When the processing module 2302 executes the program or instructions, the communication device 2300 can perform the above-described method. Figure 21 The methods shown describe the functions of the terminal devices and / or network devices.

[0285] It is understood that the communication device 2300 may be a terminal device, or a chip (system) or other component or assembly that can be disposed in a terminal device, or a device that includes a terminal device; or, the communication device 2300 may be a network device, or a chip (system) or other component or assembly that can be disposed in a network device, or a device that includes a network device. The embodiments of this application do not limit this.

[0286] In addition, the technical effects of the communication device 2300 can be referenced. Figure 21 The technical effects of the communication method shown will not be elaborated here.

[0287] For example, Figure 24 Schematic diagram of the communication device provided in the embodiments of this application Figure 2 The communication device can be a terminal device or a network device, or it can be a chip (system) or other component or assembly of the terminal device or network device. For example... Figure 24 As shown, the communication device 2400 may include a processor 2401. Optionally, the communication device 2400 may also include a memory 2402 and / or a transceiver 2403. The processor 2401 is coupled to the memory 2402 and the transceiver 2403, for example, they may be connected via a communication bus.

[0288] The following is combined with Figure 24 A detailed description of each component of the communication device 2400 is provided below:

[0289] The processor 2401 is the control center of the communication device 2400. It can be a single processor or a collective term for multiple processing elements. For example, the processor 2401 can be one or more CPUs, or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application, such as one or more DSPs, or one or more FPGAs.

[0290] Optionally, the processor 2401 can perform various functions of the communication device 2400 by running or executing software programs stored in the memory 2402 and calling data stored in the memory 2402, such as performing the above-mentioned functions. Figure 21 The communication method shown.

[0291] In a specific implementation, as one example, the processor 2401 may include one or more CPUs, for example... Figure 24 CPU0 and CPU1 are shown in the diagram.

[0292] In a specific implementation, as one example, the communication device 2400 may also include multiple processors, for example... Figure 24 The processors 2401 and 2404 are shown. Each of these processors can be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0293] The memory 2402 is used to store the software program that executes the solution of this application, and is controlled by the processor 2401 to execute it. The specific implementation method can be referred to the above method embodiment, and will not be repeated here.

[0294] Optionally, the memory 2402 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 2402 may be integrated with the processor 2401 or exist independently, and may be connected via the interface circuit of the communication device 2400. Figure 24 (Not shown in the image) is coupled to processor 2401, and this embodiment does not specifically limit this.

[0295] Transceiver 2403 is used for communication with other communication devices. For example, if communication device 2400 is a terminal device, transceiver 2403 can be used to communicate with a network device or with another terminal device. As another example, if communication device 2400 is a network device, transceiver 2403 can be used to communicate with a terminal device or with another network device.

[0296] Alternatively, transceiver 2403 may include a receiver and a transmitter. Figure 24 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the sending function.

[0297] Alternatively, the transceiver 2403 can be integrated with the processor 2401, or it can exist independently and be connected via the interface circuit of the communication device 2400. Figure 24 (Not shown in the image) is coupled to processor 2401, and this embodiment does not specifically limit this.

[0298] It should be noted that, Figure 24 The structure of the communication device 2400 shown does not constitute a limitation on the communication device. Actual communication devices may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0299] Furthermore, the technical effects of the communication device 2400 can be referred to the technical effects of the communication method described in the above method embodiments, and will not be repeated here.

[0300] This application provides a communication system. The communication system may include the first device and the second device described in the method embodiments above.

[0301] It should be understood that the processor in the embodiments of this application can be a CPU, but it can also be other general-purpose processors, DSPs, application-specific integrated circuits (ASICs), FPGAs, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0302] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0303] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0304] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0305] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0306] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0307] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0308] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0309] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0310] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0311] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0312] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks. The above descriptions are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An equalization circuit, characterized in that, include: P equalization sub-circuits are connected in parallel on the analog signal transmission line, where P is an integer greater than 1; Each of the P equalization sub-circuits performs amplitude equalization on the first signal to obtain P equalized signals. The center frequencies of any two equalized signals are different, and / or the amplitudes corresponding to the center frequencies are different. The P equalized signals are superimposed and output through the analog signal transmission line.

2. The equalization circuit according to claim 1, characterized in that, Each of the P equalization sub-circuits includes an adjustable resistor unit and an adjustable resonator unit, which are connected in series. The adjustable resistor unit is used to adjust the amplitude of the first signal, and the adjustable resonator unit is used to adjust the frequency of the first signal.

3. The equalization circuit according to claim 2, characterized in that, The adjustable resistor unit includes M fixed resistors connected in parallel, a series-to-parallel converter, and M switches; the M switches correspond one-to-one with the M fixed resistors, the series-to-parallel converter is used to control the M switches, the M switches are used to control the conduction or deactivation of the M fixed resistors, and the conduction or deactivation of the M fixed resistors is related to the resistance value formed by the M fixed resistors, where M is an integer greater than 1.

4. The equalization circuit according to claim 2, characterized in that, The adjustable resistor unit includes a sliding resistor and a mechanical component, the mechanical component being used to adjust the resistance value of the sliding resistor by adjusting the pins of the sliding resistor.

5. The equalization circuit according to claim 4, characterized in that, The mechanical device is a mechanical servo motor.

6. The equalization circuit according to any one of claims 2-5, characterized in that, The adjustable resonator unit includes a variable capacitor, a fixed inductor, and a first digital-to-analog converter (DAC), wherein the variable capacitor and the fixed inductor are connected in series. The variable capacitor is connected to the first DAC, which is used to adjust the capacitance value of the variable capacitor by adjusting the voltage value.

7. The equalization circuit according to claim 6, characterized in that, The variable capacitor is a varactor diode.

8. The equalization circuit according to claim 6 or 7, characterized in that, The adjustable resonator unit also includes a fixed capacitor, which is connected in parallel with the variable capacitor.

9. The equalization circuit according to any one of claims 2-5, characterized in that, The adjustable resonator unit includes a fixed capacitor, N microstrip lines, N-1 diodes, and a second digital-to-analog converter (DAC). The fixed capacitor is connected in series with the N microstrip lines. Two microstrip lines arranged sequentially in the N microstrip lines are connected by one of the N-1 diodes, where N is an integer greater than 1. The N-1 diodes are connected to the second DAC, which is used to control the conduction or deactivation of the N-1 diodes by adjusting the voltage value. The conduction or deactivation of the N-1 diodes is related to the connection length formed by the N microstrip lines.

10. The equalization circuit according to any one of claims 1-9, characterized in that, The frequency range of the first signal is within the first bandwidth. The P equalized signals are superimposed and output through the analog signal transmission line to obtain an equalized signal. The difference between the maximum and minimum amplitude of the equalized signal within the first bandwidth is less than or equal to a first value.

11. A communication method, characterized in that, Applied to a first device, the method includes: Obtain flatness information; wherein the flatness information is used to indicate the amplitude variation of the second signal within a first bandwidth; Based on the flatness information, the first signal is amplitude-equalized by P equalization sub-circuits respectively to obtain P equalized signals; wherein, the frequency range of the first signal is within the first bandwidth, and the center frequencies of any two equalized signals among the P equalized signals are different, and / or the amplitudes corresponding to the center frequencies are different, and P is an integer greater than 1. The P equalized signals are superimposed to obtain an equalized signal; wherein the difference between the maximum and minimum amplitude of the equalized signal within the first bandwidth is less than or equal to a first value.

12. The method according to claim 11, characterized in that, The step of performing amplitude equalization on the first signal using P equalization sub-circuits based on the flatness information to obtain P equalized signals includes: Based on the flatness information, an equalization curve is determined; wherein, the equalization curve is used to determine the hardware parameters of each of the P equalization sub-circuits, and the hardware parameters of any two equalization sub-circuits among the P equalization sub-circuits are different. Based on the hardware parameters of each of the P equalization sub-circuits, the P equalization sub-circuits are controlled to perform amplitude equalization on the first signal respectively, so as to obtain the P equalized signals.

13. The method according to claim 12, characterized in that, The first bandwidth includes X frequency points, and determining the equalization curve based on the flatness information includes: Based on the flatness information, the average amplitude of the second signal at the X frequency points is determined, where X is an integer greater than 1; Based on the average amplitude, X target amplitudes are determined; wherein, the X target amplitudes correspond one-to-one with the X frequency points, and the i-th target amplitude among the X target amplitudes is equal to the difference between the amplitude of the second signal at the i-th frequency point and the average amplitude, where i is an integer greater than 0 and less than or equal to X; The equilibrium curve is determined based on the X target amplitudes.

14. The method according to claim 12 or 13, characterized in that, Before controlling the P equalization sub-circuits to perform amplitude equalization on the first signal according to their respective hardware parameters, the process includes: Based on the hardware parameters of each of the P equalization sub-circuits, P indication messages are sent to the P equalization sub-circuits; wherein, the P indication messages correspond one-to-one with the P equalization sub-circuits, and the j-th indication message in the P indication messages is used to instruct the j-th equalization sub-circuit in the P equalization sub-circuits to use its corresponding hardware parameters to perform amplitude equalization on the first signal, where j is an integer greater than 0 and less than or equal to P.

15. The method according to any one of claims 11-14, characterized in that, The step of performing amplitude equalization on the first signal using P equalization sub-circuits based on the flatness information to obtain P equalized signals includes: Determine whether the flatness information satisfies a first condition; wherein the first condition includes: the amplitude variation range of the second signal within the first bandwidth is greater than a second value; When the flatness information satisfies the first condition, the first signal is amplitude-equalized by P equalization sub-circuits according to the flatness information to obtain the P equalized signals.

16. The method according to any one of claims 11-15, characterized in that, The acquisition of flatness information includes: The second signal is sent to the second device; wherein the second signal is used by the second device to perform flatness measurement; Receive the flatness information from the second device.

17. The method according to claim 16, characterized in that, When the first device is a network device and the second device is a terminal device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; When the first device is the terminal device and the second device is the network device, the second signal is at least one of the following: Uplink Flatness Reference Signal UP-FRS, DMRS, Probe Reference Signal SRS, PT-RS, or Physical Uplink Channel.

18. The method according to any one of claims 11-15, characterized in that, The acquisition of flatness information includes: Receive the second signal from the second device; The flatness of the second signal is measured to obtain the flatness information.

19. The method according to claim 18, characterized in that, When the first device is a terminal device and the second device is a network device, the second signal is at least one of the following: downlink flatness reference signal DL-FRS, synchronization signal and physical broadcast channel block SSB, channel state information reference signal CSI-RS, primary synchronization signal PSS, secondary synchronization signal SSS, demodulation reference signal DMRS, phase tracking reference signal PT-RS, or physical downlink channel; When the first device is the network device and the second device is the terminal device, the second signal is at least one of the following: Uplink Flatness Reference Signal UP-FRS, DMRS, Sounding Reference Signal SRS, PT-RS, or Physical Uplink Channel.

20. A communication device, characterized in that, Includes modules for performing the method as described in any one of claims 11-19.

21. A communication device, characterized in that, include: processor; The processor is configured to run computer programs or instructions to enable the implementation of the method as described in any one of claims 11-19.

22. A communication chip, characterized in that, It stores instructions that, when the chip is running on a communication device, cause the method as described in any one of claims 11-19 to be implemented.

23. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a computer program or instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 11-19.

24. A computer program product, characterized in that, The computer program product includes: a computer program or instructions that, when run on a computer, cause the computer to perform the method as described in any one of claims 11-19.

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