A switching chip scheduling algorithm verification method and related device
By employing an arbitrator to generate port selection signals and an assertion engine to load attribute checking rules in the switching chip, monitoring information is dynamically acquired and verified in conjunction with theoretical throughput. This solves the throughput bottleneck and latency jitter problems of traditional scheduling algorithms in large-scale networks, and improves the accuracy and efficiency of verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU CENTEC COMM CO LTD
- Filing Date
- 2026-03-31
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional switching chip scheduling algorithms are prone to throughput bottlenecks, latency jitter, and starvation issues in large-scale networks and complex traffic scenarios, requiring efficient verification methods to ensure their correctness and efficiency.
An arbitrator is used to generate a port selection signal, dynamically acquire target monitoring information, and combine it with the assertion engine to load attribute check rules. The monitoring information within the time window is used to verify whether it meets the preset conditions, and the theoretical number of selections and throughput are combined to make an accurate judgment.
High-precision scheduling algorithm verification was achieved, which improved the reliability and verification efficiency of chip functions and solved the problems of blindness and inefficiency in traditional scheduling verification.
Smart Images
Figure CN122120160A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communications, and more specifically, to a method and related equipment for verifying a switching chip scheduling algorithm. Background Technology
[0002] Switching chips are core components of data centers, high-performance computing (HPC), and 5G networks, responsible for high-speed data forwarding and traffic scheduling. Their performance directly impacts network throughput, latency, and fairness. Specific scenarios (such as specific load patterns, real-time services, or heterogeneous traffic) require customized scheduling algorithms (such as priority-based scheduling, weighted round-robin scheduling, etc.), but the correctness and efficiency of these algorithms need rigorous verification. As network scale increases and traffic complexity rises (such as traffic bursts and mixed traffic with multiple priorities), traditional scheduling algorithms may face throughput bottlenecks, latency jitter, or starvation issues, requiring targeted optimization and verification. Summary of the Invention
[0003] The purpose of this invention is to provide a method and related equipment for verifying switching chip scheduling algorithms, so as to improve the above-mentioned problems.
[0004] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a method for verifying a switching chip scheduling algorithm, the method comprising: The arbitrator in the target object generates a port selection signal according to the chip register configuration, so as to send the data packets injected into the target object out through the port corresponding to the selection signal; The target object is a simulation model of the switching chip under test, and the chip register configuration includes the constraints for the arbitrator to generate the selection signal. Dynamically acquire target monitoring information of the target object within the current window. The target monitoring information includes the selection signal record generated by the arbitrator, the number of selections corresponding to each port, the throughput corresponding to each port, and the current weight ratio. The assertion engine loads the attribute checking rules that match the current scene, and in each clock cycle within the current window, determines whether the acquired target monitoring information conforms to the attribute checking rules. The current scene is any one or a combination of static weight verification scene, dynamic priority switching scene, and mixed scheduling conflict scene. At the end of the current window, determine whether the current window verification passes based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput for each port within the current window.
[0005] In a second aspect, embodiments of the present invention provide a switching chip scheduling algorithm verification device, the device comprising: The first processing unit is used to generate a port selection signal for the arbitrator in the target object according to the chip register configuration, so as to send the data packet injected into the target object out through the port corresponding to the selection signal. The target object is a simulation model of the switching chip under test, and the chip register configuration includes the constraints for the arbitrator to generate the selection signal. The second processing unit is used to dynamically acquire target monitoring information of the target object in the current window. The target monitoring information includes the selection signal record generated by the arbitrator, the number of selections corresponding to each port, the throughput corresponding to each port, and the current weight ratio. The second processing unit is also used to assert that the engine loads the attribute checking rules that match the current scene, and in each clock cycle within the current window, determine whether the acquired target monitoring information conforms to the attribute checking rules, wherein the current scene is any one or a combination of static weight verification scene, dynamic priority switching scene, and mixed scheduling conflict scene. The second processing unit is also used to determine whether the current window verification passes when the current window ends, based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput of each port within the current window.
[0006] Thirdly, embodiments of the present invention provide a storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.
[0007] Fourthly, embodiments of the present invention provide an electronic device, the electronic device comprising: a processor and a memory, the memory being used to store one or more programs; when the one or more programs are executed by the processor, the above-described method is implemented.
[0008] Compared to existing technologies, the present invention provides a method and related equipment for verifying a switching chip scheduling algorithm. The arbitrator in the target object generates a port selection signal based on the chip register configuration, so that data packets injected into the target object are sent out through the port corresponding to the selection signal. The method dynamically acquires target monitoring information of the target object within the current window. An assertion engine loads attribute checking rules matching the current scenario and determines whether the acquired target monitoring information conforms to the attribute checking rules in each clock cycle within the current window. At the end of the current window, the method determines whether the current window verification passes based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput of each port within the current window. By performing targeted verification on any one or more combinations of static weight verification scenarios, dynamic priority switching scenarios, and mixed scheduling conflict scenarios, embedding an assertion engine for dynamic detection, and combining the theoretical number of selections and theoretical throughput for a comprehensive and accurate judgment at the end of the time window, the method achieves high-precision scheduling algorithm verification, solving the problems of blindness and inefficiency in traditional scheduling verification, and significantly improving chip functional reliability and verification efficiency.
[0009] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.
[0012] Figure 2 This is one of the flowcharts illustrating the verification method for the switching chip scheduling algorithm provided in an embodiment of the present invention.
[0013] Figure 3 This is the second flowchart illustrating the verification method for the switching chip scheduling algorithm provided in this embodiment of the invention.
[0014] Figure 4 This is the third flowchart illustrating the verification method for the switching chip scheduling algorithm provided in this embodiment of the invention.
[0015] Figure 5 This is a schematic diagram of a unit for verifying a switching chip scheduling algorithm provided in an embodiment of the present invention.
[0016] In the diagram: 10-Processor; 11-Memory; 12-Bus; 13-Communication interface; 501-First processing unit; 502-Second processing unit. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0018] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0019] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0020] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0021] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0022] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0023] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0024] This invention provides an electronic device, which may be a computer device, a server device, a mobile phone device, etc. Please refer to... Figure 1 This is a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12. The processor 10 is used to execute executable modules, such as computer programs, stored in the memory 11.
[0025] Processor 10 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the switching chip scheduling algorithm verification method can be completed through integrated logic circuits in the hardware or software instructions within processor 10. The aforementioned processor 10 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0026] The memory 11 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage.
[0027] Bus 12 can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. Figure 1 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus 12 or one type of bus 12.
[0028] The memory 11 is used to store programs, such as the program corresponding to the switching chip scheduling algorithm verification device. The switching chip scheduling algorithm verification device includes at least one software functional module that can be stored in the memory 11 in the form of software or firmware or embedded in the operating system (OS) of the electronic device. After receiving an execution instruction, the processor 10 executes the program to implement the switching chip scheduling algorithm verification method.
[0029] The electronic device provided in this embodiment of the invention may further include a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.
[0030] It should be understood that, Figure 1 The structure shown is only a partial schematic diagram of the electronic device; the electronic device may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.
[0031] The method for verifying a switching chip scheduling algorithm provided in this embodiment of the invention can be applied to, but is not limited to, applications of. Figure 1 For the specific process of the electronic devices shown, please refer to [link / reference]. Figure 2 The verification method for the switching chip scheduling algorithm includes S11, S12, S13 and S14, which are described in detail below.
[0032] S11, the arbitrator in the target object generates a port selection signal according to the chip register configuration, so as to send the data packet injected into the target object out through the port corresponding to the selection signal.
[0033] The target device (DUT) is a simulation model of the switching chip under test. The chip register configuration includes constraints on the arbitrator-generated selection signal. These constraints include scheduling algorithm type, weight allocation, and priority strategy. The selection signal is the signal that selects the port for data transmission in the corresponding clock cycle. Therefore, the constraints are specific to the selection of the target device's port.
[0034] It should be understood that the packet sender can inject traffic into the target object and reference model based on the current scenario and chip register configuration. During traffic injection, injection can be performed according to a preset weight ratio or a preset priority.
[0035] S12, dynamically acquire (meaning that the target object will be acquired in every clock cycle within the current window) the target monitoring information within the current window.
[0036] The target monitoring information includes the selection signal record generated by the arbitrator, the number of selections for each port, the throughput for each port, and the current weight percentage.
[0037] The select signal record includes the time and port object at which the select signal (arbiter_select) is generated.
[0038] Each port corresponds to a queue depth counter (queue_count), which counts the number of times the port was selected up to the statistical clock cycle, i.e., the number of packets sent. The statistical clock cycle belongs to the current window. The throughput for each port refers to the throughput of the port being counted up to the statistical clock cycle. The current weight percentage is the weight percentage of the number of selections for all ports up to the statistical clock cycle, which can be cached using the weight register value (weight_reg).
[0039] Dynamic acquisition refers to acquiring target monitoring information of the target object within the current window in every clock cycle. Optionally, real-time detection can be achieved by capturing signals from the target object using the i_monitor mechanism of the UVM mechanism.
[0040] S13, the assertion engine loads the attribute checking rules that match the current scene, and in each clock cycle within the current window, determines whether the acquired target monitoring information conforms to the attribute checking rules.
[0041] The current scenario is any one or a combination of static weight verification scenario, dynamic priority switching scenario, and mixed scheduling conflict scenario, and the current window refers to the current time window.
[0042] If the assertion succeeds, an assertion success record corresponding to that clock cycle is generated, indicating that the assertion check has been completed in that clock cycle. It should be understood that an assertion needs to be performed in every clock cycle; if the assertion succeeds, the process continues; if it fails, it stops. If the assertion succeeds in every clock cycle, then S14 is executed.
[0043] S14. At the end of the current window, determine whether the current window verification passes based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput of each port within the current window.
[0044] The total number of selections for each port within the current window refers to the number of times a port has been selected up to the last clock cycle of the current window, and the total throughput for each port within the current window refers to the throughput of a port up to the last clock cycle of the current window.
[0045] In the switching chip scheduling algorithm verification method provided in this embodiment of the invention, the verification is carried out by targeting any one or more combinations of static weight verification scenarios, dynamic priority switching scenarios, and mixed scheduling conflict scenarios. An assertion engine is embedded for dynamic detection, and at the end of the time window, a comprehensive and accurate judgment is made by combining the theoretical number of selections and the theoretical throughput. This achieves high-precision scheduling algorithm verification, solves the problems of blindness and inefficiency in traditional scheduling verification, and significantly improves the chip functional reliability and verification efficiency.
[0046] Based on the preceding text, regarding the content in S14, this embodiment of the invention also provides an optional implementation method, please refer to the following: S14, at the end of the current window, based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput of each port within the current window, determine whether the current window verification passes, including: S141, determine the difference in the number of selections based on the total number of port selections and the theoretical number of selections.
[0047] S142, determine the throughput ratio based on the total throughput and theoretical throughput of the port.
[0048] S143, if the difference in the number of times for any port exceeds the number of times threshold, or if the throughput ratio for any port exceeds the ratio range, it is determined that the current window verification has failed.
[0049] The number of times threshold can be, but is not limited to, 1, and the ratio range can be, but is not limited to, 0.95~1.05.
[0050] Conversely, if the difference in the number of times for all ports does not exceed the threshold and the throughput ratio for all ports does not exceed the ratio range, then the current window verification is considered successful.
[0051] Regarding how to determine the theoretical number of selections and the theoretical throughput, this embodiment of the invention also provides an optional implementation method, please refer to the following.
[0052] The reference model transmits the injected data packets through the corresponding ports according to the mathematical constraints therein. The total number of packets sent and the total throughput of each port in the reference model within the current window are obtained. The total number of packets sent by the ports in the reference model within the current window is used as the total number of times the matching ports are selected in the target object. The total throughput of the ports in the reference model within the current window is used as the total throughput of the matching ports in the target object.
[0053] The reference model is the theoretical model corresponding to the set mathematical constraints and chip register configuration. The reference model and the target object have the same traffic injection. Traffic injection refers to injecting data packets into the reference model and the target object. The number of ports in the reference model is the same as the number of ports in the target object. The ports of the reference model and the ports of the target object are matched one-to-one.
[0054] Regarding how to further improve the accuracy of verification results, this embodiment of the invention also provides an optional implementation method, please refer to... Figure 3 The verification method for the switching chip scheduling algorithm also includes S15 and S16, which are described in detail below.
[0055] S15, obtain the time delay jitter of the signal in the target object within the current window, and calculate the corresponding standard deviation; S16, if the standard deviation of the latency jitter is less than the standard deviation threshold, determine that the current window verification has failed.
[0056] The standard deviation threshold can be, but is not limited to, 1 ns.
[0057] Please refer to Figure 4 The verification method for the switching chip scheduling algorithm also includes S21 and S22, which are described in detail below.
[0058] S21, when an assertion fails, log the error context.
[0059] The error context includes the ID of the current window, the target monitoring information captured by the current window, the target monitoring information including the selected signal record, the number of selections for each port, the throughput for each port, and the current weight percentage.
[0060] S22, classify errors and determine error types based on the error context and the attribute checking rules matched to the current scenario.
[0061] Among them, the error types are any one of weight violation, priority-related timing violation, and conflict violation. Weight violation refers to the proportion of selected signals, priority-related timing violation refers to the timing of selected signals not conforming to the requirements of the current scenario, and conflict violation refers to the SP traffic not obtaining the minimum guaranteed bandwidth in the hybrid mode.
[0062] In order to trace the source of errors in the event of failure to verify, this embodiment of the invention also provides an optional implementation method. Please refer to the following: the verification method for the switching chip scheduling algorithm further includes: S23, as detailed below.
[0063] S23, if the verification fails in the current window, extract all signal waveforms of the target object within the current window and mark the defect type according to the reason for the verification failure.
[0064] The defect type is marked according to the reason for the failure of the verification, which facilitates the tracing of the error source.
[0065] In order to obtain the verification progress when the verification is successful, this embodiment of the invention also provides an optional implementation method. Please refer to the following: the switching chip scheduling algorithm verification method further includes: S24, as detailed below.
[0066] S24, if the current window verification passes, update the number of covered items and the coverage rate corresponding to the current scene, where the coverage rate is the ratio of the number of covered items to the total number of items that need to be covered.
[0067] It should be understood that if the current window verification passes and the current scenario verification is completed, the scenario type can be changed. In this case, the switching chip scheduling algorithm verification method also includes: S31, which is described in detail below.
[0068] S31, when the type of the current scene is different from the type of the previous scene, adjust the length of the time window.
[0069] Optionally, the time window length (1µs~10ms) can be adjusted according to the complexity of the scenario. For example, if a complex scenario (such as mixed conflicts) is detected, the window duration is automatically extended; if the scenario is simple (such as static weights), the window is shortened to improve efficiency. A shorter window duration allows test results to be obtained faster, thus improving efficiency.
[0070] This paper innovatively proposes a new method and system for verifying the scheduling of switching chips. It innovatively employs a time window segmentation statistical method, achieving intelligent segmentation of simulation time through a dynamically adjustable time window mechanism. Combined with a scenario-driven SVA assertion engine (static weight / dynamic priority / hybrid conflict hierarchical verification) and a uvm i_monitor signal probe (real-time capture of the arbitrator's internal state), a three-dimensional verification system of "time window division - scenario-based assertion checking - reference model comparison" is constructed. The dynamic window scheduling algorithm, the dynamic binding method between scenarios and assertion rules, and the collaborative analysis architecture of the signal probe and the reference model solve the technical challenges of traditional verification techniques in accurately locating instantaneous scheduling errors and verifying the microscopic behavior of scheduling algorithms. This effectively avoids the risk of chip fabrication failure due to scheduling logic errors.
[0071] Please see Figure 5 , Figure 5 The present invention provides a switching chip scheduling algorithm verification device, which is optionally applied to the electronic device described above.
[0072] The switching chip scheduling algorithm verification device includes: a first processing unit 501 and a second processing unit 502.
[0073] The first processing unit 501 is used to generate a port selection signal for the arbitrator in the target object according to the chip register configuration, so as to send the data packet injected into the target object out through the port corresponding to the selection signal. The target object is a simulation model of the switching chip under test, and the chip register configuration includes the constraints for the arbitrator to generate the selection signal. The second processing unit 502 is used to dynamically acquire target monitoring information of the target object in the current window. The target monitoring information includes the selection signal record generated by the arbitrator, the number of selections corresponding to each port, the throughput corresponding to each port, and the current weight ratio. The second processing unit 502 is also used to assert that the engine loads the attribute checking rules that match the current scene, and in each clock cycle within the current window, determine whether the acquired target monitoring information meets the attribute checking rules, wherein the current scene is any one or a combination of static weight verification scene, dynamic priority switching scene, and mixed scheduling conflict scene. The second processing unit 502 is also used to determine whether the current window verification passes when the current window ends, based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput of each port within the current window.
[0074] The first processing unit 501 can execute S11 as described above, and the second processing unit 502 can execute other steps in the above method embodiment.
[0075] It should be noted that the switching chip scheduling algorithm verification device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effect. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.
[0076] This invention also provides a storage medium storing computer instructions and programs, which, when read and executed, perform the switching chip scheduling algorithm verification method described in the above embodiments. The storage medium may include memory, flash memory, registers, or a combination thereof.
[0077] The following provides an electronic device, which may be a computer device, a server device, a mobile phone device, etc., such as... Figure 1 As shown, the above-described switching chip scheduling algorithm verification method can be implemented. Specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 may be a CPU. The memory 11 is used to store one or more programs, and when one or more programs are executed by the processor 10, the switching chip scheduling algorithm verification method of the above embodiment is executed.
[0078] In summary, the present invention provides a method and related equipment for verifying a switching chip scheduling algorithm. The arbitrator in the target object generates a port selection signal based on the chip register configuration to transmit data packets injected into the target object through the port corresponding to the selection signal. The method dynamically acquires target monitoring information of the target object within the current window. An assertion engine loads attribute checking rules matching the current scenario and determines whether the acquired target monitoring information conforms to the attribute checking rules at each clock cycle within the current window. At the end of the current window, the method determines whether the current window verification passes based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput of each port within the current window. By performing targeted verification on any combination of static weight verification scenarios, dynamic priority switching scenarios, and mixed scheduling conflict scenarios, embedding an assertion engine for dynamic detection, and combining the theoretical number of selections and theoretical throughput for a comprehensive and accurate judgment at the end of the time window, high-precision scheduling algorithm verification is achieved. This solves the problems of blindness and inefficiency in traditional scheduling verification, significantly improving chip functional reliability and verification efficiency.
[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
[0080] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. A method for verifying a switching chip scheduling algorithm, characterized in that, The method includes: The arbitrator in the target object generates a port selection signal according to the chip register configuration, so as to send the data packets injected into the target object out through the port corresponding to the selection signal; The target object is a simulation model of the switching chip under test, and the chip register configuration includes the constraints for the arbitrator to generate the selection signal. Dynamically acquire target monitoring information of the target object within the current window. The target monitoring information includes the selection signal record generated by the arbitrator, the number of selections corresponding to each port, the throughput corresponding to each port, and the current weight ratio. The assertion engine loads the attribute checking rules that match the current scene, and in each clock cycle within the current window, determines whether the acquired target monitoring information conforms to the attribute checking rules. The current scene is any one or a combination of static weight verification scene, dynamic priority switching scene, and mixed scheduling conflict scene. At the end of the current window, determine whether the current window verification passes based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput for each port within the current window.
2. The method for verifying the switching chip scheduling algorithm as described in claim 1, characterized in that, The step of determining whether the current window verification passes based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput of each port within the current window includes: Determine the difference in the number of selections based on the total number of port selections and the theoretical number of selections; Determine the throughput ratio based on the port's total throughput and theoretical throughput; If the difference in the number of attempts on any port exceeds the threshold, or if the throughput ratio on any port exceeds the ratio range, the current window verification is determined to have failed.
3. The method for verifying the switching chip scheduling algorithm as described in claim 1, characterized in that, The method further includes: Obtain the time delay jitter of the signal in the target object within the current window and calculate the corresponding standard deviation; If the standard deviation of latency jitter is less than the standard deviation threshold, the current window is determined to have failed verification.
4. The method for verifying the switching chip scheduling algorithm as described in any one of claims 1-3, characterized in that, The method further includes: If the verification fails in the current window, extract all signal waveforms of the target object within the current window and mark the defect type according to the reason for the verification failure.
5. The method for verifying the switching chip scheduling algorithm as described in any one of claims 1-3, characterized in that, The method further includes: If the current window passes verification, update the number of covered elements and the coverage rate for the current scene, where the coverage rate is the ratio of the number of covered elements to the total number of elements that need to be covered.
6. The method for verifying the switching chip scheduling algorithm as described in claim 1, characterized in that, The method further includes: When an assertion fails, an error context is recorded, which includes the ID of the current window and the target monitoring information captured by the current window. Errors are classified according to the error context and the attribute inspection rules matched to the current scene to determine the error type, which is weight violation, priority-related timing violation, and conflict violation.
7. The method for verifying the switching chip scheduling algorithm as described in claim 1, characterized in that, The method further includes: Adjust the time window length when the type of the current scene is different from the type of the previous scene.
8. A device for verifying a switching chip scheduling algorithm, characterized in that, The device includes: The first processing unit is used to generate a port selection signal for the arbitrator in the target object according to the chip register configuration, so as to send the data packet injected into the target object out through the port corresponding to the selection signal. The target object is a simulation model of the switching chip under test, and the chip register configuration includes the constraints for the arbitrator to generate the selection signal. The second processing unit is used to dynamically acquire target monitoring information of the target object in the current window. The target monitoring information includes the selection signal record generated by the arbitrator, the number of selections corresponding to each port, the throughput corresponding to each port, and the current weight ratio. The second processing unit is also used to assert that the engine loads the attribute checking rules that match the current scene, and in each clock cycle within the current window, determine whether the acquired target monitoring information conforms to the attribute checking rules, wherein the current scene is any one or a combination of static weight verification scene, dynamic priority switching scene, and mixed scheduling conflict scene. The second processing unit is also used to determine whether the current window verification passes when the current window ends, based on the total number of selections, total throughput, theoretical number of selections, and theoretical throughput of each port within the current window.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method as described in any one of claims 1-7.
10. An electronic device, characterized in that, include: Processor and memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method as described in any one of claims 1-7 is implemented.