imaging device

Abstract

Provided is an imaging device capable of appropriately determining whether or not a pixel is saturated. An imaging device includes: a pixel that stores a charge corresponding to the intensity of received light; a lamp voltage generator that generates a lamp voltage; a saturation determination voltage generator that generates a saturation determination voltage based on the lamp voltage; and an analog / digital conversion section that analog / digital converts an analog signal representing the amount of the charge into a digital signal using the lamp voltage, and determines whether or not the pixel is saturated based on the comparison result of the voltage of the analog signal and the saturation determination voltage.

Description

Technical Field

[0001] This disclosure relates to a photographing device. Background Technology

[0002] Japanese Patent Application Publication No. 2022-82642 discloses an imaging device. In this imaging device, a pixel outputs a potential for first image data. A circuit adds the potential of the output first image data to a reference potential to supply a potential signal. The circuit compares the signal potential of the supplied potential signal with the reference potential to determine whether the pixel node is saturated. The reference potential is a specific potential corresponding to the point at which the pixel node is saturated.

[0003] If the node is determined to be unsaturated, the circuit compares the signal potential with the ramp wave and outputs the result to the counter circuit. The counter circuit outputs digital data (segments 0053, 0057, 0060, 0062, and 0063) corresponding to the first captured data. Summary of the Invention

[0004] The technical problem to be solved by the present invention In the imaging device disclosed in Japanese Patent Application Publication No. 2022-82642, the reference potential used to determine whether a pixel node is saturated is a fixed potential. Therefore, the reference potential does not change even when the slope of the ramp wave changes. Consequently, if the slope of the ramp wave changes, it may be impossible to properly determine whether a pixel node is saturated.

[0005] This disclosure was made in view of the aforementioned problems. An object of this disclosure is, for example, to provide an imaging device capable of appropriately determining whether pixels are saturated.

[0006] Technical solutions for solving technical problems An imaging apparatus according to one aspect of this disclosure includes: a pixel storing a charge corresponding to the intensity of received light; a lamp voltage generator generating a lamp voltage; a saturation determination voltage generator generating a saturation determination voltage based on the lamp voltage; and an analog-to-digital converter converting an analog signal representing the amount of charge into a digital signal using the lamp voltage, and determining whether the pixel is saturated based on a comparison between the voltage of the analog signal and the saturation determination voltage. Attached Figure Description

[0007] Figure 1 This is a block diagram of the imaging device according to the first embodiment.

[0008] Figure 2 It is a graph showing the waveforms of the pixel signal voltage, lamp voltage, and saturation determination voltage input to the analog-to-digital converter of the imaging device in the first embodiment.

[0009] Figure 3 This is a timing diagram showing the waveforms of the lamp voltage and saturation determination voltage input to the analog-to-digital converter of the imaging device in the first embodiment.

[0010] Figure 4 This is a circuit diagram of the saturation determination voltage generator included in the imaging device of the first embodiment. Detailed Implementation

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Furthermore, in the accompanying drawings, the same or equivalent elements will be labeled with the same reference numerals, and repeated descriptions will be omitted.

[0012] 1 First Implementation Method 1.1 Filming Equipment Figure 1 This is a block diagram of the image processing apparatus according to the first embodiment.

[0013] Figure 1 The imaging device 1 of the first embodiment shown captures an image and outputs an image signal corresponding to the captured image. The imaging device 1 is a solid-state imaging device. This solid-state imaging device is a complementary metal-oxide-semiconductor (CMOS) image sensor. The techniques described below can be used in imaging devices other than CMOS image sensors.

[0014] like Figure 1 As shown, the imaging device 1 includes a pixel unit 101, a vertical scanning circuit 102, a lamp voltage generator 103, a saturation determination voltage generator 104, an analog-to-digital converter 105, and a controller 106.

[0015] like Figure 1 As shown, the pixel unit 101 has m×n pixels 111, m row selection lines 112, and n vertical signal lines 113. m and n are integers of 2 or more.

[0016] The m×n pixels 111 are arranged in a matrix. Therefore, the m×n pixels 111 form an m x n pixel array. Thus, the m×n pixels 111 have m rows 121 and n columns 122. The n pixels 111 belong to each row 121 contained in the m rows 121. The m pixels 111 belong to each column 122 contained in the n columns 122. Each pixel 111 in the m×n pixels 111 has a photodiode. The photodiode receives light, generates a signal charge corresponding to the intensity of the received light, and stores the generated signal charge. There is an upper limit to the amount of signal charge that a photodiode can store. When a row selection pulse is provided to each pixel 111, each pixel 111 discharges the stored signal charge.

[0017] Each of the m row selection lines 112 corresponds to one of the m rows 121. Each row selection line 112 is electrically connected to the vertical scanning circuit 102, and each row selection line 112 is electrically connected to the n pixels 111 belonging to its corresponding row 121. Therefore, each row selection line 112 transmits the row selection pulse 131 output by the vertical scanning circuit 102 from the vertical scanning circuit 102 to the n pixels 111, and provides the transmitted row selection pulse 131 to the n pixels 111.

[0018] n vertical signal lines 113 correspond to n columns 122. Each vertical signal line 113 is electrically connected to m pixels 111 belonging to the corresponding column 122 and to the analog-to-digital converter 105. Therefore, each vertical signal line 113 transmits an analog signal 132, representing the amount of signal charge discharged due to the pixels 111 contained in the m pixels 111, from the pixel 111 to the analog-to-digital converter 105, and provides the transmitted analog signal 132 to the analog-to-digital converter 105. The provided analog signal 132 has a voltage corresponding to the intensity of the light received by the pixel 111. The greater the intensity of the light received by the pixel 111, the lower the voltage of the analog signal 132. The greater the intensity of the light received by the pixel 111, the greater the absolute value of the voltage of the analog signal 132.

[0019] The vertical scanning circuit 102 scans the pixel section 101 in the vertical direction. The vertical scanning circuit 102 selects one row selection line 112 from the m row selection lines 112 and transmits a row selection pulse 131 to the selected row selection line 112. The vertical scanning circuit 102 sequentially changes the selected row selection line 112.

[0020] Therefore, the pixel unit 101 and the vertical scanning circuit 102 provide n analog signals 132, representing the amount of signal charge output by n pixels 111 selected from m rows 121 belonging to one row 121, to the analog-to-digital converter 105. The pixel unit 101 and the vertical scanning circuit 102 sequentially change the selected row 121. Therefore, the pixel unit 101 and the vertical scanning circuit 102 provide m×n analog signals, representing the amount of signal charge output by m×n pixels 111, to the analog-to-digital converter 105.

[0021] Lamp voltage generator 103 generates lamp voltage 133 and outputs the generated lamp voltage 133. The output lamp voltage 133 becomes the reference voltage used for analog-to-digital conversion of analog signal 132 to digital signal 135.

[0022] The saturation determination voltage generator 104 generates a saturation determination voltage 134 and outputs the generated saturation determination voltage 134. The output saturation determination voltage 134 serves as a reference voltage for determining whether pixel 111 is saturated.

[0023] The analog-to-digital converter 105 converts each of the n analog signals 132 given by the output lamp voltage 133 into a digital signal 135 and outputs the digital signal 135. The lower the voltage of each analog signal 132, the larger the grayscale value represented by the output digital signal 135; the larger the absolute value of the voltage of the analog signal 132, the larger the grayscale value.

[0024] The analog-to-digital converter 105 determines whether the pixel 111 that outputs each analog signal 132 is saturated based on the comparison result between the given analog signals 132 and the output saturation determination voltage 134. Pixel 111 saturation means that even if the intensity of light received by pixel 111 increases, the amount of signal charge stored in pixel 111 will not increase, and even if the intensity of light received by pixel 111 increases, the gray value represented by the digital signal 135 will not increase.

[0025] If the voltage of the analog signal 132 output by pixel 111 is lower than the lower limit of the voltage range for analog-to-digital conversion determined by the lamp voltage 133, the grayscale value represented by the digital signal 135 will not increase even if the intensity of the light received by pixel 111 increases. Therefore, the lamp voltage 133 must be considered in determining whether pixel 111 is saturated. However, if the lamp voltage 133 is not considered and the saturation determination voltage 134 remains constant, two types of misjudgments may occur even if the lamp voltage 133 changes but the saturation determination voltage 134 does not change: it is possible to misjudge that pixel 111 is saturated even though it is not actually saturated; or it is possible to misjudge that pixel 111 is not saturated even though it is actually saturated. Therefore, in the imaging device 1, the saturation determination voltage generator 104 generates the saturation determination voltage 134 based on the lamp voltage 133. The saturation determination voltage generator 104 increases the saturation determination voltage 134 when the lower limit of the voltage range in which analog-to-digital conversion can be performed increases, and decreases the saturation determination voltage 134 when the lower limit of the voltage range in which analog-to-digital conversion can be performed decreases.

[0026] The analog signal 132 output from the pixel unit 101 is processed, and the processed analog signal can also be provided to the analog-to-digital converter 105. The processed analog signal also represents the amount of signal charge discharged by the pixel 111.

[0027] The controller 106 controls the pixel unit 101, vertical scanning circuit 102, lamp voltage generator 103, saturation determination voltage generator 104, and analog-to-digital converter 105, and performs the following processing on the pixel unit 101, vertical scanning circuit 102, lamp voltage generator 103, saturation determination voltage generator 104, and analog-to-digital converter 105. The controller 106 is composed of electronic circuitry.

[0028] When pixel 111 is saturated, even if the light intensity received by pixel 111 increases, the grayscale value represented by digital signal 135 will not increase. Therefore, when pixel 111 is saturated, grayscale cannot be represented by digital signal 135. Therefore, when pixel 111 is saturated, the following countermeasures are taken: expanding the grayscale representation range using high dynamic range (HDR) technology; changing the conditions for accumulating signal charge so that the grayscale value represented by digital signal 135 is within the grayscale representation range; resetting the photodiode of pixel 111 and allowing the photodiode to continue accumulating signal charge, etc. If the determination of whether pixel 111 is saturated is a misjudgment, it is impossible to properly determine whether this measure is necessary and when to take it, and grayscale cannot be represented correctly. Therefore, it is desirable to suppress this misjudgment. By generating a saturation determination voltage 134 based on lamp voltage 133 and making the saturation determination voltage 134 follow lamp voltage 133, this misjudgment can be suppressed, and it is possible to properly determine whether pixel 111 is saturated.

[0029] 1.2 Analog / Digital Conversion Unit like Figure 1 As shown, the analog-to-digital converter 105 includes a lamp voltage transmission line 141, a saturation determination voltage transmission line 142, n switching circuits 143, n comparators 144, n latch counters 145, and a scan transmission circuit 146. Each of the n switching circuits 143 includes a first input terminal 143a, a second input terminal 143b, and an output terminal 143c. Each of the n comparators 144 includes a non-inverting input terminal 144a, an inverting input terminal 144b, and an output terminal 144c.

[0030] The lamp voltage transmission line 141 is electrically connected to the lamp voltage generator 103 and to the first input terminal 143a of the n switching circuits 143. Therefore, the lamp voltage transmission line 141 transmits the lamp voltage 133 output by the lamp voltage generator 103 from the lamp voltage generator 103 to the first input terminal 143a of the n switching circuits 143, and inputs the transmitted lamp voltage 133 to the first input terminal 143a of the n switching circuits 143.

[0031] The saturation determination voltage transmission line 142 is electrically connected to the saturation determination voltage generator 104 and to the second input terminal 143b of the n switching circuits 143. Therefore, the saturation determination voltage transmission line 142 transmits the saturation determination voltage 134 output by the saturation determination voltage generator 104 from the saturation determination voltage generator 104 to the second input terminal 143b of the n switching circuits 143, and inputs the transmitted saturation determination voltage 134 to the second input terminal 143b of the n switching circuits 143.

[0032] Each switching circuit 143 switches the connection destination of its output terminal 143c between its first input terminal 143a and its second input terminal 143b. Thus, each switching circuit 143 switches the voltage output from its output terminal 143c between the lamp voltage 133 and the saturation determination voltage 134.

[0033] n comparators 144 correspond to n vertical signal lines 113, and each corresponds to one of n switching circuits 143. The non-inverting input terminal 144a of each comparator 144 is electrically connected to the corresponding vertical signal line 113. Thus, the non-inverting input terminal 144a of each comparator 144 receives an analog signal 132 provided by the corresponding vertical signal line 113. The inverting input terminal 144b of each comparator 144 is electrically connected to the output terminal 143c of the corresponding switching circuit 143. Thus, the lamp voltage 133 or saturation determination voltage 134 output from the output terminal 143c of each switching circuit 143 is input to the inverting input terminal 144b of each comparator 144.

[0034] Each comparator 144 sets the voltage output from its output terminal 144c to a voltage corresponding to the comparison result, which is the comparison result of the voltage input to the non-inverting input terminal 144a of each comparator 144 and the voltage input to the inverting input terminal 144b of each comparator 144. For example, if the voltage input to the non-inverting input terminal 144a of each comparator 144 is higher than the voltage input to the inverting input terminal 144b of each comparator 144, each comparator 144 sets the voltage output from its output terminal 144c to a relatively high voltage VH; if the voltage input to the non-inverting input terminal 144a of each comparator 144 is lower than the voltage input to the inverting input terminal 144b of each comparator 144, each comparator 144 sets the voltage output from its output terminal 144c to a relatively low voltage VL. Therefore, when a lamp voltage 133 is input to the inverting input terminal 144b of each comparator 144, the voltage output from the output terminal 144c of each comparator 144 is set to the voltage corresponding to the comparison result between the voltage of the analog signal 132 transmitted by the vertical signal line 113 corresponding to each comparator 144 and the input lamp voltage 133. When a saturation determination voltage 134 is input to the inverting input terminal 144b of each comparator 144, the voltage output from the output terminal 144c of each comparator 144 is set to the voltage corresponding to the comparison result between the voltage of the analog signal 132 transmitted by the vertical signal line 113 corresponding to each comparator 144 and the input saturation determination voltage 134.

[0035] The n latch counters 145 correspond to the n comparators 144. Each latch counter 145 is electrically connected to the output terminal 144c of the comparator 144 corresponding to it. Thus, each latch counter 145 is input with the voltage output from the output terminal 144c of the corresponding comparator 144.

[0036] Each latch counter 145 counts the number of clock cycles. When the comparison result, represented by the input voltage, changes, the latch counter latches the counted number of clock cycles and outputs a digital signal 135 corresponding to the latched number of clock cycles. For example, each latch counter 145 latches the number of clock cycles as the input voltage changes from a relatively high voltage VH to a relatively low voltage VL, and outputs a digital circuit 135 representing a grayscale value corresponding to the latched number of clock cycles. The latched number of clock cycles corresponds to the voltage of the analog signal 132 input to the non-inverting input terminal 144a of the comparator 144 corresponding to each latch counter 145. Therefore, the grayscale value represented by the output digital signal 135 is the grayscale value corresponding to the voltage of the analog signal 132 input to the non-inverting input terminal 144a of the comparator 144 corresponding to each latch counter 145. Therefore, the n latch counters 145 respectively output n digital signals 135 corresponding to the voltages of the n analog signals 132 input to the non-inverting input terminals 144a of the n comparators 144.

[0037] The scan transmission circuit 146 is electrically connected to n latch counters 145. Thus, n digital signals 135 output from the n latch counters 145 are input to the scan transmission circuit 146. The scan transmission circuit 146 scans the n latch counters 145. The scan transmission circuit 146 selects one latch counter 145 from the n latch counters 145 and transmits the digital signal 135 output by the selected latch counter 145. The scan transmission circuit 146 sequentially changes the selected latch counter 145. The transmitted digital signal 135 constitutes an image signal.

[0038] 1.3 Waveforms of pixel signal voltage, lamp voltage, and saturation determination voltage Figure 2 This is a graph showing the waveforms of the pixel signal voltage, lamp voltage, and saturation determination voltage input to the analog-to-digital converter of the imaging device in the first embodiment. Figure 2 In the curve graph, the horizontal axis represents time and the vertical axis represents voltage.

[0039] During the reading operation of a line, the imaging device 1 reads n analog signals 132 from n pixels 111 of a line 121 selected from m lines 121, converts the n analog signals 132 into n digital signals 135, and outputs the n digital signals 135.

[0040] like Figure 2 As shown, the reading operation 151 includes a reset period 161, a saturation determination period 162, an analog-to-digital conversion period 163, a sampling period 164, and a signal processing period 165.

[0041] (During reset) During reset period 161, the vertical scan circuit 102 resets the pixel 111 belonging to one row 121 selected from m rows 121. The reset pixel 111 discharges signal charge after discharging noise charge. Therefore, the voltage 181 of the pixel signal output through pixel 111 decreases to a voltage VN corresponding to the amount of noise charge discharged, and then decreases to a voltage VS corresponding to the amount of signal charge discharged. Therefore, the pixel signal includes an analog signal 132 having a voltage VS corresponding to the amount of signal charge discharged.

[0042] During the reset period 161, the lamp voltage generator 103 maintains the lamp voltage 133.

[0043] During the reset period 161, the saturation determination voltage generator 104 maintains a constant voltage 192 after sampling during the sampling period 164 included in the previous line read operation period 151, and generates a saturation determination voltage 134 corresponding to the maintained constant voltage 192.

[0044] (During saturation determination period) During the saturation determination period 162 following the reset period 161, the switching circuit 143 uses the connection object electrically connected to the output terminal 143c of the switching circuit 143 as the second input terminal 143b of each switching circuit 143. As a result, the saturation determination voltage 134 is input to the inverting input terminal 144b of each comparator 144. When the pixel signal is a non-saturated signal (as shown by the solid line) and the voltage VS of the analog signal 132 is higher than the saturation determination voltage 134, each comparator 144 sets the voltage output from its output terminal 144c to a relatively high voltage VH. When the pixel signal is a saturated signal (as shown by the dashed line) and the voltage VS of the analog signal is lower than the saturation determination voltage 134, each comparator 144 sets the voltage output from its output terminal 144c to a relatively low voltage VL.

[0045] During the saturation judgment period 162, the lamp voltage generator 103 uses the lamp voltage 133 as the starting voltage V1.

[0046] During the saturation determination period 162, the saturation determination voltage generator 104 maintains a constant voltage 192 after sampling during the sampling period 164 included in the previous line read operation period 151, and generates a saturation determination voltage 134 corresponding to the maintained constant voltage 192.

[0047] (During analog / digital conversion) During the analog-to-digital conversion period 163 following the saturation judgment period 162, the switching circuit 143 uses the connection object electrically connected to its output terminal 143c as the first input terminal 143a of each switching circuit 143. Consequently, the lamp voltage 133 is input to the inverting input terminal 144b of each comparator 144. When the voltage 182 of the analog signal 132 is higher than the lamp voltage 133, each comparator 144 sets the voltage output from its output terminal 144c to a relatively high voltage VH; when the voltage of the analog signal 132 is lower than the lamp voltage 133, each comparator 144 sets the voltage output from its output terminal 144c to a relatively low voltage VL.

[0048] During the analog-to-digital conversion 163, the lamp voltage generator 103 reduces the lamp voltage 133 from a starting voltage V1 to an ending voltage V2 at a fixed voltage value change rate over time. Therefore, the lamp voltage 133 includes a ramp voltage 191 with a fixed voltage value change rate over time. The starting voltage V1 is higher than the voltage VN corresponding to the amount of noise charge discharged. The ending voltage V2 is lower than the saturation determination voltage 134. Therefore, as shown by the solid line, when the pixel signal is a non-saturated signal, the ramp voltage 191 and the voltage 182 of the analog signal 132 reverse their high and low values ​​during the analog-to-digital conversion 163. However, as shown by the dashed line, when the pixel signal is a saturated signal, there is a possibility that the ramp voltage 191 and the voltage 182 of the analog signal 132 may not reverse their high and low values ​​during the analog-to-digital conversion 163.

[0049] During the analog-to-digital conversion 163, the latch counter 145 synchronously starts counting the number of clock cycles as the lamp voltage 133 drops from the starting voltage V1 to the ending voltage V2. When the ramp voltage 191 and the voltage 182 of the analog signal 132 flip, causing the voltage at the output terminal 144c of each comparator 144 to jump from high level VH to low level VL, the clock count value at this moment is synchronously latched, and the corresponding digital signal 135 is output. In the case of converting the analog signal 132 into the digital signal 135 at the moment TM of the high-low reversal of the ramp voltage 191 and the voltage 182 of the analog signal 132, the larger the absolute value of the time change rate of the ramp voltage 191, the lower the ending voltage V2, and the lower the lower limit of the voltage range R that can be used for analog-to-digital conversion.

[0050] During the analog-to-digital conversion period 163, the saturation determination voltage generator 104 maintains a constant voltage 192 after sampling during the sampling period 164 included in the previous line read operation period 151, and generates a saturation determination voltage 134 corresponding to the maintained constant voltage 192.

[0051] When the saturation determination voltage 134 is changed according to the change in the voltage value of ramp voltage 191 over time, it is possible to suppress the misjudgment of whether pixel 111 is saturated because the lower limit of the voltage range R that can be performed for analog / digital conversion is lower when the absolute value of the voltage value of ramp voltage 191 over time is larger.

[0052] (During sampling) During sampling period 164 immediately following analog / digital conversion period 163, lamp voltage generator 103 makes lamp voltage 133 a constant voltage 192 with a constant voltage value. Therefore, lamp voltage 133 includes a constant voltage 192 with a certain voltage value. The constant voltage value of constant voltage 192 is the same as the voltage value of the termination voltage V2. Lamp voltage generator 103 then generates constant voltage 192 using ramp voltage 191. As described above, the greater the absolute value of the time-varying rate of change of the voltage value of ramp voltage 191, the lower the termination voltage V2. Therefore, the greater the absolute value of the time-varying rate of change of the voltage value of ramp voltage 191, the lower the constant voltage 192 with the same constant voltage value as the termination voltage V2.

[0053] During sampling period 164, the saturation determination voltage generator 104 samples the constant voltage 192 and generates a saturation determination voltage 134 based on the sampled constant voltage 192. The generated saturation determination voltage 134 is the voltage corresponding to the sampled constant voltage 192. For example, the saturation determination voltage 134 is generated by amplifying or shifting the sampled constant voltage 192. As described above, the constant voltage 192, which forms the basis for generating the saturation determination voltage 134, decreases as the absolute value of the rate of change of the ramp voltage 191 over time increases. Therefore, the larger the absolute value of the rate of change of the ramp voltage 191 over time, the lower the saturation determination voltage 134.

[0054] (During signal processing) During signal processing 165 immediately following sampling 164, scan transmission circuit 146 selects one latch counter 145 from n latch counters 145 and transmits the digital signal output by the selected latch counter 145. Scan transmission circuit 146 sequentially changes the selected latch counter 145.

[0055] During signal processing 165, after the lamp voltage generator 103 increases the lamp voltage 133, it maintains the lamp voltage 133.

[0056] During signal processing 165, the saturation determination voltage generator 104 maintains the constant voltage 192 sampled during sampling 164 and generates a saturation determination voltage 134 corresponding to the maintained constant voltage 192.

[0057] 1.4 Relationship between lamp voltage and saturation threshold voltage Figure 3This is a timing diagram showing the waveforms of the lamp voltage and saturation determination voltage input to the analog-to-digital converter of the imaging device in the first embodiment. Figure 3 In the timing diagram, the horizontal axis represents time, and the vertical axis represents voltage.

[0058] The rate of change of the voltage value of ramp voltage 191 over time changes. Therefore, as... Figure 3 As shown, the ramp voltage 191 can be a first ramp voltage 211 with a first voltage value time change rate, a second ramp voltage 212 with a second voltage value time change rate that is more rapid than the first voltage value time change rate, a third ramp voltage 213 with a third voltage value time change rate that is more rapid than the second voltage value time change rate, and so on. Therefore, the constant voltage 192 generated and sampled after the ramp voltage 191 can be a first constant voltage 221, a second constant voltage 222 lower than the first constant voltage 221, a third constant voltage 223 lower than the second constant voltage 222, and so on. When the constant voltage 192 changes to the first constant voltage 221, the second constant voltage 222, the third constant voltage 223, etc., the saturation determination voltage 134 is respectively the first saturation determination voltage 231, the second saturation determination voltage 232 which is lower than the first saturation determination voltage 231, and the third saturation determination voltage 233 which is lower than the second saturation determination voltage 232, so that even when the ramp voltage 191 becomes the first ramp voltage 211, the second ramp voltage 212, the third ramp voltage 213, etc., the pixel 111 can be appropriately determined to be saturated.

[0059] 1.5 Waveforms of analog signals, lamp voltages, and saturation detection voltages Figure 4 This is a circuit diagram of the saturation determination voltage generator included in the imaging device of the first embodiment.

[0060] Figure 4 The saturation determination voltage generator 104 shown samples the input constant voltage 192, maintains the sampled constant voltage 192, shifts the maintained constant voltage 192 to generate a saturation determination voltage 134, and outputs the generated saturation determination voltage 134.

[0061] The saturation determination voltage generator 104 has an input terminal 241, a switch 242, a capacitor 243, an operational amplifier 244, a voltage source 245, and an output terminal 246. The switch 242 has one terminal 242a and another terminal 242b. The capacitor 243 has one terminal 243a and another terminal 243b. The operational amplifier 244 has a non-inverting input terminal 244a, an inverting input terminal 244b, and an output terminal 244c. The voltage source 245 has a positive terminal 245a and a negative terminal 245b.

[0062] Input terminal 241 is electrically connected to lamp voltage generator 103. One terminal 242a of switch 242 is electrically connected to input terminal 241. One terminal 243a of capacitor 243 and the non-inverting input terminal 244a of operational amplifier 244 are electrically connected to the other terminal 242b of switch 242. The other terminal 243b of capacitor 243 is grounded.

[0063] Switch 242 in Figure 2 The sampling period shown is 164 closed, in Figure 2 The holding period 171 shown is open. The holding period 171 is a period other than the sampling period 164. Thus, during the sampling period 164, the terminal 242b of the other side of switch 242 is connected to the terminal 242a of one side of switch 242, and the constant voltage 192 is applied to the terminal 243a of one side of capacitor 243 via the input terminal 241 and switch 242, and a charge with an amount corresponding to the constant voltage 192 is stored in capacitor 243.

[0064] During the holding period 171, the other terminal 242b of switch 242 is not connected to one terminal 242a of switch 242. A voltage corresponding to the amount of charge stored in capacitor 243 is generated at one terminal 243a of capacitor 243. The generated voltage is input to the non-inverting input terminal 244a of operational amplifier 244. The voltage generated at one terminal 243a of capacitor 243 and input to the non-inverting input terminal 244a of operational amplifier 244 is consistent with constant voltage 192.

[0065] The negative terminal 245b of voltage source 245 is electrically connected to the inverting input terminal 244b of operational amplifier 244. The positive terminal 245a of voltage source 245 is electrically connected to the output terminal 244c of operational amplifier 244. Output terminal 246 is electrically connected to both the output terminal 244c of operational amplifier 244 and the positive terminal 245a of voltage source 245. Therefore, the voltage output from the output terminal 244c of operational amplifier 244 becomes a voltage obtained by adding the voltage generated by voltage source 245 to the constant voltage 192 input to the non-inverting input terminal 244a of operational amplifier 244, i.e., a voltage obtained by shifting the constant voltage 192 input to the non-inverting input terminal 244a of operational amplifier 244. Thus, the shifted voltage 192 is output from output terminal 246.

[0066] This disclosure is not limited to the above embodiments, and can be replaced by a configuration that is substantially the same as the configuration shown in the above embodiments, a configuration that achieves the same effect, or a configuration that can achieve the same purpose.

Claims

1. A shooting device, characterized in that, include: A pixel stores an electrical charge corresponding to the intensity of the light it receives. Lamp voltage generator, generates lamp voltage; A saturation determination voltage generator generates a saturation determination voltage based on the lamp voltage; The analog-to-digital converter uses the lamp voltage to convert the analog signal representing the amount of charge into a digital signal, and determines whether the pixel is saturated based on the comparison result between the voltage of the analog signal and the saturation determination voltage.

2. The shooting device according to claim 1, characterized in that, The lamp voltage includes: a ramp voltage with a fixed rate of change of voltage over time and a constant voltage with a fixed voltage value. The lamp voltage generator generates the constant voltage after the ramp voltage. Converting the analog signal to a digital signal using the lamp voltage includes: converting the analog signal to a digital signal based on the ramp voltage and the timing of the voltage reversal of the analog signal. Generating the saturation determination voltage based on the lamp voltage includes: generating the saturation determination voltage based on the constant voltage.

3. The shooting device according to claim 2, characterized in that, Generating the saturation determination voltage based on the constant voltage includes: amplifying or shifting the constant voltage to generate the saturation determination voltage.

4. The shooting apparatus according to any one of claims 1 to 3, characterized in that, The lamp voltage includes a ramp voltage with a fixed rate of change of voltage value over time. Converting the analog signal to a digital signal using the lamp voltage includes: converting the analog signal to a digital signal based on the ramp voltage and the timing of the voltage reversal of the analog signal. Generating the saturation determination voltage based on the lamp voltage includes: changing the saturation determination voltage according to the change in the rate of change of the slope voltage over time.

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