Power voltage generator

Abstract

The power voltage generator includes a voltage sensor and a power circuit breaker. The voltage sensor is configured to sense a first voltage during a first charge-sharing period of the gate clock signal and a second voltage during a second charge-sharing period of the gate clock signal. The power circuit breaker is configured to disconnect power based on the first and second voltages.

Description

Technical Field

[0001] Embodiments of the present invention relate to a power voltage generator, a display device including the power voltage generator, and a method for driving the display device. More specifically, embodiments of the present invention relate to a power voltage generator that senses short circuits between gate clock signal lines to improve safety and reliability, a display device including the power voltage generator, and a method for driving the display device.

[0002] Related technical descriptions

[0003] Typically, a display device includes a display panel and a display panel driver. The display panel displays an image based on an input image. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, a drive controller that controls the gate driver and the data driver, and a power voltage generator that provides power voltages to the display panel, the gate driver, and the data driver. Summary of the Invention

[0004] When a short circuit occurs between signal transmission lines in a part of the display device, heat or fire may be generated in the display device. Therefore, it is desirable to disconnect the power to the display device when a short circuit occurs between signal transmission lines in that part of the display device.

[0005] An embodiment of the present invention provides a power voltage generator capable of sensitively detecting short circuits between gate clock signal lines to improve safety and reliability.

[0006] An embodiment of the present invention also provides a display device including a power voltage generator.

[0007] Embodiments of the present invention also provide a method for driving a display device.

[0008] In an embodiment of the power voltage generator conceived according to the present invention, the power voltage generator includes a voltage sensor and a power circuit breaker. The voltage sensor is configured to sense a first voltage during a first charge-sharing period of the gate clock signal and a second voltage during a second charge-sharing period of the gate clock signal. The power circuit breaker is configured to disconnect power based on the first and second voltages.

[0009] In an embodiment, the power voltage generator may further include a comparator that compares the absolute value of the difference between the first voltage and the second voltage with a threshold to generate a comparison signal.

[0010] In an embodiment, the gate clock signal and the gate inverted clock signal, which is the inverted signal of the gate clock signal, can be temporarily connected to each other during a first charge-sharing period.

[0011] In an embodiment, the first charge-sharing period may correspond to the falling period of the gate clock signal, and the second charge-sharing period may correspond to the rising period of the gate clock signal.

[0012] In an embodiment, the first charge-sharing period and the second charge-sharing period can be controlled in response to a gate clock control signal.

[0013] In one embodiment, the voltage sensor may be configured to sense a first voltage at the rising edge of a first pulse of the gate clock control signal. The voltage sensor may also be configured to sense a second voltage at the rising edge of a second pulse of the gate clock control signal adjacent to the first pulse.

[0014] In an embodiment, when an image is written on the display area of ​​a display panel, the first charge-sharing period and the second charge-sharing period can be included in the active period. A voltage sensor can be configured to sense the first and second voltages during the active period.

[0015] In an embodiment, the length of the blank charge sharing period included in the vertical blank period when the image is not written on the display area of ​​the display panel can be longer than the length of the active charge sharing period included in the active period when the image is written on the display area of ​​the display panel.

[0016] In an embodiment, the first charge-sharing period and the second charge-sharing period may be blank charge-sharing periods included in the vertical blank period. The voltage sensor may be configured to sense the first voltage and the second voltage during the vertical blank period.

[0017] In this embodiment, the active charge sharing period and the idle charge sharing period can be controlled in response to a gate clock control signal. The pulse width of the gate clock control signal in the vertical idle period can be wider than the pulse width of the gate clock control signal in the active period.

[0018] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, a data driver, and a power voltage generator. The display panel includes gate lines, data lines, and pixels electrically connected to the gate lines and data lines. The display panel is configured to display an image based on an input image. The gate driver is configured to output a gate signal to the gate lines. The data driver is configured to output a data voltage to the data lines. The power voltage generator is configured to provide a drive voltage to the display panel, the gate driver, and the data driver. The power voltage generator includes a voltage sensor and a power circuit breaker, the voltage sensor sensing a first voltage during a first charge-sharing period of the gate clock signal and a second voltage during a second charge-sharing period of the gate clock signal, and the power circuit breaker stopping the provision of the drive voltage based on the first and second voltages.

[0019] In this embodiment, the gate driver may be disposed in the display panel. The power voltage generator may be configured to output a gate clock signal to the gate driver. The power voltage generator may be configured to stop providing the drive voltage when a short circuit is detected between the gate clock signal lines configured to apply the gate clock signal.

[0020] In an embodiment, the first charge-sharing period may correspond to the falling period of the gate clock signal, and the second charge-sharing period may correspond to the rising period of the gate clock signal.

[0021] In an embodiment, the display device may further include a drive controller that outputs a gate clock control signal for controlling the first charge sharing period and the second charge sharing period to a power voltage generator.

[0022] In one embodiment, the voltage sensor may be configured to sense a first voltage at the rising edge of a first pulse of the gate clock control signal. The voltage sensor may also be configured to sense a second voltage at the rising edge of a second pulse of the gate clock control signal adjacent to the first pulse.

[0023] In an embodiment, the length of the blank charge sharing period included in the vertical blank period when the image is not written on the display area of ​​the display panel can be longer than the length of the active charge sharing period included in the active period when the image is written on the display area of ​​the display panel.

[0024] In an embodiment, the first charge-sharing period and the second charge-sharing period can be blank charge-sharing periods included in the vertical blank period. The voltage sensor can be a sensor that senses the first voltage and the second voltage during the vertical blank period.

[0025] In an embodiment of the method for driving a display device, the method includes generating a gate clock signal based on a gate clock control signal, providing the gate clock signal to a gate driver, sensing a first voltage during a first charge-sharing period of the gate clock signal, sensing a second voltage during a second charge-sharing period of the gate clock signal, detecting a short circuit between gate clock signal lines based on the first voltage and the second voltage, and stopping power supply to the display device when a short circuit between the gate clock signal lines is detected.

[0026] In an embodiment, the first charge-sharing period may correspond to the falling period of the gate clock signal, and the second charge-sharing period may correspond to the rising period of the gate clock signal.

[0027] In an embodiment, the length of the blank charge sharing period included in the vertical blank period when the image is not written on the display area of ​​the display panel can be longer than the length of the active charge sharing period included in the active period when the image is written on the display area of ​​the display panel. The first charge sharing period and the second charge sharing period can be blank charge sharing periods included in the vertical blank period. The voltage sensor can be configured to sense the first voltage and the second voltage during the vertical blank period.

[0028] According to the method of power voltage generator, display device and driving display device, the voltage of gate clock signal is detected during the charge sharing period of gate clock signal, so that short circuits between gate clock signal lines can be detected sensitively compared with conventional current sensing methods.

[0029] During the vertical blank period when the image is not written on the display panel, the blank charge sharing period of the gate clock signal can be extended compared to the active charge sharing period in the active period. When the voltage of the gate clock signal is sensed during the extended blank charge sharing period, short circuits between the gate clock signal lines can be detected more sensitively.

[0030] Therefore, it is possible to prevent heat or fire in the display device that could occur if a short circuit between the gate clock signal lines goes undetected. Specifically, it is possible to prevent heat or fire in the display device that could occur if a short circuit between the gate clock signal lines is undetected at the lower part of the display panel. Therefore, the safety and reliability of the display device can be improved. Attached Figure Description

[0031] The above and other features and advantages of the present invention will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0032] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0033] Figure 2 It is a diagram. Figure 1 A plan view of the display device;

[0034] Figure 3 It is a diagram. Figure 1 Timing diagram of the input and output signals of the power voltage generator;

[0035] Figure 4 It is a diagram. Figure 1 A block diagram of a power voltage generator;

[0036] Figure 5 The diagram illustrates the situation when no short circuit is generated between the gate clock signal lines. Figure 4 Timing diagram of the sensing operation of the voltage sensor;

[0037] Figure 6 The diagram illustrates the situation when a short circuit occurs between the gate clock signal lines. Figure 4 Timing diagram of the sensing operation of the voltage sensor;

[0038] Figure 7 This is a timing diagram illustrating the gate clock signal in a display device according to an embodiment of the present invention;

[0039] Figure 8A It is illustrated when Figure 7 Timing diagram of the gate clock signal of the voltage sensor of the display device during the active period;

[0040] Figure 8B It is illustrated when Figure 7 A timing diagram of the gate clock signal of the voltage sensor of the display device during vertical blank periods; and

[0041] Figure 9 This is a timing diagram illustrating the gate clock signal and gate clock control signal in a display device according to an embodiment of the present invention. Detailed Implementation

[0042] The inventive concept will be explained in detail below with reference to the accompanying drawings. It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, “first element,” “first component,” “first region,” “first layer,” or “first portion” discussed below may be referred to as “second element,” “second component,” “second region,” “second layer,” or “second portion” without departing from the teachings herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms containing “at least one,” unless the context clearly indicates otherwise. “At least one” should not be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” indicate the presence of the stated features, areas, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components and / or groups thereof.

[0043] Figure 1This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0044] refer to Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver may further include a power voltage generator 600.

[0045] In embodiments, for example, the drive controller 200 and the data driver 500 may be integrally formed. As another example, the drive controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. A drive module that includes at least the integrally formed drive controller 200 and data driver 500 may be referred to as a timing controller embedded data driver (“TED”).

[0046] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0047] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple pixels P connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction D1, and the data lines DL extend in a second direction D2 that intersects the first direction D1.

[0048] The drive controller 200 receives input image data IMG and input control signal CONT from an external device (not shown). The input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. In another embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0049] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0050] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal.

[0051] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0052] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0053] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0054] The gate driver 300 generates a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 outputs the gate signal to the gate line GL. For example, the gate driver 300 can sequentially output the gate signal to the gate line GL. For example, the gate driver 300 can be mounted in the peripheral area of ​​the display panel 100. For example, the gate driver 300 can be integrated into the peripheral area of ​​the display panel 100.

[0055] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0056] In an embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or the data driver 500.

[0057] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs the data voltage to the data line DL. For example, the data driver 500 can be mounted in the peripheral area of ​​the display panel 100. Alternatively, the data driver 500 can be integrated into the peripheral area of ​​the display panel 100.

[0058] The power voltage generator 600 can provide power voltage to at least one of the display panel 100, drive controller 200, gate driver 300, gamma reference voltage generator 400, and data driver 500. For example, the power voltage generator 600 may include a DC-to-DC converter.

[0059] For example, the power voltage generator 600 can generate a common voltage VCOM and output the common voltage VCOM to the display panel 100. In this embodiment, the display device can be a liquid crystal display device including a liquid crystal layer. However, the display device of the present invention is not limited to a liquid crystal display device.

[0060] In an embodiment, for example, the power voltage generator 600 can generate a gate clock signal CKV for generating a gate signal, as well as a first gate cutoff voltage and a second gate cutoff voltage to control the operation of the gate driver 300. The power voltage generator 600 can output the gate clock signal CKV, the first gate cutoff voltage, and the second gate cutoff voltage to the gate driver 300.

[0061] The power voltage generator 600 can receive a gate clock control signal CPV from the drive controller 200. The power voltage generator 600 can generate a gate clock signal CKV based on the gate clock control signal CPV.

[0062] In one embodiment, for example, the power voltage generator 600 may generate an analog high voltage AVDD that determines the level of the data voltage and output the analog high voltage AVDD to the data driver 500.

[0063] Figure 2 It is a diagram. Figure 1 A plan view of the display device.

[0064] refer to Figure 1 and Figure 2 The drive controller 200 and the power voltage generator 600 can be disposed in the printed circuit board assembly PBA. The printed circuit board assembly PBA can be connected to the first printed circuit P1 and the second printed circuit P2.

[0065] For example, the data driver 500 may include a plurality of data driver chips (DICs) connected between the first printed circuit P1 and the display panel 100, and a plurality of other data driver chips (DICs) connected between the second printed circuit P2 and the display panel 100.

[0066] In this embodiment, the gate driver 300 can be disposed in the display panel 100. The power voltage generator 600 can output gate clock signals (e.g., CKV1 and CKV2) to the gate driver 300 disposed in the display panel 100. The gate clock signal lines for applying the gate clock signals CKV1 and CKV2 can be disposed in the display panel 100.

[0067] Figure 3 It is a diagram. Figure 1 Timing diagram of the input and output signals of the power voltage generator 600.

[0068] refer to Figures 1 to 3 The power voltage generator 600 can receive the gate clock control signal CPV from the drive controller 200 and generate a gate clock signal CKV based on the gate clock control signal CPV. The power voltage generator 600 can output the gate clock signal CKV to the gate driver 300 integrated in the display panel 100 through the gate clock signal line.

[0069] exist Figure 3 For example, the power voltage generator 600 can receive multiple gate clock control signals CPV1, CPV2, CPV3 and CPV4, and can output multiple gate clock signals CKV1, CKV2, CKV3, CKV4, CKVB1, CKVB2, CKVB3 and CKVB4.

[0070] For example, the first to eighth gate clock signals CKV1 to CKV4 and CKVB1 to CKVB4 can have different phases from each other. The phases of the first to eighth gate clock signals CKV1 to CKV4 and CKVB1 to CKVB4 can be distributed sequentially with uniform gaps.

[0071] like Figure 3 As shown, the second gate clock signal CKV2 may have a phase lag of 1 / 8 period compared to the first gate clock signal CKV1. The third gate clock signal CKV3 may have a phase lag of 1 / 8 period compared to the second gate clock signal CKV2. The fourth gate clock signal CKV4 may have a phase lag of 1 / 8 period compared to the third gate clock signal CKV3. The fifth gate clock signal CKVB1 may have a phase lag of 1 / 8 period compared to the fourth gate clock signal CKV4. The sixth gate clock signal CKVB2 may have a phase lag of 1 / 8 period compared to the fifth gate clock signal CKVB1. The seventh gate clock signal CKVB3 may have a phase lag of 1 / 8 period compared to the sixth gate clock signal CKVB2. The eighth gate clock signal CKVB4 may have a phase lag of 1 / 8 period compared to the seventh gate clock signal CKVB3.

[0072] The fifth to eighth gate clock signals CKVB1 to CKVB4 can be the inverted signals of the first to fourth gate clock signals CKV1 to CKV4. Therefore, the fifth to eighth gate clock signals CKVB1 to CKVB4 can be referred to as the inverted clock signals of the first to fourth gates CKVB1 to CKVB4. That is, for example, the fifth gate clock signal CKVB1 can have a phase that lags behind the first gate clock signal CKV1 by 1 / 2 cycle.

[0073] The first gate clock signal CKV1 and the first gate inverted clock signal CKVB1 can be changed based on the first gate clock control signal CPV1.

[0074] In an embodiment, for example, in response to a first pulse of the first gate clock control signal CPV1, the first gate clock signal CKV1 may decrease, and the first gate inverted clock signal CKVB1 may increase. For example, in response to a second pulse of the first gate clock control signal CPV1, the first gate clock signal CKV1 may increase, and the first gate inverted clock signal CKVB1 may decrease.

[0075] The power voltage generator 600 can generate the first gate clock signal CKV1 and the first gate inverted clock signal CKVB1 by a charge sharing method.

[0076] During the first charge-sharing period CS11 of the first gate clock signal CKV1, the first gate clock signal CKV1 and the first gate inverted clock signal CKVB1 can be temporarily connected to each other. When the first gate clock signal CKV1 and the first gate inverted clock signal CKVB1 are temporarily connected to each other during the first charge-sharing period CS11, the level of the first gate clock signal CKV1 can decrease towards the middle level, and the level of the first gate inverted clock signal CKVB1 can increase towards the middle level. For example, during the first charge-sharing period CS11 of the first gate clock signal CKV1, the output terminals of the first gate clock signal CKV1 and the first gate inverted clock signal CKVB1 can be temporarily short-circuited to each other. In this document, the first charge-sharing period CS11 can correspond to the first pulse of the first gate clock control signal CPV1, and the first charge-sharing period CS11 can correspond to the falling period of the first gate clock signal CKV1. The third charge-sharing period CS13 corresponds to the first charge-sharing period CS11. Therefore, the same thing may happen during the third charge-sharing period CS13.

[0077] During the second charge-sharing period CS12 of the first gate clock signal CKV1, the first gate clock signal CKV1 and the first gate inverted clock signal CKVB1 can be temporarily connected to each other. When the first gate clock signal CKV1 and the first gate inverted clock signal CKVB1 are temporarily connected to each other during the second charge-sharing period CS12, the level of the first gate clock signal CKV1 can rise towards the middle level, and the level of the first gate inverted clock signal CKVB1 can fall towards the middle level. In this document, the second charge-sharing period CS12 can correspond to the second pulse of the first gate clock control signal CPV1, and the second charge-sharing period CS12 can correspond to the rising period of the first gate clock signal CKV1.

[0078] The second gate clock signal CKV2 and the second gate inverted clock signal CKVB2 can be changed based on the second gate clock control signal CPV2.

[0079] In an embodiment, for example, in response to a first pulse of the second gate clock control signal CPV2, the second gate clock signal CKV2 may decrease, and the second gate inverted clock signal CKVB2 may increase. For example, in response to a second pulse of the second gate clock control signal CPV2, the second gate clock signal CKV2 may increase, and the second gate inverted clock signal CKVB2 may decrease.

[0080] The power voltage generator 600 can generate a second gate clock signal CKV2 and a second gate inverted clock signal CKVB2 through a charge sharing method.

[0081] During the first charge-sharing period CS21 of the second gate clock signal CKV2, the second gate clock signal CKV2 and the second gate inverted clock signal CKVB2 can be temporarily connected to each other. When the second gate clock signal CKV2 and the second gate inverted clock signal CKVB2 are temporarily connected to each other during the first charge-sharing period CS21, the level of the second gate clock signal CKV2 can decrease towards the middle level, and the level of the second gate inverted clock signal CKVB2 can increase towards the middle level. In this paper, the first charge-sharing period CS21 can correspond to the first pulse of the second gate clock control signal CPV2.

[0082] During the second charge-sharing period CS22 of the second gate clock signal CKV2, the second gate clock signal CKV2 and the second gate inverted clock signal CKVB2 can be temporarily connected to each other. When the second gate clock signal CKV2 and the second gate inverted clock signal CKVB2 are temporarily connected to each other during the second charge-sharing period CS22, the level of the second gate clock signal CKV2 can rise towards the middle level, and the level of the second gate inverted clock signal CKVB2 can fall towards the middle level. In this paper, the second charge-sharing period CS22 can correspond to the second pulse of the second gate clock control signal CPV2.

[0083] In the same manner explained above, the third gate clock signal CKV3 and the third gate inverted clock signal CKVB3 can be changed based on the third gate clock control signal CPV3, and the fourth gate clock signal CKV4 and the fourth gate inverted clock signal CKVB4 can be changed based on the fourth gate clock control signal CPV4. Figure 3 In the above, CS31 and CS32 are the first and second charge sharing periods of the third gate clock signal CKV3, respectively, and CS41 and CS42 are the first and second charge sharing periods of the fourth gate clock signal CKV4, respectively.

[0084] In addition, the power voltage generator 600 can generate the third gate clock signal CKV3 and the third gate inverted clock signal CKVB3 by a charge sharing method, and generate the fourth gate clock signal CKV4 and the fourth gate inverted clock signal CKVB4 by a charge sharing method.

[0085] In this embodiment, for example, the number of gate clock control signals is four, and the number of gate clock signals is eight. However, the inventive concept is not limited to the number of gate clock control signals and the number of gate clock signals.

[0086] Although the pulses of the gate clock control signals CPV1, CPV2, CPV3 and CPV4 in this embodiment are low pulses with a low level, the concept of the invention is not limited to this.

[0087] Figure 4 It is a diagram. Figure 1 Block diagram of the 600 power voltage generator. Figure 5 The diagram illustrates the situation when no short circuit is generated between the gate clock signal lines. Figure 4 Timing diagram of the sensing operation of voltage sensor 620. Figure 6 The diagram illustrates the situation when a short circuit occurs between the gate clock signal lines. Figure 4 Timing diagram of the sensing operation of voltage sensor 620.

[0088] refer to Figures 1 to 6The power voltage generator 600 may include a voltage sensor 620, a comparator 640, and a power circuit breaker 660.

[0089] The voltage sensor 620 can sense a first voltage VD11 during a first charge-sharing period CS11 of the gate clock signal (e.g., CKV1) and a second voltage VD12 during a second charge-sharing period CS12 of the gate clock signal (e.g., CKV1).

[0090] Comparator 640 can compare the absolute value of the difference between the first voltage VD11 and the second voltage VD12 with a threshold to generate a comparison signal.

[0091] The power circuit breaker 660 can cut off (or disconnect) the power to the display device based on the difference between the first voltage VD11 and the second voltage VD12. The power circuit breaker 660 can also cut off the power to the display device based on a comparison signal.

[0092] In an embodiment, for example, the voltage sensor 620 can sense the first voltage VD11 at the rising edge DP11 of the first pulse of the gate clock control signal (e.g., CPV1). Since the first sensing point DP11 of the voltage of the gate clock signal (e.g., CKV1) (i.e., at the rising edge DP11 of the first pulse of the first gate clock control signal CPV1) is later in the first charge sharing period CS11, changes in the first voltage VD11 caused by short circuits between the gate clock signal lines can be detected more accurately.

[0093] In an embodiment, for example, the voltage sensor 620 can sense the second voltage VD12 at the rising edge DP12 of the second pulse of the gate clock control signal (e.g., CPV1). Since the second sensing point DP12 of the voltage of the gate clock signal (e.g., CKV1) (i.e., at the rising edge DP12 of the second pulse of the first gate clock control signal CPV1) is later in the second charge sharing period CS12, changes in the second voltage VD12 caused by short circuits between the gate clock signal lines can be detected more accurately.

[0094] exist Figure 5 The diagram illustrates the normal state, in which no short circuit is generated between the first gate clock signal line for which the first gate clock signal CKV1 is applied and the second gate clock signal line for which the second gate clock signal CKV2 is applied.

[0095] Under this normal state, the first gate clock signal CKV1 can have a first voltage VD11 at the first sensing point DP11, corresponding to the intermediate voltage VM1 of the first gate clock signal CKV1, and the first gate clock signal CKV1 can have a second voltage VD12 at the second sensing point DP12, corresponding to the intermediate voltage VM1 of the first gate clock signal CKV1. In this paper, the difference between the first voltage VD11 and the second voltage VD12 of the first gate clock signal CKV1 can be zero.

[0096] Similarly, the second gate clock signal CKV2 can have a first voltage VD21 at the first sensing point DP21 corresponding to the intermediate voltage VM2 of the second gate clock signal CKV2, and the second gate clock signal CKV2 can have a second voltage VD22 at the second sensing point DP22 corresponding to the intermediate voltage VM2 of the second gate clock signal CKV2. In this paper, the difference between the first voltage VD21 and the second voltage VD22 of the second gate clock signal CKV2 can be zero.

[0097] exist Figure 6 The diagram illustrates an error state in which a short circuit is generated between the first gate clock signal line to which the first gate clock signal CKV1 is applied and the second gate clock signal line to which the second gate clock signal CKV2 is applied.

[0098] In an error state, the first gate clock signal CKV1 can have a first voltage VD11 at the first sensing point DP11 that is greater than the intermediate voltage VM1 of the first gate clock signal CKV1. Due to the short circuit between the first and second gate clock signal lines, the level of the first gate clock signal CKV1 can be pulled high toward the high level of the second gate clock signal CKV2 during the first charge sharing period CS11. The first gate clock signal CKV1 can have a second voltage VD12 at the second sensing point DP12 that is smaller than the intermediate voltage VM1 of the first gate clock signal CKV1. Due to the short circuit between the first and second gate clock signal lines, the level of the first gate clock signal CKV1 can be pulled low toward the low level of the second gate clock signal CKV2 during the second charge sharing period CS12.

[0099] For example, in Figure 6 In the first gate clock signal CKV1, the first voltage VD11 can be 12 volts (V), the second voltage VD12 can be 8V, and the absolute value of the difference between the first voltage VD11 and the second voltage VD12 can be 4V. Figure 6 For example, when the threshold is 2V, comparator 640 can detect a short circuit between the gate clock signal lines. Therefore, comparator 640 can output a comparison signal indicating a short circuit between the gate clock signal lines to power circuit breaker 660.

[0100] Similarly, the second gate clock signal CKV2 can have a first voltage VD21 at the first sensing point DP21 that is smaller than the intermediate voltage VM2 of the second gate clock signal CKV2. Due to the short circuit between the first and second gate clock signal lines, the level of the second gate clock signal CKV2 can be pulled low towards the low level of the first gate clock signal CKV1 during the first charge sharing period CS21. The second gate clock signal CKV2 can have a second voltage VD22 at the second sensing point DP22 that is larger than the intermediate voltage VM2 of the second gate clock signal CKV2. Due to the short circuit between the first and second gate clock signal lines, the level of the second gate clock signal CKV2 can be pulled high towards the high level of the first gate clock signal CKV1 during the second charge sharing period CS22. Figure 5 and Figure 6 In this context, CS23 is the third charge-sharing period of the second gate clock signal CKV2.

[0101] In this case, comparator 640 can detect a short circuit between the gate clock signal lines based on the difference between the first voltage VD21 and the second voltage VD22 of the second gate clock signal CKV2.

[0102] However, depending on the characteristics of the display panel 100 and the gate driver 300, even under normal conditions, the voltage during the charge-sharing period corresponding to the falling period of the gate clock signal (e.g., VD11) and the voltage during the charge-sharing period corresponding to the rising period of the gate clock signal (e.g., VD12) may have slight differences. Therefore, the threshold can be appropriately set taking into account the characteristics of the display panel 100 and the gate driver 300, so that the voltage difference caused by the characteristics of the display panel 100 and the gate driver 300 is not detected as a difference caused by a short circuit.

[0103] The display panel 100 can be driven in units of frames. A frame can include an active period when an image is written on the display panel 100 and a vertical blank period when an image is not written on the display panel 100.

[0104] In this embodiment, the first charge-sharing period CS11 and the second charge-sharing period CS12 can be included in the active period, and the voltage sensor 620 can sense the first voltage VD11 and the second voltage VD12 during the active period. Alternatively, the first charge-sharing period CS11 and the second charge-sharing period CS12 can be included in the vertical blank period, and the voltage sensor 620 can sense the first voltage VD11 and the second voltage VD12 during the vertical blank period.

[0105] According to this embodiment, the voltage of the first gate clock signal CKV1 is detected during the charge sharing periods CS11 and CS12 of the first gate clock signal CKV1, so that short circuits between the gate clock signal lines can be detected more sensitively compared with conventional current sensing methods.

[0106] Therefore, it is possible to prevent heat or fire in the display device that could occur if a short circuit between the gate clock signal lines goes undetected. Specifically, it is possible to prevent heat or fire in the display device that could occur if a short circuit between the gate clock signal lines goes undetected at the lower portion of the display panel 100. Therefore, the safety and reliability of the display device can be improved.

[0107] Figure 7 This is a timing diagram illustrating the gate clock signal in a display device according to an embodiment of the present invention. Figure 8A It is illustrated when Figure 7 The timing diagram of the gate clock signal when the voltage sensor 620 of the display device operates during the active period. Figure 8B It is illustrated when Figure 7 The timing diagram of the gate clock signal when the voltage sensor 620 of the display device operates during the vertical blank period.

[0108] In addition to the voltage sensor sensing the first voltage and the second voltage during the vertical blank period, the power voltage generator, the display device including the power voltage generator, and the method and reference for driving the display device according to this embodiment are also described. Figures 1 to 6 The power voltage generator, the display device including the power voltage generator, and the method of driving the display device explained in the previous embodiment are substantially the same. Therefore, the same reference numerals will be used to refer to the same... Figures 1 to 6 The parts described in the previous embodiments are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0109] refer to Figures 1 to 8B The display panel 100 can be driven in units of frames. A frame can include an active period when an image is written on the display panel 100 and a vertical blank period when an image is not written on the display panel 100.

[0110] In this embodiment, the length of the active charge sharing period CSA included in the active period ACTIVE may differ from the length of the blank charge sharing period CSB included in the vertical blank period VBLANK. For example, the length of the blank charge sharing period CSB may be longer than the length of the active charge sharing period CSA.

[0111] During the vertical blank period VBLANK, the image is not written on the display panel 100, so that even if the length of the blank charge sharing period CSB is adjusted, it has almost no impact on the display quality.

[0112] exist Figure 8A In this process, the first voltage VDA1 can be sensed at the first sensing point DP1 during the active charge sharing period CSA, and the second voltage VDA2 can be sensed at the second sensing point DP2 during the active charge sharing period CSA.

[0113] exist Figure 8B In this process, the first voltage VDB1 can be sensed at the first sensing point DP1 during the blank charge sharing period CSB, and the second voltage VDB2 can be sensed at the second sensing point DP2 during the blank charge sharing period CSB.

[0114] When a short circuit occurs between the gate clock signal lines, the gate clock signal (e.g., Figure 8A The CKVA shown is Figure 8B The voltage of CKVB (as shown) gradually moves away from the normal level (intermediate voltage) during the charge-sharing period. Therefore, during the active charge-sharing period CSA, as... Figure 8A As shown, when the voltage is short, the difference between the first voltage VDA1 and the second voltage VDA2 can be relatively small. Conversely, when the blank charge sharing period CSB is as shown... Figure 8B As shown, when the voltage is long, the difference between the first voltage VDB1 and the second voltage VDB2 can be relatively large.

[0115] Therefore, in this embodiment, the voltage sensor 620 can sense the first voltage VDB1 and the second voltage VDB2 during the blank charge sharing period CSB in the vertical blank period VBLANK. When the voltage sensor 620 senses the first voltage VDB1 and the second voltage VDB2 during the blank charge sharing period CSB in the vertical blank period VBLANK, the short circuit between the gate clock signal lines can be detected more sensitively.

[0116] According to this embodiment, the voltage of the gate clock signal is detected during the charge sharing period of the gate clock signal, so that short circuits between the gate clock signal lines can be detected more sensitively compared to conventional current sensing methods.

[0117] During the vertical blank period VBLANK when the image is not written on the display panel 100, the blank charge sharing period CSB of the gate clock signal can be extended. When the voltage of the gate clock signal is sensed during the extended blank charge sharing period CSB, short circuits between the gate clock signal lines can be detected more sensitively.

[0118] Therefore, it is possible to prevent heat or fire in the display device that could occur if a short circuit between the gate clock signal lines is not detected. Specifically, it is possible to prevent heat or fire in the display device that could occur if a short circuit between the gate clock signal lines is not detected at the lower portion of the display panel 100. Therefore, the safety and reliability of the display device can be improved.

[0119] Figure 9 This is a timing diagram illustrating the gate clock signal and gate clock control signal in a display device according to an embodiment of the present invention.

[0120] In addition to controlling the charge sharing period in response to the gate clock control signal, the power voltage generator, the display device including the power voltage generator, and the method and reference for driving the display device according to this embodiment are also described. Figures 7 to 8B The power voltage generator, the display device including the power voltage generator, and the method of driving the display device explained in the previous embodiment are substantially the same. Therefore, the same reference numerals will be used to refer to the same... Figures 7 to 8B The parts described in the previous embodiments are the same as or similar to those described above, and any repeated explanations of the above elements will be omitted.

[0121] refer to Figures 1 to 6 , Figure 8A , Figure 8B and Figure 9 The display panel 100 can be driven in units of frames. A frame can include an active period when an image is written on the display panel 100 and a vertical blank period when an image is not written on the display panel 100.

[0122] In this embodiment, the length of the active charge sharing period CSA included in the active period ACTIVE may differ from the length of the blank charge sharing period CSB included in the vertical blank period VBLANK. For example, the length of the blank charge sharing period CSB may be longer than the length of the active charge sharing period CSA.

[0123] During the vertical blank period VBLANK, the image is not written on the display panel 100, so that even if the length of the blank charge sharing period CSB is adjusted, it has almost no impact on the display quality.

[0124] In this embodiment, the active charge sharing period (CSA) and the blank charge sharing period (CSB) can be controlled in response to the gate clock control signal CPV. Therefore, the pulse width of the gate clock control signal CPV in the vertical blank period (VBLANK) can be wider than the pulse width of the gate clock control signal CPV in the active period (ACTIVE).

[0125] When a short circuit occurs between the gate clock signal lines, the voltage of the gate clock signal CKV gradually deviates from the normal level (intermediate voltage) during the charge sharing period. Therefore, during the active charge sharing period CSA, as... Figure 8A As shown, when the voltage is short, the difference between the first voltage VDA1 and the second voltage VDA2 can be relatively small. Conversely, when the blank charge sharing period CSB is as shown... Figure 8B As shown, when the voltage is long, the difference between the first voltage VDB1 and the second voltage VDB2 can be relatively large.

[0126] Therefore, in this embodiment, the voltage sensor 620 can sense the first voltage VDB1 and the second voltage VDB2 during the blank charge sharing period CSB in the vertical blank period VBLANK. When the voltage sensor 620 senses the first voltage VDB1 and the second voltage VDB2 during the blank charge sharing period CSB in the vertical blank period VBLANK, the short circuit between the gate clock signal lines can be detected more sensitively.

[0127] According to this embodiment, the voltage of the gate clock signal is detected during the charge sharing period of the gate clock signal, so that short circuits between the gate clock signal lines can be detected more sensitively compared to conventional current sensing methods.

[0128] During the vertical blank period VBLANK when the image is not written on the display panel 100, the blank charge sharing period CSB of the gate clock signal can be extended. When the voltage of the gate clock signal is sensed during the extended blank charge sharing period CSB, short circuits between the gate clock signal lines can be detected more sensitively.

[0129] Therefore, it is possible to prevent heat or fire in the display device that could occur if a short circuit between the gate clock signal lines is not detected. Specifically, it is possible to prevent heat or fire in the display device that could occur if a short circuit between the gate clock signal lines is not detected at the lower portion of the display panel 100. Therefore, the safety and reliability of the display device can be improved.

[0130] Based on the inventive concept explained above, the safety and reliability of display devices can be improved.

[0131] The foregoing description is illustrative of the inventive concept and should not be construed as limiting it. Although several embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means plus function clause is intended to cover the structures described herein for performing the recited functions, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing description is illustrative of the inventive concept and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, including the equivalents of the claims.

Claims

1. A power voltage generator, comprising: A voltage sensor senses a first voltage during a first charge-sharing period of a gate clock signal and a second voltage during a second charge-sharing period of the gate clock signal; and A power circuit breaker disconnects power based on the difference between the first voltage and the second voltage.

2. The power voltage generator according to claim 1, further comprising: A comparator compares the absolute value of the difference between the first voltage and the second voltage with a threshold to generate a comparison signal.

3. The power voltage generator according to claim 1, wherein, The gate clock signal and the gate inverted clock signal, which is the inverted signal of the gate clock signal, are temporarily connected to each other during the first charge sharing period.

4. The power voltage generator according to claim 1, wherein, The first charge-sharing period corresponds to the falling period of the gate clock signal, and the second charge-sharing period corresponds to the rising period of the gate clock signal.

5. The power voltage generator according to claim 1, wherein, The first charge-sharing period and the second charge-sharing period are controlled in response to the gate clock control signal.

6. The power voltage generator according to claim 5, wherein, The voltage sensor is configured to sense the first voltage at the rising edge of the first pulse of the gate clock control signal, and The voltage sensor is configured to sense the second voltage at the rising edge of a second pulse of the gate clock control signal that is adjacent to the first pulse of the gate clock control signal.

7. The power voltage generator according to claim 1, wherein, When an image is written onto the display area of ​​the display panel, the first charge-sharing period and the second charge-sharing period are included in the active period, and The voltage sensor is configured to sense the first voltage and the second voltage during the active period.

8. The power voltage generator according to claim 1, wherein, The length of the blank charge sharing period included in the vertical blank period when the image is not written on the display area of ​​the display panel is longer than the length of the active charge sharing period included in the active period when the image is written on the display area of ​​the display panel.

9. The power voltage generator according to claim 8, wherein, The first charge-sharing period and the second charge-sharing period are the blank charge-sharing periods included in the vertical blank period, and The voltage sensor is configured to sense the first voltage and the second voltage during the vertical blank period.

10. The power voltage generator according to claim 9, wherein, The active charge sharing period and the blank charge sharing period are controlled in response to the gate clock control signal, and The pulse width of the gate clock control signal in the vertical blank period is wider than the pulse width of the gate clock control signal in the active period.

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