A-RGB light effect control method and device

Abstract

The application relates to the technical field of lamp effect control, and discloses an A- RGB lamp effect control method and device, the method comprising the following steps: sending device query instructions to an external A- RGB device connected with a first channel and a second channel in sequence, receiving response codes returned by the external A- RGB device, and comparing the response codes with brand protocol characteristic codes stored in a flash in byte by byte, so as to obtain serial transmission code stream data; configuring a first PDMA channel and a second PDMA channel to read the serial transmission code stream data from the first channel and the second channel respectively, and outputting parallel lamp effect data of a double-path 1-wire port; calculating a timestamp difference value based on the parallel lamp effect data, and starting a delay timer to delay the PDMA enabling operation of a channel with an earlier timestamp when the timestamp difference value exceeds a preset synchronization threshold value, so that the application realizes synchronous lamp effect output of double-path channel timestamp alignment, and solves the problem of lamp effect asynchronization caused by conversion time difference of cross-brand device protocols.

Description

Technical Field

[0001] This invention relates to the field of lighting effect control technology, and in particular to an A-RGB lighting effect control method and device. Background Technology

[0002] In the current PC market, A-RGB lighting effects have become a core feature of motherboards, but existing technology has significant drawbacks. Different brands of A-RGB devices use proprietary communication protocols, making it impossible to control them uniformly on a single motherboard. This forces users to choose a single brand's ecosystem, limiting their freedom in hardware configuration.

[0003] Existing technologies only offer single-channel A-RGB output or multi-channel non-independent control solutions, failing to achieve differentiated lighting effects for different areas such as motherboard LED strips and case fans, resulting in a uniform lighting effect. Furthermore, existing technologies use general-purpose microcontrollers in conjunction with external LED driver chips, leading to long data transmission links and synchronization delays exceeding 100ms for multiple devices, and lighting effect control response delays exceeding 150ms, severely impacting the smoothness of dynamic lighting effects. Summary of the Invention

[0004] This invention provides an A-RGB lighting effect control method and device. This invention realizes synchronous lighting effect output with dual-channel timestamp alignment, and solves the problem of asynchronous lighting effects caused by the difference in protocol conversion time between cross-brand devices.

[0005] In a first aspect, the present invention provides an A-RGB lighting effect control method, the A-RGB lighting effect control method comprising: Device query commands are sent sequentially to the external A-RGB devices connected to the first and second channels. The response codes returned by the external A-RGB devices are received and compared byte by byte with the brand protocol feature codes stored in Flash to obtain serial transmission code stream data. Configure the first PDMA channel and the second PDMA channel to read the serial transmission code stream data from the first channel and the second channel respectively, and output the parallel lighting effect data of the dual-channel 1-wire port; Based on the parallel lighting effect data, the timestamp difference is calculated. When the timestamp difference exceeds a preset synchronization threshold, a delay timer is started to delay the PDMA enable operation of the channel with the earlier timestamp.

[0006] In conjunction with the first aspect, in a first implementation of the first aspect of the present invention, before sequentially sending device query commands to the external A-RGB devices connected to the first channel and the second channel, the method further includes: Configure the system clock control register, set the internal high-speed oscillator to the preset main frequency and enable the phase-locked loop, switch the GPIO function multiplexing register of the first and second pins to the multiplexing function mode and set the drive strength to the preset current value; Set the clock prescaler register of the first and second timers to the preset division ratio, set the auto-reload register to the preset resolution minus one count value, and configure the output compare mode register to PWM mode.

[0007] In conjunction with the first aspect, in a second implementation of the first aspect of the present invention, device query commands are sequentially sent to the external A-RGB devices connected to the first and second channels, and the response codes returned by the external A-RGB devices are received and compared byte-by-byte with the brand protocol feature codes stored in Flash to obtain serial transmission code stream data, including: Send a preset number of brand query commands sequentially to an external A-RGB device via a 1-wire interface and receive the response code returned by the external A-RGB device; The response code is compared byte by byte with the brand protocol feature code stored in Flash. When the number of matching bytes exceeds a preset comparison threshold, the brand type identifier is recorded. Based on the brand type identifier, the RGB color value field is extracted from the brand private protocol instruction, and the RGB color value field is combined with the supplementary LED index field and lighting effect mode field to form a lighting effect control instruction; The lighting effect control data, including LED index and RGB color value, is obtained by parsing the lighting effect control command. The PWM duty cycle value is queried based on the RGB color value in the lighting effect control data. The PWM duty cycle value is converted into the corresponding comparison register value to obtain serial transmission code stream data that conforms to the 1-wire protocol timing.

[0008] In conjunction with the first aspect, in a third implementation of the first aspect of the present invention, the lighting effect control data containing LED indexes and RGB color values ​​is obtained by parsing the lighting effect control instructions, including: Extract the R component field, G component field, and B component field of the 16-bit color depth format RGB value from the lighting effect control command; The R component field, G component field, and B component field are respectively subjected to bitwise OR operation to obtain RGB color values. The RGB color values ​​are then combined with the LED index field in the lighting effect control instruction to obtain lighting effect control data.

[0009] In conjunction with the first aspect, in the fourth implementation of the first aspect of the present invention, the PWM duty cycle value is queried based on the RGB color value in the lighting effect control data, and the PWM duty cycle value is converted into a corresponding comparison register value to obtain serial transmission code stream data conforming to the 1-wire protocol timing, including: The RGB color values ​​are extracted from the lighting control data and used as an index to query the Gamma correction lookup table stored in Flash to obtain the PWM duty cycle value. Extract each bit value of the PWM duty cycle value, and map the bit value to the comparison register value corresponding to the preset high duty cycle when the bit value is 1, and to the comparison register value corresponding to the preset low duty cycle when the bit value is 0, to obtain the comparison register value sequence; The sequence of comparison register values ​​is written into the PDMA source buffer in the order of the RGB data of each LED to obtain serial transmission code stream data conforming to the 1-wire protocol timing.

[0010] In conjunction with the first aspect, in the fifth implementation of the first aspect of the present invention, each bit value of the PWM duty cycle is extracted, and a comparison register value sequence is obtained by mapping a bit value of 1 to a comparison register value corresponding to a preset high duty cycle and a bit value of 0 to a comparison register value corresponding to a preset low duty cycle, including: Perform a bit-right shift operation on the PWM duty cycle value by a preset number of bits to extract an 8-bit color value; Perform a right shift and a bitwise AND operation on the 8-bit color value sequentially from the most significant bit to the least significant bit to extract the 8-bit value; Traverse the 8 bit values, map the positions with bit values ​​of 1 to the comparison register values ​​corresponding to the preset high duty cycle, and map the positions with bit values ​​of 0 to the comparison register values ​​corresponding to the preset low duty cycle, to obtain the comparison register value sequence.

[0011] In conjunction with the first aspect, in a sixth implementation of the first aspect of the present invention, configuring a first PDMA channel and a second PDMA channel to read the serial transmission code stream data from the first channel and the second channel respectively, and outputting parallel lighting effect data from dual-channel 1-wire ports, includes: Configure the control registers of the first PDMA channel and the second PDMA channel, set the source address to point to the corresponding PDMA source buffer, the destination address to point to the comparison register of the corresponding timer, and configure the trigger source to be the timer update event; Configure the slave mode control register of the second timer to set the trigger source to the internal trigger output of the first timer, and configure the master mode control register of the first timer to set the output to the update event trigger signal; Configure the corresponding PDMA channel enable bit, start the counter of the first timer, and trigger the second timer to start synchronously through the master-slave synchronization configuration of the first timer, and output parallel lighting effect data of dual 1-wire ports.

[0012] In conjunction with the first aspect, in the seventh implementation of the first aspect of the present invention, after outputting the parallel lighting effect data of the dual-channel 1-wire ports, it further includes: The LED color data of the current frame and the previous frame are traversed to calculate the RGB color Euclidean distance of each LED, and the number of LEDs whose RGB color Euclidean distance exceeds the preset color difference threshold is counted and the color change rate is calculated. The cumulative value of color difference is calculated based on the LED color data. The corresponding refresh frequency is obtained by querying the preset mapping table from the lighting effect mode field. The color change rate, the cumulative value of color difference and the refresh frequency are weighted and summed to obtain the comprehensive complexity score. The comprehensive complexity score is mapped to the corresponding main frequency level value according to the preset score range, and the frequency division coefficient corresponding to the main frequency level value is written into the system clock control register.

[0013] In conjunction with the first aspect, in the eighth implementation of the first aspect of the present invention, a timestamp difference is calculated based on the parallel lighting effect data. When the timestamp difference exceeds a preset synchronization threshold, a delay timer is started to delay the PDMA enable operation of the channel with the earlier timestamp, including: Read the first timestamp field of the first frame data from the frame queue of the first channel and the second timestamp field of the first frame data from the frame queue of the second channel; Calculate the timestamp difference between the first timestamp field and the second timestamp field; Determine whether the absolute value of the timestamp difference exceeds a preset synchronization threshold. If it does, determine the channel with the earlier timestamp based on the positive or negative sign of the timestamp difference to obtain the channel identifier and delay time value. Configure the auto-reload register of the delay timer according to the required delay channel identifier, set the count value corresponding to the delay time value, start the delay timer, and enable the PDMA channel enable bit of the corresponding channel when an overflow interrupt is triggered.

[0014] Secondly, the present invention provides an A-RGB lighting effect control device, the A-RGB lighting effect control device comprising: The feature code comparison module is used to sequentially send device query commands to the external A-RGB devices connected to the first channel and the second channel, receive the response codes returned by the external A-RGB devices, and compare them byte by byte with the brand protocol feature codes stored in Flash to obtain serial transmission code stream data; The reading module is configured to read the serial transmission code stream data from the first channel and the second channel respectively, and output parallel lighting effect data from dual-channel 1-wire ports; The enable operation module is used to calculate the timestamp difference based on the parallel lighting effect data. When the timestamp difference exceeds a preset synchronization threshold, a delay timer is started to delay the PDMA enable operation of the channel with the earlier timestamp.

[0015] The technical solution provided by this invention constructs a dual-channel independent PWM time base generator using a microcontroller, achieving completely independent control of the first and second channels to meet the differentiated lighting effect settings requirements of different areas such as motherboard LED strips and chassis fans; it identifies different brand devices by comparing brand protocol feature codes byte by byte, converting each brand's proprietary protocol instructions into a unified internal instruction format, breaking through the limitations of a single brand ecosystem and achieving cross-brand compatibility; it uses a flash-stored Gamma correction lookup table to map RGB color values ​​to 10-bit PWM duty cycle values, and combines preset logic encoding rules to convert them into serial transmission bitstream data conforming to the 1-wire protocol timing, improving color accuracy and color coverage; it configures the first and second PDMA channels to read data from independent source buffers respectively and triggers the first PDMA channel data through a first timer update event. The system moves and synchronously triggers a second timer to start the second PDMA channel data transfer, using a timer master-slave synchronization mechanism to eliminate the dual-channel transmission start-up time deviation and ensure accurate synchronization of parallel lighting effect data output. A comprehensive complexity score is obtained by calculating the LED color change rate between the current and previous frames, the cumulative value of adjacent LED color differences, and the lighting effect mode refresh frequency. This score is dynamically mapped to a preset main frequency level and the system clock control register is modified. For simple static lighting effects, the main frequency is reduced to decrease power consumption, while for complex dynamic lighting effects, the main frequency is increased to ensure response speed. The system reads the timestamp of the first frame from the dual-channel frame queue and calculates the timestamp difference. When the difference exceeds a preset synchronization threshold, a delay timer is started to delay the PDMA enable operation of the channel with the earlier timestamp, achieving synchronized lighting effect output with timestamp alignment between the two channels. This solves the problem of lighting effect asynchrony caused by protocol conversion time differences between cross-brand devices. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram illustrating the steps of the A-RGB lighting effect control method in an embodiment of the present invention; Figure 2 This is a schematic diagram of the overall structure of the dual-channel independent A-RGB lighting effect control system based on the ENE 6K7732 microcontroller in an embodiment of the present invention; Figure 3 This is a schematic diagram of the USB communication interface and PWM control signal conversion circuit in an embodiment of the present invention; Figure 4This is a schematic diagram of the first channel A-RGB lighting effect 1-wire data output interface circuit in an embodiment of the present invention; Figure 5 This is a schematic diagram of the second channel A-RGB lighting effect 1-wire data output interface circuit in an embodiment of the present invention; Figure 6 This is a schematic diagram of the onboard LED red channel MOSFET driving circuit in an embodiment of the present invention; Figure 7 This is a schematic diagram of the onboard LED green channel MOSFET driving circuit in an embodiment of the present invention; Figure 8 This is a schematic diagram of the onboard LED blue channel MOSFET driving circuit in an embodiment of the present invention; Figure 9 This is a schematic diagram of the A-RGB lighting effect control device in an embodiment of the present invention. Detailed Implementation

[0018] This invention provides an A-RGB lighting effect control method and apparatus. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 One embodiment of the A-RGB lighting effect control method in this invention includes: Step S1: Send device query commands to the external A-RGB devices connected to the first and second channels in sequence, receive the response codes returned by the external A-RGB devices and compare them byte by byte with the brand protocol feature codes stored in Flash to obtain serial transmission code stream data; Step S2: Configure the first PDMA channel and the second PDMA channel to read the serial transmission code stream data from the first channel and the second channel respectively, and output the parallel lighting effect data of the dual-channel 1-wire port; Step S3: Calculate the timestamp difference based on the parallel lighting effect data. When the timestamp difference exceeds the preset synchronization threshold, start the delay timer to delay the PDMA enable operation of the channel with the earlier timestamp.

[0020] In one specific embodiment, before sequentially sending device query commands to the external A-RGB devices connected to the first and second channels, the method further includes: Configure the system clock control register, set the internal high-speed oscillator to the preset main frequency and enable the phase-locked loop, switch the GPIO function multiplexing register of the first and second pins to the multiplexing function mode and set the drive strength to the preset current value; Set the clock prescaler register of the first and second timers to the preset division ratio, set the auto-reload register to the preset resolution minus one count value, and configure the output compare mode register to PWM mode.

[0021] Specifically, the system clock source is set to the internal high-speed oscillator HSI, with its main frequency set to 32MHz as the system's base clock. HSI is enabled by writing to the clock source selection field in the system clock control register, and the enable bit of the PLL (phase-locked loop) is set to a high level. Simultaneously, the PLL's lock flag is polled until it is set to ensure a stable and usable PLL output clock. The system bus clock division factor is configured so that the APB bus and peripheral subsystems obtain a stable clock signal synchronized with or divided from the main system clock. The GPIO function multiplexing registers corresponding to the first and second pins are configured. The function selection bit in the GPIO port mode register corresponding to the first pin is set to the multiplexing function state, causing it to exit general-purpose I / O mode and connect to the on-chip timer channel, thus enabling PWM signal output capability. The same multiplexing switching process is performed on the second pin. After completing the multiplexing function configuration, the GPIO drive strength register is set, writing a 12mA current drive level to the output drive capability control bit of the corresponding pin. Configure the clock prescaler registers of the first and second timers, setting them to a preset division ratio to effectively downscale the main frequency and use it as the time base frequency for the PWM signal. For example, with a 32MHz main frequency, setting the prescaler register to 1 achieves a 1:2 division, resulting in a 16MHz timer input clock frequency. Combined with the auto-reload register configuration, if the target PWM resolution is 10 bits, the auto-reload register is set to 1023, meaning a count range of 0 to 1023, totaling 1024 count cycles. The corresponding PWM period is 1024 count cycles divided by the 16MHz frequency, resulting in a PWM period length of approximately 64 microseconds, achieving a PWM output frequency of 15.625kHz. After completing the clock division and period setting, configure the output compare mode registers of both timers to PWM operating mode. Set the output comparison mode field of the corresponding channel to PWM mode 1, that is, output a high level when the counter CNT value is less than the comparison register CCR value, and output a low level when the CNT value is equal to or greater than the CCR value, thereby constructing a standard duty cycle adjustable PWM signal waveform.

[0022] Figure 2 The overall system architecture of the ENE 6K7732UA0 microcontroller is shown below. On the left is the USB interface circuit for communication with the host computer. In the center is the ENE 6K7732UA0 main control chip, which is connected to multiple output pins on the right through the system clock control unit and GPIO function multiplexing configuration unit. These include dual 1-wire data output ports of 7732_RGB0 and 7732_RGB1, and onboard LED control signal output ports of 7732_RED / GREEN / BLUE. The top is the power management circuit, and the bottom is the clock source and reset circuit.

[0023] Figure 3 The RGB_PWI signal is input through the Header 1X4 interface, and connected to the SMBIL_CK and SMBIL_DA signal lines through pull-up resistors R23318 and R23319. The PWM signal level is converted through a MOSFET switching circuit below, and the signal is output to the SMBIL_CK and SMBIL_DA ports on the right side for communication with external devices or receiving control commands from the host computer.

[0024] In one specific embodiment, device query commands are sequentially sent to the external A-RGB devices connected to the first and second channels. The response codes returned by the external A-RGB devices are received and compared byte-by-byte with the brand protocol feature codes stored in Flash to obtain serial transmission stream data, including: Send a preset number of brand query commands sequentially to an external A-RGB device via a 1-wire interface and receive the response code returned by the external A-RGB device; The response code is compared byte by byte with the brand protocol feature code stored in Flash. When the number of matching bytes exceeds a preset comparison threshold, the brand type identifier is recorded. Based on the brand type identifier, the RGB color value field is extracted from the brand private protocol instruction, and the RGB color value field is combined with the supplementary LED index field and lighting effect mode field to form a lighting effect control instruction; The lighting effect control data, including LED index and RGB color value, is obtained by parsing the lighting effect control command. The PWM duty cycle value is queried based on the RGB color value in the lighting effect control data. The PWM duty cycle value is converted into the corresponding comparison register value to obtain serial transmission code stream data that conforms to the 1-wire protocol timing.

[0025] Figure 4 Connect the 7732_RGB0 signal to the A_RGB0 four-pin interface socket. Pins 1 and 2 provide +5VS power supply, and pin 4 is grounded (GND). The microcontroller outputs a serial data stream conforming to the 1-wire protocol timing through the 7732_RGB0 pin to the first channel of the external A-RGB device, realizing independent control of the first channel.

[0026] Figure 5 Connect the 7732_RGB1 signal to the A_RGB1 four-pin interface socket. Pins 1 and 2 provide +5VS power supply, and pin 4 is grounded (GND). The microcontroller outputs a serial data stream conforming to the 1-wire protocol timing through the 7732_RGB1 pin to the second channel of the external A-RGB device, realizing independent control of the second channel.

[0027] Specifically, an active probing process is initiated via a 1-wire single-bus communication interface. The microcontroller sequentially sends a preset number of brand query commands to the A-RGB devices connected to the first or second control channel in a preset order. A loop structure reads preset brand protocol feature command templates from Flash memory one by one. Each set of commands is written byte-by-byte into the 1-wire transmission buffer and serialized and encoded by the GPIO driver using high and low level pulses conforming to the WS2812B protocol timing requirements. Logic 1 and logic 0 correspond to specific high and low level duty cycle combinations, respectively. After each query command is sent, the corresponding GPIO pin is configured as an input state, and an interrupt listener is enabled to capture the response signal returned by the A-RGB device. When the response code arrives, the high-level duration is recorded by the SysTick timer and converted into a binary bit stream, constructing a response code data frame and buffering it in SRAM. A byte-by-byte comparison process is then performed between the response code and the brand protocol feature code template stored in Flash memory. During the comparison process, the number of bytes in each response code that completely match the preset template is counted. When the number of matching bytes exceeds the preset comparison threshold (e.g., more than 2 out of 3 bytes match), the brand type of the external device is identified, and its corresponding brand identification code is written into the device information structure. Based on the brand type identifier, the corresponding brand-specific protocol instruction parsing function is called to extract the field containing the RGB color value from its lighting effect control data frame. Since some brand protocols do not fully provide standardized LED indexes or lighting effect mode fields, the default LED start index (e.g., set to 0), lighting effect mode (e.g., set to static or flowing mode), and speed level parameters are actively supplemented in the unified control logic. The supplemented fields are integrated with the RGB color fields to form a fixed-format internal lighting effect control instruction structure. The structure is 8 bytes long and includes information such as channel number, LED index, quantity, RGB three primary color values, mode field, and refresh rate parameter field. The internal control instructions are parsed to extract the RGB color values ​​and LED position indexes, forming a structured lighting effect control data queue. The PWM duty cycle lookup table module is then started to perform color conversion processing. Each RGB color value is an 8-bit data (0-255). By accessing a pre-defined Gamma 2.2 LUT lookup table, it is non-linearly mapped to a 10-bit resolution PWM duty cycle value. For example, an input value of 128 is mapped to 228 after Gamma LUT processing, and an input value of 255 is mapped to 1023, thus maintaining linear consistency in visual brightness presentation. After the lookup is complete, each PWM duty cycle value is converted into a Compare Register (CCR) value recognizable by the hardware timer. Based on the logical encoding rules of the 1-wire protocol, logic 1 is encoded as a 64% duty cycle, and logic 0 is encoded as a 32% duty cycle, corresponding to CCR values ​​of 655 and 328 respectively.A 24-bit serialized PWM code stream is generated based on the RGB three-channel data of each LED. This stream is then converted bit by bit into a PWM compare register update sequence and written to the PDMA source buffer. The PWM code stream is converted into a continuous 1-wire serial waveform output by the collaborative mechanism of the PDMA controller and timer, thereby driving an external A-RGB device to display lighting effects according to the expected colors.

[0028] In one specific embodiment, the lighting effect control data containing LED indexes and RGB color values ​​is obtained by parsing the lighting effect control command, including: Extract the R component field, G component field, and B component field of the 16-bit color depth format RGB value from the lighting effect control command; The R component field, G component field, and B component field are respectively subjected to bitwise OR operation to obtain RGB color values. The RGB color values ​​are then combined with the LED index field in the lighting effect control instruction to obtain lighting effect control data.

[0029] Figure 6 The 7732_RED signal is connected to the gate G of the N-channel MOSFET PQ31 (model L2N7002LT1G) through a 10K / 1% / 4 power gate resistor R23316. The source S of the MOSFET is grounded and the drain D is connected to the CONN_RED output terminal. The microcontroller controls the MOSFET's conduction state by modulating the 7732_RED signal with PWM to achieve precise brightness control of the onboard LED red channel.

[0030] Figure 7 The 7732_GREEN signal is connected to the gate G of the N-channel MOSFET PQ30 (model L2N7002LT1G) through a 10K / 1% / 4 power gate resistor R23315. The source S of the MOSFET is grounded, and the drain D is connected to the CONN_GREEN output terminal. The microcontroller controls the MOSFET's conduction state by modulating the 7732_GREEN signal with PWM to achieve precise brightness control of the onboard LED green channel.

[0031] Figure 8 The 7732_BLUE signal is connected to the gate G of the N-channel MOSFET PQ32 (model L2N7002LT1G) through a 10K / 1% / 4 power gate resistor R23317. The source S of the MOSFET is grounded, and the drain D is connected to the CONN_BLUE output terminal. The microcontroller controls the MOSFET's conduction state by modulating the 7732_BLUE signal with PWM, realizing precise brightness control of the blue channel of the onboard LED. Together with the red and green channels, it realizes RGB three-primary-color mixing display of 16.77 million colors.

[0032] Specifically, when the received lighting control command uses 16-bit color depth format to encode RGB information, two byte fields containing color information are extracted from the command byte structure, representing the combined encoding of 5-bit red (R) components, 6-bit green (G) components, and 5-bit blue (B) components, respectively. This 16-bit color depth format uses the RGB565 arrangement, where the high 5 bits represent the red component, the middle 6 bits represent the green component, and the low 5 bits represent the blue component. The two bytes are concatenated into a 16-bit unsigned integer value, and the R, G, and B component fields are extracted separately using shift and masking operations. For example, the R field is extracted by right-shifting the 16-bit value by 11 bits and performing a bitwise AND operation with 0x1F; the G field is extracted by right-shifting by 5 bits and performing a mask operation with 0x3F; and the B field is extracted directly with 0x1F. A bit extension operation is performed on each component field to adapt to the 8-bit RGB control structure, logically shifting the 5-bit or 6-bit component to the left by a certain number of bits, and then performing a bitwise OR operation to supplement the precision of the high bits. For example, when the R component is 5 bits, it is first shifted left by 3 bits, then shifted right by 2 bits and bitwise ORed with the left shift result to expand it to an 8-bit approximation. This is achieved by executing the expression R8 bits = (R5 bits << 3) | (R5 bits >> 2), mapping the original 5-bit color depth to an 8-bit representation closer to high-precision color. A similar approach is used for the G component, shifting left by 2 bits and right by 4 bits, resulting in G8 bits = (G6 bits << 2) | (G6 bits >> 4). The B component is processed the same way as R, shifting left by 3 bits and right by 2 bits before bitwise ORing. After completing the bit expansion and bitwise OR operations, a standard 8-bit RGB color value is obtained, with R8, G8, and B8 bits each ranging from 0 to 255. The LED start index field is extracted synchronously from the lighting effect control command to identify the physical number of the LED to which the current color value should be applied. The LED index and the corresponding RGB color value triplet are combined into a complete data structure to form a standardized lighting effect control data unit.

[0033] In one specific embodiment, the PWM duty cycle value is queried based on the RGB color value in the lighting effect control data, and the PWM duty cycle value is converted into a corresponding compare register value to obtain serial transmission code stream data conforming to the 1-wire protocol timing, including: The RGB color values ​​are extracted from the lighting control data and used as an index to query the Gamma correction lookup table stored in Flash to obtain the PWM duty cycle value. Extract each bit value of the PWM duty cycle value, and map the bit value to the comparison register value corresponding to the preset high duty cycle when the bit value is 1, and to the comparison register value corresponding to the preset low duty cycle when the bit value is 0, to obtain the comparison register value sequence; The sequence of comparison register values ​​is written into the PDMA source buffer in the order of the RGB data of each LED to obtain serial transmission code stream data conforming to the 1-wire protocol timing.

[0034] Specifically, RGB color values ​​are extracted from each lighting effect control data unit, and the R, G, and B components of the RGB color values ​​are used as index parameters to sequentially access the Gamma correction lookup table stored in Flash. The Gamma correction lookup table has a fixed 256-byte structure, pre-calculated and stored according to the Gamma 2.2 nonlinear response relationship. Each index value corresponds to a 10-bit PWM duty cycle value, making the visual brightness of the LED during the electro-optical conversion process more consistent with human visual perception. When using the R component value as an index to look up the table, the corresponding R channel PWM duty cycle value is read. Similarly, the same lookup is performed on the G and B components to obtain the 10-bit PWM brightness control values ​​for the R, G, and B channels, respectively. Bit-by-bit splitting is performed on each of these three PWM duty cycle values, extracting each bit from the binary representation of each 10-bit PWM value into an independent bit value, and determining the comparison register value to be used in 1-wire transmission based on the bit value. Specifically, when the bit value is 1, it is mapped to a PWM pulse with a duty cycle of approximately 64% according to the protocol specification, and the corresponding compare register value is calculated and determined to be 655. When the bit value is 0, it is mapped to a PWM pulse with a duty cycle of approximately 32%, and the corresponding compare register value is set to 328. In this way, each PWM duty cycle value is decomposed into a sequence of 10 compare register values, each element being 16 bits of data, which can be directly loaded into the timer PWM output module for waveform control. After decomposing the 10-bit data for each of the R, G, and B channels, the compare register values ​​are written to the PDMA source buffer in the RGB order as specified in the WS2812B protocol. That is, each LED occupies 30 register values, namely 10 bits for the R channel, 10 bits for the G channel, and 10 bits for the B channel, with each value occupying 2 bytes, for a total of 60 bytes of data space. The PDMA source buffer is moved byte by byte by byte by the PDMA channel triggered by the timer into the compare register, which is used to output the PWM waveform cycle by cycle and accurately form a serial code stream through a 1-wire data line.

[0035] In one specific embodiment, each bit value of the PWM duty cycle is extracted, and a comparison register value sequence is obtained by mapping a bit value of 1 to a comparison register value corresponding to a preset high duty cycle and a bit value of 0 to a comparison register value corresponding to a preset low duty cycle, including: Perform a bit-right shift operation on the PWM duty cycle value by a preset number of bits to extract an 8-bit color value; Perform a right shift and a bitwise AND operation on the 8-bit color value sequentially from the most significant bit to the least significant bit to extract the 8-bit value; Traverse the 8 bit values, map the positions with bit values ​​of 1 to the comparison register values ​​corresponding to the preset high duty cycle, and map the positions with bit values ​​of 0 to the comparison register values ​​corresponding to the preset low duty cycle, to obtain the comparison register value sequence.

[0036] Specifically, a right-shift operation is performed on the PWM duty cycle value of each channel to achieve precision truncation. Since the PWM duty cycle value has a 10-bit resolution and the target RGB color value must be limited to an 8-bit format, a preset right-shift number, such as 2 bits, is used to simplify the data from 10 bits to 8 bits. This is achieved by performing the operation "PWM value >> 2", mapping the original PWM value (range 0 to 1023) to an 8-bit integer value (range 0 to 255). For example, when the PWM value is 1023, a right shift of 2 bits results in 255; if the PWM value is 512, a right shift of 2 bits results in 128. The 8-bit value is then extracted bit-by-bit sequentially from the most significant bit to the least significant bit, using a combination of right shift and bitwise AND operations to perform logical judgments from bit 7 to bit 0. The value of the nth bit is extracted using the expression "(color value >> n) & 0x01". This expression first right-shifts the color value by n bits, then performs a bitwise AND operation with 0x01, retaining only the least significant bit to obtain the state of each bit. This process is repeated 8 times to completely restore the 8-bit color value into 8 individual bit values, each with a value of 0 or 1, representing whether the current logic bit is high. These 8 bit values ​​are then iterated through, performing the duty cycle encoding mapping operation corresponding to the 1-wire protocol. According to the protocol, logic 1 needs to be mapped to a high duty cycle PWM waveform, and its corresponding compare register value is a preset high duty cycle value, such as 655; while logic 0 needs to be mapped to a low duty cycle PWM waveform, and its corresponding compare register value is a preset low duty cycle value, such as 328. When processing each bit value, if the current value is 1, 655 is written to the current position in the compare register value sequence; if the current value is 0, 328 is written to that position. After eight complete iterations, a sequence of 8 compare register values ​​is constructed, where each element is a 16-bit integer occupying 2 bytes, used to describe the complete serial PWM code stream of a single color channel. The compare register value sequence is then concatenated with the sequences of the R, G, and B channels to form the complete 24-bit serial code stream required for one LED.

[0037] In one specific embodiment, a first PDMA channel and a second PDMA channel are configured to read the serial transmission code stream data from the first channel and the second channel, respectively, and output parallel lighting effect data from dual 1-wire ports, including: Configure the control registers of the first PDMA channel and the second PDMA channel, set the source address to point to the corresponding PDMA source buffer, the destination address to point to the comparison register of the corresponding timer, and configure the trigger source to be the timer update event; Configure the slave mode control register of the second timer to set the trigger source to the internal trigger output of the first timer, and configure the master mode control register of the first timer to set the output to the update event trigger signal; Configure the corresponding PDMA channel enable bit, start the counter of the first timer, and trigger the second timer to start synchronously through the master-slave synchronization configuration of the first timer, and output parallel lighting effect data of dual 1-wire ports.

[0038] Specifically, the control registers of the first and second PDMA channels are configured sequentially to establish a data transfer path from the PDMA source buffer to the timer compare register. The source address register of the first PDMA channel is configured to point to the starting address of the PDMA source buffer for channel A. The buffer contains PWM code stream data, including 24-bit RGB three-primary-color data and a total of 2880 16-bit compare values, generated according to the LED encoding. Simultaneously, the destination address register is set to point to the address of the first timer's compare register, such as the CCR0 register of Timer0. The trigger source selection field of the PDMA channel is configured to map to the update event of the first timer; that is, whenever the Timer0 counter reaches the auto-reload value and generates an update event, the PDMA is automatically triggered to perform a 16-bit data transfer operation. Using the same configuration logic, the second PDMA channel is initialized, setting its source address to the PDMA source buffer address of channel B and its destination address to the compare register address (e.g., CCR10) of the second timer (e.g., Timer1). Its trigger source is configured to the update event of Timer1, enabling the two PDMA channels to maintain linkage with two independent timer outputs. Configure the slave mode control register of the second timer, setting its trigger source selection field to ITR0 (the internal trigger output line of the first timer), and configuring the SMS field to select the trigger mode, so that the second timer automatically starts after detecting an update event signal from the first timer. Simultaneously, configure the master mode control register of the first timer, setting its main output signal MMS field to an update event, meaning that when Timer0 completes a counting cycle, it immediately outputs a TRGO signal, which is connected to Timer1 via the internal bus, realizing a hardware-level synchronous startup mechanism where the master timer drives the slave timer. Enable the start control bits of both PDMA channels sequentially, putting them into a ready-to-trigger state, and write the counter enable bit CEN in the first timer control register to 1, enabling Timer0 to officially start counting. Since Timer1 is already set to slave mode and waiting for the ITR0 signal, when Timer0 generates its first update event and outputs TRGO, Timer1 will immediately start synchronously, achieving parallel operation of the two counters. At this time, the two PDMA channels write the prepared comparison register values ​​into the corresponding CCR registers one by one under the update events of Timer0 and Timer1, respectively. This drives the GPIO output port to generate PWM waveform sequences in real time according to the 1-wire protocol timing. The serial lighting effect code streams of channel A and channel B are output through the two physical pins P2.0 and P2.1, respectively, realizing the parallel synchronous transmission of dual-channel RGB lighting effect data in the time domain.

[0039] In one specific embodiment, after outputting the parallel lighting effect data from the dual 1-wire ports, the method further includes: The LED color data of the current frame and the previous frame are traversed to calculate the RGB color Euclidean distance of each LED, and the number of LEDs whose RGB color Euclidean distance exceeds the preset color difference threshold is counted and the color change rate is calculated. The cumulative value of color difference is calculated based on the LED color data. The corresponding refresh frequency is obtained by querying the preset mapping table from the lighting effect mode field. The color change rate, the cumulative value of color difference and the refresh frequency are weighted and summed to obtain the comprehensive complexity score. The comprehensive complexity score is mapped to the corresponding main frequency level value according to the preset score range, and the frequency division coefficient corresponding to the main frequency level value is written into the system clock control register.

[0040] Specifically, the RGB color data of all LEDs in the current frame and the previous frame are traversed, and the color change of each LED is calculated separately. The R, G, and B components of the i-th LED in the current frame are read sequentially, along with the R′, G′, and B′ components of the same-numbered LED in the previous frame. A color difference measure is constructed based on the Euclidean distance formula, i.e., ΔEi = √[(R... i R′ i ) 2 + (G i G′ i ) 2 + (B i B′ i ) 2 The calculation uses a weighted sum of integer squares combined with a fixed-point square root algorithm to avoid introducing floating-point calculations. For each LED, ΔE... i The color difference is compared with a preset color difference threshold (e.g., 8, corresponding to 3% human eye sensitivity). When the Euclidean distance of an LED exceeds the color difference threshold, it is counted as a valid color change event. After traversing all LEDs (e.g., 120 LEDs), the number of LEDs with significant color differences is divided by the total number of LEDs and multiplied by 100% to obtain the color change rate parameter between the current frame and the previous frame, which is used to measure the coverage of color changes within the spatial range. The LED sequence of the current frame is traversed again, and the RGB Euclidean distance ΔE between all adjacent LED pairs is continuously calculated. i,i+1 That is, by accumulating ΔE i With ΔE i+1The color difference is used to construct a cumulative color difference value, reflecting the intensity of spatial gradation in the LED arrangement. This cumulative color difference value is normalized to the average color difference of each LED pair, forming a quantitative measure of the smoothness of color transition. Simultaneously, the lighting effect mode code is read from the lighting effect mode field in the current frame's lighting effect control data. For example, static mode code is 0x01, breathing mode is 0x02, flowing mode is 0x03, rainbow mode is 0x04, etc. The mode code is then used to look up the corresponding refresh rate value in the mapping table stored in Flash, reflecting the frame refresh intensity of the lighting effect mode per unit time. The color change rate, cumulative color difference value, and refresh rate are weighted and summed to obtain a comprehensive complexity score, with weights set as w1, w2, and w3, for example, w1=40%, w2=30%, w3=30%. The comprehensive complexity score is then compared with a set of preset scoring interval mapping tables to determine the main frequency level. If the score is less than 20, it is mapped to a low clock frequency, such as 16MHz; if the score is between 20 and 50, it corresponds to the standard clock frequency of 24MHz; if the score is between 50 and 80, it selects the high-performance clock frequency of 28MHz; if the score is higher than 80, it corresponds to the extreme clock frequency of 32MHz. The PLL division parameters required for the target clock frequency are written to the system clock control register. This includes first adjusting the Flash access wait period parameters, then configuring the PLL multiplier and input division coefficient, then starting the PLL phase-locked loop and polling its stability flag, and finally updating the main system clock source to switch to the PLL signal output at the new frequency, and simultaneously adjusting the clock dividers of various peripherals such as the Timer and USB controller. This ensures that the PWM waveform, PDMA transmission, and other control links maintain periodic consistency and signal integrity under the new clock frequency, supporting the real-time response and visual consistency of the lighting system during dynamic changes in complexity with optimal power efficiency.

[0041] In one specific embodiment, a timestamp difference is calculated based on the parallel lighting effect data. When the timestamp difference exceeds a preset synchronization threshold, a delay timer is initiated to delay the PDMA enable operation of the channel with the earlier timestamp, including: Read the first timestamp field of the first frame data from the frame queue of the first channel and the second timestamp field of the first frame data from the frame queue of the second channel; Calculate the timestamp difference between the first timestamp field and the second timestamp field; Determine whether the absolute value of the timestamp difference exceeds a preset synchronization threshold. If it does, determine the channel with the earlier timestamp based on the positive or negative sign of the timestamp difference to obtain the channel identifier and delay time value. Configure the auto-reload register of the delay timer according to the required delay channel identifier, set the count value corresponding to the delay time value, start the delay timer, and enable the PDMA channel enable bit of the corresponding channel when an overflow interrupt is triggered.

[0042] Specifically, the system reads the first timestamp field of the first frame from the frame queue structure of the first channel and simultaneously reads the second timestamp field of the first frame from the frame queue of the second channel. Both timestamp fields are SysTick timer counts recorded by the system during frame generation, in milliseconds, and exhibit monotonically increasing temporal continuity. The second timestamp is subtracted from the first timestamp to obtain the timestamp difference ΔT, which measures the time offset between the two frames at their generation time. The absolute value of the timestamp difference is judged. If its absolute value does not exceed a preset synchronization threshold (e.g., 5 milliseconds), the frame synchronization of the two channels is considered acceptable, and dual-channel PDMA parallel transmission operation is directly initiated. However, when the absolute value of the timestamp difference ΔT exceeds the synchronization threshold, it indicates a significant offset in the frame generation time of the two channels, and a control mechanism is introduced to correct the frame output timing to restore display synchronization between the channels. Under these conditions, the sign of ΔT determines which channel's frame data was generated earlier. If ΔT is positive, it indicates the second channel's frame generation time is newer, and the first channel's is earlier; therefore, a delay control is applied to the PDMA startup operation of the first channel. Conversely, if ΔT is negative, the PDMA startup process of the second channel is delayed. Based on this determination, the channel identifier of the channel requiring delay and its corresponding delay time value are obtained. According to the identified channel identifier requiring delay, an auxiliary timer resource for delayed execution is selected, and the automatic reload register (ARR) of this timer is configured numerically. Since the system uses a 32kHz low-speed clock as the base frequency for the delay timer, the millisecond time value to be delayed is multiplied by 32 to obtain the count value of the timer's ARR register. For example, when ΔT = 10ms, ARR should be set to 320. After configuration, the initial value of the timer counter is cleared and set to single-count mode. Simultaneously, the overflow interrupt enable bit is enabled to ensure that overflow events can be captured by the interrupt handler. When the timer is started, its internal counter increments from 0 at a frequency of 32kHz until it reaches the ARR set value, triggering an overflow event. Upon overflow interrupt, the interrupt service routine writes to the target channel's PDMA control register, setting the enable bit EN in the channel's PDMA control register to 1, thus initiating the PDMA data transfer process for the delayed channel. Simultaneously, a PDMA start command is executed on the main channel (the non-delayed channel), causing it to enter the data transfer state first. The delayed channel starts only after the delay count is complete, achieving synchronized PWM data output between the two channels.

[0043] The A-RGB lighting effect control method in the embodiments of the present invention has been described above. The A-RGB lighting effect control device in the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 9 One embodiment of the A-RGB lighting effect control device in this invention includes: The feature code comparison module 901 is used to send device query commands to the external A-RGB devices connected to the first channel and the second channel in sequence, receive the response code returned by the external A-RGB devices and compare it byte by byte with the brand protocol feature code stored in Flash to obtain serial transmission code stream data; The reading module 902 is configured to read the serial transmission code stream data from the first channel and the second channel respectively, and output parallel lighting effect data from dual-channel 1-wire ports; The enable operation module 903 is used to calculate the timestamp difference based on the parallel lighting effect data. When the timestamp difference exceeds a preset synchronization threshold, the delay timer is started to delay the PDMA enable operation of the channel with the earlier timestamp.

[0044] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0045] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0046] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling A-RGB lighting effects, characterized in that, include: Device query commands are sent sequentially to the external A-RGB devices connected to the first and second channels. The response codes returned by the external A-RGB devices are received and compared byte by byte with the brand protocol feature codes stored in Flash to obtain serial transmission code stream data. Configure the first PDMA channel and the second PDMA channel to read the serial transmission code stream data from the first channel and the second channel respectively, and output the parallel lighting effect data of the dual-channel 1-wire port; Based on the parallel lighting effect data, the timestamp difference is calculated. When the timestamp difference exceeds a preset synchronization threshold, a delay timer is started to delay the PDMA enable operation of the channel with the earlier timestamp.

2. The A-RGB lighting effect control method according to claim 1, characterized in that, Before sequentially sending device query commands to the external A-RGB devices connected to the first and second channels, the process also includes: Configure the system clock control register, set the internal high-speed oscillator to the preset main frequency and enable the phase-locked loop, switch the GPIO function multiplexing register of the first and second pins to the multiplexing function mode and set the drive strength to the preset current value; Set the clock prescaler register of the first and second timers to the preset division ratio, set the auto-reload register to the preset resolution minus one count value, and configure the output compare mode register to PWM mode.

3. The A-RGB lighting effect control method according to claim 2, characterized in that, Device query commands are sequentially sent to the external A-RGB devices connected to the first and second channels. The response codes returned by the external A-RGB devices are received and compared byte-by-byte with the brand protocol feature codes stored in Flash to obtain the serial transmission code stream data, including: Send a preset number of brand query commands sequentially to an external A-RGB device via a 1-wire interface and receive the response code returned by the external A-RGB device; The response code is compared byte by byte with the brand protocol feature code stored in Flash. When the number of matching bytes exceeds a preset comparison threshold, the brand type identifier is recorded. Based on the brand type identifier, the RGB color value field is extracted from the brand private protocol instruction, and the RGB color value field is combined with the supplementary LED index field and lighting effect mode field to form a lighting effect control instruction; The lighting effect control data, including LED index and RGB color value, is obtained by parsing the lighting effect control command. The PWM duty cycle value is queried based on the RGB color value in the lighting effect control data. The PWM duty cycle value is converted into the corresponding comparison register value to obtain serial transmission code stream data that conforms to the 1-wire protocol timing.

4. The A-RGB lighting effect control method according to claim 3, characterized in that, The lighting effect control data, including LED indexes and RGB color values, is obtained by parsing the lighting effect control instructions, including: Extract the R component field, G component field, and B component field of the 16-bit color depth format RGB value from the lighting effect control command; The R component field, G component field, and B component field are respectively subjected to bitwise OR operation to obtain RGB color values. The RGB color values ​​are then combined with the LED index field in the lighting effect control instruction to obtain lighting effect control data.

5. The A-RGB lighting effect control method according to claim 3, characterized in that, The PWM duty cycle value is retrieved based on the RGB color values ​​in the lighting effect control data. This PWM duty cycle value is then converted into a corresponding compare register value to obtain serial transmission bitstream data conforming to the 1-wire protocol timing, including: The RGB color values ​​are extracted from the lighting control data and used as an index to query the Gamma correction lookup table stored in Flash to obtain the PWM duty cycle value. Extract each bit value of the PWM duty cycle value, and map the bit value to the comparison register value corresponding to the preset high duty cycle when the bit value is 1, and to the comparison register value corresponding to the preset low duty cycle when the bit value is 0, to obtain the comparison register value sequence; The sequence of comparison register values ​​is written into the PDMA source buffer in the order of the RGB data of each LED to obtain serial transmission code stream data conforming to the 1-wire protocol timing.

6. The A-RGB lighting effect control method according to claim 5, characterized in that, Extract each bit value of the PWM duty cycle value, and map a bit value of 1 to a comparison register value corresponding to a preset high duty cycle, and a bit value of 0 to a comparison register value corresponding to a preset low duty cycle, to obtain a comparison register value sequence, including: Perform a bit-right shift operation on the PWM duty cycle value by a preset number of bits to extract an 8-bit color value; Perform a right shift and a bitwise AND operation on the 8-bit color value sequentially from the most significant bit to the least significant bit to extract the 8-bit value; Traverse the 8 bit values, map the positions with bit values ​​of 1 to the comparison register values ​​corresponding to the preset high duty cycle, and map the positions with bit values ​​of 0 to the comparison register values ​​corresponding to the preset low duty cycle, to obtain the comparison register value sequence.

7. The A-RGB lighting effect control method according to claim 6, characterized in that, Configure the first PDMA channel and the second PDMA channel to read the serial transmission code stream data from the first channel and the second channel respectively, and output parallel lighting effect data from dual 1-wire ports, including: Configure the control registers of the first PDMA channel and the second PDMA channel, set the source address to point to the corresponding PDMA source buffer, the destination address to point to the comparison register of the corresponding timer, and configure the trigger source to be the timer update event; Configure the slave mode control register of the second timer to set the trigger source to the internal trigger output of the first timer, and configure the master mode control register of the first timer to set the output to the update event trigger signal; Configure the corresponding PDMA channel enable bit, start the counter of the first timer, and trigger the second timer to start synchronously through the master-slave synchronization configuration of the first timer, and output parallel lighting effect data of dual 1-wire ports.

8. The A-RGB lighting effect control method according to claim 7, characterized in that, After outputting parallel lighting effect data from dual 1-wire ports, it also includes: The LED color data of the current frame and the previous frame are traversed to calculate the RGB color Euclidean distance of each LED, and the number of LEDs whose RGB color Euclidean distance exceeds the preset color difference threshold is counted and the color change rate is calculated. The cumulative value of color difference is calculated based on the LED color data. The corresponding refresh frequency is obtained by querying the preset mapping table from the lighting effect mode field. The color change rate, the cumulative value of color difference and the refresh frequency are weighted and summed to obtain the comprehensive complexity score. The comprehensive complexity score is mapped to the corresponding main frequency level value according to the preset score range, and the frequency division coefficient corresponding to the main frequency level value is written into the system clock control register.

9. The A-RGB lighting effect control method according to claim 8, characterized in that, Based on the parallel lighting effect data, a timestamp difference is calculated. When the timestamp difference exceeds a preset synchronization threshold, a delay timer is started to delay the PDMA enable operation of the channel with the earlier timestamp, including: Read the first timestamp field of the first frame data from the frame queue of the first channel and the second timestamp field of the first frame data from the frame queue of the second channel; Calculate the timestamp difference between the first timestamp field and the second timestamp field; Determine whether the absolute value of the timestamp difference exceeds a preset synchronization threshold. If it does, determine the channel with the earlier timestamp based on the positive or negative sign of the timestamp difference to obtain the channel identifier and delay time value. Configure the auto-reload register of the delay timer according to the required delay channel identifier, set the count value corresponding to the delay time value, start the delay timer, and enable the PDMA channel enable bit of the corresponding channel when an overflow interrupt is triggered.

10. An A-RGB lighting effect control device, characterized in that, For performing the A-RGB lighting effect control method as described in any one of claims 1-9, the A-RGB lighting effect control device comprises: The feature code comparison module is used to sequentially send device query commands to the external A-RGB devices connected to the first channel and the second channel, receive the response codes returned by the external A-RGB devices, and compare them byte by byte with the brand protocol feature codes stored in Flash to obtain serial transmission code stream data; The reading module is configured to read the serial transmission code stream data from the first channel and the second channel respectively, and output parallel lighting effect data from dual-channel 1-wire ports; The enable operation module is used to calculate the timestamp difference based on the parallel lighting effect data. When the timestamp difference exceeds a preset synchronization threshold, a delay timer is started to delay the PDMA enable operation of the channel with the earlier timestamp.

Images